diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v new file mode 100644 index 0000000..6cb0345 --- /dev/null +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v @@ -0,0 +1,1389 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RDY_reset O 1 +// from_master_awready O 1 reg +// from_master_wready O 1 reg +// from_master_bvalid O 1 reg +// from_master_bid O 4 reg +// from_master_bresp O 2 reg +// from_master_arready O 1 reg +// from_master_rvalid O 1 reg +// from_master_rid O 4 reg +// from_master_rdata O 64 reg +// from_master_rresp O 2 reg +// from_master_rlast O 1 reg +// to_slave_awvalid O 1 reg +// to_slave_awid O 4 reg +// to_slave_awaddr O 64 reg +// to_slave_awlen O 8 reg +// to_slave_awsize O 3 reg +// to_slave_awburst O 2 reg +// to_slave_awlock O 1 reg +// to_slave_awcache O 4 reg +// to_slave_awprot O 3 reg +// to_slave_awqos O 4 reg +// to_slave_awregion O 4 reg +// to_slave_wvalid O 1 reg +// to_slave_wdata O 64 reg +// to_slave_wstrb O 8 reg +// to_slave_wlast O 1 reg +// to_slave_bready O 1 reg +// to_slave_arvalid O 1 reg +// to_slave_arid O 4 reg +// to_slave_araddr O 64 reg +// to_slave_arlen O 8 reg +// to_slave_arsize O 3 reg +// to_slave_arburst O 2 reg +// to_slave_arlock O 1 reg +// to_slave_arcache O 4 reg +// to_slave_arprot O 3 reg +// to_slave_arqos O 4 reg +// to_slave_arregion O 4 reg +// to_slave_rready O 1 reg +// CLK I 1 clock +// RST_N I 1 reset +// from_master_awvalid I 1 +// from_master_awid I 4 reg +// from_master_awaddr I 64 reg +// from_master_awlen I 8 reg +// from_master_awsize I 3 reg +// from_master_awburst I 2 reg +// from_master_awlock I 1 reg +// from_master_awcache I 4 reg +// from_master_awprot I 3 reg +// from_master_awqos I 4 reg +// from_master_awregion I 4 reg +// from_master_wvalid I 1 +// from_master_wdata I 64 reg +// from_master_wstrb I 8 reg +// from_master_wlast I 1 reg +// from_master_bready I 1 +// from_master_arvalid I 1 +// from_master_arid I 4 reg +// from_master_araddr I 64 reg +// from_master_arlen I 8 reg +// from_master_arsize I 3 reg +// from_master_arburst I 2 reg +// from_master_arlock I 1 reg +// from_master_arcache I 4 reg +// from_master_arprot I 3 reg +// from_master_arqos I 4 reg +// from_master_arregion I 4 reg +// from_master_rready I 1 +// to_slave_awready I 1 +// to_slave_wready I 1 +// to_slave_bvalid I 1 +// to_slave_bid I 4 reg +// to_slave_bresp I 2 reg +// to_slave_arready I 1 +// to_slave_rvalid I 1 +// to_slave_rid I 4 reg +// to_slave_rdata I 64 reg +// to_slave_rresp I 2 reg +// to_slave_rlast I 1 reg +// EN_reset I 1 +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkAXI4_Deburster_A(CLK, + RST_N, + + EN_reset, + RDY_reset, + + from_master_awvalid, + from_master_awid, + from_master_awaddr, + from_master_awlen, + from_master_awsize, + from_master_awburst, + from_master_awlock, + from_master_awcache, + from_master_awprot, + from_master_awqos, + from_master_awregion, + + from_master_awready, + + from_master_wvalid, + from_master_wdata, + from_master_wstrb, + from_master_wlast, + + from_master_wready, + + from_master_bvalid, + + from_master_bid, + + from_master_bresp, + + from_master_bready, + + from_master_arvalid, + from_master_arid, + from_master_araddr, + from_master_arlen, + from_master_arsize, + from_master_arburst, + from_master_arlock, + from_master_arcache, + from_master_arprot, + from_master_arqos, + from_master_arregion, + + from_master_arready, + + from_master_rvalid, + + from_master_rid, + + from_master_rdata, + + from_master_rresp, + + from_master_rlast, + + from_master_rready, + + to_slave_awvalid, + + to_slave_awid, + + to_slave_awaddr, + + to_slave_awlen, + + to_slave_awsize, + + to_slave_awburst, + + to_slave_awlock, + + to_slave_awcache, + + to_slave_awprot, + + to_slave_awqos, + + to_slave_awregion, + + to_slave_awready, + + to_slave_wvalid, + + to_slave_wdata, + + to_slave_wstrb, + + to_slave_wlast, + + to_slave_wready, + + to_slave_bvalid, + to_slave_bid, + to_slave_bresp, + + to_slave_bready, + + to_slave_arvalid, + + to_slave_arid, + + to_slave_araddr, + + to_slave_arlen, + + to_slave_arsize, + + to_slave_arburst, + + to_slave_arlock, + + to_slave_arcache, + + to_slave_arprot, + + to_slave_arqos, + + to_slave_arregion, + + to_slave_arready, + + to_slave_rvalid, + to_slave_rid, + to_slave_rdata, + to_slave_rresp, + to_slave_rlast, + + to_slave_rready); + input CLK; + input RST_N; + + // action method reset + input EN_reset; + output RDY_reset; + + // action method from_master_m_awvalid + input from_master_awvalid; + input [3 : 0] from_master_awid; + input [63 : 0] from_master_awaddr; + input [7 : 0] from_master_awlen; + input [2 : 0] from_master_awsize; + input [1 : 0] from_master_awburst; + input from_master_awlock; + input [3 : 0] from_master_awcache; + input [2 : 0] from_master_awprot; + input [3 : 0] from_master_awqos; + input [3 : 0] from_master_awregion; + + // value method from_master_m_awready + output from_master_awready; + + // action method from_master_m_wvalid + input from_master_wvalid; + input [63 : 0] from_master_wdata; + input [7 : 0] from_master_wstrb; + input from_master_wlast; + + // value method from_master_m_wready + output from_master_wready; + + // value method from_master_m_bvalid + output from_master_bvalid; + + // value method from_master_m_bid + output [3 : 0] from_master_bid; + + // value method from_master_m_bresp + output [1 : 0] from_master_bresp; + + // value method from_master_m_buser + + // action method from_master_m_bready + input from_master_bready; + + // action method from_master_m_arvalid + input from_master_arvalid; + input [3 : 0] from_master_arid; + input [63 : 0] from_master_araddr; + input [7 : 0] from_master_arlen; + input [2 : 0] from_master_arsize; + input [1 : 0] from_master_arburst; + input from_master_arlock; + input [3 : 0] from_master_arcache; + input [2 : 0] from_master_arprot; + input [3 : 0] from_master_arqos; + input [3 : 0] from_master_arregion; + + // value method from_master_m_arready + output from_master_arready; + + // value method from_master_m_rvalid + output from_master_rvalid; + + // value method from_master_m_rid + output [3 : 0] from_master_rid; + + // value method from_master_m_rdata + output [63 : 0] from_master_rdata; + + // value method from_master_m_rresp + output [1 : 0] from_master_rresp; + + // value method from_master_m_rlast + output from_master_rlast; + + // value method from_master_m_ruser + + // action method from_master_m_rready + input from_master_rready; + + // value method to_slave_m_awvalid + output to_slave_awvalid; + + // value method to_slave_m_awid + output [3 : 0] to_slave_awid; + + // value method to_slave_m_awaddr + output [63 : 0] to_slave_awaddr; + + // value method to_slave_m_awlen + output [7 : 0] to_slave_awlen; + + // value method to_slave_m_awsize + output [2 : 0] to_slave_awsize; + + // value method to_slave_m_awburst + output [1 : 0] to_slave_awburst; + + // value method to_slave_m_awlock + output to_slave_awlock; + + // value method to_slave_m_awcache + output [3 : 0] to_slave_awcache; + + // value method to_slave_m_awprot + output [2 : 0] to_slave_awprot; + + // value method to_slave_m_awqos + output [3 : 0] to_slave_awqos; + + // value method to_slave_m_awregion + output [3 : 0] to_slave_awregion; + + // value method to_slave_m_awuser + + // action method to_slave_m_awready + input to_slave_awready; + + // value method to_slave_m_wvalid + output to_slave_wvalid; + + // value method to_slave_m_wdata + output [63 : 0] to_slave_wdata; + + // value method to_slave_m_wstrb + output [7 : 0] to_slave_wstrb; + + // value method to_slave_m_wlast + output to_slave_wlast; + + // value method to_slave_m_wuser + + // action method to_slave_m_wready + input to_slave_wready; + + // action method to_slave_m_bvalid + input to_slave_bvalid; + input [3 : 0] to_slave_bid; + input [1 : 0] to_slave_bresp; + + // value method to_slave_m_bready + output to_slave_bready; + + // value method to_slave_m_arvalid + output to_slave_arvalid; + + // value method to_slave_m_arid + output [3 : 0] to_slave_arid; + + // value method to_slave_m_araddr + output [63 : 0] to_slave_araddr; + + // value method to_slave_m_arlen + output [7 : 0] to_slave_arlen; + + // value method to_slave_m_arsize + output [2 : 0] to_slave_arsize; + + // value method to_slave_m_arburst + output [1 : 0] to_slave_arburst; + + // value method to_slave_m_arlock + output to_slave_arlock; + + // value method to_slave_m_arcache + output [3 : 0] to_slave_arcache; + + // value method to_slave_m_arprot + output [2 : 0] to_slave_arprot; + + // value method to_slave_m_arqos + output [3 : 0] to_slave_arqos; + + // value method to_slave_m_arregion + output [3 : 0] to_slave_arregion; + + // value method to_slave_m_aruser + + // action method to_slave_m_arready + input to_slave_arready; + + // action method to_slave_m_rvalid + input to_slave_rvalid; + input [3 : 0] to_slave_rid; + input [63 : 0] to_slave_rdata; + input [1 : 0] to_slave_rresp; + input to_slave_rlast; + + // value method to_slave_m_rready + output to_slave_rready; + + // signals for module outputs + wire [63 : 0] from_master_rdata, + to_slave_araddr, + to_slave_awaddr, + to_slave_wdata; + wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; + wire [3 : 0] from_master_bid, + from_master_rid, + to_slave_arcache, + to_slave_arid, + to_slave_arqos, + to_slave_arregion, + to_slave_awcache, + to_slave_awid, + to_slave_awqos, + to_slave_awregion; + wire [2 : 0] to_slave_arprot, + to_slave_arsize, + to_slave_awprot, + to_slave_awsize; + wire [1 : 0] from_master_bresp, + from_master_rresp, + to_slave_arburst, + to_slave_awburst; + wire RDY_reset, + from_master_arready, + from_master_awready, + from_master_bvalid, + from_master_rlast, + from_master_rvalid, + from_master_wready, + to_slave_arlock, + to_slave_arvalid, + to_slave_awlock, + to_slave_awvalid, + to_slave_bready, + to_slave_rready, + to_slave_wlast, + to_slave_wvalid; + + // register m_rg_ar_beat_count + reg [7 : 0] m_rg_ar_beat_count; + wire [7 : 0] m_rg_ar_beat_count$D_IN; + wire m_rg_ar_beat_count$EN; + + // register m_rg_b_beat_count + reg [7 : 0] m_rg_b_beat_count; + wire [7 : 0] m_rg_b_beat_count$D_IN; + wire m_rg_b_beat_count$EN; + + // register m_rg_b_resp + reg [1 : 0] m_rg_b_resp; + wire [1 : 0] m_rg_b_resp$D_IN; + wire m_rg_b_resp$EN; + + // register m_rg_r_beat_count + reg [7 : 0] m_rg_r_beat_count; + wire [7 : 0] m_rg_r_beat_count$D_IN; + wire m_rg_r_beat_count$EN; + + // register m_rg_reset + reg m_rg_reset; + wire m_rg_reset$D_IN, m_rg_reset$EN; + + // register m_rg_w_beat_count + reg [7 : 0] m_rg_w_beat_count; + wire [7 : 0] m_rg_w_beat_count$D_IN; + wire m_rg_w_beat_count$EN; + + // ports of submodule m_f_r_arlen + wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; + wire m_f_r_arlen$CLR, + m_f_r_arlen$DEQ, + m_f_r_arlen$EMPTY_N, + m_f_r_arlen$ENQ, + m_f_r_arlen$FULL_N; + + // ports of submodule m_f_w_awlen + wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; + wire m_f_w_awlen$CLR, + m_f_w_awlen$DEQ, + m_f_w_awlen$EMPTY_N, + m_f_w_awlen$ENQ, + m_f_w_awlen$FULL_N; + + // ports of submodule m_xactor_from_master_f_rd_addr + wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, + m_xactor_from_master_f_rd_addr$D_OUT; + wire m_xactor_from_master_f_rd_addr$CLR, + m_xactor_from_master_f_rd_addr$DEQ, + m_xactor_from_master_f_rd_addr$EMPTY_N, + m_xactor_from_master_f_rd_addr$ENQ, + m_xactor_from_master_f_rd_addr$FULL_N; + + // ports of submodule m_xactor_from_master_f_rd_data + wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, + m_xactor_from_master_f_rd_data$D_OUT; + wire m_xactor_from_master_f_rd_data$CLR, + m_xactor_from_master_f_rd_data$DEQ, + m_xactor_from_master_f_rd_data$EMPTY_N, + m_xactor_from_master_f_rd_data$ENQ, + m_xactor_from_master_f_rd_data$FULL_N; + + // ports of submodule m_xactor_from_master_f_wr_addr + wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, + m_xactor_from_master_f_wr_addr$D_OUT; + wire m_xactor_from_master_f_wr_addr$CLR, + m_xactor_from_master_f_wr_addr$DEQ, + m_xactor_from_master_f_wr_addr$EMPTY_N, + m_xactor_from_master_f_wr_addr$ENQ, + m_xactor_from_master_f_wr_addr$FULL_N; + + // ports of submodule m_xactor_from_master_f_wr_data + wire [72 : 0] m_xactor_from_master_f_wr_data$D_IN, + m_xactor_from_master_f_wr_data$D_OUT; + wire m_xactor_from_master_f_wr_data$CLR, + m_xactor_from_master_f_wr_data$DEQ, + m_xactor_from_master_f_wr_data$EMPTY_N, + m_xactor_from_master_f_wr_data$ENQ, + m_xactor_from_master_f_wr_data$FULL_N; + + // ports of submodule m_xactor_from_master_f_wr_resp + wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, + m_xactor_from_master_f_wr_resp$D_OUT; + wire m_xactor_from_master_f_wr_resp$CLR, + m_xactor_from_master_f_wr_resp$DEQ, + m_xactor_from_master_f_wr_resp$EMPTY_N, + m_xactor_from_master_f_wr_resp$ENQ, + m_xactor_from_master_f_wr_resp$FULL_N; + + // ports of submodule m_xactor_to_slave_f_rd_addr + wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, + m_xactor_to_slave_f_rd_addr$D_OUT; + wire m_xactor_to_slave_f_rd_addr$CLR, + m_xactor_to_slave_f_rd_addr$DEQ, + m_xactor_to_slave_f_rd_addr$EMPTY_N, + m_xactor_to_slave_f_rd_addr$ENQ, + m_xactor_to_slave_f_rd_addr$FULL_N; + + // ports of submodule m_xactor_to_slave_f_rd_data + wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, + m_xactor_to_slave_f_rd_data$D_OUT; + wire m_xactor_to_slave_f_rd_data$CLR, + m_xactor_to_slave_f_rd_data$DEQ, + m_xactor_to_slave_f_rd_data$EMPTY_N, + m_xactor_to_slave_f_rd_data$ENQ, + m_xactor_to_slave_f_rd_data$FULL_N; + + // ports of submodule m_xactor_to_slave_f_wr_addr + wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, + m_xactor_to_slave_f_wr_addr$D_OUT; + wire m_xactor_to_slave_f_wr_addr$CLR, + m_xactor_to_slave_f_wr_addr$DEQ, + m_xactor_to_slave_f_wr_addr$EMPTY_N, + m_xactor_to_slave_f_wr_addr$ENQ, + m_xactor_to_slave_f_wr_addr$FULL_N; + + // ports of submodule m_xactor_to_slave_f_wr_data + wire [72 : 0] m_xactor_to_slave_f_wr_data$D_IN, + m_xactor_to_slave_f_wr_data$D_OUT; + wire m_xactor_to_slave_f_wr_data$CLR, + m_xactor_to_slave_f_wr_data$DEQ, + m_xactor_to_slave_f_wr_data$EMPTY_N, + m_xactor_to_slave_f_wr_data$ENQ, + m_xactor_to_slave_f_wr_data$FULL_N; + + // ports of submodule m_xactor_to_slave_f_wr_resp + wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, + m_xactor_to_slave_f_wr_resp$D_OUT; + wire m_xactor_to_slave_f_wr_resp$CLR, + m_xactor_to_slave_f_wr_resp$DEQ, + m_xactor_to_slave_f_wr_resp$EMPTY_N, + m_xactor_to_slave_f_wr_resp$ENQ, + m_xactor_to_slave_f_wr_resp$FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, + CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, + CAN_FIRE_RL_m_rl_reset, + CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, + CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, + CAN_FIRE_from_master_m_arvalid, + CAN_FIRE_from_master_m_awvalid, + CAN_FIRE_from_master_m_bready, + CAN_FIRE_from_master_m_rready, + CAN_FIRE_from_master_m_wvalid, + CAN_FIRE_reset, + CAN_FIRE_to_slave_m_arready, + CAN_FIRE_to_slave_m_awready, + CAN_FIRE_to_slave_m_bvalid, + CAN_FIRE_to_slave_m_rvalid, + CAN_FIRE_to_slave_m_wready, + WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, + WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, + WILL_FIRE_RL_m_rl_reset, + WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, + WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, + WILL_FIRE_from_master_m_arvalid, + WILL_FIRE_from_master_m_awvalid, + WILL_FIRE_from_master_m_bready, + WILL_FIRE_from_master_m_rready, + WILL_FIRE_from_master_m_wvalid, + WILL_FIRE_reset, + WILL_FIRE_to_slave_m_arready, + WILL_FIRE_to_slave_m_awready, + WILL_FIRE_to_slave_m_bvalid, + WILL_FIRE_to_slave_m_rvalid, + WILL_FIRE_to_slave_m_wready; + + // inputs to muxes for submodule ports + wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, + MUX_m_rg_b_beat_count$write_1__VAL_2, + MUX_m_rg_r_beat_count$write_1__VAL_2, + MUX_m_rg_w_beat_count$write_1__VAL_2; + wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; + wire MUX_m_rg_b_resp$write_1__SEL_2; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h2422; + reg [31 : 0] v__h1446; + reg [31 : 0] v__h1440; + reg [31 : 0] v__h2416; + // synopsys translate_on + + // remaining internal signals + wire [63 : 0] a_out_araddr__h2934, + a_out_awaddr__h1951, + addr___1__h2036, + addr___1__h3019; + wire [7 : 0] x__h2297, x__h2788, x__h3180, x__h3378; + wire m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94, + m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50, + m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105, + m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; + + // action method reset + assign RDY_reset = !m_rg_reset ; + assign CAN_FIRE_reset = !m_rg_reset ; + assign WILL_FIRE_reset = EN_reset ; + + // action method from_master_m_awvalid + assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; + assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; + + // value method from_master_m_awready + assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; + + // action method from_master_m_wvalid + assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; + assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; + + // value method from_master_m_wready + assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; + + // value method from_master_m_bvalid + assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; + + // value method from_master_m_bid + assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; + + // value method from_master_m_bresp + assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; + + // action method from_master_m_bready + assign CAN_FIRE_from_master_m_bready = 1'd1 ; + assign WILL_FIRE_from_master_m_bready = 1'd1 ; + + // action method from_master_m_arvalid + assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; + assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; + + // value method from_master_m_arready + assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; + + // value method from_master_m_rvalid + assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; + + // value method from_master_m_rid + assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; + + // value method from_master_m_rdata + assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; + + // value method from_master_m_rresp + assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; + + // value method from_master_m_rlast + assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; + + // action method from_master_m_rready + assign CAN_FIRE_from_master_m_rready = 1'd1 ; + assign WILL_FIRE_from_master_m_rready = 1'd1 ; + + // value method to_slave_m_awvalid + assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; + + // value method to_slave_m_awid + assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; + + // value method to_slave_m_awaddr + assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; + + // value method to_slave_m_awlen + assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; + + // value method to_slave_m_awsize + assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; + + // value method to_slave_m_awburst + assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; + + // value method to_slave_m_awlock + assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; + + // value method to_slave_m_awcache + assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; + + // value method to_slave_m_awprot + assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; + + // value method to_slave_m_awqos + assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; + + // value method to_slave_m_awregion + assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; + + // action method to_slave_m_awready + assign CAN_FIRE_to_slave_m_awready = 1'd1 ; + assign WILL_FIRE_to_slave_m_awready = 1'd1 ; + + // value method to_slave_m_wvalid + assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; + + // value method to_slave_m_wdata + assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; + + // value method to_slave_m_wstrb + assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; + + // value method to_slave_m_wlast + assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; + + // action method to_slave_m_wready + assign CAN_FIRE_to_slave_m_wready = 1'd1 ; + assign WILL_FIRE_to_slave_m_wready = 1'd1 ; + + // action method to_slave_m_bvalid + assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; + assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; + + // value method to_slave_m_bready + assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; + + // value method to_slave_m_arvalid + assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; + + // value method to_slave_m_arid + assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; + + // value method to_slave_m_araddr + assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; + + // value method to_slave_m_arlen + assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; + + // value method to_slave_m_arsize + assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; + + // value method to_slave_m_arburst + assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; + + // value method to_slave_m_arlock + assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; + + // value method to_slave_m_arcache + assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; + + // value method to_slave_m_arprot + assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; + + // value method to_slave_m_arqos + assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; + + // value method to_slave_m_arregion + assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; + + // action method to_slave_m_arready + assign CAN_FIRE_to_slave_m_arready = 1'd1 ; + assign WILL_FIRE_to_slave_m_arready = 1'd1 ; + + // action method to_slave_m_rvalid + assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; + assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; + + // value method to_slave_m_rready + assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; + + // submodule m_f_r_arlen + SizedFIFO #(.p1width(32'd8), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), + .CLK(CLK), + .D_IN(m_f_r_arlen$D_IN), + .ENQ(m_f_r_arlen$ENQ), + .DEQ(m_f_r_arlen$DEQ), + .CLR(m_f_r_arlen$CLR), + .D_OUT(m_f_r_arlen$D_OUT), + .FULL_N(m_f_r_arlen$FULL_N), + .EMPTY_N(m_f_r_arlen$EMPTY_N)); + + // submodule m_f_w_awlen + SizedFIFO #(.p1width(32'd8), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), + .CLK(CLK), + .D_IN(m_f_w_awlen$D_IN), + .ENQ(m_f_w_awlen$ENQ), + .DEQ(m_f_w_awlen$DEQ), + .CLR(m_f_w_awlen$CLR), + .D_OUT(m_f_w_awlen$D_OUT), + .FULL_N(m_f_w_awlen$FULL_N), + .EMPTY_N(m_f_w_awlen$EMPTY_N)); + + // submodule m_xactor_from_master_f_rd_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_from_master_f_rd_addr$D_IN), + .ENQ(m_xactor_from_master_f_rd_addr$ENQ), + .DEQ(m_xactor_from_master_f_rd_addr$DEQ), + .CLR(m_xactor_from_master_f_rd_addr$CLR), + .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), + .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), + .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); + + // submodule m_xactor_from_master_f_rd_data + FIFO2 #(.width(32'd71), + .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_from_master_f_rd_data$D_IN), + .ENQ(m_xactor_from_master_f_rd_data$ENQ), + .DEQ(m_xactor_from_master_f_rd_data$DEQ), + .CLR(m_xactor_from_master_f_rd_data$CLR), + .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), + .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), + .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); + + // submodule m_xactor_from_master_f_wr_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_from_master_f_wr_addr$D_IN), + .ENQ(m_xactor_from_master_f_wr_addr$ENQ), + .DEQ(m_xactor_from_master_f_wr_addr$DEQ), + .CLR(m_xactor_from_master_f_wr_addr$CLR), + .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), + .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), + .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); + + // submodule m_xactor_from_master_f_wr_data + FIFO2 #(.width(32'd73), + .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_from_master_f_wr_data$D_IN), + .ENQ(m_xactor_from_master_f_wr_data$ENQ), + .DEQ(m_xactor_from_master_f_wr_data$DEQ), + .CLR(m_xactor_from_master_f_wr_data$CLR), + .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), + .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), + .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); + + // submodule m_xactor_from_master_f_wr_resp + FIFO2 #(.width(32'd6), + .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_from_master_f_wr_resp$D_IN), + .ENQ(m_xactor_from_master_f_wr_resp$ENQ), + .DEQ(m_xactor_from_master_f_wr_resp$DEQ), + .CLR(m_xactor_from_master_f_wr_resp$CLR), + .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), + .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), + .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); + + // submodule m_xactor_to_slave_f_rd_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), + .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), + .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), + .CLR(m_xactor_to_slave_f_rd_addr$CLR), + .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), + .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), + .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); + + // submodule m_xactor_to_slave_f_rd_data + FIFO2 #(.width(32'd71), + .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_to_slave_f_rd_data$D_IN), + .ENQ(m_xactor_to_slave_f_rd_data$ENQ), + .DEQ(m_xactor_to_slave_f_rd_data$DEQ), + .CLR(m_xactor_to_slave_f_rd_data$CLR), + .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), + .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), + .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); + + // submodule m_xactor_to_slave_f_wr_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), + .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), + .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), + .CLR(m_xactor_to_slave_f_wr_addr$CLR), + .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), + .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), + .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); + + // submodule m_xactor_to_slave_f_wr_data + FIFO2 #(.width(32'd73), + .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_to_slave_f_wr_data$D_IN), + .ENQ(m_xactor_to_slave_f_wr_data$ENQ), + .DEQ(m_xactor_to_slave_f_wr_data$DEQ), + .CLR(m_xactor_to_slave_f_wr_data$CLR), + .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), + .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), + .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); + + // submodule m_xactor_to_slave_f_wr_resp + FIFO2 #(.width(32'd6), + .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), + .CLK(CLK), + .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), + .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), + .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), + .CLR(m_xactor_to_slave_f_wr_resp$CLR), + .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), + .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), + .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); + + // rule RL_m_rl_wr_xaction_master_to_slave + assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = + m_xactor_to_slave_f_wr_addr$FULL_N && + m_xactor_from_master_f_wr_addr$EMPTY_N && + m_xactor_to_slave_f_wr_data$FULL_N && + m_xactor_from_master_f_wr_data$EMPTY_N && + (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; + assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = + CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; + + // rule RL_m_rl_wr_resp_slave_to_master + assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = + m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && + (m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 || + m_xactor_from_master_f_wr_resp$FULL_N) ; + assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = + CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; + + // rule RL_m_rl_rd_xaction_master_to_slave + assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = + m_xactor_to_slave_f_rd_addr$FULL_N && + m_xactor_from_master_f_rd_addr$EMPTY_N && + (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; + assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = + CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; + + // rule RL_m_rl_rd_resp_slave_to_master + assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = + m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && + m_xactor_from_master_f_rd_data$FULL_N ; + assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = + CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; + + // rule RL_m_rl_reset + assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; + assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; + + // inputs to muxes for submodule ports + assign MUX_m_rg_b_resp$write_1__SEL_2 = + WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && + (m_rg_b_resp == 2'b0 && + m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || + !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50) ; + assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = + m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 ? + x__h3180 : + 8'd0 ; + assign MUX_m_rg_b_beat_count$write_1__VAL_2 = + m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ? + x__h2788 : + 8'd0 ; + assign MUX_m_rg_b_resp$write_1__VAL_2 = + m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ? + m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : + 2'b0 ; + assign MUX_m_rg_r_beat_count$write_1__VAL_2 = + m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 ? + x__h3378 : + 8'd0 ; + assign MUX_m_rg_w_beat_count$write_1__VAL_2 = + m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? + x__h2297 : + 8'd0 ; + + // register m_rg_ar_beat_count + assign m_rg_ar_beat_count$D_IN = + m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; + assign m_rg_ar_beat_count$EN = + WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; + + // register m_rg_b_beat_count + assign m_rg_b_beat_count$D_IN = + m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; + assign m_rg_b_beat_count$EN = + WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; + + // register m_rg_b_resp + assign m_rg_b_resp$D_IN = + m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; + assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; + + // register m_rg_r_beat_count + assign m_rg_r_beat_count$D_IN = + m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; + assign m_rg_r_beat_count$EN = + WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; + + // register m_rg_reset + assign m_rg_reset$D_IN = !m_rg_reset ; + assign m_rg_reset$EN = m_rg_reset || EN_reset ; + + // register m_rg_w_beat_count + assign m_rg_w_beat_count$D_IN = + m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; + assign m_rg_w_beat_count$EN = + WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; + + // submodule m_f_r_arlen + assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; + assign m_f_r_arlen$ENQ = + WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && + m_rg_ar_beat_count == 8'd0 ; + assign m_f_r_arlen$DEQ = + WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && + !m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 ; + assign m_f_r_arlen$CLR = m_rg_reset ; + + // submodule m_f_w_awlen + assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; + assign m_f_w_awlen$ENQ = + WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + m_rg_w_beat_count == 8'd0 ; + assign m_f_w_awlen$DEQ = + WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && + !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ; + assign m_f_w_awlen$CLR = m_rg_reset ; + + // submodule m_xactor_from_master_f_rd_addr + assign m_xactor_from_master_f_rd_addr$D_IN = + { from_master_arid, + from_master_araddr, + from_master_arlen, + from_master_arsize, + from_master_arburst, + from_master_arlock, + from_master_arcache, + from_master_arprot, + from_master_arqos, + from_master_arregion } ; + assign m_xactor_from_master_f_rd_addr$ENQ = + from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; + assign m_xactor_from_master_f_rd_addr$DEQ = + WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && + !m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 ; + assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; + + // submodule m_xactor_from_master_f_rd_data + assign m_xactor_from_master_f_rd_data$D_IN = + { m_xactor_to_slave_f_rd_data$D_OUT[70:1], + !m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 } ; + assign m_xactor_from_master_f_rd_data$ENQ = + CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; + assign m_xactor_from_master_f_rd_data$DEQ = + from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; + assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; + + // submodule m_xactor_from_master_f_wr_addr + assign m_xactor_from_master_f_wr_addr$D_IN = + { from_master_awid, + from_master_awaddr, + from_master_awlen, + from_master_awsize, + from_master_awburst, + from_master_awlock, + from_master_awcache, + from_master_awprot, + from_master_awqos, + from_master_awregion } ; + assign m_xactor_from_master_f_wr_addr$ENQ = + from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; + assign m_xactor_from_master_f_wr_addr$DEQ = + WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; + assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; + + // submodule m_xactor_from_master_f_wr_data + assign m_xactor_from_master_f_wr_data$D_IN = + { from_master_wdata, from_master_wstrb, from_master_wlast } ; + assign m_xactor_from_master_f_wr_data$ENQ = + from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; + assign m_xactor_from_master_f_wr_data$DEQ = + CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; + assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; + + // submodule m_xactor_from_master_f_wr_resp + assign m_xactor_from_master_f_wr_resp$D_IN = + { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], + (m_rg_b_resp == 2'b0) ? + m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : + m_rg_b_resp } ; + assign m_xactor_from_master_f_wr_resp$ENQ = + WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && + !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ; + assign m_xactor_from_master_f_wr_resp$DEQ = + from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; + assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; + + // submodule m_xactor_to_slave_f_rd_addr + assign m_xactor_to_slave_f_rd_addr$D_IN = + { m_xactor_from_master_f_rd_addr$D_OUT[96:93], + a_out_araddr__h2934, + 8'd0, + m_xactor_from_master_f_rd_addr$D_OUT[20:18], + 2'b0, + m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; + assign m_xactor_to_slave_f_rd_addr$ENQ = + CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; + assign m_xactor_to_slave_f_rd_addr$DEQ = + m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; + assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; + + // submodule m_xactor_to_slave_f_rd_data + assign m_xactor_to_slave_f_rd_data$D_IN = + { to_slave_rid, + to_slave_rdata, + to_slave_rresp, + to_slave_rlast } ; + assign m_xactor_to_slave_f_rd_data$ENQ = + to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; + assign m_xactor_to_slave_f_rd_data$DEQ = + CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; + assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; + + // submodule m_xactor_to_slave_f_wr_addr + assign m_xactor_to_slave_f_wr_addr$D_IN = + { m_xactor_from_master_f_wr_addr$D_OUT[96:93], + a_out_awaddr__h1951, + 8'd0, + m_xactor_from_master_f_wr_addr$D_OUT[20:18], + 2'b0, + m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; + assign m_xactor_to_slave_f_wr_addr$ENQ = + CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; + assign m_xactor_to_slave_f_wr_addr$DEQ = + m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; + assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; + + // submodule m_xactor_to_slave_f_wr_data + assign m_xactor_to_slave_f_wr_data$D_IN = + { m_xactor_from_master_f_wr_data$D_OUT[72:1], 1'd1 } ; + assign m_xactor_to_slave_f_wr_data$ENQ = + CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; + assign m_xactor_to_slave_f_wr_data$DEQ = + m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; + assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; + + // submodule m_xactor_to_slave_f_wr_resp + assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; + assign m_xactor_to_slave_f_wr_resp$ENQ = + to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; + assign m_xactor_to_slave_f_wr_resp$DEQ = + CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; + assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; + + // remaining internal signals + assign a_out_araddr__h2934 = + (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? + addr___1__h3019 : + m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; + assign a_out_awaddr__h1951 = + (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? + addr___1__h2036 : + m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; + assign addr___1__h2036 = + m_xactor_from_master_f_wr_addr$D_OUT[92:29] + + ({ 56'd0, m_rg_w_beat_count } << + m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; + assign addr___1__h3019 = + m_xactor_from_master_f_rd_addr$D_OUT[92:29] + + ({ 56'd0, m_rg_ar_beat_count } << + m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; + assign m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 = + m_rg_ar_beat_count < + m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; + assign m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 = + m_rg_b_beat_count < m_f_w_awlen$D_OUT ; + assign m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 = + m_rg_r_beat_count < m_f_r_arlen$D_OUT ; + assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = + m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; + assign x__h2297 = m_rg_w_beat_count + 8'd1 ; + assign x__h2788 = m_rg_b_beat_count + 8'd1 ; + assign x__h3180 = m_rg_ar_beat_count + 8'd1 ; + assign x__h3378 = m_rg_r_beat_count + 8'd1 ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; + m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; + m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; + m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; + m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; + end + else + begin + if (m_rg_ar_beat_count$EN) + m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; + if (m_rg_b_beat_count$EN) + m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; + if (m_rg_b_resp$EN) + m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; + if (m_rg_r_beat_count$EN) + m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; + if (m_rg_reset$EN) + m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; + if (m_rg_w_beat_count$EN) + m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + m_rg_ar_beat_count = 8'hAA; + m_rg_b_beat_count = 8'hAA; + m_rg_b_resp = 2'h2; + m_rg_r_beat_count = 8'hAA; + m_rg_reset = 1'h0; + m_rg_w_beat_count = 8'hAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + begin + v__h2422 = $stime; + #0; + end + v__h2416 = v__h2422 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", + v__h2416); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $display(" WLAST not set on last data beat (awlen = %0d)", + m_xactor_from_master_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && + !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && + !m_xactor_from_master_f_wr_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (m_rg_reset) + begin + v__h1446 = $stime; + #0; + end + v__h1440 = v__h1446 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); + end + // synopsys translate_on +endmodule // mkAXI4_Deburster_A + diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v index e5bc87e..aebf97a 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v @@ -34,7 +34,6 @@ // slave_awqos I 4 reg // slave_awregion I 4 reg // slave_wvalid I 1 -// slave_wid I 4 reg // slave_wdata I 64 reg // slave_wstrb I 8 reg // slave_wlast I 1 reg @@ -93,7 +92,6 @@ module mkBoot_ROM(CLK, slave_awready, slave_wvalid, - slave_wid, slave_wdata, slave_wstrb, slave_wlast, @@ -160,7 +158,6 @@ module mkBoot_ROM(CLK, // action method slave_m_wvalid input slave_wvalid; - input [3 : 0] slave_wid; input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; @@ -269,7 +266,7 @@ module mkBoot_ROM(CLK, slave_xactor_f_wr_addr$FULL_N; // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; + wire [72 : 0] slave_xactor_f_wr_data$D_IN; wire slave_xactor_f_wr_data$CLR, slave_xactor_f_wr_data$DEQ, slave_xactor_f_wr_data$EMPTY_N, @@ -305,13 +302,13 @@ module mkBoot_ROM(CLK, // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; + reg [31 : 0] v__h8925; + reg [31 : 0] v__h9218; + reg [31 : 0] v__h9328; reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; + reg [31 : 0] v__h8919; + reg [31 : 0] v__h9212; + reg [31 : 0] v__h9322; // synopsys translate_on // remaining internal signals @@ -415,7 +412,7 @@ module mkBoot_ROM(CLK, .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), + FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(slave_xactor_f_wr_data$D_IN), .ENQ(slave_xactor_f_wr_data$ENQ), @@ -510,7 +507,7 @@ module mkBoot_ROM(CLK, // submodule slave_xactor_f_wr_data assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; + { slave_wdata, slave_wstrb, slave_wlast } ; assign slave_xactor_f_wr_data$ENQ = slave_wvalid && slave_xactor_f_wr_data$FULL_N ; assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; @@ -2022,15 +2019,15 @@ module mkBoot_ROM(CLK, if (WILL_FIRE_RL_rl_process_wr_req && NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) begin - v__h8928 = $stime; + v__h8925 = $stime; #0; end - v__h8922 = v__h8928 / 32'd10; + v__h8919 = v__h8925 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); + v__h8919); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) @@ -2130,26 +2127,26 @@ module mkBoot_ROM(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) begin - v__h9221 = $stime; + v__h9218 = $stime; #0; end - v__h9215 = v__h9221 / 32'd10; + v__h9212 = v__h9218 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, + v__h9212, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) begin - v__h9331 = $stime; + v__h9328 = $stime; #0; end - v__h9325 = v__h9331 / 32'd10; + v__h9322 = v__h9328 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, + v__h9322, set_addr_map_addr_lim); end // synopsys translate_on diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 7d9cb43..3be4a4e 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -6,8 +6,6 @@ // // Ports: // Name I/O size props -// RDY_init_server_request_put O 1 reg -// RDY_init_server_response_get O 1 reg // RDY_coreReq_start O 1 const // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 @@ -100,12 +98,10 @@ // tlbToMem_respLd_enq_x I 65 // mmioToPlatform_pRs_enq_x I 67 // mmioToPlatform_pRq_enq_x I 39 -// mmioToPlatform_setTime_t I 64 +// mmioToPlatform_setTime_t I 64 reg // recvDoStats_x I 1 reg // setMEIP_v I 1 // setSEIP_v I 1 -// EN_init_server_request_put I 1 -// EN_init_server_response_get I 1 // EN_coreReq_start I 1 // EN_coreReq_perfReq I 1 // EN_coreIndInv_terminate I 1 @@ -158,12 +154,6 @@ module mkCore(CLK, RST_N, - EN_init_server_request_put, - RDY_init_server_request_put, - - EN_init_server_response_get, - RDY_init_server_response_get, - coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -341,14 +331,6 @@ module mkCore(CLK, input CLK; input RST_N; - // action method init_server_request_put - input EN_init_server_request_put; - output RDY_init_server_request_put; - - // action method init_server_response_get - input EN_init_server_response_get; - output RDY_init_server_response_get; - // action method coreReq_start input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; @@ -617,8 +599,6 @@ module mkCore(CLK, RDY_iCacheToParent_rsToP_deq, RDY_iCacheToParent_rsToP_first, RDY_iCacheToParent_rsToP_notEmpty, - RDY_init_server_request_put, - RDY_init_server_response_get, RDY_mmioToPlatform_cRq_deq, RDY_mmioToPlatform_cRq_first, RDY_mmioToPlatform_cRq_notEmpty, @@ -676,6 +656,7 @@ module mkCore(CLK, wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget; wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget, mmio_dataRespQ_enqReq_lat_0$wget; + wire [63 : 0] csrf_mcycle_ehr_data_lat_0$wget; wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget; wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget; wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget; @@ -1243,13 +1224,11 @@ module mkCore(CLK, // register csrf_external_int_pend_vec_1 reg csrf_external_int_pend_vec_1; - reg csrf_external_int_pend_vec_1$D_IN; - wire csrf_external_int_pend_vec_1$EN; + wire csrf_external_int_pend_vec_1$D_IN, csrf_external_int_pend_vec_1$EN; // register csrf_external_int_pend_vec_3 reg csrf_external_int_pend_vec_3; - reg csrf_external_int_pend_vec_3$D_IN; - wire csrf_external_int_pend_vec_3$EN; + wire csrf_external_int_pend_vec_3$D_IN, csrf_external_int_pend_vec_3$EN; // register csrf_fflags_reg reg [4 : 0] csrf_fflags_reg; @@ -1263,7 +1242,7 @@ module mkCore(CLK, // register csrf_fs_reg reg [1 : 0] csrf_fs_reg; - reg [1 : 0] csrf_fs_reg$D_IN; + wire [1 : 0] csrf_fs_reg$D_IN; wire csrf_fs_reg$EN; // register csrf_ie_vec_0 @@ -1349,7 +1328,7 @@ module mkCore(CLK, // register csrf_mpp_reg reg [1 : 0] csrf_mpp_reg; - reg [1 : 0] csrf_mpp_reg$D_IN; + wire [1 : 0] csrf_mpp_reg$D_IN; wire csrf_mpp_reg$EN; // register csrf_mprv_reg @@ -1390,17 +1369,15 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 reg csrf_prev_ie_vec_1; - reg csrf_prev_ie_vec_1$D_IN; - wire csrf_prev_ie_vec_1$EN; + wire csrf_prev_ie_vec_1$D_IN, csrf_prev_ie_vec_1$EN; // register csrf_prev_ie_vec_3 reg csrf_prev_ie_vec_3; - reg csrf_prev_ie_vec_3$D_IN; - wire csrf_prev_ie_vec_3$EN; + wire csrf_prev_ie_vec_3$D_IN, csrf_prev_ie_vec_3$EN; // register csrf_prv_reg reg [1 : 0] csrf_prv_reg; - reg [1 : 0] csrf_prv_reg$D_IN; + wire [1 : 0] csrf_prv_reg$D_IN; wire csrf_prv_reg$EN; // register csrf_scause_code_reg @@ -1451,13 +1428,11 @@ module mkCore(CLK, // register csrf_software_int_pend_vec_3 reg csrf_software_int_pend_vec_3; - reg csrf_software_int_pend_vec_3$D_IN; - wire csrf_software_int_pend_vec_3$EN; + wire csrf_software_int_pend_vec_3$D_IN, csrf_software_int_pend_vec_3$EN; // register csrf_spp_reg reg csrf_spp_reg; - reg csrf_spp_reg$D_IN; - wire csrf_spp_reg$EN; + wire csrf_spp_reg$D_IN, csrf_spp_reg$EN; // register csrf_sscratch_csr reg [63 : 0] csrf_sscratch_csr; @@ -2961,20 +2936,6 @@ module mkCore(CLK, epochManager$checkEpoch_0_check, epochManager$checkEpoch_1_check; - // ports of submodule f_init_reqs - wire f_init_reqs$CLR, - f_init_reqs$DEQ, - f_init_reqs$EMPTY_N, - f_init_reqs$ENQ, - f_init_reqs$FULL_N; - - // ports of submodule f_init_rsps - wire f_init_rsps$CLR, - f_init_rsps$DEQ, - f_init_rsps$EMPTY_N, - f_init_rsps$ENQ, - f_init_rsps$FULL_N; - // ports of submodule fetchStage reg [63 : 0] fetchStage$redirect_pc; wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x; @@ -3690,7 +3651,6 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_SystemInst, CAN_FIRE_RL_renameStage_doRenaming_Trap, CAN_FIRE_RL_renameStage_doRenaming_wrongPath, - CAN_FIRE_RL_rl_init, CAN_FIRE_RL_rl_outOfReset, CAN_FIRE_RL_sendDTlbReq, CAN_FIRE_RL_sendFlushDone, @@ -3717,8 +3677,6 @@ module mkCore(CLK, CAN_FIRE_iCacheToParent_fromP_enq, CAN_FIRE_iCacheToParent_rqToP_deq, CAN_FIRE_iCacheToParent_rsToP_deq, - CAN_FIRE_init_server_request_put, - CAN_FIRE_init_server_response_get, CAN_FIRE_mmioToPlatform_cRq_deq, CAN_FIRE_mmioToPlatform_cRs_deq, CAN_FIRE_mmioToPlatform_pRq_enq, @@ -3905,7 +3863,6 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst, WILL_FIRE_RL_renameStage_doRenaming_Trap, WILL_FIRE_RL_renameStage_doRenaming_wrongPath, - WILL_FIRE_RL_rl_init, WILL_FIRE_RL_rl_outOfReset, WILL_FIRE_RL_sendDTlbReq, WILL_FIRE_RL_sendFlushDone, @@ -3932,8 +3889,6 @@ module mkCore(CLK, WILL_FIRE_iCacheToParent_fromP_enq, WILL_FIRE_iCacheToParent_rqToP_deq, WILL_FIRE_iCacheToParent_rsToP_deq, - WILL_FIRE_init_server_request_put, - WILL_FIRE_init_server_response_get, WILL_FIRE_mmioToPlatform_cRq_deq, WILL_FIRE_mmioToPlatform_cRs_deq, WILL_FIRE_mmioToPlatform_pRq_enq, @@ -3953,7 +3908,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_5; reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1, MUX_coreFix_memExe_lsq$respLd_1__VAL_2; - reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2; + reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_1; wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3, @@ -3994,13 +3949,12 @@ module mkCore(CLK, MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3; wire [63 : 0] MUX_commitStage_rg_serialnum$write_1__VAL_1, MUX_commitStage_rg_serialnum$write_1__VAL_2, - MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_1, + MUX_csrf_mepc_csr$write_1__VAL_2, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2, MUX_csrf_mtval_csr$write_1__VAL_1, MUX_csrf_mtval_csr$write_1__VAL_2, MUX_csrf_sepc_csr$write_1__VAL_2, - MUX_csrf_stval_csr$write_1__VAL_2, MUX_fetchStage$redirect_1__VAL_4, MUX_rf$write_2_wr_2__VAL_2, MUX_rf$write_2_wr_2__VAL_3, @@ -4035,7 +3989,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, @@ -4085,33 +4039,19 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, - MUX_csrf_external_int_en_vec_0$write_1__SEL_1, - MUX_csrf_external_int_en_vec_3$write_1__SEL_1, - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1, + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1, MUX_csrf_external_int_pend_vec_3$write_1__SEL_1, MUX_csrf_fflags_reg$write_1__SEL_1, - MUX_csrf_fflags_reg$write_1__SEL_2, - MUX_csrf_fs_reg$write_1__SEL_2, - MUX_csrf_ie_vec_0$write_1__SEL_1, + MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1, - MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_mprv_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, - MUX_csrf_software_int_pend_vec_3$write_1__SEL_2, MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4155,33 +4095,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - addr__h293729, - curData__h194420, - rVal1__h615015, - rVal1__h639319, - trap_val__h705834, - x__h199463; + addr__h293551, + curData__h194242, + rVal1__h614837, + rVal1__h639141, + trap_val__h705656, + x__h199285; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q209, - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q210, - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q211, - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q212, - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q197, - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q198, - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q199, - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q200, - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q201, - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q202, - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q213, - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q214, - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q215, - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q216, - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q217, - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q218, - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q207, - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q208, + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q207, + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q208, + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q211, + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q212, + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q197, + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q198, + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q201, + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q202, + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q199, + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q200, + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q213, + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q214, + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q215, + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q216, + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q217, + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q218, + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q209, + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q210, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755, @@ -4193,50 +4133,50 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77, - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q78, - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79, - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q80, - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81, - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q82, - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112, - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q113, - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42, - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q43, - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110, - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q111, - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40, - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q41, - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114, - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q115, - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44, - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q45, - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116, - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q117, - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46, - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q47, - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75, - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q76, - _theResult___fst_sfd__h349834, - _theResult___fst_sfd__h358557, - _theResult___fst_sfd__h367139, - _theResult___fst_sfd__h376323, - _theResult___fst_sfd__h384959, - _theResult___fst_sfd__h395533, - _theResult___fst_sfd__h404254, - _theResult___fst_sfd__h412836, - _theResult___fst_sfd__h422020, - _theResult___fst_sfd__h430656, - _theResult___fst_sfd__h441228, - _theResult___fst_sfd__h449949, - _theResult___fst_sfd__h458531, - _theResult___fst_sfd__h467715, - _theResult___fst_sfd__h476351; + reg [22 : 0] CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77, + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q78, + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79, + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q80, + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81, + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q82, + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112, + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q113, + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42, + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q43, + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110, + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q111, + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40, + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q41, + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114, + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q115, + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44, + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q45, + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116, + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q117, + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47, + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q48, + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75, + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q76, + _theResult___fst_sfd__h349656, + _theResult___fst_sfd__h358379, + _theResult___fst_sfd__h366961, + _theResult___fst_sfd__h376145, + _theResult___fst_sfd__h384781, + _theResult___fst_sfd__h395355, + _theResult___fst_sfd__h404076, + _theResult___fst_sfd__h412658, + _theResult___fst_sfd__h421842, + _theResult___fst_sfd__h430478, + _theResult___fst_sfd__h441050, + _theResult___fst_sfd__h449771, + _theResult___fst_sfd__h458353, + _theResult___fst_sfd__h467537, + _theResult___fst_sfd__h476173; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q220, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q223, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280, @@ -4245,34 +4185,34 @@ module mkCore(CLK, reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q221, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q224, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, IF_fetchStage_pipelines_0_first__2863_BITS_172_ETC___d13055; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q203, - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q204, - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q205, - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q206, - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q175, - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q176, - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q179, - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q180, - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q177, - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q178, - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q152, - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q153, - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q181, - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q182, - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q183, - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q184, - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q135, - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q136, + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q203, + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q204, + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q205, + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q206, + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q175, + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q176, + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q177, + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q178, + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q179, + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q180, + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q152, + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q153, + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q181, + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q182, + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q183, + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q184, + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q135, + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684, @@ -4282,47 +4222,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914; - reg [7 : 0] CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60, - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q61, - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68, - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q69, - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73, - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q74, - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97, - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q98, - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27, - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q28, - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95, - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q96, - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25, - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q26, - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103, - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q104, - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33, - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q34, - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108, - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q109, - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38, - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q39, - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62, - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q63, + reg [7 : 0] CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60, + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q61, + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68, + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q69, + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73, + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q74, + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97, + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q98, + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27, + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q28, + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95, + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q96, + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25, + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q26, + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103, + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q104, + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33, + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q34, + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108, + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q109, + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38, + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q39, + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62, + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q63, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h349833, - _theResult___fst_exp__h358556, - _theResult___fst_exp__h367138, - _theResult___fst_exp__h376322, - _theResult___fst_exp__h384958, - _theResult___fst_exp__h395532, - _theResult___fst_exp__h404253, - _theResult___fst_exp__h412835, - _theResult___fst_exp__h422019, - _theResult___fst_exp__h430655, - _theResult___fst_exp__h441227, - _theResult___fst_exp__h449948, - _theResult___fst_exp__h458530, - _theResult___fst_exp__h467714, - _theResult___fst_exp__h476350; + _theResult___fst_exp__h349655, + _theResult___fst_exp__h358378, + _theResult___fst_exp__h366960, + _theResult___fst_exp__h376144, + _theResult___fst_exp__h384780, + _theResult___fst_exp__h395354, + _theResult___fst_exp__h404075, + _theResult___fst_exp__h412657, + _theResult___fst_exp__h421841, + _theResult___fst_exp__h430477, + _theResult___fst_exp__h441049, + _theResult___fst_exp__h449770, + _theResult___fst_exp__h458352, + _theResult___fst_exp__h467536, + _theResult___fst_exp__h476172; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, @@ -4340,13 +4280,13 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133, IF_fetchStage_pipelines_0_first__2863_BIT_68_2_ETC___d13193, IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293, - i__h704826, - i__h704986; + i__h704648, + i__h704808; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q219, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q222, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, @@ -4355,8 +4295,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, - x__h289508, - x__h295278; + x__h289330, + x__h295100; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -4388,46 +4328,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard04267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, - CASE_guard04267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_guard07381_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard13197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, - CASE_guard13197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, - CASE_guard16450_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard22033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, - CASE_guard22033_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard36922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard36922_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard41255_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, - CASE_guard41255_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, - CASE_guard46234_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard46234_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard49861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48, - CASE_guard49861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49, - CASE_guard49962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard49962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, - CASE_guard55303_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard55303_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard58570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, - CASE_guard58570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard58892_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, - CASE_guard58892_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard67500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard67500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard67728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard67728_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, - CASE_guard76226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard76226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard76336_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard76336_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, - CASE_guard85538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard85538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard94607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard94607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard95560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard95560_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, - CASE_guard98069_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k71653_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard04089_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, + CASE_guard04089_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, + CASE_guard07203_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard13019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, + CASE_guard13019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, + CASE_guard16272_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard21855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, + CASE_guard21855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard36744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard36744_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard41077_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard41077_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard46056_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard46056_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard49683_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard49683_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46, + CASE_guard49784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, + CASE_guard49784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard58392_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, + CASE_guard58392_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, + CASE_guard58714_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, + CASE_guard58714_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, + CASE_guard67322_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard67322_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard67550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard67550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard76048_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard76048_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard76158_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, + CASE_guard76158_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, + CASE_guard85360_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard85360_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard94429_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard94429_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard95382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, + CASE_guard95382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, + CASE_guard97891_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_k71475_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4498,21 +4438,21 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15193; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15190; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15184; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15181; wire [321 : 0] basicExec___d12068, basicExec___d12710; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15175, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15172, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; - wire [127 : 0] b__h607636, b__h607712, b__h607813, b__h607825, x__h608665; + wire [127 : 0] b__h607458, b__h607534, b__h607635, b__h607647, x__h608487; wire [68 : 0] execFpuSimple___d11167; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598; @@ -4547,163 +4487,161 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987, - _theResult___fst__h608036, - _theResult___snd__h608037, - a___1__h607650, - a___1__h608041, - a__h607488, + _theResult___fst__h607858, + _theResult___snd__h607859, + a___1__h607472, + a___1__h607863, + a__h607310, amoExec___d882, - b___1__h607651, - b___1__h608102, - b__h607489, - base__h707397, - base__h707600, + b___1__h607473, + b___1__h607924, + b__h607311, + base__h707219, + base__h707422, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, - data___1__h478889, - data___1__h479821, - data__h478377, - data__h479309, - fallthrough_pc__h668013, - fallthrough_pc__h683505, - fcsr_csr__read__h615293, - fflags_csr__read__h615268, - frm_csr__read__h615279, - mcause_csr__read__h616933, - mcounteren_csr__read__h616678, - medeleg_csr__read__h616285, - mideleg_csr__read__h616380, - mie_csr__read__h616504, - mip_csr__read__h617166, - mstatus_csr__read__h616137, - mtvec_csr__read__h616586, - n___1__h200866, - n__h195958, - n__read__h617270, - n__read__h617461, - n__read__h6352, - n__read__h716179, - next_pc__h715420, - q___1__h479896, - rVal1__h486258, - rVal2__h486259, - r___1__h479923, - res_data__h341635, - res_data__h341640, - res_data__h387337, - res_data__h387342, - res_data__h433032, - res_data__h433037, - resp_addr__h295744, + data___1__h478711, + data___1__h479643, + data__h478199, + data__h479131, + fallthrough_pc__h667835, + fallthrough_pc__h683327, + fcsr_csr__read__h615115, + fflags_csr__read__h615090, + frm_csr__read__h615101, + mcause_csr__read__h616755, + mcounteren_csr__read__h616500, + medeleg_csr__read__h616107, + mideleg_csr__read__h616202, + mie_csr__read__h616326, + mip_csr__read__h616988, + mstatus_csr__read__h615959, + mtvec_csr__read__h616408, + n___1__h200688, + n__h195780, + n__read__h617092, + n__read__h617283, + n__read__h6174, + n__read__h716001, + next_pc__h715242, + q___1__h479718, + rVal1__h486080, + rVal2__h486081, + r___1__h479745, + res_data__h341457, + res_data__h341462, + res_data__h387159, + res_data__h387164, + res_data__h432854, + res_data__h432859, + resp_addr__h295566, rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846, robdeqPort_0_deq_data_BITS_95_TO_32__q262, - satp_csr__read__h615994, - scause_csr__read__h615792, - scounteren_csr__read__h615654, - shiftData__h184726, - sie_csr__read__h615558, - sip_csr__read__h615931, - sstatus_csr__read__h615489, - stvec_csr__read__h615601, - upd__h3857, - upd__h5174, - upd__h6466, - upd__h716290, - v__h613787, - v__h638244, - vaddr__h184721, - x__h155079, - x__h158626, - x__h161440, - x__h163288, - x__h17914, - x__h184633, - x__h184634, - x__h20452, - x__h290953, - x__h292807, - x__h45821, - x__h48357, - x__h486164, - x__h486165, - x__h486166, - x__h608025, - x__h622251, - x__h622252, - x__h644281, - x__h644282, - x__h701147, - x_addr__h317841, - x_quotient__h479073, - x_reg_ifc__read__h615398, - x_remainder__h479074, - y__h625021, - y__h646758, - y__h719350, - y_avValue__h183761, - y_avValue__h184480, - y_avValue__h483227, - y_avValue__h483948, - y_avValue__h484663, - y_avValue__h614958, - y_avValue__h620293, - y_avValue__h639264, - y_avValue__h642333, - y_avValue__h705681, - y_avValue__h707434, - y_avValue_snd_snd_snd_snd_snd__h718758, - y_avValue_snd_snd_snd_snd_snd__h719403, - y_avValue_snd_snd_snd_snd_snd__h719432; + satp_csr__read__h615816, + scause_csr__read__h615614, + scounteren_csr__read__h615476, + shiftData__h184548, + sie_csr__read__h615380, + sip_csr__read__h615753, + sstatus_csr__read__h615311, + stvec_csr__read__h615423, + upd__h3679, + upd__h4996, + v__h613609, + v__h638066, + vaddr__h184543, + x__h154900, + x__h158447, + x__h161261, + x__h163109, + x__h17735, + x__h184455, + x__h184456, + x__h20273, + x__h290775, + x__h292629, + x__h45642, + x__h48178, + x__h485986, + x__h485987, + x__h485988, + x__h607847, + x__h622073, + x__h622074, + x__h644103, + x__h644104, + x__h700969, + x_addr__h317663, + x_quotient__h478895, + x_reg_ifc__read__h615220, + x_remainder__h478896, + y__h624843, + y__h646580, + y__h719172, + y_avValue__h183583, + y_avValue__h184302, + y_avValue__h483049, + y_avValue__h483770, + y_avValue__h484485, + y_avValue__h614780, + y_avValue__h620115, + y_avValue__h639086, + y_avValue__h642155, + y_avValue__h705503, + y_avValue__h707256, + y_avValue_snd_snd_snd_snd_snd__h718580, + y_avValue_snd_snd_snd_snd_snd__h719225, + y_avValue_snd_snd_snd_snd_snd__h719254; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, - r1__read__h617968, - r1__read__h618372, - r1__read__h618902, - r1__read__h618907, - r1__read__h618926, - r1__read__h619179, - r1__read__h619345, - r1__read__h619456, - r1__read__h619461, - r1__read__h619480; - wire [61 : 0] r1__read__h617970, - r1__read__h618374, - r1__read__h618909, - r1__read__h618928, - r1__read__h619181, - r1__read__h619321, - r1__read__h619347, - r1__read__h619463, - r1__read__h619482; - wire [60 : 0] r1__read__h619183, - r1__read__h619323, - r1__read__h619349, - r1__read__h619484; - wire [59 : 0] r1__read__h617972, - r1__read__h618376, - r1__read__h618920, - r1__read__h618930, - r1__read__h619185, - r1__read__h619351, - r1__read__h619474, - r1__read__h619486; - wire [58 : 0] r1__read__h617974, - r1__read__h618378, - r1__read__h618932, - r1__read__h619187, - r1__read__h619353, - r1__read__h619488; + r1__read__h617790, + r1__read__h618194, + r1__read__h618724, + r1__read__h618729, + r1__read__h618748, + r1__read__h619001, + r1__read__h619167, + r1__read__h619278, + r1__read__h619283, + r1__read__h619302; + wire [61 : 0] r1__read__h617792, + r1__read__h618196, + r1__read__h618731, + r1__read__h618750, + r1__read__h619003, + r1__read__h619143, + r1__read__h619169, + r1__read__h619285, + r1__read__h619304; + wire [60 : 0] r1__read__h619005, + r1__read__h619145, + r1__read__h619171, + r1__read__h619306; + wire [59 : 0] r1__read__h617794, + r1__read__h618198, + r1__read__h618742, + r1__read__h618752, + r1__read__h619007, + r1__read__h619173, + r1__read__h619296, + r1__read__h619308; + wire [58 : 0] r1__read__h617796, + r1__read__h618200, + r1__read__h618754, + r1__read__h619009, + r1__read__h619175, + r1__read__h619310; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, - r1__read__h617976, - r1__read__h618380, - r1__read__h618934, - r1__read__h619189, - r1__read__h619325, - r1__read__h619355, - r1__read__h619490, - y__h257551; + r1__read__h617798, + r1__read__h618202, + r1__read__h618756, + r1__read__h619011, + r1__read__h619147, + r1__read__h619177, + r1__read__h619312, + y__h257373; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, @@ -4731,187 +4669,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438, - _theResult____h349851, - _theResult____h367490, - _theResult____h395550, - _theResult____h413187, - _theResult____h441245, - _theResult____h458882, - _theResult____h507371, - _theResult____h546224, - _theResult____h585528, - _theResult___snd__h357973, - _theResult___snd__h357984, - _theResult___snd__h357986, - _theResult___snd__h357996, - _theResult___snd__h358002, - _theResult___snd__h358025, - _theResult___snd__h366569, - _theResult___snd__h366571, - _theResult___snd__h366578, - _theResult___snd__h366584, - _theResult___snd__h366607, - _theResult___snd__h375739, - _theResult___snd__h375750, - _theResult___snd__h375752, - _theResult___snd__h375762, - _theResult___snd__h375768, - _theResult___snd__h375791, - _theResult___snd__h384359, - _theResult___snd__h384373, - _theResult___snd__h384379, - _theResult___snd__h384397, - _theResult___snd__h403670, - _theResult___snd__h403681, - _theResult___snd__h403683, - _theResult___snd__h403693, - _theResult___snd__h403699, - _theResult___snd__h403722, - _theResult___snd__h412266, - _theResult___snd__h412268, - _theResult___snd__h412275, - _theResult___snd__h412281, - _theResult___snd__h412304, - _theResult___snd__h421436, - _theResult___snd__h421447, - _theResult___snd__h421449, - _theResult___snd__h421459, - _theResult___snd__h421465, - _theResult___snd__h421488, - _theResult___snd__h430056, - _theResult___snd__h430070, - _theResult___snd__h430076, - _theResult___snd__h430094, - _theResult___snd__h449365, - _theResult___snd__h449376, - _theResult___snd__h449378, - _theResult___snd__h449388, - _theResult___snd__h449394, - _theResult___snd__h449417, - _theResult___snd__h457961, - _theResult___snd__h457963, - _theResult___snd__h457970, - _theResult___snd__h457976, - _theResult___snd__h457999, - _theResult___snd__h467131, - _theResult___snd__h467142, - _theResult___snd__h467144, - _theResult___snd__h467154, - _theResult___snd__h467160, - _theResult___snd__h467183, - _theResult___snd__h475751, - _theResult___snd__h475765, - _theResult___snd__h475771, - _theResult___snd__h475789, - _theResult___snd__h505981, - _theResult___snd__h505983, - _theResult___snd__h505990, - _theResult___snd__h505996, - _theResult___snd__h506019, - _theResult___snd__h515618, - _theResult___snd__h515629, - _theResult___snd__h515631, - _theResult___snd__h515641, - _theResult___snd__h515647, - _theResult___snd__h515670, - _theResult___snd__h524386, - _theResult___snd__h524400, - _theResult___snd__h524406, - _theResult___snd__h524424, - _theResult___snd__h544834, - _theResult___snd__h544836, - _theResult___snd__h544843, - _theResult___snd__h544849, - _theResult___snd__h544872, - _theResult___snd__h554471, - _theResult___snd__h554482, - _theResult___snd__h554484, - _theResult___snd__h554494, - _theResult___snd__h554500, - _theResult___snd__h554523, - _theResult___snd__h563239, - _theResult___snd__h563253, - _theResult___snd__h563259, - _theResult___snd__h563277, - _theResult___snd__h584138, - _theResult___snd__h584140, - _theResult___snd__h584147, - _theResult___snd__h584153, - _theResult___snd__h584176, - _theResult___snd__h593775, - _theResult___snd__h593786, - _theResult___snd__h593788, - _theResult___snd__h593798, - _theResult___snd__h593804, - _theResult___snd__h593827, - _theResult___snd__h602543, - _theResult___snd__h602557, - _theResult___snd__h602563, - _theResult___snd__h602581, - r1__read__h619191, - r1__read__h619327, - r1__read__h619357, - r1__read__h619492, - result__h368103, - result__h413800, - result__h459495, - result__h507984, - result__h546837, - result__h586141, - sfd__h342246, - sfd__h387948, - sfd__h433643, - sfd__h487004, - sfd__h525998, - sfd__h565302, - sfdin__h357956, - sfdin__h375722, - sfdin__h403653, - sfdin__h421419, - sfdin__h449348, - sfdin__h467114, - sfdin__h515601, - sfdin__h554454, - sfdin__h593758, - x__h368200, - x__h413897, - x__h459592, - x__h508079, - x__h546932, - x__h586236; - wire [55 : 0] r1__read__h617978, - r1__read__h618382, - r1__read__h618936, - r1__read__h619193, - r1__read__h619359, - r1__read__h619494; - wire [54 : 0] r1__read__h617980, - r1__read__h618384, - r1__read__h618938, - r1__read__h619195, - r1__read__h619361, - r1__read__h619496; - wire [53 : 0] r1__read__h619304, - r1__read__h619329, - r1__read__h619363, - r1__read__h619498, - sfd__h506048, - sfd__h515699, - sfd__h524459, - sfd__h544901, - sfd__h554552, - sfd__h563312, - sfd__h584205, - sfd__h593856, - sfd__h602616, - value__h350473, - value__h396170, - value__h441865; - wire [52 : 0] r1__read__h619197, - r1__read__h619306, - r1__read__h619331, - r1__read__h619365, - r1__read__h619500; + _theResult____h349673, + _theResult____h367312, + _theResult____h395372, + _theResult____h413009, + _theResult____h441067, + _theResult____h458704, + _theResult____h507193, + _theResult____h546046, + _theResult____h585350, + _theResult___snd__h357795, + _theResult___snd__h357806, + _theResult___snd__h357808, + _theResult___snd__h357818, + _theResult___snd__h357824, + _theResult___snd__h357847, + _theResult___snd__h366391, + _theResult___snd__h366393, + _theResult___snd__h366400, + _theResult___snd__h366406, + _theResult___snd__h366429, + _theResult___snd__h375561, + _theResult___snd__h375572, + _theResult___snd__h375574, + _theResult___snd__h375584, + _theResult___snd__h375590, + _theResult___snd__h375613, + _theResult___snd__h384181, + _theResult___snd__h384195, + _theResult___snd__h384201, + _theResult___snd__h384219, + _theResult___snd__h403492, + _theResult___snd__h403503, + _theResult___snd__h403505, + _theResult___snd__h403515, + _theResult___snd__h403521, + _theResult___snd__h403544, + _theResult___snd__h412088, + _theResult___snd__h412090, + _theResult___snd__h412097, + _theResult___snd__h412103, + _theResult___snd__h412126, + _theResult___snd__h421258, + _theResult___snd__h421269, + _theResult___snd__h421271, + _theResult___snd__h421281, + _theResult___snd__h421287, + _theResult___snd__h421310, + _theResult___snd__h429878, + _theResult___snd__h429892, + _theResult___snd__h429898, + _theResult___snd__h429916, + _theResult___snd__h449187, + _theResult___snd__h449198, + _theResult___snd__h449200, + _theResult___snd__h449210, + _theResult___snd__h449216, + _theResult___snd__h449239, + _theResult___snd__h457783, + _theResult___snd__h457785, + _theResult___snd__h457792, + _theResult___snd__h457798, + _theResult___snd__h457821, + _theResult___snd__h466953, + _theResult___snd__h466964, + _theResult___snd__h466966, + _theResult___snd__h466976, + _theResult___snd__h466982, + _theResult___snd__h467005, + _theResult___snd__h475573, + _theResult___snd__h475587, + _theResult___snd__h475593, + _theResult___snd__h475611, + _theResult___snd__h505803, + _theResult___snd__h505805, + _theResult___snd__h505812, + _theResult___snd__h505818, + _theResult___snd__h505841, + _theResult___snd__h515440, + _theResult___snd__h515451, + _theResult___snd__h515453, + _theResult___snd__h515463, + _theResult___snd__h515469, + _theResult___snd__h515492, + _theResult___snd__h524208, + _theResult___snd__h524222, + _theResult___snd__h524228, + _theResult___snd__h524246, + _theResult___snd__h544656, + _theResult___snd__h544658, + _theResult___snd__h544665, + _theResult___snd__h544671, + _theResult___snd__h544694, + _theResult___snd__h554293, + _theResult___snd__h554304, + _theResult___snd__h554306, + _theResult___snd__h554316, + _theResult___snd__h554322, + _theResult___snd__h554345, + _theResult___snd__h563061, + _theResult___snd__h563075, + _theResult___snd__h563081, + _theResult___snd__h563099, + _theResult___snd__h583960, + _theResult___snd__h583962, + _theResult___snd__h583969, + _theResult___snd__h583975, + _theResult___snd__h583998, + _theResult___snd__h593597, + _theResult___snd__h593608, + _theResult___snd__h593610, + _theResult___snd__h593620, + _theResult___snd__h593626, + _theResult___snd__h593649, + _theResult___snd__h602365, + _theResult___snd__h602379, + _theResult___snd__h602385, + _theResult___snd__h602403, + r1__read__h619013, + r1__read__h619149, + r1__read__h619179, + r1__read__h619314, + result__h367925, + result__h413622, + result__h459317, + result__h507806, + result__h546659, + result__h585963, + sfd__h342068, + sfd__h387770, + sfd__h433465, + sfd__h486826, + sfd__h525820, + sfd__h565124, + sfdin__h357778, + sfdin__h375544, + sfdin__h403475, + sfdin__h421241, + sfdin__h449170, + sfdin__h466936, + sfdin__h515423, + sfdin__h554276, + sfdin__h593580, + x__h368022, + x__h413719, + x__h459414, + x__h507901, + x__h546754, + x__h586058; + wire [55 : 0] r1__read__h617800, + r1__read__h618204, + r1__read__h618758, + r1__read__h619015, + r1__read__h619181, + r1__read__h619316; + wire [54 : 0] r1__read__h617802, + r1__read__h618206, + r1__read__h618760, + r1__read__h619017, + r1__read__h619183, + r1__read__h619318; + wire [53 : 0] r1__read__h619126, + r1__read__h619151, + r1__read__h619185, + r1__read__h619320, + sfd__h505870, + sfd__h515521, + sfd__h524281, + sfd__h544723, + sfd__h554374, + sfd__h563134, + sfd__h584027, + sfd__h593678, + sfd__h602438, + value__h350295, + value__h395992, + value__h441687; + wire [52 : 0] r1__read__h619019, + r1__read__h619128, + r1__read__h619153, + r1__read__h619187, + r1__read__h619322; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251, @@ -4933,109 +4871,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992, - _theResult___fst_sfd__h490958, - _theResult___fst_sfd__h506786, - _theResult___fst_sfd__h506789, - _theResult___fst_sfd__h516437, - _theResult___fst_sfd__h516440, - _theResult___fst_sfd__h525221, - _theResult___fst_sfd__h525224, - _theResult___fst_sfd__h525233, - _theResult___fst_sfd__h525239, - _theResult___fst_sfd__h529811, - _theResult___fst_sfd__h545639, - _theResult___fst_sfd__h545642, - _theResult___fst_sfd__h555290, - _theResult___fst_sfd__h555293, - _theResult___fst_sfd__h564074, - _theResult___fst_sfd__h564077, - _theResult___fst_sfd__h564086, - _theResult___fst_sfd__h564092, - _theResult___fst_sfd__h569115, - _theResult___fst_sfd__h584943, - _theResult___fst_sfd__h584946, - _theResult___fst_sfd__h594594, - _theResult___fst_sfd__h594597, - _theResult___fst_sfd__h603378, - _theResult___fst_sfd__h603381, - _theResult___fst_sfd__h603390, - _theResult___fst_sfd__h603396, - _theResult___sfd__h506686, - _theResult___sfd__h516337, - _theResult___sfd__h525121, - _theResult___sfd__h545539, - _theResult___sfd__h555190, - _theResult___sfd__h563974, - _theResult___sfd__h584843, - _theResult___sfd__h594494, - _theResult___sfd__h603278, - _theResult___snd_fst_sfd__h486958, - _theResult___snd_fst_sfd__h506792, - _theResult___snd_fst_sfd__h525227, - _theResult___snd_fst_sfd__h525952, - _theResult___snd_fst_sfd__h545645, - _theResult___snd_fst_sfd__h564080, - _theResult___snd_fst_sfd__h565256, - _theResult___snd_fst_sfd__h584949, - _theResult___snd_fst_sfd__h603384, - out___1_sfd__h486706, - out___1_sfd__h525700, - out___1_sfd__h565004, - out_sfd__h506689, - out_sfd__h516340, - out_sfd__h525124, - out_sfd__h545542, - out_sfd__h555193, - out_sfd__h563977, - out_sfd__h584846, - out_sfd__h594497, - out_sfd__h603281; - wire [50 : 0] r1__read__h617982, r1__read__h619199; - wire [49 : 0] r1__read__h619308; - wire [48 : 0] r1__read__h617984, r1__read__h619201, r1__read__h619310; - wire [46 : 0] r1__read__h617986, r1__read__h619203; - wire [45 : 0] r1__read__h617988, r1__read__h619205; - wire [44 : 0] r1__read__h617990, r1__read__h619207; - wire [43 : 0] r1__read__h617992, r1__read__h619209; - wire [42 : 0] r1__read__h619211; - wire [41 : 0] r1__read__h619213; - wire [40 : 0] r1__read__h619215; + _theResult___fst_sfd__h490780, + _theResult___fst_sfd__h506608, + _theResult___fst_sfd__h506611, + _theResult___fst_sfd__h516259, + _theResult___fst_sfd__h516262, + _theResult___fst_sfd__h525043, + _theResult___fst_sfd__h525046, + _theResult___fst_sfd__h525055, + _theResult___fst_sfd__h525061, + _theResult___fst_sfd__h529633, + _theResult___fst_sfd__h545461, + _theResult___fst_sfd__h545464, + _theResult___fst_sfd__h555112, + _theResult___fst_sfd__h555115, + _theResult___fst_sfd__h563896, + _theResult___fst_sfd__h563899, + _theResult___fst_sfd__h563908, + _theResult___fst_sfd__h563914, + _theResult___fst_sfd__h568937, + _theResult___fst_sfd__h584765, + _theResult___fst_sfd__h584768, + _theResult___fst_sfd__h594416, + _theResult___fst_sfd__h594419, + _theResult___fst_sfd__h603200, + _theResult___fst_sfd__h603203, + _theResult___fst_sfd__h603212, + _theResult___fst_sfd__h603218, + _theResult___sfd__h506508, + _theResult___sfd__h516159, + _theResult___sfd__h524943, + _theResult___sfd__h545361, + _theResult___sfd__h555012, + _theResult___sfd__h563796, + _theResult___sfd__h584665, + _theResult___sfd__h594316, + _theResult___sfd__h603100, + _theResult___snd_fst_sfd__h486780, + _theResult___snd_fst_sfd__h506614, + _theResult___snd_fst_sfd__h525049, + _theResult___snd_fst_sfd__h525774, + _theResult___snd_fst_sfd__h545467, + _theResult___snd_fst_sfd__h563902, + _theResult___snd_fst_sfd__h565078, + _theResult___snd_fst_sfd__h584771, + _theResult___snd_fst_sfd__h603206, + out___1_sfd__h486528, + out___1_sfd__h525522, + out___1_sfd__h564826, + out_sfd__h506511, + out_sfd__h516162, + out_sfd__h524946, + out_sfd__h545364, + out_sfd__h555015, + out_sfd__h563799, + out_sfd__h584668, + out_sfd__h594319, + out_sfd__h603103; + wire [50 : 0] r1__read__h617804, r1__read__h619021; + wire [49 : 0] r1__read__h619130; + wire [48 : 0] r1__read__h617806, r1__read__h619023, r1__read__h619132; + wire [46 : 0] r1__read__h617808, r1__read__h619025; + wire [45 : 0] r1__read__h617810, r1__read__h619027; + wire [44 : 0] r1__read__h617812, r1__read__h619029; + wire [43 : 0] r1__read__h617814, r1__read__h619031; + wire [42 : 0] r1__read__h619033; + wire [41 : 0] r1__read__h619035; + wire [40 : 0] r1__read__h619037; wire [37 : 0] IF_fetchStage_pipelines_0_first__2863_BIT_160__ETC___d14136, IF_fetchStage_pipelines_1_first__2872_BIT_160__ETC___d14296; - wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, + wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q4, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, - data78377_BITS_31_TO_0__q2, - data79309_BITS_31_TO_0__q7, - imm__h659779, - r1__read__h617994, - r1__read__h619217, - x__h195183, - x__h341650, - x__h387352, - x__h433047, - x__h75766, - x_data__h65615, - x_data_imm__h678934, - x_data_imm__h694584; - wire [29 : 0] r1__read__h617996, r1__read__h619219; - wire [27 : 0] r1__read__h619221; + data78199_BITS_31_TO_0__q2, + data79131_BITS_31_TO_0__q6, + imm__h659601, + r1__read__h617816, + r1__read__h619039, + x__h195005, + x__h341472, + x__h387174, + x__h432869, + x__h75587, + x_data__h65436, + x_data_imm__h678756, + x_data_imm__h694406; + wire [29 : 0] r1__read__h617818, r1__read__h619041; + wire [27 : 0] r1__read__h619043; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d14182, - sfd__h358054, - sfd__h366636, - sfd__h375820, - sfd__h384432, - sfd__h403751, - sfd__h412333, - sfd__h421517, - sfd__h430129, - sfd__h449446, - sfd__h458028, - sfd__h467212, - sfd__h475824, - value__h491587, - value__h530440, - value__h569744; + sfd__h357876, + sfd__h366458, + sfd__h375642, + sfd__h384254, + sfd__h403573, + sfd__h412155, + sfd__h421339, + sfd__h429951, + sfd__h449268, + sfd__h457850, + sfd__h467034, + sfd__h475646, + value__h491409, + value__h530262, + value__h569566; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445, @@ -5060,67 +4998,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904, - _theResult___fst_sfd__h358560, - _theResult___fst_sfd__h367142, - _theResult___fst_sfd__h376326, - _theResult___fst_sfd__h384962, - _theResult___fst_sfd__h384971, - _theResult___fst_sfd__h384977, - _theResult___fst_sfd__h404257, - _theResult___fst_sfd__h412839, - _theResult___fst_sfd__h422023, - _theResult___fst_sfd__h430659, - _theResult___fst_sfd__h430668, - _theResult___fst_sfd__h430674, - _theResult___fst_sfd__h449952, - _theResult___fst_sfd__h458534, - _theResult___fst_sfd__h467718, - _theResult___fst_sfd__h476354, - _theResult___fst_sfd__h476363, - _theResult___fst_sfd__h476369, - _theResult___sfd__h358479, - _theResult___sfd__h367061, - _theResult___sfd__h376245, - _theResult___sfd__h384881, - _theResult___sfd__h384983, - _theResult___sfd__h404176, - _theResult___sfd__h412758, - _theResult___sfd__h421942, - _theResult___sfd__h430578, - _theResult___sfd__h430680, - _theResult___sfd__h449871, - _theResult___sfd__h458453, - _theResult___sfd__h467637, - _theResult___sfd__h476273, - _theResult___sfd__h476375, - _theResult___snd_fst_sfd__h342196, - _theResult___snd_fst_sfd__h367145, - _theResult___snd_fst_sfd__h384965, - _theResult___snd_fst_sfd__h387898, - _theResult___snd_fst_sfd__h412842, - _theResult___snd_fst_sfd__h430662, - _theResult___snd_fst_sfd__h433593, - _theResult___snd_fst_sfd__h458537, - _theResult___snd_fst_sfd__h476357, - f1_sfd__h486643, - f2_sfd__h525637, - f3_sfd__h564941, - out_f_sfd__h385260, - out_f_sfd__h430957, - out_f_sfd__h476652, - out_sfd__h358482, - out_sfd__h367064, - out_sfd__h376248, - out_sfd__h384884, - out_sfd__h404179, - out_sfd__h412761, - out_sfd__h421945, - out_sfd__h430581, - out_sfd__h449874, - out_sfd__h458456, - out_sfd__h467640, - out_sfd__h476276; - wire [19 : 0] r1__read__h619156; + _theResult___fst_sfd__h358382, + _theResult___fst_sfd__h366964, + _theResult___fst_sfd__h376148, + _theResult___fst_sfd__h384784, + _theResult___fst_sfd__h384793, + _theResult___fst_sfd__h384799, + _theResult___fst_sfd__h404079, + _theResult___fst_sfd__h412661, + _theResult___fst_sfd__h421845, + _theResult___fst_sfd__h430481, + _theResult___fst_sfd__h430490, + _theResult___fst_sfd__h430496, + _theResult___fst_sfd__h449774, + _theResult___fst_sfd__h458356, + _theResult___fst_sfd__h467540, + _theResult___fst_sfd__h476176, + _theResult___fst_sfd__h476185, + _theResult___fst_sfd__h476191, + _theResult___sfd__h358301, + _theResult___sfd__h366883, + _theResult___sfd__h376067, + _theResult___sfd__h384703, + _theResult___sfd__h384805, + _theResult___sfd__h403998, + _theResult___sfd__h412580, + _theResult___sfd__h421764, + _theResult___sfd__h430400, + _theResult___sfd__h430502, + _theResult___sfd__h449693, + _theResult___sfd__h458275, + _theResult___sfd__h467459, + _theResult___sfd__h476095, + _theResult___sfd__h476197, + _theResult___snd_fst_sfd__h342018, + _theResult___snd_fst_sfd__h366967, + _theResult___snd_fst_sfd__h384787, + _theResult___snd_fst_sfd__h387720, + _theResult___snd_fst_sfd__h412664, + _theResult___snd_fst_sfd__h430484, + _theResult___snd_fst_sfd__h433415, + _theResult___snd_fst_sfd__h458359, + _theResult___snd_fst_sfd__h476179, + f1_sfd__h486465, + f2_sfd__h525459, + f3_sfd__h564763, + out_f_sfd__h385082, + out_f_sfd__h430779, + out_f_sfd__h476474, + out_sfd__h358304, + out_sfd__h366886, + out_sfd__h376070, + out_sfd__h384706, + out_sfd__h404001, + out_sfd__h412583, + out_sfd__h421767, + out_sfd__h430403, + out_sfd__h449696, + out_sfd__h458278, + out_sfd__h467462, + out_sfd__h476098; + wire [19 : 0] r1__read__h618978; wire [12 : 0] fetchStage_pipelines_1_first__2872_BIT_173_361_ETC___d13685; wire [11 : 0] IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542, @@ -5152,29 +5090,29 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434, - _theResult____h655999, - enabled_ints___1__h656412, - enabled_ints__h656459, - pend_ints__h655997, - renaming_spec_bits__h686863, - result__h651706, - result__h651757, - spec_bits__h689958, - w__h651701, - x__h368233, - x__h413930, - x__h459625, - x__h508112, - x__h546965, - x__h586269, - x__h651705, - x__h651756, - y__h651735, - y__h656424, - y__h689971, - y_avValue_fst__h683355, - y_avValue_snd_fst__h683629, - y_avValue_snd_fst__h683664; + _theResult____h655821, + enabled_ints___1__h656234, + enabled_ints__h656281, + pend_ints__h655819, + renaming_spec_bits__h686685, + result__h651528, + result__h651579, + spec_bits__h689780, + w__h651523, + x__h368055, + x__h413752, + x__h459447, + x__h507934, + x__h546787, + x__h586091, + x__h651527, + x__h651578, + y__h651557, + y__h656246, + y__h689793, + y_avValue_fst__h683177, + y_avValue_snd_fst__h683451, + y_avValue_snd_fst__h683486; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167, @@ -5196,103 +5134,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172, - _theResult___exp__h506685, - _theResult___exp__h516336, - _theResult___exp__h525120, - _theResult___exp__h545538, - _theResult___exp__h555189, - _theResult___exp__h563973, - _theResult___exp__h584842, - _theResult___exp__h594493, - _theResult___exp__h603277, - _theResult___fst_exp__h490957, - _theResult___fst_exp__h506021, - _theResult___fst_exp__h506027, - _theResult___fst_exp__h506030, - _theResult___fst_exp__h506785, - _theResult___fst_exp__h506788, - _theResult___fst_exp__h515607, - _theResult___fst_exp__h515672, - _theResult___fst_exp__h515678, - _theResult___fst_exp__h515681, - _theResult___fst_exp__h516436, - _theResult___fst_exp__h516439, - _theResult___fst_exp__h524392, - _theResult___fst_exp__h524431, - _theResult___fst_exp__h524437, - _theResult___fst_exp__h524440, - _theResult___fst_exp__h525220, - _theResult___fst_exp__h525223, - _theResult___fst_exp__h525232, - _theResult___fst_exp__h525235, - _theResult___fst_exp__h529810, - _theResult___fst_exp__h544874, - _theResult___fst_exp__h544880, - _theResult___fst_exp__h544883, - _theResult___fst_exp__h545638, - _theResult___fst_exp__h545641, - _theResult___fst_exp__h554460, - _theResult___fst_exp__h554525, - _theResult___fst_exp__h554531, - _theResult___fst_exp__h554534, - _theResult___fst_exp__h555289, - _theResult___fst_exp__h555292, - _theResult___fst_exp__h563245, - _theResult___fst_exp__h563284, - _theResult___fst_exp__h563290, - _theResult___fst_exp__h563293, - _theResult___fst_exp__h564073, - _theResult___fst_exp__h564076, - _theResult___fst_exp__h564085, - _theResult___fst_exp__h564088, - _theResult___fst_exp__h569114, - _theResult___fst_exp__h584178, - _theResult___fst_exp__h584184, - _theResult___fst_exp__h584187, - _theResult___fst_exp__h584942, - _theResult___fst_exp__h584945, - _theResult___fst_exp__h593764, - _theResult___fst_exp__h593829, - _theResult___fst_exp__h593835, - _theResult___fst_exp__h593838, - _theResult___fst_exp__h594593, - _theResult___fst_exp__h594596, - _theResult___fst_exp__h602549, - _theResult___fst_exp__h602588, - _theResult___fst_exp__h602594, - _theResult___fst_exp__h602597, - _theResult___fst_exp__h603377, - _theResult___fst_exp__h603380, - _theResult___fst_exp__h603389, - _theResult___fst_exp__h603392, - _theResult___snd_fst_exp__h506791, - _theResult___snd_fst_exp__h525226, - _theResult___snd_fst_exp__h545644, - _theResult___snd_fst_exp__h564079, - _theResult___snd_fst_exp__h584948, - _theResult___snd_fst_exp__h603383, + _theResult___exp__h506507, + _theResult___exp__h516158, + _theResult___exp__h524942, + _theResult___exp__h545360, + _theResult___exp__h555011, + _theResult___exp__h563795, + _theResult___exp__h584664, + _theResult___exp__h594315, + _theResult___exp__h603099, + _theResult___fst_exp__h490779, + _theResult___fst_exp__h505843, + _theResult___fst_exp__h505849, + _theResult___fst_exp__h505852, + _theResult___fst_exp__h506607, + _theResult___fst_exp__h506610, + _theResult___fst_exp__h515429, + _theResult___fst_exp__h515494, + _theResult___fst_exp__h515500, + _theResult___fst_exp__h515503, + _theResult___fst_exp__h516258, + _theResult___fst_exp__h516261, + _theResult___fst_exp__h524214, + _theResult___fst_exp__h524253, + _theResult___fst_exp__h524259, + _theResult___fst_exp__h524262, + _theResult___fst_exp__h525042, + _theResult___fst_exp__h525045, + _theResult___fst_exp__h525054, + _theResult___fst_exp__h525057, + _theResult___fst_exp__h529632, + _theResult___fst_exp__h544696, + _theResult___fst_exp__h544702, + _theResult___fst_exp__h544705, + _theResult___fst_exp__h545460, + _theResult___fst_exp__h545463, + _theResult___fst_exp__h554282, + _theResult___fst_exp__h554347, + _theResult___fst_exp__h554353, + _theResult___fst_exp__h554356, + _theResult___fst_exp__h555111, + _theResult___fst_exp__h555114, + _theResult___fst_exp__h563067, + _theResult___fst_exp__h563106, + _theResult___fst_exp__h563112, + _theResult___fst_exp__h563115, + _theResult___fst_exp__h563895, + _theResult___fst_exp__h563898, + _theResult___fst_exp__h563907, + _theResult___fst_exp__h563910, + _theResult___fst_exp__h568936, + _theResult___fst_exp__h584000, + _theResult___fst_exp__h584006, + _theResult___fst_exp__h584009, + _theResult___fst_exp__h584764, + _theResult___fst_exp__h584767, + _theResult___fst_exp__h593586, + _theResult___fst_exp__h593651, + _theResult___fst_exp__h593657, + _theResult___fst_exp__h593660, + _theResult___fst_exp__h594415, + _theResult___fst_exp__h594418, + _theResult___fst_exp__h602371, + _theResult___fst_exp__h602410, + _theResult___fst_exp__h602416, + _theResult___fst_exp__h602419, + _theResult___fst_exp__h603199, + _theResult___fst_exp__h603202, + _theResult___fst_exp__h603211, + _theResult___fst_exp__h603214, + _theResult___snd_fst_exp__h506613, + _theResult___snd_fst_exp__h525048, + _theResult___snd_fst_exp__h545466, + _theResult___snd_fst_exp__h563901, + _theResult___snd_fst_exp__h584770, + _theResult___snd_fst_exp__h603205, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, - din_inc___2_exp__h525280, - din_inc___2_exp__h525315, - din_inc___2_exp__h525341, - din_inc___2_exp__h564133, - din_inc___2_exp__h564168, - din_inc___2_exp__h564194, - din_inc___2_exp__h603437, - din_inc___2_exp__h603472, - din_inc___2_exp__h603498, - out_exp__h506688, - out_exp__h516339, - out_exp__h525123, - out_exp__h545541, - out_exp__h555192, - out_exp__h563976, - out_exp__h584845, - out_exp__h594496, - out_exp__h603280; - wire [9 : 0] r1__read_BITS_9_TO_0___h656435; + din_inc___2_exp__h525102, + din_inc___2_exp__h525137, + din_inc___2_exp__h525163, + din_inc___2_exp__h563955, + din_inc___2_exp__h563990, + din_inc___2_exp__h564016, + din_inc___2_exp__h603259, + din_inc___2_exp__h603294, + din_inc___2_exp__h603320, + out_exp__h506510, + out_exp__h516161, + out_exp__h524945, + out_exp__h545363, + out_exp__h555014, + out_exp__h563798, + out_exp__h584667, + out_exp__h594318, + out_exp__h603102; + wire [9 : 0] r1__read_BITS_9_TO_0___h656257; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752; @@ -5323,125 +5261,125 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105, - _theResult___exp__h358478, - _theResult___exp__h367060, - _theResult___exp__h376244, - _theResult___exp__h384880, - _theResult___exp__h384982, - _theResult___exp__h404175, - _theResult___exp__h412757, - _theResult___exp__h421941, - _theResult___exp__h430577, - _theResult___exp__h430679, - _theResult___exp__h449870, - _theResult___exp__h458452, - _theResult___exp__h467636, - _theResult___exp__h476272, - _theResult___exp__h476374, - _theResult___fst_exp__h357962, - _theResult___fst_exp__h358027, - _theResult___fst_exp__h358033, - _theResult___fst_exp__h358036, - _theResult___fst_exp__h358559, - _theResult___fst_exp__h366609, - _theResult___fst_exp__h366615, - _theResult___fst_exp__h366618, - _theResult___fst_exp__h367141, - _theResult___fst_exp__h375728, - _theResult___fst_exp__h375793, - _theResult___fst_exp__h375799, - _theResult___fst_exp__h375802, - _theResult___fst_exp__h376325, - _theResult___fst_exp__h384365, - _theResult___fst_exp__h384404, - _theResult___fst_exp__h384410, - _theResult___fst_exp__h384413, - _theResult___fst_exp__h384961, - _theResult___fst_exp__h384970, - _theResult___fst_exp__h384973, - _theResult___fst_exp__h403659, - _theResult___fst_exp__h403724, - _theResult___fst_exp__h403730, - _theResult___fst_exp__h403733, - _theResult___fst_exp__h404256, - _theResult___fst_exp__h412306, - _theResult___fst_exp__h412312, - _theResult___fst_exp__h412315, - _theResult___fst_exp__h412838, - _theResult___fst_exp__h421425, - _theResult___fst_exp__h421490, - _theResult___fst_exp__h421496, - _theResult___fst_exp__h421499, - _theResult___fst_exp__h422022, - _theResult___fst_exp__h430062, - _theResult___fst_exp__h430101, - _theResult___fst_exp__h430107, - _theResult___fst_exp__h430110, - _theResult___fst_exp__h430658, - _theResult___fst_exp__h430667, - _theResult___fst_exp__h430670, - _theResult___fst_exp__h449354, - _theResult___fst_exp__h449419, - _theResult___fst_exp__h449425, - _theResult___fst_exp__h449428, - _theResult___fst_exp__h449951, - _theResult___fst_exp__h458001, - _theResult___fst_exp__h458007, - _theResult___fst_exp__h458010, - _theResult___fst_exp__h458533, - _theResult___fst_exp__h467120, - _theResult___fst_exp__h467185, - _theResult___fst_exp__h467191, - _theResult___fst_exp__h467194, - _theResult___fst_exp__h467717, - _theResult___fst_exp__h475757, - _theResult___fst_exp__h475796, - _theResult___fst_exp__h475802, - _theResult___fst_exp__h475805, - _theResult___fst_exp__h476353, - _theResult___fst_exp__h476362, - _theResult___fst_exp__h476365, - _theResult___snd_fst_exp__h367144, - _theResult___snd_fst_exp__h384964, - _theResult___snd_fst_exp__h412841, - _theResult___snd_fst_exp__h430661, - _theResult___snd_fst_exp__h458536, - _theResult___snd_fst_exp__h476356, + _theResult___exp__h358300, + _theResult___exp__h366882, + _theResult___exp__h376066, + _theResult___exp__h384702, + _theResult___exp__h384804, + _theResult___exp__h403997, + _theResult___exp__h412579, + _theResult___exp__h421763, + _theResult___exp__h430399, + _theResult___exp__h430501, + _theResult___exp__h449692, + _theResult___exp__h458274, + _theResult___exp__h467458, + _theResult___exp__h476094, + _theResult___exp__h476196, + _theResult___fst_exp__h357784, + _theResult___fst_exp__h357849, + _theResult___fst_exp__h357855, + _theResult___fst_exp__h357858, + _theResult___fst_exp__h358381, + _theResult___fst_exp__h366431, + _theResult___fst_exp__h366437, + _theResult___fst_exp__h366440, + _theResult___fst_exp__h366963, + _theResult___fst_exp__h375550, + _theResult___fst_exp__h375615, + _theResult___fst_exp__h375621, + _theResult___fst_exp__h375624, + _theResult___fst_exp__h376147, + _theResult___fst_exp__h384187, + _theResult___fst_exp__h384226, + _theResult___fst_exp__h384232, + _theResult___fst_exp__h384235, + _theResult___fst_exp__h384783, + _theResult___fst_exp__h384792, + _theResult___fst_exp__h384795, + _theResult___fst_exp__h403481, + _theResult___fst_exp__h403546, + _theResult___fst_exp__h403552, + _theResult___fst_exp__h403555, + _theResult___fst_exp__h404078, + _theResult___fst_exp__h412128, + _theResult___fst_exp__h412134, + _theResult___fst_exp__h412137, + _theResult___fst_exp__h412660, + _theResult___fst_exp__h421247, + _theResult___fst_exp__h421312, + _theResult___fst_exp__h421318, + _theResult___fst_exp__h421321, + _theResult___fst_exp__h421844, + _theResult___fst_exp__h429884, + _theResult___fst_exp__h429923, + _theResult___fst_exp__h429929, + _theResult___fst_exp__h429932, + _theResult___fst_exp__h430480, + _theResult___fst_exp__h430489, + _theResult___fst_exp__h430492, + _theResult___fst_exp__h449176, + _theResult___fst_exp__h449241, + _theResult___fst_exp__h449247, + _theResult___fst_exp__h449250, + _theResult___fst_exp__h449773, + _theResult___fst_exp__h457823, + _theResult___fst_exp__h457829, + _theResult___fst_exp__h457832, + _theResult___fst_exp__h458355, + _theResult___fst_exp__h466942, + _theResult___fst_exp__h467007, + _theResult___fst_exp__h467013, + _theResult___fst_exp__h467016, + _theResult___fst_exp__h467539, + _theResult___fst_exp__h475579, + _theResult___fst_exp__h475618, + _theResult___fst_exp__h475624, + _theResult___fst_exp__h475627, + _theResult___fst_exp__h476175, + _theResult___fst_exp__h476184, + _theResult___fst_exp__h476187, + _theResult___snd_fst_exp__h366966, + _theResult___snd_fst_exp__h384786, + _theResult___snd_fst_exp__h412663, + _theResult___snd_fst_exp__h430483, + _theResult___snd_fst_exp__h458358, + _theResult___snd_fst_exp__h476178, csrf_external_int_en_vec_3_read__1834_AND_csrf_ETC___d12904, - din_inc___2_exp__h384995, - din_inc___2_exp__h385019, - din_inc___2_exp__h385049, - din_inc___2_exp__h385073, - din_inc___2_exp__h430692, - din_inc___2_exp__h430716, - din_inc___2_exp__h430746, - din_inc___2_exp__h430770, - din_inc___2_exp__h476387, - din_inc___2_exp__h476411, - din_inc___2_exp__h476441, - din_inc___2_exp__h476465, - f1_exp86642_MINUS_127__q128, - f1_exp__h486642, - f2_exp25636_MINUS_127__q168, - f2_exp__h525636, - f3_exp64940_MINUS_127__q145, - f3_exp__h564940, - out_exp__h358481, - out_exp__h367063, - out_exp__h376247, - out_exp__h384883, - out_exp__h404178, - out_exp__h412760, - out_exp__h421944, - out_exp__h430580, - out_exp__h449873, - out_exp__h458455, - out_exp__h467639, - out_exp__h476275, - out_f_exp__h385259, - out_f_exp__h430956, - out_f_exp__h476651, - x__h617953; + din_inc___2_exp__h384817, + din_inc___2_exp__h384841, + din_inc___2_exp__h384871, + din_inc___2_exp__h384895, + din_inc___2_exp__h430514, + din_inc___2_exp__h430538, + din_inc___2_exp__h430568, + din_inc___2_exp__h430592, + din_inc___2_exp__h476209, + din_inc___2_exp__h476233, + din_inc___2_exp__h476263, + din_inc___2_exp__h476287, + f1_exp86464_MINUS_127__q128, + f1_exp__h486464, + f2_exp25458_MINUS_127__q168, + f2_exp__h525458, + f3_exp64762_MINUS_127__q145, + f3_exp__h564762, + out_exp__h358303, + out_exp__h366885, + out_exp__h376069, + out_exp__h384705, + out_exp__h404000, + out_exp__h412582, + out_exp__h421766, + out_exp__h430402, + out_exp__h449695, + out_exp__h458277, + out_exp__h467461, + out_exp__h476097, + out_f_exp__h385081, + out_f_exp__h430778, + out_f_exp__h476473, + x__h617775; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127, @@ -5461,9 +5399,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15219, - x__h184855, - x__h707412; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15216, + x__h184677, + x__h707234; wire [4 : 0] IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14349, IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, @@ -5483,18 +5421,18 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, checkForException___d13089, checkForException___d13706, - fflags__h719327, - res_fflags__h341636, - res_fflags__h387338, - res_fflags__h433033, - rs1__h659778, - x__h155073, - x__h158620, - x__h161436, - x__h290941, - y_avValue_fst__h718332, - y_avValue_fst__h719246, - y_avValue_fst__h719274; + fflags__h719149, + res_fflags__h341458, + res_fflags__h387160, + res_fflags__h432855, + rs1__h659600, + x__h154894, + x__h158441, + x__h161257, + x__h290763, + y_avValue_fst__h718154, + y_avValue_fst__h719068, + y_avValue_fst__h719096; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, @@ -5521,75 +5459,75 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, IF_fetchStage_pipelines_0_first__2863_BIT_68_2_ETC___d13312, - cause_code__h704811, + cause_code__h704633, csrf_external_int_en_vec_3_read__1834_AND_csrf_ETC___d12899, - vm_mode_reg__read__h619162; + vm_mode_reg__read__h618984; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h300288, - next_deqP___1__h300567, - v__h299708, - v__h299939, - x__h305918, - x_decodeInfo_frm__h659462; + _theResult_____2__h300110, + next_deqP___1__h300389, + v__h299530, + v__h299761, + x__h305740, + x_decodeInfo_frm__h659284; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097, - IF_sfdin03653_BIT_33_THEN_2_ELSE_0__q57, - IF_sfdin15601_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin21419_BIT_33_THEN_2_ELSE_0__q67, - IF_sfdin49348_BIT_33_THEN_2_ELSE_0__q92, - IF_sfdin54454_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin57956_BIT_33_THEN_2_ELSE_0__q22, - IF_sfdin67114_BIT_33_THEN_2_ELSE_0__q102, - IF_sfdin75722_BIT_33_THEN_2_ELSE_0__q32, - IF_sfdin93758_BIT_4_THEN_2_ELSE_0__q148, - IF_theResult___snd02543_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd05981_BIT_4_THEN_2_ELSE_0__q127, - IF_theResult___snd12266_BIT_33_THEN_2_ELSE_0__q59, - IF_theResult___snd24386_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd30056_BIT_33_THEN_2_ELSE_0__q72, - IF_theResult___snd44834_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd57961_BIT_33_THEN_2_ELSE_0__q94, - IF_theResult___snd63239_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd66569_BIT_33_THEN_2_ELSE_0__q24, - IF_theResult___snd75751_BIT_33_THEN_2_ELSE_0__q107, - IF_theResult___snd84138_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd84359_BIT_33_THEN_2_ELSE_0__q37, - guard__h349861, - guard__h358570, - guard__h367500, - guard__h376336, - guard__h395560, - guard__h404267, - guard__h413197, - guard__h422033, - guard__h441255, - guard__h449962, - guard__h458892, - guard__h467728, - guard__h498069, - guard__h507381, - guard__h516450, - guard__h536922, - guard__h546234, - guard__h555303, - guard__h576226, - guard__h585538, - guard__h594607, - prv__h720841, - prv__h720885, - r1__read_BITS_13_TO_12___h659647, - sbIdx__h158499, - v__h608735, - v__h608745, - v__h609803, - x__h715589, - x__h719574, - y_avValue_snd_snd_snd_fst__h718752, - y_avValue_snd_snd_snd_fst__h719397, - y_avValue_snd_snd_snd_fst__h719426; + IF_sfdin03475_BIT_33_THEN_2_ELSE_0__q57, + IF_sfdin15423_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin21241_BIT_33_THEN_2_ELSE_0__q67, + IF_sfdin49170_BIT_33_THEN_2_ELSE_0__q92, + IF_sfdin54276_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin57778_BIT_33_THEN_2_ELSE_0__q22, + IF_sfdin66936_BIT_33_THEN_2_ELSE_0__q102, + IF_sfdin75544_BIT_33_THEN_2_ELSE_0__q32, + IF_sfdin93580_BIT_4_THEN_2_ELSE_0__q148, + IF_theResult___snd02365_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd05803_BIT_4_THEN_2_ELSE_0__q127, + IF_theResult___snd12088_BIT_33_THEN_2_ELSE_0__q59, + IF_theResult___snd24208_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd29878_BIT_33_THEN_2_ELSE_0__q72, + IF_theResult___snd44656_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd57783_BIT_33_THEN_2_ELSE_0__q94, + IF_theResult___snd63061_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd66391_BIT_33_THEN_2_ELSE_0__q24, + IF_theResult___snd75573_BIT_33_THEN_2_ELSE_0__q107, + IF_theResult___snd83960_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd84181_BIT_33_THEN_2_ELSE_0__q37, + guard__h349683, + guard__h358392, + guard__h367322, + guard__h376158, + guard__h395382, + guard__h404089, + guard__h413019, + guard__h421855, + guard__h441077, + guard__h449784, + guard__h458714, + guard__h467550, + guard__h497891, + guard__h507203, + guard__h516272, + guard__h536744, + guard__h546056, + guard__h555125, + guard__h576048, + guard__h585360, + guard__h594429, + prv__h720663, + prv__h720707, + r1__read_BITS_13_TO_12___h659469, + sbIdx__h158320, + v__h608557, + v__h608567, + v__h609625, + x__h715411, + x__h719396, + y_avValue_snd_snd_snd_fst__h718574, + y_avValue_snd_snd_snd_fst__h719219, + y_avValue_snd_snd_snd_fst__h719248; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5945,7 +5883,7 @@ module mkCore(CLK, NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13861, NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13916, NOT_regRenamingTable_rename_1_canRename__3555__ETC___d13974, - NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917, + NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917, NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070, NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14674, NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14859, @@ -6042,11 +5980,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h308284, - _theResult_____2__h314278, - _theResult_____2__h322132, - _theResult_____2__h332476, - _theResult_____2__h335701, + _theResult_____2__h308106, + _theResult_____2__h314100, + _theResult_____2__h321954, + _theResult_____2__h332298, + _theResult_____2__h335523, coreFix_aluExe_0_bypassWire_0_wget__2326_BITS__ETC___d12328, coreFix_aluExe_0_bypassWire_0_wget__2326_BITS__ETC___d12369, coreFix_aluExe_0_bypassWire_1_wget__2339_BITS__ETC___d12341, @@ -6171,8 +6109,8 @@ module mkCore(CLK, csrf_prv_reg_read__2891_ULE_1___d14503, csrf_prv_reg_read__2891_ULT_IF_fetchStage_pipe_ETC___d13121, fetchStage_RDY_pipelines_0_first__2860_AND_NOT_ETC___d13459, + fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333, fetchStage_RDY_pipelines_0_first__2860_AND_fet_ETC___d13525, - fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14006, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085, fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14203, @@ -6197,14 +6135,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2872_BITS_194_TO_ETC___d13968, fetchStage_pipelines_1_first__2872_BITS_199_TO_ETC___d13803, fetchStage_pipelines_1_first__2872_BIT_68_3583_ETC___d13972, - guard__h368098, - guard__h413795, - guard__h459490, - guard__h507979, - guard__h546832, - guard__h586136, - idx__h686994, - k__h671653, + guard__h367920, + guard__h413617, + guard__h459312, + guard__h507801, + guard__h546654, + guard__h585958, + idx__h686816, + k__h671475, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6215,15 +6153,14 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14079, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h75651, - next_deqP___1__h308563, - next_deqP___1__h314844, - next_deqP___1__h322698, - next_deqP___1__h332755, - next_deqP___1__h335980, - r1__read_BIT_20___h660275, - r__h618000, - regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333, + msip__h75472, + next_deqP___1__h308385, + next_deqP___1__h314666, + next_deqP___1__h322520, + next_deqP___1__h332577, + next_deqP___1__h335802, + r1__read_BIT_20___h660097, + r__h617822, regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13936, regRenamingTable_RDY_rename_1_getRename__3992__ETC___d14010, regRenamingTable_rename_0_canRename__3436_AND__ETC___d13506, @@ -6243,31 +6180,21 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14216, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14300, regRenamingTable_rename_1_canRename__3555_AND__ETC___d14310, + rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13740, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13874, rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13891, - v__h303053, - v__h303571, - v__h313567, - v__h313798, - v__h317443, - v__h317674, - v__h332044, - v__h332275, - v__h335269, - v__h335500, - value_BIT_52___h450620, - x__h608051; - - // action method init_server_request_put - assign RDY_init_server_request_put = f_init_reqs$FULL_N ; - assign CAN_FIRE_init_server_request_put = f_init_reqs$FULL_N ; - assign WILL_FIRE_init_server_request_put = EN_init_server_request_put ; - - // action method init_server_response_get - assign RDY_init_server_response_get = f_init_rsps$EMPTY_N ; - assign CAN_FIRE_init_server_response_get = f_init_rsps$EMPTY_N ; - assign WILL_FIRE_init_server_response_get = EN_init_server_response_get ; + v__h302875, + v__h303393, + v__h313389, + v__h313620, + v__h317265, + v__h317496, + v__h331866, + v__h332097, + v__h335091, + v__h335322, + x__h607873; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6308,7 +6235,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15193 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15190 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6328,7 +6255,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15219 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15216 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -8354,24 +8281,6 @@ module mkCore(CLK, .isFull_ehrPort0(), .RDY_isFull_ehrPort0()); - // submodule f_init_reqs - FIFO20 #(.guarded(32'd1)) f_init_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_init_reqs$ENQ), - .DEQ(f_init_reqs$DEQ), - .CLR(f_init_reqs$CLR), - .FULL_N(f_init_reqs$FULL_N), - .EMPTY_N(f_init_reqs$EMPTY_N)); - - // submodule f_init_rsps - FIFO20 #(.guarded(32'd1)) f_init_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_init_rsps$ENQ), - .DEQ(f_init_rsps$DEQ), - .CLR(f_init_rsps$CLR), - .FULL_N(f_init_rsps$FULL_N), - .EMPTY_N(f_init_rsps$EMPTY_N)); - // submodule fetchStage mkFetchStage fetchStage(.CLK(CLK), .RST_N(RST_N), @@ -9333,10 +9242,6 @@ module mkCore(CLK, assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ; assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ; - // rule RL_rl_init - assign CAN_FIRE_RL_rl_init = f_init_reqs$EMPTY_N && f_init_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_init = CAN_FIRE_RL_rl_init ; - // rule RL_mmio_handlePRq assign CAN_FIRE_RL_mmio_handlePRq = !mmio_pRqQ_empty && !mmio_cRsQ_full && @@ -9664,10 +9569,10 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9681,8 +9586,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -9703,8 +9608,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9713,10 +9618,10 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9730,8 +9635,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -9758,7 +9663,6 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_init && !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_csrf_incCycle @@ -9784,7 +9688,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917 && + NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9815,6 +9719,7 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9828,8 +9733,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -9859,8 +9764,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -9871,8 +9776,7 @@ module mkCore(CLK, coreFix_aluExe_0_exeToFinQ$RDY_deq && coreFix_aluExe_0_exeToFinQ_RDY_first__2746_AND_ETC___d12786 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = - CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ; // rule RL_coreFix_aluExe_1_doFinishAlu_F assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = @@ -10187,8 +10091,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -10208,8 +10112,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -10533,6 +10437,10 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon = 1'd1 ; + // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize + assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon = 1'd1 ; @@ -10551,10 +10459,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize - assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ; @@ -10627,14 +10531,14 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_data_0_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_empty_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLdQ_data_0_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq && @@ -10707,9 +10611,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13135 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10718,8 +10623,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13385 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10993,19 +10898,7 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[9] || IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[10] || IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[11]) ; - assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd9 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd22) ; - assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd22 ; - assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 = + assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == @@ -11024,10 +10917,7 @@ module mkCore(CLK, 6'd0 || IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd2) ; - assign MUX_csrf_fflags_reg$write_1__SEL_2 = - WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 ; - assign MUX_csrf_fs_reg$write_1__SEL_2 = + assign MUX_csrf_fs_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == @@ -11040,54 +10930,16 @@ module mkCore(CLK, 6'd8 || IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd18) ; - assign MUX_csrf_ie_vec_0$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd8 || - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 ; - assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd30 ; - assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd31 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_mprv_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; - assign MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 = - WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] && - mmio_pRqQ_data_0[37:36] != 2'd0 && - mmio_pRqQ_data_0[37:36] != 2'd1 ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -11144,7 +10996,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h701147, + x__h700969, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 : @@ -11152,7 +11004,7 @@ module mkCore(CLK, assign MUX_commitStage_rg_serialnum$write_1__VAL_1 = commitStage_rg_serialnum + 64'd1 ; assign MUX_commitStage_rg_serialnum$write_1__VAL_2 = - commitStage_rg_serialnum + y__h719350 ; + commitStage_rg_serialnum + y__h719172 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d12981, @@ -11166,7 +11018,7 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h671653 == 1'd0 && + (k__h671475 == 1'd0 && fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d12981, @@ -11187,7 +11039,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686863, + renaming_spec_bits__h686685, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11278,7 +11130,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, @@ -11292,10 +11144,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h289508 } ; + x__h289330 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h290953, + x__h290775, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11303,7 +11155,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h293729, + addr__h293551, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11316,12 +11168,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155073, x__h155079, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h154894, x__h154900, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158620, x__h158626, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158441, x__h158447, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161436, - x__h161440, + { x__h161257, + x__h161261, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -11332,7 +11184,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163288, + x__h163109, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -11345,7 +11197,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h295744, + resp_addr__h295566, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11425,7 +11277,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h199463 } ; + x__h199285 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11460,8 +11312,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h194420 : - { {32{x__h195183[31]}}, x__h195183 } } ; + curData__h194242 : + { {32{x__h195005[31]}}, x__h195005 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -11494,17 +11346,17 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h719327 ; + csrf_fflags_reg | fflags__h719149 ; always@(IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin case (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664) - 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; - default: MUX_csrf_fs_reg$write_1__VAL_2 = + 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11; + default: MUX_csrf_fs_reg$write_1__VAL_1 = robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd8 || @@ -11512,42 +11364,41 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] : csrf_prev_ie_vec_3 ; - assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_1 = - rob$deqPort_0_deq_data[95:32] ; + assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h716179 + 64'd1 ; + n__read__h716001 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h716179 + { 62'd0, x__h719574 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + n__read__h716001 + { 62'd0, x__h719396 } ; + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd18) ? - MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_1[12:11] : + MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h705834 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h705656 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != 6'd8 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] != 5'd13 || IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h715589 : + x__h715411 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ? @@ -11558,25 +11409,24 @@ module mkCore(CLK, (mmio_pRqQ_data_0[37:36] == 2'd2) ? mmio_pRqQ_data_0[0] : amoExec___d882[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd8 || IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_2[8] ; - assign MUX_csrf_stval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 ? - y_avValue__h705681 : - y_avValue__h707434 ; + y_avValue__h705503 : + y_avValue__h707256 ; always@(rob$deqPort_0_deq_data or - next_pc__h715420 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h715242 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h715420; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h715242; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11611,24 +11461,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h341640 : - res_data__h341635 ; + res_data__h341462 : + res_data__h341457 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h387342 : - res_data__h387337 ; + res_data__h387164 : + res_data__h387159 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h433037 : - res_data__h433032 ; + res_data__h432859 : + res_data__h432854 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h478889 : - data__h478377 ; + data___1__h478711 : + data__h478199 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h479821 : - data__h479309 ; + data___1__h479643 : + data__h479131 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -11703,29 +11553,34 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h341636 ; + res_fflags__h341458 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h387338 ; + res_fflags__h387160 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h433033 ; + res_fflags__h432855 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = - MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd31 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst ; assign csrf_minstret_ehr_data_dummy_1_0$whas = WILL_FIRE_RL_commitStage_doCommitNormalInst || WILL_FIRE_RL_commitStage_doCommitSystemInst ; + assign csrf_mcycle_ehr_data_lat_0$wget = rob$deqPort_0_deq_data[95:32] ; assign csrf_mcycle_ehr_data_lat_0$whas = - MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd30 ; assign csrInstOrInterruptInflight_lat_1$whas = WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[199:195] == 5'd13 || @@ -12041,8 +11896,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h609803 : - v__h608735 ; + v__h609625 : + v__h608557 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12188,7 +12043,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h300288 ; + _theResult_____2__h300110 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12210,7 +12065,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h299708 ; + v__h299530 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12256,7 +12111,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - _theResult_____2__h308284 ; + _theResult_____2__h308106 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12274,7 +12129,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - v__h303053 ; + v__h302875 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12374,7 +12229,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - _theResult_____2__h314278 ; + _theResult_____2__h314100 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12392,7 +12247,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - v__h313567 ; + v__h313389 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12413,7 +12268,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h317841, + { x_addr__h317663, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12443,7 +12298,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - _theResult_____2__h322132 ; + _theResult_____2__h321954 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12461,7 +12316,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - v__h317443 ; + v__h317265 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12538,7 +12393,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - _theResult_____2__h335701 ; + _theResult_____2__h335523 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12556,7 +12411,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - v__h335269 ; + v__h335091 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12599,7 +12454,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - _theResult_____2__h332476 ; + _theResult_____2__h332298 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12617,7 +12472,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - v__h332044 ; + v__h331866 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12774,81 +12629,65 @@ module mkCore(CLK, // register csrf_external_int_en_vec_0 assign csrf_external_int_en_vec_0$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[8] ; + csrf_mcycle_ehr_data_lat_0$wget[8] ; assign csrf_external_int_en_vec_0$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_external_int_en_vec_1 assign csrf_external_int_en_vec_1$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[9] ; + csrf_mcycle_ehr_data_lat_0$wget[9] ; assign csrf_external_int_en_vec_1$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_external_int_en_vec_3 assign csrf_external_int_en_vec_3$D_IN = - MUX_csrf_external_int_en_vec_3$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[11] ; + csrf_mcycle_ehr_data_lat_0$wget[11] ; assign csrf_external_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd22 || - WILL_FIRE_RL_rl_init ; + 6'd22 ; // register csrf_external_int_pend_vec_0 assign csrf_external_int_pend_vec_0$D_IN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[8] ; + csrf_mcycle_ehr_data_lat_0$wget[8] ; assign csrf_external_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; // register csrf_external_int_pend_vec_1 - always@(MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 or - MUX_csrf_stval_csr$write_1__VAL_2 or - WILL_FIRE_RL_rl_init or EN_setSEIP or setSEIP_v) - case (1'b1) - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1: - csrf_external_int_pend_vec_1$D_IN = - MUX_csrf_stval_csr$write_1__VAL_2[9]; - WILL_FIRE_RL_rl_init: csrf_external_int_pend_vec_1$D_IN = 1'd0; - EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v; - default: csrf_external_int_pend_vec_1$D_IN = - 1'b0 /* unspecified value */ ; - endcase + assign csrf_external_int_pend_vec_1$D_IN = + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ? + csrf_mcycle_ehr_data_lat_0$wget[9] : + setSEIP_v ; assign csrf_external_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || EN_setSEIP || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || EN_setSEIP ; // register csrf_external_int_pend_vec_3 - always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or - MUX_csrf_stval_csr$write_1__VAL_2 or - WILL_FIRE_RL_rl_init or EN_setMEIP or setMEIP_v) - case (1'b1) - MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: - csrf_external_int_pend_vec_3$D_IN = - MUX_csrf_stval_csr$write_1__VAL_2[11]; - WILL_FIRE_RL_rl_init: csrf_external_int_pend_vec_3$D_IN = 1'd0; - EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v; - default: csrf_external_int_pend_vec_3$D_IN = - 1'b0 /* unspecified value */ ; - endcase + assign csrf_external_int_pend_vec_3$D_IN = + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 ? + csrf_mcycle_ehr_data_lat_0$wget[11] : + setMEIP_v ; assign csrf_external_int_pend_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd29 || - EN_setMEIP || - WILL_FIRE_RL_rl_init ; + EN_setMEIP ; // register csrf_fflags_reg assign csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__SEL_1 ? - MUX_csrf_stval_csr$write_1__VAL_2[4:0] : + csrf_mcycle_ehr_data_lat_0$wget[4:0] : MUX_csrf_fflags_reg$write_1__VAL_2 ; assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -12864,8 +12703,8 @@ module mkCore(CLK, assign csrf_frm_reg$D_IN = (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == 6'd1) ? - MUX_csrf_stval_csr$write_1__VAL_2[2:0] : - MUX_csrf_stval_csr$write_1__VAL_2[7:5] ; + csrf_mcycle_ehr_data_lat_0$wget[2:0] : + csrf_mcycle_ehr_data_lat_0$wget[7:5] ; assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12875,54 +12714,48 @@ module mkCore(CLK, 6'd2) ; // register csrf_fs_reg - always@(MUX_csrf_fflags_reg$write_1__SEL_2 or - MUX_csrf_fs_reg$write_1__SEL_2 or - MUX_csrf_fs_reg$write_1__VAL_2 or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_fflags_reg$write_1__SEL_2: csrf_fs_reg$D_IN = 2'b11; - MUX_csrf_fs_reg$write_1__SEL_2: - csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2; - WILL_FIRE_RL_rl_init: csrf_fs_reg$D_IN = 2'd0; - default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ; - endcase + assign csrf_fs_reg$D_IN = + MUX_csrf_fs_reg$write_1__SEL_1 ? + MUX_csrf_fs_reg$write_1__VAL_1 : + 2'b11 ; assign csrf_fs_reg$EN = - MUX_csrf_fs_reg$write_1__SEL_2 || + MUX_csrf_fs_reg$write_1__SEL_1 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 || - WILL_FIRE_RL_rl_init ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 ; // register csrf_ie_vec_0 - assign csrf_ie_vec_0$D_IN = - MUX_csrf_ie_vec_0$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[0] ; + assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; assign csrf_ie_vec_0$EN = - MUX_csrf_ie_vec_0$write_1__SEL_1 || WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd8 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd18) ; // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h704811 : - MUX_csrf_stval_csr$write_1__VAL_2[3:0] ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + cause_code__h704633 : + csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || @@ -12933,9 +12766,9 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[4] : - MUX_csrf_stval_csr$write_1__VAL_2[63] ; + csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || @@ -12945,7 +12778,7 @@ module mkCore(CLK, 6'd27 ; // register csrf_mcounteren_cy_reg - assign csrf_mcounteren_cy_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[0] ; + assign csrf_mcounteren_cy_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; assign csrf_mcounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12953,7 +12786,7 @@ module mkCore(CLK, 6'd24 ; // register csrf_mcounteren_ir_reg - assign csrf_mcounteren_ir_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[2] ; + assign csrf_mcounteren_ir_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[2] ; assign csrf_mcounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12961,7 +12794,7 @@ module mkCore(CLK, 6'd24 ; // register csrf_mcounteren_tm_reg - assign csrf_mcounteren_tm_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[1] ; + assign csrf_mcounteren_tm_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1] ; assign csrf_mcounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12969,12 +12802,12 @@ module mkCore(CLK, 6'd24 ; // register csrf_mcycle_ehr_data_rl - assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5174 ; + assign csrf_mcycle_ehr_data_rl$D_IN = upd__h4996 ; assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ; // register csrf_medeleg_13_11_reg assign csrf_medeleg_13_11_reg$D_IN = - MUX_csrf_stval_csr$write_1__VAL_2[13:11] ; + csrf_mcycle_ehr_data_lat_0$wget[13:11] ; assign csrf_medeleg_13_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12982,7 +12815,7 @@ module mkCore(CLK, 6'd20 ; // register csrf_medeleg_15_reg - assign csrf_medeleg_15_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[15] ; + assign csrf_medeleg_15_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[15] ; assign csrf_medeleg_15_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12990,7 +12823,7 @@ module mkCore(CLK, 6'd20 ; // register csrf_medeleg_9_0_reg - assign csrf_medeleg_9_0_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[9:0] ; + assign csrf_medeleg_9_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:0] ; assign csrf_medeleg_9_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -12999,7 +12832,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -13011,7 +12844,7 @@ module mkCore(CLK, 6'd26 ; // register csrf_mideleg_11_reg - assign csrf_mideleg_11_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[11] ; + assign csrf_mideleg_11_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[11] ; assign csrf_mideleg_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -13019,7 +12852,7 @@ module mkCore(CLK, 6'd21 ; // register csrf_mideleg_1_0_reg - assign csrf_mideleg_1_0_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[1:0] ; + assign csrf_mideleg_1_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1:0] ; assign csrf_mideleg_1_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -13027,7 +12860,7 @@ module mkCore(CLK, 6'd21 ; // register csrf_mideleg_5_3_reg - assign csrf_mideleg_5_3_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[5:3] ; + assign csrf_mideleg_5_3_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[5:3] ; assign csrf_mideleg_5_3_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -13035,7 +12868,7 @@ module mkCore(CLK, 6'd21 ; // register csrf_mideleg_9_7_reg - assign csrf_mideleg_9_7_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_2[9:7] ; + assign csrf_mideleg_9_7_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:7] ; assign csrf_mideleg_9_7_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && @@ -13045,38 +12878,27 @@ module mkCore(CLK, // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? - upd__h3857 : + upd__h3679 : IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg - always@(MUX_csrf_mpp_reg$write_1__SEL_1 or - MUX_csrf_mpp_reg$write_1__VAL_1 or - MUX_csrf_ie_vec_3$write_1__SEL_2 or - csrf_prv_reg or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_mpp_reg$write_1__SEL_1: - csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg; - WILL_FIRE_RL_rl_init: csrf_mpp_reg$D_IN = 2'd0; - default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; - endcase + assign csrf_mpp_reg$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg - assign csrf_mprv_reg$D_IN = - MUX_csrf_mprv_reg$write_1__SEL_1 && - MUX_csrf_stval_csr$write_1__VAL_2[17] ; + assign csrf_mprv_reg$D_IN = csrf_mscratch_csr$D_IN[17] ; assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18 || - WILL_FIRE_RL_rl_init ; + 6'd18 ; // register csrf_mscratch_csr assign csrf_mscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13088,7 +12910,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -13116,10 +12938,14 @@ module mkCore(CLK, 6'd23 ; // register csrf_mxr_reg - assign csrf_mxr_reg$D_IN = - MUX_csrf_ie_vec_0$write_1__SEL_1 && csrf_mscratch_csr$D_IN[19] ; + assign csrf_mxr_reg$D_IN = csrf_mscratch_csr$D_IN[19] ; assign csrf_mxr_reg$EN = - MUX_csrf_ie_vec_0$write_1__SEL_1 || WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd8 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd18) ; // register csrf_ppn_reg assign csrf_ppn_reg$D_IN = csrf_mscratch_csr$D_IN[43:0] ; @@ -13130,71 +12956,50 @@ module mkCore(CLK, 6'd17 ; // register csrf_prev_ie_vec_0 - assign csrf_prev_ie_vec_0$D_IN = - MUX_csrf_ie_vec_0$write_1__SEL_1 && csrf_mscratch_csr$D_IN[4] ; + assign csrf_prev_ie_vec_0$D_IN = csrf_mscratch_csr$D_IN[4] ; assign csrf_prev_ie_vec_0$EN = - MUX_csrf_ie_vec_0$write_1__SEL_1 || WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd8 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd18) ; // register csrf_prev_ie_vec_1 - always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or - MUX_csrf_ie_vec_1$write_1__SEL_2 or - csrf_ie_vec_1 or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_prev_ie_vec_1$write_1__SEL_1: - csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1; - WILL_FIRE_RL_rl_init: csrf_prev_ie_vec_1$D_IN = 1'd0; - default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; - endcase + assign csrf_prev_ie_vec_1$D_IN = + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 - always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or - MUX_csrf_ie_vec_3$write_1__SEL_2 or - csrf_ie_vec_3 or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_prev_ie_vec_3$write_1__SEL_1: - csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3; - WILL_FIRE_RL_rl_init: csrf_prev_ie_vec_3$D_IN = 1'd0; - default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; - endcase + assign csrf_prev_ie_vec_3$D_IN = + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2891_ULE_1_4503_4566_OR_ETC___d14570 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg - always@(MUX_csrf_prv_reg$write_1__SEL_1 or - MUX_csrf_prv_reg$write_1__VAL_1 or - WILL_FIRE_RL_commitStage_doCommitTrap_handle or - MUX_csrf_prv_reg$write_1__VAL_2 or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_prv_reg$write_1__SEL_1: - csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; - WILL_FIRE_RL_commitStage_doCommitTrap_handle: - csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2; - WILL_FIRE_RL_rl_init: csrf_prv_reg$D_IN = 2'd3; - default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; - endcase + assign csrf_prv_reg$D_IN = + MUX_csrf_prv_reg$write_1__SEL_1 ? + MUX_csrf_prv_reg$write_1__VAL_1 : + MUX_csrf_prv_reg$write_1__VAL_2 ; assign csrf_prv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) || - WILL_FIRE_RL_commitStage_doCommitTrap_handle || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitTrap_handle ; // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h704811 : + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + cause_code__h704633 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -13206,7 +13011,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[4] : csrf_mscratch_csr$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13243,7 +13048,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[132:69] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13255,64 +13060,48 @@ module mkCore(CLK, 6'd13 ; // register csrf_software_int_en_vec_0 - assign csrf_software_int_en_vec_0$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - csrf_mscratch_csr$D_IN[0] ; + assign csrf_software_int_en_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ; assign csrf_software_int_en_vec_0$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_software_int_en_vec_1 - assign csrf_software_int_en_vec_1$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - csrf_mscratch_csr$D_IN[1] ; + assign csrf_software_int_en_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ; assign csrf_software_int_en_vec_1$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_software_int_en_vec_3 - assign csrf_software_int_en_vec_3$D_IN = - MUX_csrf_external_int_en_vec_3$write_1__SEL_1 && - csrf_mscratch_csr$D_IN[3] ; + assign csrf_software_int_en_vec_3$D_IN = csrf_mscratch_csr$D_IN[3] ; assign csrf_software_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd22 || - WILL_FIRE_RL_rl_init ; + 6'd22 ; // register csrf_software_int_pend_vec_0 - assign csrf_software_int_pend_vec_0$D_IN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 && - csrf_mscratch_csr$D_IN[0] ; + assign csrf_software_int_pend_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ; assign csrf_software_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; // register csrf_software_int_pend_vec_1 - assign csrf_software_int_pend_vec_1$D_IN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 && - csrf_mscratch_csr$D_IN[1] ; + assign csrf_software_int_pend_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ; assign csrf_software_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; // register csrf_software_int_pend_vec_3 - always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or - csrf_mscratch_csr$D_IN or - MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or - MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or - WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: - csrf_software_int_pend_vec_3$D_IN = csrf_mscratch_csr$D_IN[3]; - MUX_csrf_software_int_pend_vec_3$write_1__SEL_2: - csrf_software_int_pend_vec_3$D_IN = - MUX_csrf_software_int_pend_vec_3$write_1__VAL_2; - WILL_FIRE_RL_rl_init: csrf_software_int_pend_vec_3$D_IN = 1'd0; - default: csrf_software_int_pend_vec_3$D_IN = - 1'b0 /* unspecified value */ ; - endcase + assign csrf_software_int_pend_vec_3$D_IN = + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 ? + csrf_mscratch_csr$D_IN[3] : + MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 ; assign csrf_software_int_pend_vec_3$EN = WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] && mmio_pRqQ_data_0[37:36] != 2'd0 && @@ -13320,26 +13109,17 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd29 || - WILL_FIRE_RL_rl_init ; + 6'd29 ; // register csrf_spp_reg - always@(MUX_csrf_spp_reg$write_1__SEL_1 or - MUX_csrf_spp_reg$write_1__VAL_1 or - MUX_csrf_ie_vec_1$write_1__SEL_2 or - csrf_prv_reg or WILL_FIRE_RL_rl_init) - case (1'b1) - MUX_csrf_spp_reg$write_1__SEL_1: - csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0]; - WILL_FIRE_RL_rl_init: csrf_spp_reg$D_IN = 1'd0; - default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; - endcase + assign csrf_spp_reg$D_IN = + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2891_ULE_1_4503_AND_IF_comm_ETC___d14542 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13355,7 +13135,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13383,59 +13163,56 @@ module mkCore(CLK, 6'd10 ; // register csrf_sum_reg - assign csrf_sum_reg$D_IN = - MUX_csrf_ie_vec_0$write_1__SEL_1 && csrf_sscratch_csr$D_IN[18] ; + assign csrf_sum_reg$D_IN = csrf_sscratch_csr$D_IN[18] ; assign csrf_sum_reg$EN = - MUX_csrf_ie_vec_0$write_1__SEL_1 || WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd8 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd18) ; // register csrf_time_reg - assign csrf_time_reg$D_IN = - WILL_FIRE_RL_rl_init ? 64'd0 : mmioToPlatform_setTime_t ; - assign csrf_time_reg$EN = - EN_mmioToPlatform_setTime || WILL_FIRE_RL_rl_init ; + assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ; + assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ; // register csrf_timer_int_en_vec_0 - assign csrf_timer_int_en_vec_0$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - csrf_sscratch_csr$D_IN[4] ; + assign csrf_timer_int_en_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ; assign csrf_timer_int_en_vec_0$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_timer_int_en_vec_1 - assign csrf_timer_int_en_vec_1$D_IN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 && - csrf_sscratch_csr$D_IN[5] ; + assign csrf_timer_int_en_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ; assign csrf_timer_int_en_vec_1$EN = - MUX_csrf_external_int_en_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + (IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd9 || + IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == + 6'd22) ; // register csrf_timer_int_en_vec_3 - assign csrf_timer_int_en_vec_3$D_IN = - MUX_csrf_external_int_en_vec_3$write_1__SEL_1 && - csrf_sscratch_csr$D_IN[7] ; + assign csrf_timer_int_en_vec_3$D_IN = csrf_sscratch_csr$D_IN[7] ; assign csrf_timer_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd22 || - WILL_FIRE_RL_rl_init ; + 6'd22 ; // register csrf_timer_int_pend_vec_0 - assign csrf_timer_int_pend_vec_0$D_IN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 && - csrf_sscratch_csr$D_IN[4] ; + assign csrf_timer_int_pend_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ; assign csrf_timer_int_pend_vec_0$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; // register csrf_timer_int_pend_vec_1 - assign csrf_timer_int_pend_vec_1$D_IN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 && - csrf_sscratch_csr$D_IN[5] ; + assign csrf_timer_int_pend_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ; assign csrf_timer_int_pend_vec_1$EN = - MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 || - WILL_FIRE_RL_rl_init ; + MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ; // register csrf_timer_int_pend_vec_3 assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ; @@ -13444,34 +13221,28 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] == 2'd2 ; // register csrf_tsr_reg - assign csrf_tsr_reg$D_IN = - MUX_csrf_mprv_reg$write_1__SEL_1 && csrf_sscratch_csr$D_IN[22] ; + assign csrf_tsr_reg$D_IN = csrf_sscratch_csr$D_IN[22] ; assign csrf_tsr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18 || - WILL_FIRE_RL_rl_init ; + 6'd18 ; // register csrf_tvm_reg - assign csrf_tvm_reg$D_IN = - MUX_csrf_mprv_reg$write_1__SEL_1 && csrf_sscratch_csr$D_IN[20] ; + assign csrf_tvm_reg$D_IN = csrf_sscratch_csr$D_IN[20] ; assign csrf_tvm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18 || - WILL_FIRE_RL_rl_init ; + 6'd18 ; // register csrf_tw_reg - assign csrf_tw_reg$D_IN = - MUX_csrf_mprv_reg$write_1__SEL_1 && csrf_sscratch_csr$D_IN[21] ; + assign csrf_tw_reg$D_IN = csrf_sscratch_csr$D_IN[21] ; assign csrf_tw_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd18 || - WILL_FIRE_RL_rl_init ; + 6'd18 ; // register csrf_vm_mode_sv39_reg assign csrf_vm_mode_sv39_reg$D_IN = csrf_sscratch_csr$D_IN[63] ; @@ -13504,7 +13275,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h45821, + { x__h45642, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -13516,7 +13287,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48357 } ; + x__h48178 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -13609,7 +13380,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h17914, + { x__h17735, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -13621,7 +13392,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20452 } ; + x__h20273 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -13705,7 +13476,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65615 } ; + x_data__h65436 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -13775,8 +13546,8 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register started - assign started$D_IN = !WILL_FIRE_RL_rl_init ; - assign started$EN = WILL_FIRE_RL_rl_init || EN_coreReq_start ; + assign started$D_IN = 1'd1 ; + assign started$EN = EN_coreReq_start ; // register update_vm_info assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_1 ; @@ -13886,8 +13657,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h644281, - x__h644282, + x__h644103, + x__h644104, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -14177,8 +13948,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h622251, - x__h622252, + x__h622073, + x__h622074, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -14220,7 +13991,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h671653 == 1'd1 && + (k__h671475 == 1'd1 && fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d12981, @@ -14241,7 +14012,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686863, + renaming_spec_bits__h686685, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14339,7 +14110,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h671653 == 1'd1 && + (k__h671475 == 1'd1 && fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085 || fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14203 == 1'd1 && @@ -14724,12 +14495,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h608025, - b__h607489 == 64'd0, - a__h607488, + { x__h607847, + b__h607311 == 64'd0, + a__h607310, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h608051, - a__h607488[63], + x__h607873, + a__h607310[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -14744,8 +14515,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h608037 : - b__h607489 ; + _theResult___snd__h607859 : + b__h607311 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14758,7 +14529,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h608665, + { x__h608487, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -14839,9 +14610,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h486164, - x__h486165, - x__h486166, + x__h485986, + x__h485987, + x__h485988, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12804 ; @@ -14893,7 +14664,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d13609, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686863, + renaming_spec_bits__h686685, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15051,8 +14822,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h290941, - x__h290953, + { x__h290763, + x__h290775, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890, @@ -15063,26 +14834,26 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921, - x__h292807, + x__h292629, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h289508 ; + x__h289330 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] : (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] : 3'd0) ; + assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or @@ -15706,13 +15477,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h184721[2:0], - vaddr__h184721, + coreFix_memExe_lsq$getOrigBE << vaddr__h184543[2:0], + vaddr__h184543, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h184721[2:0] != 3'd0 : + vaddr__h184543[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h184721[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184721[0]), + vaddr__h184543[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184543[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12804 ; @@ -15742,8 +15513,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h720885, - prv__h720885 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h720707, + prv__h720707 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15868,7 +15639,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3436_AND__ETC___d14154) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686863 ; + renaming_spec_bits__h686685 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3436_AND__ETC___d14162) ? @@ -15888,7 +15659,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3436_AND__ETC___d14162) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686863 ; + renaming_spec_bits__h686685 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15968,7 +15739,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184726 ; + shiftData__h184548 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -16068,8 +15839,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h184633, - x__h184634, + x__h184455, + x__h184456, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12804 ; @@ -16333,7 +16104,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2872_BIT_160__ETC___d14296, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686863, + renaming_spec_bits__h686685, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16557,12 +16328,7 @@ module mkCore(CLK, // submodule csrf_mcycle_ehr_data_dummy2_0 assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ; - assign csrf_mcycle_ehr_data_dummy2_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd30 || - WILL_FIRE_RL_rl_init ; + assign csrf_mcycle_ehr_data_dummy2_0$EN = csrf_mcycle_ehr_data_lat_0$whas ; // submodule csrf_mcycle_ehr_data_dummy2_1 assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ; @@ -16571,11 +16337,7 @@ module mkCore(CLK, // submodule csrf_minstret_ehr_data_dummy2_0 assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ; assign csrf_minstret_ehr_data_dummy2_0$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4363_BIT_181_4590_T_ETC___d14664 == - 6'd31 || - WILL_FIRE_RL_rl_init ; + csrf_minstret_ehr_data_lat_0$whas ; // submodule csrf_minstret_ehr_data_dummy2_1 assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ; @@ -16636,16 +16398,6 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; - // submodule f_init_reqs - assign f_init_reqs$ENQ = EN_init_server_request_put ; - assign f_init_reqs$DEQ = CAN_FIRE_RL_rl_init ; - assign f_init_reqs$CLR = 1'b0 ; - - // submodule f_init_rsps - assign f_init_rsps$ENQ = CAN_FIRE_RL_rl_init ; - assign f_init_rsps$DEQ = EN_init_server_response_get ; - assign f_init_rsps$CLR = 1'b0 ; - // submodule fetchStage assign fetchStage$iMemIfc_perf_req_r = 2'h0 ; assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ; @@ -17065,7 +16817,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h686863 ; + renaming_spec_bits__h686685 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17330,7 +17082,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14290, IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14349, 7'd32, - renaming_spec_bits__h686863 } ; + renaming_spec_bits__h686685 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17835,33 +17587,21 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h194420), + .amoExec_current_data(curData__h194242), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h195958)); + .amoExec(n__h195780)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h75651 }), - .amoExec_in_data({ 32'd0, x__h75766 }), + msip__h75472 }), + .amoExec_in_data({ 32'd0, x__h75587 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d882)); - module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q220, - { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q221, - coreFix_aluExe_0_regToExeQ$first[382], - coreFix_aluExe_0_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12710)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q223, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q224, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, coreFix_aluExe_1_regToExeQ$first[382], coreFix_aluExe_1_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), @@ -17870,12 +17610,24 @@ module mkCore(CLK, .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d12068)); + module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, + { coreFix_aluExe_0_regToExeQ$first[395], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, + coreFix_aluExe_0_regToExeQ$first[382], + coreFix_aluExe_0_regToExeQ$first[381:350] } }), + .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), + .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), + .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), + .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), + .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), + .basicExec(basicExec___d12710)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d12981, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2863_BITS_172_ETC___d13055 }, fetchStage$pipelines_0_first[160], - x_data_imm__h678934 } }), + x_data_imm__h678756 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17884,12 +17636,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h659462, - r1__read_BITS_13_TO_12___h659647 != + .checkForException_csrState({ x_decodeInfo_frm__h659284, + r1__read_BITS_13_TO_12___h659469 != 2'd0, - { prv__h720841, + { prv__h720663, csrf_tvm_reg, - { r1__read_BIT_20___h660275, + { r1__read_BIT_20___h660097, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17905,7 +17657,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d13609, { fetchStage_pipelines_1_first__2872_BIT_173_361_ETC___d13685, fetchStage$pipelines_1_first[160], - x_data_imm__h694584 } }), + x_data_imm__h694406 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17914,12 +17666,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h659462, - r1__read_BITS_13_TO_12___h659647 != + .checkForException_csrState({ x_decodeInfo_frm__h659284, + r1__read_BITS_13_TO_12___h659469 != 2'd0, - { prv__h720841, + { prv__h720663, csrf_tvm_reg, - { r1__read_BIT_20___h660275, + { r1__read_BIT_20___h660097, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17934,1196 +17686,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h486258), - .execFpuSimple_rVal2(rVal2__h486259), + .execFpuSimple_rVal1(rVal1__h486080), + .execFpuSimple_rVal2(rVal2__h486081), .execFpuSimple(execFpuSimple___d11167)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? - _theResult___snd__h358025 : - _theResult____h349851 ; + _theResult___snd__h357847 : + _theResult____h349673 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ? - _theResult___snd__h403722 : - _theResult____h395550 ; + _theResult___snd__h403544 : + _theResult____h395372 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ? - _theResult___snd__h449417 : - _theResult____h441245 ; + _theResult___snd__h449239 : + _theResult____h441067 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 ? - _theResult___snd__h515670 : - _theResult____h507371 ; + _theResult___snd__h515492 : + _theResult____h507193 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 ? - _theResult___snd__h593827 : - _theResult____h585528 ; + _theResult___snd__h593649 : + _theResult____h585350 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 ? - _theResult___snd__h554523 : - _theResult____h546224 ; + _theResult___snd__h554345 : + _theResult____h546046 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ? - _theResult___snd__h467183 : - _theResult____h458882 ; + _theResult___snd__h467005 : + _theResult____h458704 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ? - _theResult___snd__h375791 : - _theResult____h367490 ; + _theResult___snd__h375613 : + _theResult____h367312 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ? - _theResult___snd__h421488 : - _theResult____h413187 ; + _theResult___snd__h421310 : + _theResult____h413009 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 ? - _theResult___snd__h506019 : + _theResult___snd__h505841 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 ? - _theResult___snd__h506019 : - _theResult___snd__h524424 ; + _theResult___snd__h505841 : + _theResult___snd__h524246 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 ? - _theResult___snd__h584176 : + _theResult___snd__h583998 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 ? - _theResult___snd__h584176 : - _theResult___snd__h602581 ; + _theResult___snd__h583998 : + _theResult___snd__h602403 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 ? - _theResult___snd__h544872 : + _theResult___snd__h544694 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 ? - _theResult___snd__h544872 : - _theResult___snd__h563277 ; + _theResult___snd__h544694 : + _theResult___snd__h563099 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? - _theResult___snd__h457999 : - _theResult___snd__h475789 ; + _theResult___snd__h457821 : + _theResult___snd__h475611 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? - _theResult___snd__h366607 : + _theResult___snd__h366429 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ? - _theResult___snd__h366607 : - _theResult___snd__h384397 ; + _theResult___snd__h366429 : + _theResult___snd__h384219 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ? - _theResult___snd__h412304 : + _theResult___snd__h412126 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ? - _theResult___snd__h412304 : - _theResult___snd__h430094 ; + _theResult___snd__h412126 : + _theResult___snd__h429916 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? - _theResult___snd__h457999 : + _theResult___snd__h457821 : 57'd0 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h357962 == 8'd255) ? + ((_theResult___fst_exp__h357784 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) : - ((_theResult___fst_exp__h366618 == 8'd255) ? + ((_theResult___fst_exp__h366440 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h357962 == 8'd255) ? + ((_theResult___fst_exp__h357784 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) : - ((_theResult___fst_exp__h366618 == 8'd255) ? + ((_theResult___fst_exp__h366440 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h403659 == 8'd255) ? + ((_theResult___fst_exp__h403481 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) : - ((_theResult___fst_exp__h412315 == 8'd255) ? + ((_theResult___fst_exp__h412137 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h403659 == 8'd255) ? + ((_theResult___fst_exp__h403481 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) : - ((_theResult___fst_exp__h412315 == 8'd255) ? + ((_theResult___fst_exp__h412137 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h449354 == 8'd255) ? + ((_theResult___fst_exp__h449176 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) : - ((_theResult___fst_exp__h458010 == 8'd255) ? + ((_theResult___fst_exp__h457832 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h449354 == 8'd255) ? + ((_theResult___fst_exp__h449176 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) : - ((_theResult___fst_exp__h458010 == 8'd255) ? + ((_theResult___fst_exp__h457832 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 = - (_theResult____h349851[56] ? + (_theResult____h349673[56] ? 6'd0 : - (_theResult____h349851[55] ? + (_theResult____h349673[55] ? 6'd1 : - (_theResult____h349851[54] ? + (_theResult____h349673[54] ? 6'd2 : - (_theResult____h349851[53] ? + (_theResult____h349673[53] ? 6'd3 : - (_theResult____h349851[52] ? + (_theResult____h349673[52] ? 6'd4 : - (_theResult____h349851[51] ? + (_theResult____h349673[51] ? 6'd5 : - (_theResult____h349851[50] ? + (_theResult____h349673[50] ? 6'd6 : - (_theResult____h349851[49] ? + (_theResult____h349673[49] ? 6'd7 : - (_theResult____h349851[48] ? + (_theResult____h349673[48] ? 6'd8 : - (_theResult____h349851[47] ? + (_theResult____h349673[47] ? 6'd9 : - (_theResult____h349851[46] ? + (_theResult____h349673[46] ? 6'd10 : - (_theResult____h349851[45] ? + (_theResult____h349673[45] ? 6'd11 : - (_theResult____h349851[44] ? + (_theResult____h349673[44] ? 6'd12 : - (_theResult____h349851[43] ? + (_theResult____h349673[43] ? 6'd13 : - (_theResult____h349851[42] ? + (_theResult____h349673[42] ? 6'd14 : - (_theResult____h349851[41] ? + (_theResult____h349673[41] ? 6'd15 : - (_theResult____h349851[40] ? + (_theResult____h349673[40] ? 6'd16 : - (_theResult____h349851[39] ? + (_theResult____h349673[39] ? 6'd17 : - (_theResult____h349851[38] ? + (_theResult____h349673[38] ? 6'd18 : - (_theResult____h349851[37] ? + (_theResult____h349673[37] ? 6'd19 : - (_theResult____h349851[36] ? + (_theResult____h349673[36] ? 6'd20 : - (_theResult____h349851[35] ? + (_theResult____h349673[35] ? 6'd21 : - (_theResult____h349851[34] ? + (_theResult____h349673[34] ? 6'd22 : - (_theResult____h349851[33] ? + (_theResult____h349673[33] ? 6'd23 : - (_theResult____h349851[32] ? + (_theResult____h349673[32] ? 6'd24 : - (_theResult____h349851[31] ? + (_theResult____h349673[31] ? 6'd25 : - (_theResult____h349851[30] ? + (_theResult____h349673[30] ? 6'd26 : - (_theResult____h349851[29] ? + (_theResult____h349673[29] ? 6'd27 : - (_theResult____h349851[28] ? + (_theResult____h349673[28] ? 6'd28 : - (_theResult____h349851[27] ? + (_theResult____h349673[27] ? 6'd29 : - (_theResult____h349851[26] ? + (_theResult____h349673[26] ? 6'd30 : - (_theResult____h349851[25] ? + (_theResult____h349673[25] ? 6'd31 : - (_theResult____h349851[24] ? + (_theResult____h349673[24] ? 6'd32 : - (_theResult____h349851[23] ? + (_theResult____h349673[23] ? 6'd33 : - (_theResult____h349851[22] ? + (_theResult____h349673[22] ? 6'd34 : - (_theResult____h349851[21] ? + (_theResult____h349673[21] ? 6'd35 : - (_theResult____h349851[20] ? + (_theResult____h349673[20] ? 6'd36 : - (_theResult____h349851[19] ? + (_theResult____h349673[19] ? 6'd37 : - (_theResult____h349851[18] ? + (_theResult____h349673[18] ? 6'd38 : - (_theResult____h349851[17] ? + (_theResult____h349673[17] ? 6'd39 : - (_theResult____h349851[16] ? + (_theResult____h349673[16] ? 6'd40 : - (_theResult____h349851[15] ? + (_theResult____h349673[15] ? 6'd41 : - (_theResult____h349851[14] ? + (_theResult____h349673[14] ? 6'd42 : - (_theResult____h349851[13] ? + (_theResult____h349673[13] ? 6'd43 : - (_theResult____h349851[12] ? + (_theResult____h349673[12] ? 6'd44 : - (_theResult____h349851[11] ? + (_theResult____h349673[11] ? 6'd45 : - (_theResult____h349851[10] ? + (_theResult____h349673[10] ? 6'd46 : - (_theResult____h349851[9] ? + (_theResult____h349673[9] ? 6'd47 : - (_theResult____h349851[8] ? + (_theResult____h349673[8] ? 6'd48 : - (_theResult____h349851[7] ? + (_theResult____h349673[7] ? 6'd49 : - (_theResult____h349851[6] ? + (_theResult____h349673[6] ? 6'd50 : - (_theResult____h349851[5] ? + (_theResult____h349673[5] ? 6'd51 : - (_theResult____h349851[4] ? + (_theResult____h349673[4] ? 6'd52 : - (_theResult____h349851[3] ? + (_theResult____h349673[3] ? 6'd53 : - (_theResult____h349851[2] ? + (_theResult____h349673[2] ? 6'd54 : - (_theResult____h349851[1] ? + (_theResult____h349673[1] ? 6'd55 : - (_theResult____h349851[0] ? + (_theResult____h349673[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 = - (_theResult____h395550[56] ? + (_theResult____h395372[56] ? 6'd0 : - (_theResult____h395550[55] ? + (_theResult____h395372[55] ? 6'd1 : - (_theResult____h395550[54] ? + (_theResult____h395372[54] ? 6'd2 : - (_theResult____h395550[53] ? + (_theResult____h395372[53] ? 6'd3 : - (_theResult____h395550[52] ? + (_theResult____h395372[52] ? 6'd4 : - (_theResult____h395550[51] ? + (_theResult____h395372[51] ? 6'd5 : - (_theResult____h395550[50] ? + (_theResult____h395372[50] ? 6'd6 : - (_theResult____h395550[49] ? + (_theResult____h395372[49] ? 6'd7 : - (_theResult____h395550[48] ? + (_theResult____h395372[48] ? 6'd8 : - (_theResult____h395550[47] ? + (_theResult____h395372[47] ? 6'd9 : - (_theResult____h395550[46] ? + (_theResult____h395372[46] ? 6'd10 : - (_theResult____h395550[45] ? + (_theResult____h395372[45] ? 6'd11 : - (_theResult____h395550[44] ? + (_theResult____h395372[44] ? 6'd12 : - (_theResult____h395550[43] ? + (_theResult____h395372[43] ? 6'd13 : - (_theResult____h395550[42] ? + (_theResult____h395372[42] ? 6'd14 : - (_theResult____h395550[41] ? + (_theResult____h395372[41] ? 6'd15 : - (_theResult____h395550[40] ? + (_theResult____h395372[40] ? 6'd16 : - (_theResult____h395550[39] ? + (_theResult____h395372[39] ? 6'd17 : - (_theResult____h395550[38] ? + (_theResult____h395372[38] ? 6'd18 : - (_theResult____h395550[37] ? + (_theResult____h395372[37] ? 6'd19 : - (_theResult____h395550[36] ? + (_theResult____h395372[36] ? 6'd20 : - (_theResult____h395550[35] ? + (_theResult____h395372[35] ? 6'd21 : - (_theResult____h395550[34] ? + (_theResult____h395372[34] ? 6'd22 : - (_theResult____h395550[33] ? + (_theResult____h395372[33] ? 6'd23 : - (_theResult____h395550[32] ? + (_theResult____h395372[32] ? 6'd24 : - (_theResult____h395550[31] ? + (_theResult____h395372[31] ? 6'd25 : - (_theResult____h395550[30] ? + (_theResult____h395372[30] ? 6'd26 : - (_theResult____h395550[29] ? + (_theResult____h395372[29] ? 6'd27 : - (_theResult____h395550[28] ? + (_theResult____h395372[28] ? 6'd28 : - (_theResult____h395550[27] ? + (_theResult____h395372[27] ? 6'd29 : - (_theResult____h395550[26] ? + (_theResult____h395372[26] ? 6'd30 : - (_theResult____h395550[25] ? + (_theResult____h395372[25] ? 6'd31 : - (_theResult____h395550[24] ? + (_theResult____h395372[24] ? 6'd32 : - (_theResult____h395550[23] ? + (_theResult____h395372[23] ? 6'd33 : - (_theResult____h395550[22] ? + (_theResult____h395372[22] ? 6'd34 : - (_theResult____h395550[21] ? + (_theResult____h395372[21] ? 6'd35 : - (_theResult____h395550[20] ? + (_theResult____h395372[20] ? 6'd36 : - (_theResult____h395550[19] ? + (_theResult____h395372[19] ? 6'd37 : - (_theResult____h395550[18] ? + (_theResult____h395372[18] ? 6'd38 : - (_theResult____h395550[17] ? + (_theResult____h395372[17] ? 6'd39 : - (_theResult____h395550[16] ? + (_theResult____h395372[16] ? 6'd40 : - (_theResult____h395550[15] ? + (_theResult____h395372[15] ? 6'd41 : - (_theResult____h395550[14] ? + (_theResult____h395372[14] ? 6'd42 : - (_theResult____h395550[13] ? + (_theResult____h395372[13] ? 6'd43 : - (_theResult____h395550[12] ? + (_theResult____h395372[12] ? 6'd44 : - (_theResult____h395550[11] ? + (_theResult____h395372[11] ? 6'd45 : - (_theResult____h395550[10] ? + (_theResult____h395372[10] ? 6'd46 : - (_theResult____h395550[9] ? + (_theResult____h395372[9] ? 6'd47 : - (_theResult____h395550[8] ? + (_theResult____h395372[8] ? 6'd48 : - (_theResult____h395550[7] ? + (_theResult____h395372[7] ? 6'd49 : - (_theResult____h395550[6] ? + (_theResult____h395372[6] ? 6'd50 : - (_theResult____h395550[5] ? + (_theResult____h395372[5] ? 6'd51 : - (_theResult____h395550[4] ? + (_theResult____h395372[4] ? 6'd52 : - (_theResult____h395550[3] ? + (_theResult____h395372[3] ? 6'd53 : - (_theResult____h395550[2] ? + (_theResult____h395372[2] ? 6'd54 : - (_theResult____h395550[1] ? + (_theResult____h395372[1] ? 6'd55 : - (_theResult____h395550[0] ? + (_theResult____h395372[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 = - (_theResult____h441245[56] ? + (_theResult____h441067[56] ? 6'd0 : - (_theResult____h441245[55] ? + (_theResult____h441067[55] ? 6'd1 : - (_theResult____h441245[54] ? + (_theResult____h441067[54] ? 6'd2 : - (_theResult____h441245[53] ? + (_theResult____h441067[53] ? 6'd3 : - (_theResult____h441245[52] ? + (_theResult____h441067[52] ? 6'd4 : - (_theResult____h441245[51] ? + (_theResult____h441067[51] ? 6'd5 : - (_theResult____h441245[50] ? + (_theResult____h441067[50] ? 6'd6 : - (_theResult____h441245[49] ? + (_theResult____h441067[49] ? 6'd7 : - (_theResult____h441245[48] ? + (_theResult____h441067[48] ? 6'd8 : - (_theResult____h441245[47] ? + (_theResult____h441067[47] ? 6'd9 : - (_theResult____h441245[46] ? + (_theResult____h441067[46] ? 6'd10 : - (_theResult____h441245[45] ? + (_theResult____h441067[45] ? 6'd11 : - (_theResult____h441245[44] ? + (_theResult____h441067[44] ? 6'd12 : - (_theResult____h441245[43] ? + (_theResult____h441067[43] ? 6'd13 : - (_theResult____h441245[42] ? + (_theResult____h441067[42] ? 6'd14 : - (_theResult____h441245[41] ? + (_theResult____h441067[41] ? 6'd15 : - (_theResult____h441245[40] ? + (_theResult____h441067[40] ? 6'd16 : - (_theResult____h441245[39] ? + (_theResult____h441067[39] ? 6'd17 : - (_theResult____h441245[38] ? + (_theResult____h441067[38] ? 6'd18 : - (_theResult____h441245[37] ? + (_theResult____h441067[37] ? 6'd19 : - (_theResult____h441245[36] ? + (_theResult____h441067[36] ? 6'd20 : - (_theResult____h441245[35] ? + (_theResult____h441067[35] ? 6'd21 : - (_theResult____h441245[34] ? + (_theResult____h441067[34] ? 6'd22 : - (_theResult____h441245[33] ? + (_theResult____h441067[33] ? 6'd23 : - (_theResult____h441245[32] ? + (_theResult____h441067[32] ? 6'd24 : - (_theResult____h441245[31] ? + (_theResult____h441067[31] ? 6'd25 : - (_theResult____h441245[30] ? + (_theResult____h441067[30] ? 6'd26 : - (_theResult____h441245[29] ? + (_theResult____h441067[29] ? 6'd27 : - (_theResult____h441245[28] ? + (_theResult____h441067[28] ? 6'd28 : - (_theResult____h441245[27] ? + (_theResult____h441067[27] ? 6'd29 : - (_theResult____h441245[26] ? + (_theResult____h441067[26] ? 6'd30 : - (_theResult____h441245[25] ? + (_theResult____h441067[25] ? 6'd31 : - (_theResult____h441245[24] ? + (_theResult____h441067[24] ? 6'd32 : - (_theResult____h441245[23] ? + (_theResult____h441067[23] ? 6'd33 : - (_theResult____h441245[22] ? + (_theResult____h441067[22] ? 6'd34 : - (_theResult____h441245[21] ? + (_theResult____h441067[21] ? 6'd35 : - (_theResult____h441245[20] ? + (_theResult____h441067[20] ? 6'd36 : - (_theResult____h441245[19] ? + (_theResult____h441067[19] ? 6'd37 : - (_theResult____h441245[18] ? + (_theResult____h441067[18] ? 6'd38 : - (_theResult____h441245[17] ? + (_theResult____h441067[17] ? 6'd39 : - (_theResult____h441245[16] ? + (_theResult____h441067[16] ? 6'd40 : - (_theResult____h441245[15] ? + (_theResult____h441067[15] ? 6'd41 : - (_theResult____h441245[14] ? + (_theResult____h441067[14] ? 6'd42 : - (_theResult____h441245[13] ? + (_theResult____h441067[13] ? 6'd43 : - (_theResult____h441245[12] ? + (_theResult____h441067[12] ? 6'd44 : - (_theResult____h441245[11] ? + (_theResult____h441067[11] ? 6'd45 : - (_theResult____h441245[10] ? + (_theResult____h441067[10] ? 6'd46 : - (_theResult____h441245[9] ? + (_theResult____h441067[9] ? 6'd47 : - (_theResult____h441245[8] ? + (_theResult____h441067[8] ? 6'd48 : - (_theResult____h441245[7] ? + (_theResult____h441067[7] ? 6'd49 : - (_theResult____h441245[6] ? + (_theResult____h441067[6] ? 6'd50 : - (_theResult____h441245[5] ? + (_theResult____h441067[5] ? 6'd51 : - (_theResult____h441245[4] ? + (_theResult____h441067[4] ? 6'd52 : - (_theResult____h441245[3] ? + (_theResult____h441067[3] ? 6'd53 : - (_theResult____h441245[2] ? + (_theResult____h441067[2] ? 6'd54 : - (_theResult____h441245[1] ? + (_theResult____h441067[1] ? 6'd55 : - (_theResult____h441245[0] ? + (_theResult____h441067[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 = - (_theResult____h546224[56] ? + (_theResult____h546046[56] ? 6'd0 : - (_theResult____h546224[55] ? + (_theResult____h546046[55] ? 6'd1 : - (_theResult____h546224[54] ? + (_theResult____h546046[54] ? 6'd2 : - (_theResult____h546224[53] ? + (_theResult____h546046[53] ? 6'd3 : - (_theResult____h546224[52] ? + (_theResult____h546046[52] ? 6'd4 : - (_theResult____h546224[51] ? + (_theResult____h546046[51] ? 6'd5 : - (_theResult____h546224[50] ? + (_theResult____h546046[50] ? 6'd6 : - (_theResult____h546224[49] ? + (_theResult____h546046[49] ? 6'd7 : - (_theResult____h546224[48] ? + (_theResult____h546046[48] ? 6'd8 : - (_theResult____h546224[47] ? + (_theResult____h546046[47] ? 6'd9 : - (_theResult____h546224[46] ? + (_theResult____h546046[46] ? 6'd10 : - (_theResult____h546224[45] ? + (_theResult____h546046[45] ? 6'd11 : - (_theResult____h546224[44] ? + (_theResult____h546046[44] ? 6'd12 : - (_theResult____h546224[43] ? + (_theResult____h546046[43] ? 6'd13 : - (_theResult____h546224[42] ? + (_theResult____h546046[42] ? 6'd14 : - (_theResult____h546224[41] ? + (_theResult____h546046[41] ? 6'd15 : - (_theResult____h546224[40] ? + (_theResult____h546046[40] ? 6'd16 : - (_theResult____h546224[39] ? + (_theResult____h546046[39] ? 6'd17 : - (_theResult____h546224[38] ? + (_theResult____h546046[38] ? 6'd18 : - (_theResult____h546224[37] ? + (_theResult____h546046[37] ? 6'd19 : - (_theResult____h546224[36] ? + (_theResult____h546046[36] ? 6'd20 : - (_theResult____h546224[35] ? + (_theResult____h546046[35] ? 6'd21 : - (_theResult____h546224[34] ? + (_theResult____h546046[34] ? 6'd22 : - (_theResult____h546224[33] ? + (_theResult____h546046[33] ? 6'd23 : - (_theResult____h546224[32] ? + (_theResult____h546046[32] ? 6'd24 : - (_theResult____h546224[31] ? + (_theResult____h546046[31] ? 6'd25 : - (_theResult____h546224[30] ? + (_theResult____h546046[30] ? 6'd26 : - (_theResult____h546224[29] ? + (_theResult____h546046[29] ? 6'd27 : - (_theResult____h546224[28] ? + (_theResult____h546046[28] ? 6'd28 : - (_theResult____h546224[27] ? + (_theResult____h546046[27] ? 6'd29 : - (_theResult____h546224[26] ? + (_theResult____h546046[26] ? 6'd30 : - (_theResult____h546224[25] ? + (_theResult____h546046[25] ? 6'd31 : - (_theResult____h546224[24] ? + (_theResult____h546046[24] ? 6'd32 : - (_theResult____h546224[23] ? + (_theResult____h546046[23] ? 6'd33 : - (_theResult____h546224[22] ? + (_theResult____h546046[22] ? 6'd34 : - (_theResult____h546224[21] ? + (_theResult____h546046[21] ? 6'd35 : - (_theResult____h546224[20] ? + (_theResult____h546046[20] ? 6'd36 : - (_theResult____h546224[19] ? + (_theResult____h546046[19] ? 6'd37 : - (_theResult____h546224[18] ? + (_theResult____h546046[18] ? 6'd38 : - (_theResult____h546224[17] ? + (_theResult____h546046[17] ? 6'd39 : - (_theResult____h546224[16] ? + (_theResult____h546046[16] ? 6'd40 : - (_theResult____h546224[15] ? + (_theResult____h546046[15] ? 6'd41 : - (_theResult____h546224[14] ? + (_theResult____h546046[14] ? 6'd42 : - (_theResult____h546224[13] ? + (_theResult____h546046[13] ? 6'd43 : - (_theResult____h546224[12] ? + (_theResult____h546046[12] ? 6'd44 : - (_theResult____h546224[11] ? + (_theResult____h546046[11] ? 6'd45 : - (_theResult____h546224[10] ? + (_theResult____h546046[10] ? 6'd46 : - (_theResult____h546224[9] ? + (_theResult____h546046[9] ? 6'd47 : - (_theResult____h546224[8] ? + (_theResult____h546046[8] ? 6'd48 : - (_theResult____h546224[7] ? + (_theResult____h546046[7] ? 6'd49 : - (_theResult____h546224[6] ? + (_theResult____h546046[6] ? 6'd50 : - (_theResult____h546224[5] ? + (_theResult____h546046[5] ? 6'd51 : - (_theResult____h546224[4] ? + (_theResult____h546046[4] ? 6'd52 : - (_theResult____h546224[3] ? + (_theResult____h546046[3] ? 6'd53 : - (_theResult____h546224[2] ? + (_theResult____h546046[2] ? 6'd54 : - (_theResult____h546224[1] ? + (_theResult____h546046[1] ? 6'd55 : - (_theResult____h546224[0] ? + (_theResult____h546046[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 = - (_theResult____h507371[56] ? + (_theResult____h507193[56] ? 6'd0 : - (_theResult____h507371[55] ? + (_theResult____h507193[55] ? 6'd1 : - (_theResult____h507371[54] ? + (_theResult____h507193[54] ? 6'd2 : - (_theResult____h507371[53] ? + (_theResult____h507193[53] ? 6'd3 : - (_theResult____h507371[52] ? + (_theResult____h507193[52] ? 6'd4 : - (_theResult____h507371[51] ? + (_theResult____h507193[51] ? 6'd5 : - (_theResult____h507371[50] ? + (_theResult____h507193[50] ? 6'd6 : - (_theResult____h507371[49] ? + (_theResult____h507193[49] ? 6'd7 : - (_theResult____h507371[48] ? + (_theResult____h507193[48] ? 6'd8 : - (_theResult____h507371[47] ? + (_theResult____h507193[47] ? 6'd9 : - (_theResult____h507371[46] ? + (_theResult____h507193[46] ? 6'd10 : - (_theResult____h507371[45] ? + (_theResult____h507193[45] ? 6'd11 : - (_theResult____h507371[44] ? + (_theResult____h507193[44] ? 6'd12 : - (_theResult____h507371[43] ? + (_theResult____h507193[43] ? 6'd13 : - (_theResult____h507371[42] ? + (_theResult____h507193[42] ? 6'd14 : - (_theResult____h507371[41] ? + (_theResult____h507193[41] ? 6'd15 : - (_theResult____h507371[40] ? + (_theResult____h507193[40] ? 6'd16 : - (_theResult____h507371[39] ? + (_theResult____h507193[39] ? 6'd17 : - (_theResult____h507371[38] ? + (_theResult____h507193[38] ? 6'd18 : - (_theResult____h507371[37] ? + (_theResult____h507193[37] ? 6'd19 : - (_theResult____h507371[36] ? + (_theResult____h507193[36] ? 6'd20 : - (_theResult____h507371[35] ? + (_theResult____h507193[35] ? 6'd21 : - (_theResult____h507371[34] ? + (_theResult____h507193[34] ? 6'd22 : - (_theResult____h507371[33] ? + (_theResult____h507193[33] ? 6'd23 : - (_theResult____h507371[32] ? + (_theResult____h507193[32] ? 6'd24 : - (_theResult____h507371[31] ? + (_theResult____h507193[31] ? 6'd25 : - (_theResult____h507371[30] ? + (_theResult____h507193[30] ? 6'd26 : - (_theResult____h507371[29] ? + (_theResult____h507193[29] ? 6'd27 : - (_theResult____h507371[28] ? + (_theResult____h507193[28] ? 6'd28 : - (_theResult____h507371[27] ? + (_theResult____h507193[27] ? 6'd29 : - (_theResult____h507371[26] ? + (_theResult____h507193[26] ? 6'd30 : - (_theResult____h507371[25] ? + (_theResult____h507193[25] ? 6'd31 : - (_theResult____h507371[24] ? + (_theResult____h507193[24] ? 6'd32 : - (_theResult____h507371[23] ? + (_theResult____h507193[23] ? 6'd33 : - (_theResult____h507371[22] ? + (_theResult____h507193[22] ? 6'd34 : - (_theResult____h507371[21] ? + (_theResult____h507193[21] ? 6'd35 : - (_theResult____h507371[20] ? + (_theResult____h507193[20] ? 6'd36 : - (_theResult____h507371[19] ? + (_theResult____h507193[19] ? 6'd37 : - (_theResult____h507371[18] ? + (_theResult____h507193[18] ? 6'd38 : - (_theResult____h507371[17] ? + (_theResult____h507193[17] ? 6'd39 : - (_theResult____h507371[16] ? + (_theResult____h507193[16] ? 6'd40 : - (_theResult____h507371[15] ? + (_theResult____h507193[15] ? 6'd41 : - (_theResult____h507371[14] ? + (_theResult____h507193[14] ? 6'd42 : - (_theResult____h507371[13] ? + (_theResult____h507193[13] ? 6'd43 : - (_theResult____h507371[12] ? + (_theResult____h507193[12] ? 6'd44 : - (_theResult____h507371[11] ? + (_theResult____h507193[11] ? 6'd45 : - (_theResult____h507371[10] ? + (_theResult____h507193[10] ? 6'd46 : - (_theResult____h507371[9] ? + (_theResult____h507193[9] ? 6'd47 : - (_theResult____h507371[8] ? + (_theResult____h507193[8] ? 6'd48 : - (_theResult____h507371[7] ? + (_theResult____h507193[7] ? 6'd49 : - (_theResult____h507371[6] ? + (_theResult____h507193[6] ? 6'd50 : - (_theResult____h507371[5] ? + (_theResult____h507193[5] ? 6'd51 : - (_theResult____h507371[4] ? + (_theResult____h507193[4] ? 6'd52 : - (_theResult____h507371[3] ? + (_theResult____h507193[3] ? 6'd53 : - (_theResult____h507371[2] ? + (_theResult____h507193[2] ? 6'd54 : - (_theResult____h507371[1] ? + (_theResult____h507193[1] ? 6'd55 : - (_theResult____h507371[0] ? + (_theResult____h507193[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 = - (_theResult____h585528[56] ? + (_theResult____h585350[56] ? 6'd0 : - (_theResult____h585528[55] ? + (_theResult____h585350[55] ? 6'd1 : - (_theResult____h585528[54] ? + (_theResult____h585350[54] ? 6'd2 : - (_theResult____h585528[53] ? + (_theResult____h585350[53] ? 6'd3 : - (_theResult____h585528[52] ? + (_theResult____h585350[52] ? 6'd4 : - (_theResult____h585528[51] ? + (_theResult____h585350[51] ? 6'd5 : - (_theResult____h585528[50] ? + (_theResult____h585350[50] ? 6'd6 : - (_theResult____h585528[49] ? + (_theResult____h585350[49] ? 6'd7 : - (_theResult____h585528[48] ? + (_theResult____h585350[48] ? 6'd8 : - (_theResult____h585528[47] ? + (_theResult____h585350[47] ? 6'd9 : - (_theResult____h585528[46] ? + (_theResult____h585350[46] ? 6'd10 : - (_theResult____h585528[45] ? + (_theResult____h585350[45] ? 6'd11 : - (_theResult____h585528[44] ? + (_theResult____h585350[44] ? 6'd12 : - (_theResult____h585528[43] ? + (_theResult____h585350[43] ? 6'd13 : - (_theResult____h585528[42] ? + (_theResult____h585350[42] ? 6'd14 : - (_theResult____h585528[41] ? + (_theResult____h585350[41] ? 6'd15 : - (_theResult____h585528[40] ? + (_theResult____h585350[40] ? 6'd16 : - (_theResult____h585528[39] ? + (_theResult____h585350[39] ? 6'd17 : - (_theResult____h585528[38] ? + (_theResult____h585350[38] ? 6'd18 : - (_theResult____h585528[37] ? + (_theResult____h585350[37] ? 6'd19 : - (_theResult____h585528[36] ? + (_theResult____h585350[36] ? 6'd20 : - (_theResult____h585528[35] ? + (_theResult____h585350[35] ? 6'd21 : - (_theResult____h585528[34] ? + (_theResult____h585350[34] ? 6'd22 : - (_theResult____h585528[33] ? + (_theResult____h585350[33] ? 6'd23 : - (_theResult____h585528[32] ? + (_theResult____h585350[32] ? 6'd24 : - (_theResult____h585528[31] ? + (_theResult____h585350[31] ? 6'd25 : - (_theResult____h585528[30] ? + (_theResult____h585350[30] ? 6'd26 : - (_theResult____h585528[29] ? + (_theResult____h585350[29] ? 6'd27 : - (_theResult____h585528[28] ? + (_theResult____h585350[28] ? 6'd28 : - (_theResult____h585528[27] ? + (_theResult____h585350[27] ? 6'd29 : - (_theResult____h585528[26] ? + (_theResult____h585350[26] ? 6'd30 : - (_theResult____h585528[25] ? + (_theResult____h585350[25] ? 6'd31 : - (_theResult____h585528[24] ? + (_theResult____h585350[24] ? 6'd32 : - (_theResult____h585528[23] ? + (_theResult____h585350[23] ? 6'd33 : - (_theResult____h585528[22] ? + (_theResult____h585350[22] ? 6'd34 : - (_theResult____h585528[21] ? + (_theResult____h585350[21] ? 6'd35 : - (_theResult____h585528[20] ? + (_theResult____h585350[20] ? 6'd36 : - (_theResult____h585528[19] ? + (_theResult____h585350[19] ? 6'd37 : - (_theResult____h585528[18] ? + (_theResult____h585350[18] ? 6'd38 : - (_theResult____h585528[17] ? + (_theResult____h585350[17] ? 6'd39 : - (_theResult____h585528[16] ? + (_theResult____h585350[16] ? 6'd40 : - (_theResult____h585528[15] ? + (_theResult____h585350[15] ? 6'd41 : - (_theResult____h585528[14] ? + (_theResult____h585350[14] ? 6'd42 : - (_theResult____h585528[13] ? + (_theResult____h585350[13] ? 6'd43 : - (_theResult____h585528[12] ? + (_theResult____h585350[12] ? 6'd44 : - (_theResult____h585528[11] ? + (_theResult____h585350[11] ? 6'd45 : - (_theResult____h585528[10] ? + (_theResult____h585350[10] ? 6'd46 : - (_theResult____h585528[9] ? + (_theResult____h585350[9] ? 6'd47 : - (_theResult____h585528[8] ? + (_theResult____h585350[8] ? 6'd48 : - (_theResult____h585528[7] ? + (_theResult____h585350[7] ? 6'd49 : - (_theResult____h585528[6] ? + (_theResult____h585350[6] ? 6'd50 : - (_theResult____h585528[5] ? + (_theResult____h585350[5] ? 6'd51 : - (_theResult____h585528[4] ? + (_theResult____h585350[4] ? 6'd52 : - (_theResult____h585528[3] ? + (_theResult____h585350[3] ? 6'd53 : - (_theResult____h585528[2] ? + (_theResult____h585350[2] ? 6'd54 : - (_theResult____h585528[1] ? + (_theResult____h585350[1] ? 6'd55 : - (_theResult____h585528[0] ? + (_theResult____h585350[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 = - (_theResult____h367490[56] ? + (_theResult____h367312[56] ? 6'd0 : - (_theResult____h367490[55] ? + (_theResult____h367312[55] ? 6'd1 : - (_theResult____h367490[54] ? + (_theResult____h367312[54] ? 6'd2 : - (_theResult____h367490[53] ? + (_theResult____h367312[53] ? 6'd3 : - (_theResult____h367490[52] ? + (_theResult____h367312[52] ? 6'd4 : - (_theResult____h367490[51] ? + (_theResult____h367312[51] ? 6'd5 : - (_theResult____h367490[50] ? + (_theResult____h367312[50] ? 6'd6 : - (_theResult____h367490[49] ? + (_theResult____h367312[49] ? 6'd7 : - (_theResult____h367490[48] ? + (_theResult____h367312[48] ? 6'd8 : - (_theResult____h367490[47] ? + (_theResult____h367312[47] ? 6'd9 : - (_theResult____h367490[46] ? + (_theResult____h367312[46] ? 6'd10 : - (_theResult____h367490[45] ? + (_theResult____h367312[45] ? 6'd11 : - (_theResult____h367490[44] ? + (_theResult____h367312[44] ? 6'd12 : - (_theResult____h367490[43] ? + (_theResult____h367312[43] ? 6'd13 : - (_theResult____h367490[42] ? + (_theResult____h367312[42] ? 6'd14 : - (_theResult____h367490[41] ? + (_theResult____h367312[41] ? 6'd15 : - (_theResult____h367490[40] ? + (_theResult____h367312[40] ? 6'd16 : - (_theResult____h367490[39] ? + (_theResult____h367312[39] ? 6'd17 : - (_theResult____h367490[38] ? + (_theResult____h367312[38] ? 6'd18 : - (_theResult____h367490[37] ? + (_theResult____h367312[37] ? 6'd19 : - (_theResult____h367490[36] ? + (_theResult____h367312[36] ? 6'd20 : - (_theResult____h367490[35] ? + (_theResult____h367312[35] ? 6'd21 : - (_theResult____h367490[34] ? + (_theResult____h367312[34] ? 6'd22 : - (_theResult____h367490[33] ? + (_theResult____h367312[33] ? 6'd23 : - (_theResult____h367490[32] ? + (_theResult____h367312[32] ? 6'd24 : - (_theResult____h367490[31] ? + (_theResult____h367312[31] ? 6'd25 : - (_theResult____h367490[30] ? + (_theResult____h367312[30] ? 6'd26 : - (_theResult____h367490[29] ? + (_theResult____h367312[29] ? 6'd27 : - (_theResult____h367490[28] ? + (_theResult____h367312[28] ? 6'd28 : - (_theResult____h367490[27] ? + (_theResult____h367312[27] ? 6'd29 : - (_theResult____h367490[26] ? + (_theResult____h367312[26] ? 6'd30 : - (_theResult____h367490[25] ? + (_theResult____h367312[25] ? 6'd31 : - (_theResult____h367490[24] ? + (_theResult____h367312[24] ? 6'd32 : - (_theResult____h367490[23] ? + (_theResult____h367312[23] ? 6'd33 : - (_theResult____h367490[22] ? + (_theResult____h367312[22] ? 6'd34 : - (_theResult____h367490[21] ? + (_theResult____h367312[21] ? 6'd35 : - (_theResult____h367490[20] ? + (_theResult____h367312[20] ? 6'd36 : - (_theResult____h367490[19] ? + (_theResult____h367312[19] ? 6'd37 : - (_theResult____h367490[18] ? + (_theResult____h367312[18] ? 6'd38 : - (_theResult____h367490[17] ? + (_theResult____h367312[17] ? 6'd39 : - (_theResult____h367490[16] ? + (_theResult____h367312[16] ? 6'd40 : - (_theResult____h367490[15] ? + (_theResult____h367312[15] ? 6'd41 : - (_theResult____h367490[14] ? + (_theResult____h367312[14] ? 6'd42 : - (_theResult____h367490[13] ? + (_theResult____h367312[13] ? 6'd43 : - (_theResult____h367490[12] ? + (_theResult____h367312[12] ? 6'd44 : - (_theResult____h367490[11] ? + (_theResult____h367312[11] ? 6'd45 : - (_theResult____h367490[10] ? + (_theResult____h367312[10] ? 6'd46 : - (_theResult____h367490[9] ? + (_theResult____h367312[9] ? 6'd47 : - (_theResult____h367490[8] ? + (_theResult____h367312[8] ? 6'd48 : - (_theResult____h367490[7] ? + (_theResult____h367312[7] ? 6'd49 : - (_theResult____h367490[6] ? + (_theResult____h367312[6] ? 6'd50 : - (_theResult____h367490[5] ? + (_theResult____h367312[5] ? 6'd51 : - (_theResult____h367490[4] ? + (_theResult____h367312[4] ? 6'd52 : - (_theResult____h367490[3] ? + (_theResult____h367312[3] ? 6'd53 : - (_theResult____h367490[2] ? + (_theResult____h367312[2] ? 6'd54 : - (_theResult____h367490[1] ? + (_theResult____h367312[1] ? 6'd55 : - (_theResult____h367490[0] ? + (_theResult____h367312[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 = - (_theResult____h413187[56] ? + (_theResult____h413009[56] ? 6'd0 : - (_theResult____h413187[55] ? + (_theResult____h413009[55] ? 6'd1 : - (_theResult____h413187[54] ? + (_theResult____h413009[54] ? 6'd2 : - (_theResult____h413187[53] ? + (_theResult____h413009[53] ? 6'd3 : - (_theResult____h413187[52] ? + (_theResult____h413009[52] ? 6'd4 : - (_theResult____h413187[51] ? + (_theResult____h413009[51] ? 6'd5 : - (_theResult____h413187[50] ? + (_theResult____h413009[50] ? 6'd6 : - (_theResult____h413187[49] ? + (_theResult____h413009[49] ? 6'd7 : - (_theResult____h413187[48] ? + (_theResult____h413009[48] ? 6'd8 : - (_theResult____h413187[47] ? + (_theResult____h413009[47] ? 6'd9 : - (_theResult____h413187[46] ? + (_theResult____h413009[46] ? 6'd10 : - (_theResult____h413187[45] ? + (_theResult____h413009[45] ? 6'd11 : - (_theResult____h413187[44] ? + (_theResult____h413009[44] ? 6'd12 : - (_theResult____h413187[43] ? + (_theResult____h413009[43] ? 6'd13 : - (_theResult____h413187[42] ? + (_theResult____h413009[42] ? 6'd14 : - (_theResult____h413187[41] ? + (_theResult____h413009[41] ? 6'd15 : - (_theResult____h413187[40] ? + (_theResult____h413009[40] ? 6'd16 : - (_theResult____h413187[39] ? + (_theResult____h413009[39] ? 6'd17 : - (_theResult____h413187[38] ? + (_theResult____h413009[38] ? 6'd18 : - (_theResult____h413187[37] ? + (_theResult____h413009[37] ? 6'd19 : - (_theResult____h413187[36] ? + (_theResult____h413009[36] ? 6'd20 : - (_theResult____h413187[35] ? + (_theResult____h413009[35] ? 6'd21 : - (_theResult____h413187[34] ? + (_theResult____h413009[34] ? 6'd22 : - (_theResult____h413187[33] ? + (_theResult____h413009[33] ? 6'd23 : - (_theResult____h413187[32] ? + (_theResult____h413009[32] ? 6'd24 : - (_theResult____h413187[31] ? + (_theResult____h413009[31] ? 6'd25 : - (_theResult____h413187[30] ? + (_theResult____h413009[30] ? 6'd26 : - (_theResult____h413187[29] ? + (_theResult____h413009[29] ? 6'd27 : - (_theResult____h413187[28] ? + (_theResult____h413009[28] ? 6'd28 : - (_theResult____h413187[27] ? + (_theResult____h413009[27] ? 6'd29 : - (_theResult____h413187[26] ? + (_theResult____h413009[26] ? 6'd30 : - (_theResult____h413187[25] ? + (_theResult____h413009[25] ? 6'd31 : - (_theResult____h413187[24] ? + (_theResult____h413009[24] ? 6'd32 : - (_theResult____h413187[23] ? + (_theResult____h413009[23] ? 6'd33 : - (_theResult____h413187[22] ? + (_theResult____h413009[22] ? 6'd34 : - (_theResult____h413187[21] ? + (_theResult____h413009[21] ? 6'd35 : - (_theResult____h413187[20] ? + (_theResult____h413009[20] ? 6'd36 : - (_theResult____h413187[19] ? + (_theResult____h413009[19] ? 6'd37 : - (_theResult____h413187[18] ? + (_theResult____h413009[18] ? 6'd38 : - (_theResult____h413187[17] ? + (_theResult____h413009[17] ? 6'd39 : - (_theResult____h413187[16] ? + (_theResult____h413009[16] ? 6'd40 : - (_theResult____h413187[15] ? + (_theResult____h413009[15] ? 6'd41 : - (_theResult____h413187[14] ? + (_theResult____h413009[14] ? 6'd42 : - (_theResult____h413187[13] ? + (_theResult____h413009[13] ? 6'd43 : - (_theResult____h413187[12] ? + (_theResult____h413009[12] ? 6'd44 : - (_theResult____h413187[11] ? + (_theResult____h413009[11] ? 6'd45 : - (_theResult____h413187[10] ? + (_theResult____h413009[10] ? 6'd46 : - (_theResult____h413187[9] ? + (_theResult____h413009[9] ? 6'd47 : - (_theResult____h413187[8] ? + (_theResult____h413009[8] ? 6'd48 : - (_theResult____h413187[7] ? + (_theResult____h413009[7] ? 6'd49 : - (_theResult____h413187[6] ? + (_theResult____h413009[6] ? 6'd50 : - (_theResult____h413187[5] ? + (_theResult____h413009[5] ? 6'd51 : - (_theResult____h413187[4] ? + (_theResult____h413009[4] ? 6'd52 : - (_theResult____h413187[3] ? + (_theResult____h413009[3] ? 6'd53 : - (_theResult____h413187[2] ? + (_theResult____h413009[2] ? 6'd54 : - (_theResult____h413187[1] ? + (_theResult____h413009[1] ? 6'd55 : - (_theResult____h413187[0] ? + (_theResult____h413009[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 = - (_theResult____h458882[56] ? + (_theResult____h458704[56] ? 6'd0 : - (_theResult____h458882[55] ? + (_theResult____h458704[55] ? 6'd1 : - (_theResult____h458882[54] ? + (_theResult____h458704[54] ? 6'd2 : - (_theResult____h458882[53] ? + (_theResult____h458704[53] ? 6'd3 : - (_theResult____h458882[52] ? + (_theResult____h458704[52] ? 6'd4 : - (_theResult____h458882[51] ? + (_theResult____h458704[51] ? 6'd5 : - (_theResult____h458882[50] ? + (_theResult____h458704[50] ? 6'd6 : - (_theResult____h458882[49] ? + (_theResult____h458704[49] ? 6'd7 : - (_theResult____h458882[48] ? + (_theResult____h458704[48] ? 6'd8 : - (_theResult____h458882[47] ? + (_theResult____h458704[47] ? 6'd9 : - (_theResult____h458882[46] ? + (_theResult____h458704[46] ? 6'd10 : - (_theResult____h458882[45] ? + (_theResult____h458704[45] ? 6'd11 : - (_theResult____h458882[44] ? + (_theResult____h458704[44] ? 6'd12 : - (_theResult____h458882[43] ? + (_theResult____h458704[43] ? 6'd13 : - (_theResult____h458882[42] ? + (_theResult____h458704[42] ? 6'd14 : - (_theResult____h458882[41] ? + (_theResult____h458704[41] ? 6'd15 : - (_theResult____h458882[40] ? + (_theResult____h458704[40] ? 6'd16 : - (_theResult____h458882[39] ? + (_theResult____h458704[39] ? 6'd17 : - (_theResult____h458882[38] ? + (_theResult____h458704[38] ? 6'd18 : - (_theResult____h458882[37] ? + (_theResult____h458704[37] ? 6'd19 : - (_theResult____h458882[36] ? + (_theResult____h458704[36] ? 6'd20 : - (_theResult____h458882[35] ? + (_theResult____h458704[35] ? 6'd21 : - (_theResult____h458882[34] ? + (_theResult____h458704[34] ? 6'd22 : - (_theResult____h458882[33] ? + (_theResult____h458704[33] ? 6'd23 : - (_theResult____h458882[32] ? + (_theResult____h458704[32] ? 6'd24 : - (_theResult____h458882[31] ? + (_theResult____h458704[31] ? 6'd25 : - (_theResult____h458882[30] ? + (_theResult____h458704[30] ? 6'd26 : - (_theResult____h458882[29] ? + (_theResult____h458704[29] ? 6'd27 : - (_theResult____h458882[28] ? + (_theResult____h458704[28] ? 6'd28 : - (_theResult____h458882[27] ? + (_theResult____h458704[27] ? 6'd29 : - (_theResult____h458882[26] ? + (_theResult____h458704[26] ? 6'd30 : - (_theResult____h458882[25] ? + (_theResult____h458704[25] ? 6'd31 : - (_theResult____h458882[24] ? + (_theResult____h458704[24] ? 6'd32 : - (_theResult____h458882[23] ? + (_theResult____h458704[23] ? 6'd33 : - (_theResult____h458882[22] ? + (_theResult____h458704[22] ? 6'd34 : - (_theResult____h458882[21] ? + (_theResult____h458704[21] ? 6'd35 : - (_theResult____h458882[20] ? + (_theResult____h458704[20] ? 6'd36 : - (_theResult____h458882[19] ? + (_theResult____h458704[19] ? 6'd37 : - (_theResult____h458882[18] ? + (_theResult____h458704[18] ? 6'd38 : - (_theResult____h458882[17] ? + (_theResult____h458704[17] ? 6'd39 : - (_theResult____h458882[16] ? + (_theResult____h458704[16] ? 6'd40 : - (_theResult____h458882[15] ? + (_theResult____h458704[15] ? 6'd41 : - (_theResult____h458882[14] ? + (_theResult____h458704[14] ? 6'd42 : - (_theResult____h458882[13] ? + (_theResult____h458704[13] ? 6'd43 : - (_theResult____h458882[12] ? + (_theResult____h458704[12] ? 6'd44 : - (_theResult____h458882[11] ? + (_theResult____h458704[11] ? 6'd45 : - (_theResult____h458882[10] ? + (_theResult____h458704[10] ? 6'd46 : - (_theResult____h458882[9] ? + (_theResult____h458704[9] ? 6'd47 : - (_theResult____h458882[8] ? + (_theResult____h458704[8] ? 6'd48 : - (_theResult____h458882[7] ? + (_theResult____h458704[7] ? 6'd49 : - (_theResult____h458882[6] ? + (_theResult____h458704[6] ? 6'd50 : - (_theResult____h458882[5] ? + (_theResult____h458704[5] ? 6'd51 : - (_theResult____h458882[4] ? + (_theResult____h458704[4] ? 6'd52 : - (_theResult____h458882[3] ? + (_theResult____h458704[3] ? 6'd53 : - (_theResult____h458882[2] ? + (_theResult____h458704[2] ? 6'd54 : - (_theResult____h458882[1] ? + (_theResult____h458704[1] ? 6'd55 : - (_theResult____h458882[0] ? + (_theResult____h458704[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 = - (_theResult___fst_exp__h593764 == 11'd2047) ? + (_theResult___fst_exp__h593586 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19131,10 +18883,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard85360_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 = - (_theResult___fst_exp__h554460 == 11'd2047) ? + (_theResult___fst_exp__h554282 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19142,10 +18894,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46234_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; + CASE_guard46056_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 = - (_theResult___fst_exp__h554460 == 11'd2047) ? + (_theResult___fst_exp__h554282 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19153,10 +18905,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46234_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard46056_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 = - (_theResult___fst_exp__h515607 == 11'd2047) ? + (_theResult___fst_exp__h515429 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19164,10 +18916,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07381_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard07203_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 = - (_theResult___fst_exp__h593764 == 11'd2047) ? + (_theResult___fst_exp__h593586 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19175,538 +18927,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard85360_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = - (guard__h349861 == 2'b0 || + (guard__h349683 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h357962 : - _theResult___exp__h358478 ; + _theResult___fst_exp__h357784 : + _theResult___exp__h358300 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 = - (guard__h349861 == 2'b0) ? - _theResult___fst_exp__h357962 : + (guard__h349683 == 2'b0) ? + _theResult___fst_exp__h357784 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h358478 : - _theResult___fst_exp__h357962) ; + _theResult___exp__h358300 : + _theResult___fst_exp__h357784) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 = - (guard__h349861 == 2'b0 || + (guard__h349683 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h357956[56:34] : - _theResult___sfd__h358479 ; + sfdin__h357778[56:34] : + _theResult___sfd__h358301 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 = - (guard__h349861 == 2'b0) ? - sfdin__h357956[56:34] : + (guard__h349683 == 2'b0) ? + sfdin__h357778[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h358479 : - sfdin__h357956[56:34]) ; + _theResult___sfd__h358301 : + sfdin__h357778[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 = - (guard__h395560 == 2'b0 || + (guard__h395382 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h403659 : - _theResult___exp__h404175 ; + _theResult___fst_exp__h403481 : + _theResult___exp__h403997 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 = - (guard__h395560 == 2'b0) ? - _theResult___fst_exp__h403659 : + (guard__h395382 == 2'b0) ? + _theResult___fst_exp__h403481 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h404175 : - _theResult___fst_exp__h403659) ; + _theResult___exp__h403997 : + _theResult___fst_exp__h403481) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 = - (guard__h395560 == 2'b0 || + (guard__h395382 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h403653[56:34] : - _theResult___sfd__h404176 ; + sfdin__h403475[56:34] : + _theResult___sfd__h403998 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 = - (guard__h395560 == 2'b0) ? - sfdin__h403653[56:34] : + (guard__h395382 == 2'b0) ? + sfdin__h403475[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h404176 : - sfdin__h403653[56:34]) ; + _theResult___sfd__h403998 : + sfdin__h403475[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 = - (guard__h441255 == 2'b0 || + (guard__h441077 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h449354 : - _theResult___exp__h449870 ; + _theResult___fst_exp__h449176 : + _theResult___exp__h449692 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 = - (guard__h441255 == 2'b0) ? - _theResult___fst_exp__h449354 : + (guard__h441077 == 2'b0) ? + _theResult___fst_exp__h449176 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h449870 : - _theResult___fst_exp__h449354) ; + _theResult___exp__h449692 : + _theResult___fst_exp__h449176) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 = - (guard__h441255 == 2'b0 || + (guard__h441077 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h449348[56:34] : - _theResult___sfd__h449871 ; + sfdin__h449170[56:34] : + _theResult___sfd__h449693 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 = - (guard__h441255 == 2'b0) ? - sfdin__h449348[56:34] : + (guard__h441077 == 2'b0) ? + sfdin__h449170[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h449871 : - sfdin__h449348[56:34]) ; + _theResult___sfd__h449693 : + sfdin__h449170[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 = - (guard__h546234 == 2'b0 || + (guard__h546056 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h554460 : - _theResult___exp__h555189 ; + _theResult___fst_exp__h554282 : + _theResult___exp__h555011 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 = - (guard__h546234 == 2'b0) ? - _theResult___fst_exp__h554460 : + (guard__h546056 == 2'b0) ? + _theResult___fst_exp__h554282 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h555189 : - _theResult___fst_exp__h554460) ; + _theResult___exp__h555011 : + _theResult___fst_exp__h554282) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 = - (guard__h546234 == 2'b0 || + (guard__h546056 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h554454[56:5] : - _theResult___sfd__h555190 ; + sfdin__h554276[56:5] : + _theResult___sfd__h555012 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 = - (guard__h546234 == 2'b0) ? - sfdin__h554454[56:5] : + (guard__h546056 == 2'b0) ? + sfdin__h554276[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h555190 : - sfdin__h554454[56:5]) ; + _theResult___sfd__h555012 : + sfdin__h554276[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 = - (guard__h507381 == 2'b0 || + (guard__h507203 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h515607 : - _theResult___exp__h516336 ; + _theResult___fst_exp__h515429 : + _theResult___exp__h516158 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 = - (guard__h507381 == 2'b0) ? - _theResult___fst_exp__h515607 : + (guard__h507203 == 2'b0) ? + _theResult___fst_exp__h515429 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h516336 : - _theResult___fst_exp__h515607) ; + _theResult___exp__h516158 : + _theResult___fst_exp__h515429) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 = - (guard__h507381 == 2'b0 || + (guard__h507203 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h515601[56:5] : - _theResult___sfd__h516337 ; + sfdin__h515423[56:5] : + _theResult___sfd__h516159 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 = - (guard__h507381 == 2'b0) ? - sfdin__h515601[56:5] : + (guard__h507203 == 2'b0) ? + sfdin__h515423[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h516337 : - sfdin__h515601[56:5]) ; + _theResult___sfd__h516159 : + sfdin__h515423[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 = - (guard__h585538 == 2'b0 || + (guard__h585360 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h593764 : - _theResult___exp__h594493 ; + _theResult___fst_exp__h593586 : + _theResult___exp__h594315 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 = - (guard__h585538 == 2'b0) ? - _theResult___fst_exp__h593764 : + (guard__h585360 == 2'b0) ? + _theResult___fst_exp__h593586 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h594493 : - _theResult___fst_exp__h593764) ; + _theResult___exp__h594315 : + _theResult___fst_exp__h593586) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 = - (guard__h585538 == 2'b0 || + (guard__h585360 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h593758[56:5] : - _theResult___sfd__h594494 ; + sfdin__h593580[56:5] : + _theResult___sfd__h594316 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 = - (guard__h585538 == 2'b0) ? - sfdin__h593758[56:5] : + (guard__h585360 == 2'b0) ? + sfdin__h593580[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h594494 : - sfdin__h593758[56:5]) ; + _theResult___sfd__h594316 : + sfdin__h593580[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 = - (guard__h367500 == 2'b0 || + (guard__h367322 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h375728 : - _theResult___exp__h376244 ; + _theResult___fst_exp__h375550 : + _theResult___exp__h376066 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 = - (guard__h367500 == 2'b0) ? - _theResult___fst_exp__h375728 : + (guard__h367322 == 2'b0) ? + _theResult___fst_exp__h375550 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h376244 : - _theResult___fst_exp__h375728) ; + _theResult___exp__h376066 : + _theResult___fst_exp__h375550) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 = - (guard__h367500 == 2'b0 || + (guard__h367322 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h375722[56:34] : - _theResult___sfd__h376245 ; + sfdin__h375544[56:34] : + _theResult___sfd__h376067 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 = - (guard__h367500 == 2'b0) ? - sfdin__h375722[56:34] : + (guard__h367322 == 2'b0) ? + sfdin__h375544[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h376245 : - sfdin__h375722[56:34]) ; + _theResult___sfd__h376067 : + sfdin__h375544[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 = - (guard__h413197 == 2'b0 || + (guard__h413019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h421425 : - _theResult___exp__h421941 ; + _theResult___fst_exp__h421247 : + _theResult___exp__h421763 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 = - (guard__h413197 == 2'b0) ? - _theResult___fst_exp__h421425 : + (guard__h413019 == 2'b0) ? + _theResult___fst_exp__h421247 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h421941 : - _theResult___fst_exp__h421425) ; + _theResult___exp__h421763 : + _theResult___fst_exp__h421247) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 = - (guard__h413197 == 2'b0 || + (guard__h413019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h421419[56:34] : - _theResult___sfd__h421942 ; + sfdin__h421241[56:34] : + _theResult___sfd__h421764 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 = - (guard__h413197 == 2'b0) ? - sfdin__h421419[56:34] : + (guard__h413019 == 2'b0) ? + sfdin__h421241[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h421942 : - sfdin__h421419[56:34]) ; + _theResult___sfd__h421764 : + sfdin__h421241[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 = - (guard__h458892 == 2'b0 || + (guard__h458714 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h467120 : - _theResult___exp__h467636 ; + _theResult___fst_exp__h466942 : + _theResult___exp__h467458 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 = - (guard__h458892 == 2'b0) ? - _theResult___fst_exp__h467120 : + (guard__h458714 == 2'b0) ? + _theResult___fst_exp__h466942 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h467636 : - _theResult___fst_exp__h467120) ; + _theResult___exp__h467458 : + _theResult___fst_exp__h466942) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 = - (guard__h458892 == 2'b0 || + (guard__h458714 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h467114[56:34] : - _theResult___sfd__h467637 ; + sfdin__h466936[56:34] : + _theResult___sfd__h467459 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 = - (guard__h458892 == 2'b0) ? - sfdin__h467114[56:34] : + (guard__h458714 == 2'b0) ? + sfdin__h466936[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h467637 : - sfdin__h467114[56:34]) ; + _theResult___sfd__h467459 : + sfdin__h466936[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 = - (guard__h536922 == 2'b0 || + (guard__h536744 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h544883 : - _theResult___exp__h545538 ; + _theResult___fst_exp__h544705 : + _theResult___exp__h545360 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 = - (guard__h536922 == 2'b0) ? - _theResult___fst_exp__h544883 : + (guard__h536744 == 2'b0) ? + _theResult___fst_exp__h544705 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h545538 : - _theResult___fst_exp__h544883) ; + _theResult___exp__h545360 : + _theResult___fst_exp__h544705) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 = - (guard__h555303 == 2'b0 || + (guard__h555125 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h563293 : - _theResult___exp__h563973 ; + _theResult___fst_exp__h563115 : + _theResult___exp__h563795 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 = - (guard__h555303 == 2'b0) ? - _theResult___fst_exp__h563293 : + (guard__h555125 == 2'b0) ? + _theResult___fst_exp__h563115 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h563973 : - _theResult___fst_exp__h563293) ; + _theResult___exp__h563795 : + _theResult___fst_exp__h563115) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 = - (guard__h536922 == 2'b0 || + (guard__h536744 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h544834[56:5] : - _theResult___sfd__h545539 ; + _theResult___snd__h544656[56:5] : + _theResult___sfd__h545361 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 = - (guard__h536922 == 2'b0) ? - _theResult___snd__h544834[56:5] : + (guard__h536744 == 2'b0) ? + _theResult___snd__h544656[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h545539 : - _theResult___snd__h544834[56:5]) ; + _theResult___sfd__h545361 : + _theResult___snd__h544656[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 = - (guard__h555303 == 2'b0 || + (guard__h555125 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h563239[56:5] : - _theResult___sfd__h563974 ; + _theResult___snd__h563061[56:5] : + _theResult___sfd__h563796 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 = - (guard__h555303 == 2'b0) ? - _theResult___snd__h563239[56:5] : + (guard__h555125 == 2'b0) ? + _theResult___snd__h563061[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h563974 : - _theResult___snd__h563239[56:5]) ; + _theResult___sfd__h563796 : + _theResult___snd__h563061[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 = - (guard__h498069 == 2'b0 || + (guard__h497891 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h506030 : - _theResult___exp__h506685 ; + _theResult___fst_exp__h505852 : + _theResult___exp__h506507 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 = - (guard__h498069 == 2'b0) ? - _theResult___fst_exp__h506030 : + (guard__h497891 == 2'b0) ? + _theResult___fst_exp__h505852 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h506685 : - _theResult___fst_exp__h506030) ; + _theResult___exp__h506507 : + _theResult___fst_exp__h505852) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 = - (guard__h516450 == 2'b0 || + (guard__h516272 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h524440 : - _theResult___exp__h525120 ; + _theResult___fst_exp__h524262 : + _theResult___exp__h524942 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 = - (guard__h516450 == 2'b0) ? - _theResult___fst_exp__h524440 : + (guard__h516272 == 2'b0) ? + _theResult___fst_exp__h524262 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h525120 : - _theResult___fst_exp__h524440) ; + _theResult___exp__h524942 : + _theResult___fst_exp__h524262) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 = - (guard__h498069 == 2'b0 || + (guard__h497891 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h505981[56:5] : - _theResult___sfd__h506686 ; + _theResult___snd__h505803[56:5] : + _theResult___sfd__h506508 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 = - (guard__h498069 == 2'b0) ? - _theResult___snd__h505981[56:5] : + (guard__h497891 == 2'b0) ? + _theResult___snd__h505803[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h506686 : - _theResult___snd__h505981[56:5]) ; + _theResult___sfd__h506508 : + _theResult___snd__h505803[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 = - (guard__h516450 == 2'b0 || + (guard__h516272 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h524386[56:5] : - _theResult___sfd__h525121 ; + _theResult___snd__h524208[56:5] : + _theResult___sfd__h524943 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 = - (guard__h516450 == 2'b0) ? - _theResult___snd__h524386[56:5] : + (guard__h516272 == 2'b0) ? + _theResult___snd__h524208[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h525121 : - _theResult___snd__h524386[56:5]) ; + _theResult___sfd__h524943 : + _theResult___snd__h524208[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 = - (guard__h576226 == 2'b0 || + (guard__h576048 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h584187 : - _theResult___exp__h584842 ; + _theResult___fst_exp__h584009 : + _theResult___exp__h584664 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 = - (guard__h576226 == 2'b0) ? - _theResult___fst_exp__h584187 : + (guard__h576048 == 2'b0) ? + _theResult___fst_exp__h584009 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h584842 : - _theResult___fst_exp__h584187) ; + _theResult___exp__h584664 : + _theResult___fst_exp__h584009) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 = - (guard__h594607 == 2'b0 || + (guard__h594429 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h602597 : - _theResult___exp__h603277 ; + _theResult___fst_exp__h602419 : + _theResult___exp__h603099 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 = - (guard__h594607 == 2'b0) ? - _theResult___fst_exp__h602597 : + (guard__h594429 == 2'b0) ? + _theResult___fst_exp__h602419 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h603277 : - _theResult___fst_exp__h602597) ; + _theResult___exp__h603099 : + _theResult___fst_exp__h602419) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 = - (guard__h576226 == 2'b0 || + (guard__h576048 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h584138[56:5] : - _theResult___sfd__h584843 ; + _theResult___snd__h583960[56:5] : + _theResult___sfd__h584665 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 = - (guard__h576226 == 2'b0) ? - _theResult___snd__h584138[56:5] : + (guard__h576048 == 2'b0) ? + _theResult___snd__h583960[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h584843 : - _theResult___snd__h584138[56:5]) ; + _theResult___sfd__h584665 : + _theResult___snd__h583960[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 = - (guard__h594607 == 2'b0 || + (guard__h594429 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h602543[56:5] : - _theResult___sfd__h603278 ; + _theResult___snd__h602365[56:5] : + _theResult___sfd__h603100 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 = - (guard__h594607 == 2'b0) ? - _theResult___snd__h602543[56:5] : + (guard__h594429 == 2'b0) ? + _theResult___snd__h602365[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h603278 : - _theResult___snd__h602543[56:5]) ; + _theResult___sfd__h603100 : + _theResult___snd__h602365[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 = - (guard__h358570 == 2'b0 || + (guard__h358392 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h366618 : - _theResult___exp__h367060 ; + _theResult___fst_exp__h366440 : + _theResult___exp__h366882 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 = - (guard__h358570 == 2'b0) ? - _theResult___fst_exp__h366618 : + (guard__h358392 == 2'b0) ? + _theResult___fst_exp__h366440 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h367060 : - _theResult___fst_exp__h366618) ; + _theResult___exp__h366882 : + _theResult___fst_exp__h366440) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h376336 == 2'b0 || + (guard__h376158 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h384413 : - _theResult___exp__h384880 ; + _theResult___fst_exp__h384235 : + _theResult___exp__h384702 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h376336 == 2'b0) ? - _theResult___fst_exp__h384413 : + (guard__h376158 == 2'b0) ? + _theResult___fst_exp__h384235 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h384880 : - _theResult___fst_exp__h384413) ; + _theResult___exp__h384702 : + _theResult___fst_exp__h384235) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 = - (guard__h358570 == 2'b0 || + (guard__h358392 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h366569[56:34] : - _theResult___sfd__h367061 ; + _theResult___snd__h366391[56:34] : + _theResult___sfd__h366883 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 = - (guard__h358570 == 2'b0) ? - _theResult___snd__h366569[56:34] : + (guard__h358392 == 2'b0) ? + _theResult___snd__h366391[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h367061 : - _theResult___snd__h366569[56:34]) ; + _theResult___sfd__h366883 : + _theResult___snd__h366391[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 = - (guard__h376336 == 2'b0 || + (guard__h376158 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h384359[56:34] : - _theResult___sfd__h384881 ; + _theResult___snd__h384181[56:34] : + _theResult___sfd__h384703 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 = - (guard__h376336 == 2'b0) ? - _theResult___snd__h384359[56:34] : + (guard__h376158 == 2'b0) ? + _theResult___snd__h384181[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h384881 : - _theResult___snd__h384359[56:34]) ; + _theResult___sfd__h384703 : + _theResult___snd__h384181[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 = - (guard__h404267 == 2'b0 || + (guard__h404089 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h412315 : - _theResult___exp__h412757 ; + _theResult___fst_exp__h412137 : + _theResult___exp__h412579 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 = - (guard__h404267 == 2'b0) ? - _theResult___fst_exp__h412315 : + (guard__h404089 == 2'b0) ? + _theResult___fst_exp__h412137 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h412757 : - _theResult___fst_exp__h412315) ; + _theResult___exp__h412579 : + _theResult___fst_exp__h412137) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h422033 == 2'b0 || + (guard__h421855 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h430110 : - _theResult___exp__h430577 ; + _theResult___fst_exp__h429932 : + _theResult___exp__h430399 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h422033 == 2'b0) ? - _theResult___fst_exp__h430110 : + (guard__h421855 == 2'b0) ? + _theResult___fst_exp__h429932 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h430577 : - _theResult___fst_exp__h430110) ; + _theResult___exp__h430399 : + _theResult___fst_exp__h429932) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 = - (guard__h404267 == 2'b0 || + (guard__h404089 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h412266[56:34] : - _theResult___sfd__h412758 ; + _theResult___snd__h412088[56:34] : + _theResult___sfd__h412580 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 = - (guard__h404267 == 2'b0) ? - _theResult___snd__h412266[56:34] : + (guard__h404089 == 2'b0) ? + _theResult___snd__h412088[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h412758 : - _theResult___snd__h412266[56:34]) ; + _theResult___sfd__h412580 : + _theResult___snd__h412088[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 = - (guard__h422033 == 2'b0 || + (guard__h421855 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h430056[56:34] : - _theResult___sfd__h430578 ; + _theResult___snd__h429878[56:34] : + _theResult___sfd__h430400 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 = - (guard__h422033 == 2'b0) ? - _theResult___snd__h430056[56:34] : + (guard__h421855 == 2'b0) ? + _theResult___snd__h429878[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h430578 : - _theResult___snd__h430056[56:34]) ; + _theResult___sfd__h430400 : + _theResult___snd__h429878[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 = - (guard__h449962 == 2'b0 || + (guard__h449784 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h458010 : - _theResult___exp__h458452 ; + _theResult___fst_exp__h457832 : + _theResult___exp__h458274 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 = - (guard__h449962 == 2'b0) ? - _theResult___fst_exp__h458010 : + (guard__h449784 == 2'b0) ? + _theResult___fst_exp__h457832 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h458452 : - _theResult___fst_exp__h458010) ; + _theResult___exp__h458274 : + _theResult___fst_exp__h457832) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h467728 == 2'b0 || + (guard__h467550 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h475805 : - _theResult___exp__h476272 ; + _theResult___fst_exp__h475627 : + _theResult___exp__h476094 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h467728 == 2'b0) ? - _theResult___fst_exp__h475805 : + (guard__h467550 == 2'b0) ? + _theResult___fst_exp__h475627 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h476272 : - _theResult___fst_exp__h475805) ; + _theResult___exp__h476094 : + _theResult___fst_exp__h475627) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 = - (guard__h449962 == 2'b0 || + (guard__h449784 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h457961[56:34] : - _theResult___sfd__h458453 ; + _theResult___snd__h457783[56:34] : + _theResult___sfd__h458275 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 = - (guard__h449962 == 2'b0) ? - _theResult___snd__h457961[56:34] : + (guard__h449784 == 2'b0) ? + _theResult___snd__h457783[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h458453 : - _theResult___snd__h457961[56:34]) ; + _theResult___sfd__h458275 : + _theResult___snd__h457783[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 = - (guard__h467728 == 2'b0 || + (guard__h467550 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h475751[56:34] : - _theResult___sfd__h476273 ; + _theResult___snd__h475573[56:34] : + _theResult___sfd__h476095 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 = - (guard__h467728 == 2'b0) ? - _theResult___snd__h475751[56:34] : + (guard__h467550 == 2'b0) ? + _theResult___snd__h475573[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h476273 : - _theResult___snd__h475751[56:34]) ; + _theResult___sfd__h476095 : + _theResult___snd__h475573[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018 = - (_theResult___fst_exp__h584187 == 11'd2047) ? + (_theResult___fst_exp__h584009 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19714,10 +19466,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard76048_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = - (_theResult___fst_exp__h602597 == 11'd2047) ? + (_theResult___fst_exp__h602419 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19725,10 +19477,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard94607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard94429_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = - (_theResult___fst_exp__h563293 == 11'd2047) ? + (_theResult___fst_exp__h563115 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19736,10 +19488,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55303_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; + CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787 = - (_theResult___fst_exp__h544883 == 11'd2047) ? + (_theResult___fst_exp__h544705 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19747,10 +19499,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard36744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = - (_theResult___fst_exp__h563293 == 11'd2047) ? + (_theResult___fst_exp__h563115 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19758,10 +19510,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55303_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = - (_theResult___fst_exp__h524440 == 11'd2047) ? + (_theResult___fst_exp__h524262 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19769,10 +19521,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16450_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard16272_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811 = - (_theResult___fst_exp__h602597 == 11'd2047) ? + (_theResult___fst_exp__h602419 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19780,14 +19532,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard94607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard94429_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930 = - (_theResult____h655999 == 12'd0 && + (_theResult____h655821 == 12'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h656459 : - _theResult____h655999 ; + enabled_ints__h656281 : + _theResult____h655821 ; assign IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d13131 = IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[0] || IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[1] || @@ -19837,7 +19589,7 @@ module mkCore(CLK, checkForException___d13706[4] || csrf_fs_reg_read__1710_EQ_0_3078_AND_fetchStag_ETC___d13795 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -19847,85 +19599,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 = - (f3_exp__h564940 == 8'd255 && f3_sfd__h564941 != 23'd0 || - (f3_exp__h564940 == 8'd255 || f3_exp__h564940 == 8'd0) && - f3_sfd__h564941 == 23'd0) ? + (f3_exp__h564762 == 8'd255 && f3_sfd__h564763 != 23'd0 || + (f3_exp__h564762 == 8'd255 || f3_exp__h564762 == 8'd0) && + f3_sfd__h564763 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 = - ((f2_exp__h525636 == 8'd0) ? - (f2_sfd__h525637[22] ? + ((f2_exp__h525458 == 8'd0) ? + (f2_sfd__h525459[22] ? 6'd2 : - (f2_sfd__h525637[21] ? + (f2_sfd__h525459[21] ? 6'd3 : - (f2_sfd__h525637[20] ? + (f2_sfd__h525459[20] ? 6'd4 : - (f2_sfd__h525637[19] ? + (f2_sfd__h525459[19] ? 6'd5 : - (f2_sfd__h525637[18] ? + (f2_sfd__h525459[18] ? 6'd6 : - (f2_sfd__h525637[17] ? + (f2_sfd__h525459[17] ? 6'd7 : - (f2_sfd__h525637[16] ? + (f2_sfd__h525459[16] ? 6'd8 : - (f2_sfd__h525637[15] ? + (f2_sfd__h525459[15] ? 6'd9 : - (f2_sfd__h525637[14] ? + (f2_sfd__h525459[14] ? 6'd10 : - (f2_sfd__h525637[13] ? + (f2_sfd__h525459[13] ? 6'd11 : - (f2_sfd__h525637[12] ? + (f2_sfd__h525459[12] ? 6'd12 : - (f2_sfd__h525637[11] ? + (f2_sfd__h525459[11] ? 6'd13 : - (f2_sfd__h525637[10] ? + (f2_sfd__h525459[10] ? 6'd14 : - (f2_sfd__h525637[9] ? + (f2_sfd__h525459[9] ? 6'd15 : - (f2_sfd__h525637[8] ? + (f2_sfd__h525459[8] ? 6'd16 : - (f2_sfd__h525637[7] ? + (f2_sfd__h525459[7] ? 6'd17 : - (f2_sfd__h525637[6] ? + (f2_sfd__h525459[6] ? 6'd18 : - (f2_sfd__h525637[5] ? + (f2_sfd__h525459[5] ? 6'd19 : - (f2_sfd__h525637[4] ? + (f2_sfd__h525459[4] ? 6'd20 : - (f2_sfd__h525637[3] ? + (f2_sfd__h525459[3] ? 6'd21 : - (f2_sfd__h525637[2] ? + (f2_sfd__h525459[2] ? 6'd22 : - (f2_sfd__h525637[1] ? + (f2_sfd__h525459[1] ? 6'd23 : - (f2_sfd__h525637[0] ? + (f2_sfd__h525459[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585 = - (f2_exp__h525636 == 8'd255 && f2_sfd__h525637 != 23'd0 || - (f2_exp__h525636 == 8'd255 || f2_exp__h525636 == 8'd0) && - f2_sfd__h525637 == 23'd0) ? + (f2_exp__h525458 == 8'd255 && f2_sfd__h525459 != 23'd0 || + (f2_exp__h525458 == 8'd255 || f2_exp__h525458 == 8'd0) && + f2_sfd__h525459 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h525636 == 8'd0) ? + ((f2_exp__h525458 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f2_exp__h525636 == 8'd255 && f2_sfd__h525637 != 23'd0) ? - _theResult___snd_fst_sfd__h525952 : - _theResult___fst_sfd__h564092 ; + (f2_exp__h525458 == 8'd255 && f2_sfd__h525459 != 23'd0) ? + _theResult___snd_fst_sfd__h525774 : + _theResult___fst_sfd__h563914 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 = - { (f2_exp__h525636 == 8'd255) ? + { (f2_exp__h525458 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h564088, + _theResult___fst_exp__h563910, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -19935,15 +19687,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 = - (f2_exp__h525636 == 8'd255 && f2_sfd__h525637 != 23'd0 || - (f2_exp__h525636 == 8'd255 || f2_exp__h525636 == 8'd0) && - f2_sfd__h525637 == 23'd0) ? + (f2_exp__h525458 == 8'd255 && f2_sfd__h525459 != 23'd0 || + (f2_exp__h525458 == 8'd255 || f2_exp__h525458 == 8'd0) && + f2_sfd__h525459 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 = - (f1_exp__h486642 == 8'd0) ? + (f1_exp__h486464 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[4] : @@ -19951,7 +19703,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[4] : @@ -19959,7 +19711,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[4] : @@ -19967,7 +19719,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f1_exp__h486642 == 8'd0) ? + (f1_exp__h486464 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[3] : @@ -19975,7 +19727,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[3] : @@ -19983,7 +19735,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[3] : @@ -19991,208 +19743,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 = - (f1_exp__h486642 == 8'd0) ? + (f1_exp__h486464 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 = - (f1_exp__h486642 == 8'd0) ? + (f1_exp__h486464 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 = - (f1_exp__h486642 == 8'd0) ? + (f1_exp__h486464 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113 = - (f2_exp__h525636 == 8'd0) ? + (f2_exp__h525458 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126 = - (f3_exp__h564940 == 8'd0) ? + (f3_exp__h564762 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 = - ((f1_exp__h486642 == 8'd0) ? - (f1_sfd__h486643[22] ? + ((f1_exp__h486464 == 8'd0) ? + (f1_sfd__h486465[22] ? 6'd2 : - (f1_sfd__h486643[21] ? + (f1_sfd__h486465[21] ? 6'd3 : - (f1_sfd__h486643[20] ? + (f1_sfd__h486465[20] ? 6'd4 : - (f1_sfd__h486643[19] ? + (f1_sfd__h486465[19] ? 6'd5 : - (f1_sfd__h486643[18] ? + (f1_sfd__h486465[18] ? 6'd6 : - (f1_sfd__h486643[17] ? + (f1_sfd__h486465[17] ? 6'd7 : - (f1_sfd__h486643[16] ? + (f1_sfd__h486465[16] ? 6'd8 : - (f1_sfd__h486643[15] ? + (f1_sfd__h486465[15] ? 6'd9 : - (f1_sfd__h486643[14] ? + (f1_sfd__h486465[14] ? 6'd10 : - (f1_sfd__h486643[13] ? + (f1_sfd__h486465[13] ? 6'd11 : - (f1_sfd__h486643[12] ? + (f1_sfd__h486465[12] ? 6'd12 : - (f1_sfd__h486643[11] ? + (f1_sfd__h486465[11] ? 6'd13 : - (f1_sfd__h486643[10] ? + (f1_sfd__h486465[10] ? 6'd14 : - (f1_sfd__h486643[9] ? + (f1_sfd__h486465[9] ? 6'd15 : - (f1_sfd__h486643[8] ? + (f1_sfd__h486465[8] ? 6'd16 : - (f1_sfd__h486643[7] ? + (f1_sfd__h486465[7] ? 6'd17 : - (f1_sfd__h486643[6] ? + (f1_sfd__h486465[6] ? 6'd18 : - (f1_sfd__h486643[5] ? + (f1_sfd__h486465[5] ? 6'd19 : - (f1_sfd__h486643[4] ? + (f1_sfd__h486465[4] ? 6'd20 : - (f1_sfd__h486643[3] ? + (f1_sfd__h486465[3] ? 6'd21 : - (f1_sfd__h486643[2] ? + (f1_sfd__h486465[2] ? 6'd22 : - (f1_sfd__h486643[1] ? + (f1_sfd__h486465[1] ? 6'd23 : - (f1_sfd__h486643[0] ? + (f1_sfd__h486465[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100 = - (f1_exp__h486642 == 8'd255 && f1_sfd__h486643 != 23'd0 || - (f1_exp__h486642 == 8'd255 || f1_exp__h486642 == 8'd0) && - f1_sfd__h486643 == 23'd0) ? + (f1_exp__h486464 == 8'd255 && f1_sfd__h486465 != 23'd0 || + (f1_exp__h486464 == 8'd255 || f1_exp__h486464 == 8'd0) && + f1_sfd__h486465 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h486642 == 8'd0) ? + ((f1_exp__h486464 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 = - (f1_exp__h486642 == 8'd255 && f1_sfd__h486643 != 23'd0) ? - _theResult___snd_fst_sfd__h486958 : - _theResult___fst_sfd__h525239 ; + (f1_exp__h486464 == 8'd255 && f1_sfd__h486465 != 23'd0) ? + _theResult___snd_fst_sfd__h486780 : + _theResult___fst_sfd__h525061 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100, - (f1_exp__h486642 == 8'd255) ? + (f1_exp__h486464 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h525235, + _theResult___fst_exp__h525057, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 = - ((f3_exp__h564940 == 8'd0) ? - (f3_sfd__h564941[22] ? + ((f3_exp__h564762 == 8'd0) ? + (f3_sfd__h564763[22] ? 6'd2 : - (f3_sfd__h564941[21] ? + (f3_sfd__h564763[21] ? 6'd3 : - (f3_sfd__h564941[20] ? + (f3_sfd__h564763[20] ? 6'd4 : - (f3_sfd__h564941[19] ? + (f3_sfd__h564763[19] ? 6'd5 : - (f3_sfd__h564941[18] ? + (f3_sfd__h564763[18] ? 6'd6 : - (f3_sfd__h564941[17] ? + (f3_sfd__h564763[17] ? 6'd7 : - (f3_sfd__h564941[16] ? + (f3_sfd__h564763[16] ? 6'd8 : - (f3_sfd__h564941[15] ? + (f3_sfd__h564763[15] ? 6'd9 : - (f3_sfd__h564941[14] ? + (f3_sfd__h564763[14] ? 6'd10 : - (f3_sfd__h564941[13] ? + (f3_sfd__h564763[13] ? 6'd11 : - (f3_sfd__h564941[12] ? + (f3_sfd__h564763[12] ? 6'd12 : - (f3_sfd__h564941[11] ? + (f3_sfd__h564763[11] ? 6'd13 : - (f3_sfd__h564941[10] ? + (f3_sfd__h564763[10] ? 6'd14 : - (f3_sfd__h564941[9] ? + (f3_sfd__h564763[9] ? 6'd15 : - (f3_sfd__h564941[8] ? + (f3_sfd__h564763[8] ? 6'd16 : - (f3_sfd__h564941[7] ? + (f3_sfd__h564763[7] ? 6'd17 : - (f3_sfd__h564941[6] ? + (f3_sfd__h564763[6] ? 6'd18 : - (f3_sfd__h564941[5] ? + (f3_sfd__h564763[5] ? 6'd19 : - (f3_sfd__h564941[4] ? + (f3_sfd__h564763[4] ? 6'd20 : - (f3_sfd__h564941[3] ? + (f3_sfd__h564763[3] ? 6'd21 : - (f3_sfd__h564941[2] ? + (f3_sfd__h564763[2] ? 6'd22 : - (f3_sfd__h564941[1] ? + (f3_sfd__h564763[1] ? 6'd23 : - (f3_sfd__h564941[0] ? + (f3_sfd__h564763[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815 = - (f3_exp__h564940 == 8'd255 && f3_sfd__h564941 != 23'd0 || - (f3_exp__h564940 == 8'd255 || f3_exp__h564940 == 8'd0) && - f3_sfd__h564941 == 23'd0) ? + (f3_exp__h564762 == 8'd255 && f3_sfd__h564763 != 23'd0 || + (f3_exp__h564762 == 8'd255 || f3_exp__h564762 == 8'd0) && + f3_sfd__h564763 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h564940 == 8'd0) ? + ((f3_exp__h564762 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 = - (f3_exp__h564940 == 8'd255 && f3_sfd__h564941 != 23'd0) ? - _theResult___snd_fst_sfd__h565256 : - _theResult___fst_sfd__h603396 ; + (f3_exp__h564762 == 8'd255 && f3_sfd__h564763 != 23'd0) ? + _theResult___snd_fst_sfd__h565078 : + _theResult___fst_sfd__h603218 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 = - { (f3_exp__h564940 == 8'd255) ? + { (f3_exp__h564762 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h603392, + _theResult___fst_exp__h603214, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 = IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ? @@ -20398,7 +20150,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || - _theResult___fst_exp__h544883 == 11'd2047) ? + _theResult___fst_exp__h544705 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20406,12 +20158,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36922_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard36744_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || - _theResult___fst_exp__h506030 == 11'd2047) ? + _theResult___fst_exp__h505852 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20419,12 +20171,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98069_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard97891_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || - _theResult___fst_exp__h584187 == 11'd2047) ? + _theResult___fst_exp__h584009 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20432,7 +20184,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard76048_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3__ETC___d13295 = IF_IF_NOT_csrf_prv_reg_read__2891_EQ_3_2892_28_ETC___d12930[0] ? @@ -20916,48 +20668,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[2] : - _theResult___fst_exp__h525223 == 11'd2047 && - _theResult___fst_sfd__h525224 == 52'd0 ; + _theResult___fst_exp__h525045 == 11'd2047 && + _theResult___fst_sfd__h525046 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[2] : - _theResult___fst_exp__h564076 == 11'd2047 && - _theResult___fst_sfd__h564077 == 52'd0 ; + _theResult___fst_exp__h563898 == 11'd2047 && + _theResult___fst_sfd__h563899 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[2] : - _theResult___fst_exp__h603380 == 11'd2047 && - _theResult___fst_sfd__h603381 == 52'd0 ; + _theResult___fst_exp__h603202 == 11'd2047 && + _theResult___fst_sfd__h603203 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[1] : - _theResult___fst_exp__h524440 == 11'd0 && - guard__h516450 != 2'b0 ; + _theResult___fst_exp__h524262 == 11'd0 && + guard__h516272 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[1] : - _theResult___fst_exp__h563293 == 11'd0 && - guard__h555303 != 2'b0 ; + _theResult___fst_exp__h563115 == 11'd0 && + guard__h555125 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[1] : - _theResult___fst_exp__h602597 == 11'd0 && - guard__h594607 != 2'b0 ; + _theResult___fst_exp__h602419 == 11'd0 && + guard__h594429 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[0] : - _theResult___fst_exp__h524440 != 11'd2047 && - guard__h516450 != 2'b0 ; + _theResult___fst_exp__h524262 != 11'd2047 && + guard__h516272 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[0] : - _theResult___fst_exp__h563293 != 11'd2047 && - guard__h555303 != 2'b0 ; + _theResult___fst_exp__h563115 != 11'd2047 && + guard__h555125 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[0] : - _theResult___fst_exp__h602597 != 11'd2047 && - guard__h594607 != 2'b0 ; + _theResult___fst_exp__h602419 != 11'd2047 && + guard__h594429 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? @@ -20997,35 +20749,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h375728 == 8'd255) ? + ((_theResult___fst_exp__h375550 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) : - ((_theResult___fst_exp__h384413 == 8'd255) ? + ((_theResult___fst_exp__h384235 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h375728 == 8'd255) ? + ((_theResult___fst_exp__h375550 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) : - ((_theResult___fst_exp__h384413 == 8'd255) ? + ((_theResult___fst_exp__h384235 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] : - _theResult___fst_exp__h384961 == 8'd255 && - _theResult___fst_sfd__h384962 == 23'd0 ; + _theResult___fst_exp__h384783 == 8'd255 && + _theResult___fst_sfd__h384784 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] : - _theResult___fst_exp__h384413 == 8'd0 && - guard__h376336 != 2'b0 ; + _theResult___fst_exp__h384235 == 8'd0 && + guard__h376158 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] : - _theResult___fst_exp__h384413 != 8'd255 && - guard__h376336 != 2'b0 ; + _theResult___fst_exp__h384235 != 8'd255 && + guard__h376158 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? @@ -21035,35 +20787,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h421425 == 8'd255) ? + ((_theResult___fst_exp__h421247 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) : - ((_theResult___fst_exp__h430110 == 8'd255) ? + ((_theResult___fst_exp__h429932 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h421425 == 8'd255) ? + ((_theResult___fst_exp__h421247 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) : - ((_theResult___fst_exp__h430110 == 8'd255) ? + ((_theResult___fst_exp__h429932 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] : - _theResult___fst_exp__h430658 == 8'd255 && - _theResult___fst_sfd__h430659 == 23'd0 ; + _theResult___fst_exp__h430480 == 8'd255 && + _theResult___fst_sfd__h430481 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] : - _theResult___fst_exp__h430110 == 8'd0 && - guard__h422033 != 2'b0 ; + _theResult___fst_exp__h429932 == 8'd0 && + guard__h421855 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] : - _theResult___fst_exp__h430110 != 8'd255 && - guard__h422033 != 2'b0 ; + _theResult___fst_exp__h429932 != 8'd255 && + guard__h421855 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? @@ -21073,35 +20825,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h467120 == 8'd255) ? + ((_theResult___fst_exp__h466942 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) : - ((_theResult___fst_exp__h475805 == 8'd255) ? + ((_theResult___fst_exp__h475627 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h467120 == 8'd255) ? + ((_theResult___fst_exp__h466942 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) : - ((_theResult___fst_exp__h475805 == 8'd255) ? + ((_theResult___fst_exp__h475627 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] : - _theResult___fst_exp__h476353 == 8'd255 && - _theResult___fst_sfd__h476354 == 23'd0 ; + _theResult___fst_exp__h476175 == 8'd255 && + _theResult___fst_sfd__h476176 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] : - _theResult___fst_exp__h475805 == 8'd0 && - guard__h467728 != 2'b0 ; + _theResult___fst_exp__h475627 == 8'd0 && + guard__h467550 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] : - _theResult___fst_exp__h475805 != 8'd255 && - guard__h467728 != 2'b0 ; + _theResult___fst_exp__h475627 != 8'd255 && + guard__h467550 != 2'b0 ; assign IF_checkForException_3089_BIT_4_3090_THEN_IF_c_ETC___d13222 = checkForException___d13089[4] ? CASE_checkForException_3089_BITS_3_TO_0_0_chec_ETC__q226 : @@ -21759,8 +21511,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12804 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h651706 : - w__h651701 ; + result__h651528 : + w__h651523 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21782,39 +21534,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h200866 : + n___1__h200688 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21867,7 +21619,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h199463 : + x__h199285 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ? 64'd0 : 64'd1) ; @@ -21879,7 +21631,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 = - _theResult_____2__h300288 == v__h299708 ; + _theResult_____2__h300110 == v__h299530 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21888,7 +21640,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 = - _theResult_____2__h308284 == v__h303053 ; + _theResult_____2__h308106 == v__h302875 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21917,7 +21669,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h305918 } ; + x__h305740 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -22015,35 +21767,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h195958 : + n__h195780 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -22071,7 +21823,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 = - _theResult_____2__h314278 == v__h313567 ; + _theResult_____2__h314100 == v__h313389 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -22080,7 +21832,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 = - _theResult_____2__h322132 == v__h317443 ; + _theResult_____2__h321954 == v__h317265 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -22232,7 +21984,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 = - _theResult_____2__h335701 == v__h335269 ; + _theResult_____2__h335523 == v__h335091 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -22281,7 +22033,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 = - _theResult_____2__h332476 == v__h332044 ; + _theResult_____2__h332298 == v__h331866 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -22313,7 +22065,7 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h716290 : + rob$deqPort_0_deq_data[95:32] : csrf_minstret_ehr_data_rl ; assign IF_fetchStage_RDY_pipelines_0_first__2860_AND__ETC___d13463 = fetchStage_RDY_pipelines_0_first__2860_AND_NOT_ETC___d13459 ? @@ -22344,10 +22096,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13949 = IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13942 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2863_BIT_160__ETC___d14136 = @@ -22381,10 +22133,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14029 && IF_fetchStage_RDY_pipelines_1_first__2871_AND__ETC___d13836 && (IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14054 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064) ; + rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064) ; assign IF_fetchStage_pipelines_1_first__2872_BITS_194_ETC___d14349 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d14284 && @@ -22425,60 +22177,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h718758 : + y_avValue_snd_snd_snd_snd_snd__h718580 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 = - rob$deqPort_0_canDeq ? y_avValue_fst__h718332 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h718154 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h718752 : + y_avValue_snd_snd_snd_fst__h718574 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4882_THEN_IF_NOT_rob__ETC___d15089 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4885_BIT_25_488_ETC___d15088 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin03653_BIT_33_THEN_2_ELSE_0__q57 = - sfdin__h403653[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin15601_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h515601[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin21419_BIT_33_THEN_2_ELSE_0__q67 = - sfdin__h421419[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin49348_BIT_33_THEN_2_ELSE_0__q92 = - sfdin__h449348[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin54454_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h554454[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin57956_BIT_33_THEN_2_ELSE_0__q22 = - sfdin__h357956[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin67114_BIT_33_THEN_2_ELSE_0__q102 = - sfdin__h467114[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin75722_BIT_33_THEN_2_ELSE_0__q32 = - sfdin__h375722[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93758_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h593758[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02543_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h602543[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05981_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h505981[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12266_BIT_33_THEN_2_ELSE_0__q59 = - _theResult___snd__h412266[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd24386_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h524386[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30056_BIT_33_THEN_2_ELSE_0__q72 = - _theResult___snd__h430056[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd44834_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h544834[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd57961_BIT_33_THEN_2_ELSE_0__q94 = - _theResult___snd__h457961[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63239_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h563239[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd66569_BIT_33_THEN_2_ELSE_0__q24 = - _theResult___snd__h366569[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd75751_BIT_33_THEN_2_ELSE_0__q107 = - _theResult___snd__h475751[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84138_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h584138[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84359_BIT_33_THEN_2_ELSE_0__q37 = - _theResult___snd__h384359[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin03475_BIT_33_THEN_2_ELSE_0__q57 = + sfdin__h403475[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin15423_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h515423[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin21241_BIT_33_THEN_2_ELSE_0__q67 = + sfdin__h421241[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin49170_BIT_33_THEN_2_ELSE_0__q92 = + sfdin__h449170[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin54276_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h554276[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin57778_BIT_33_THEN_2_ELSE_0__q22 = + sfdin__h357778[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin66936_BIT_33_THEN_2_ELSE_0__q102 = + sfdin__h466936[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin75544_BIT_33_THEN_2_ELSE_0__q32 = + sfdin__h375544[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93580_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h593580[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02365_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h602365[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05803_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h505803[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12088_BIT_33_THEN_2_ELSE_0__q59 = + _theResult___snd__h412088[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd24208_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h524208[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd29878_BIT_33_THEN_2_ELSE_0__q72 = + _theResult___snd__h429878[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd44656_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h544656[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd57783_BIT_33_THEN_2_ELSE_0__q94 = + _theResult___snd__h457783[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd63061_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h563061[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd66391_BIT_33_THEN_2_ELSE_0__q24 = + _theResult___snd__h366391[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd75573_BIT_33_THEN_2_ELSE_0__q107 = + _theResult___snd__h475573[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd83960_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h583960[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84181_BIT_33_THEN_2_ELSE_0__q37 = + _theResult___snd__h384181[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? @@ -22558,133 +22310,133 @@ module mkCore(CLK, !checkForException___d13706[4] && NOT_csrf_fs_reg_read__1710_EQ_0_3078_3079_OR_N_ETC___d13731 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4878_4879_OR__ETC___d15094 = - (fflags__h719327 & csrf_fflags_reg) != fflags__h719327 || - !r__h618000 && + (fflags__h719149 & csrf_fflags_reg) != fflags__h719149 || + !r__h617822 && (IF_rob_deqPort_1_canDeq__4882_THEN_IF_NOT_rob__ETC___d15089 || - fflags__h719327 != 5'd0) ; + fflags__h719149 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = - !f2_sfd__h525637[21] && !f2_sfd__h525637[20] && - !f2_sfd__h525637[19] && - !f2_sfd__h525637[18] && - !f2_sfd__h525637[17] && - !f2_sfd__h525637[16] && - !f2_sfd__h525637[15] && - !f2_sfd__h525637[14] && - !f2_sfd__h525637[13] && - !f2_sfd__h525637[12] && - !f2_sfd__h525637[11] && - !f2_sfd__h525637[10] && - !f2_sfd__h525637[9] && - !f2_sfd__h525637[8] && - !f2_sfd__h525637[7] && - !f2_sfd__h525637[6] && - !f2_sfd__h525637[5] && - !f2_sfd__h525637[4] && - !f2_sfd__h525637[3] && - !f2_sfd__h525637[2] && - !f2_sfd__h525637[1] && - !f2_sfd__h525637[0] ; + !f2_sfd__h525459[21] && !f2_sfd__h525459[20] && + !f2_sfd__h525459[19] && + !f2_sfd__h525459[18] && + !f2_sfd__h525459[17] && + !f2_sfd__h525459[16] && + !f2_sfd__h525459[15] && + !f2_sfd__h525459[14] && + !f2_sfd__h525459[13] && + !f2_sfd__h525459[12] && + !f2_sfd__h525459[11] && + !f2_sfd__h525459[10] && + !f2_sfd__h525459[9] && + !f2_sfd__h525459[8] && + !f2_sfd__h525459[7] && + !f2_sfd__h525459[6] && + !f2_sfd__h525459[5] && + !f2_sfd__h525459[4] && + !f2_sfd__h525459[3] && + !f2_sfd__h525459[2] && + !f2_sfd__h525459[1] && + !f2_sfd__h525459[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 == 23'd0) && - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 != 23'd0) && - (f1_exp__h486642 != 8'd0 || f1_sfd__h486643 != 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 == 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 != 23'd0) && + (f1_exp__h486464 != 8'd0 || f1_sfd__h486465 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f2_exp__h525636 != 8'd255 || f2_sfd__h525637 == 23'd0) && - (f2_exp__h525636 != 8'd255 || f2_sfd__h525637 != 23'd0) && - (f2_exp__h525636 != 8'd0 || f2_sfd__h525637 != 23'd0) && + ((f2_exp__h525458 != 8'd255 || f2_sfd__h525459 == 23'd0) && + (f2_exp__h525458 != 8'd255 || f2_sfd__h525459 != 23'd0) && + (f2_exp__h525458 != 8'd0 || f2_sfd__h525459 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 = - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 == 23'd0) && - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 != 23'd0) && - (f1_exp__h486642 != 8'd0 || f1_sfd__h486643 != 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 == 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 != 23'd0) && + (f1_exp__h486464 != 8'd0 || f1_sfd__h486465 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 | - ((f2_exp__h525636 != 8'd255 || f2_sfd__h525637 == 23'd0) && - (f2_exp__h525636 != 8'd255 || f2_sfd__h525637 != 23'd0) && - (f2_exp__h525636 != 8'd0 || f2_sfd__h525637 != 23'd0) && + ((f2_exp__h525458 != 8'd255 || f2_sfd__h525459 == 23'd0) && + (f2_exp__h525458 != 8'd255 || f2_sfd__h525459 != 23'd0) && + (f2_exp__h525458 != 8'd0 || f2_sfd__h525459 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 = - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 == 23'd0) && - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 != 23'd0) && - (f1_exp__h486642 != 8'd0 || f1_sfd__h486643 != 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 == 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 != 23'd0) && + (f1_exp__h486464 != 8'd0 || f1_sfd__h486465 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 | - ((f2_exp__h525636 != 8'd255 || f2_sfd__h525637 == 23'd0) && - (f2_exp__h525636 != 8'd255 || f2_sfd__h525637 != 23'd0) && - (f2_exp__h525636 != 8'd0 || f2_sfd__h525637 != 23'd0) && + ((f2_exp__h525458 != 8'd255 || f2_sfd__h525459 == 23'd0) && + (f2_exp__h525458 != 8'd255 || f2_sfd__h525459 != 23'd0) && + (f2_exp__h525458 != 8'd0 || f2_sfd__h525459 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 = - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 == 23'd0) && - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 != 23'd0) && - (f1_exp__h486642 != 8'd0 || f1_sfd__h486643 != 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 == 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 != 23'd0) && + (f1_exp__h486464 != 8'd0 || f1_sfd__h486465 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 | - ((f2_exp__h525636 != 8'd255 || f2_sfd__h525637 == 23'd0) && - (f2_exp__h525636 != 8'd255 || f2_sfd__h525637 != 23'd0) && - (f2_exp__h525636 != 8'd0 || f2_sfd__h525637 != 23'd0) && + ((f2_exp__h525458 != 8'd255 || f2_sfd__h525459 == 23'd0) && + (f2_exp__h525458 != 8'd255 || f2_sfd__h525459 != 23'd0) && + (f2_exp__h525458 != 8'd0 || f2_sfd__h525459 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 = - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 == 23'd0) && - (f1_exp__h486642 != 8'd255 || f1_sfd__h486643 != 23'd0) && - (f1_exp__h486642 != 8'd0 || f1_sfd__h486643 != 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 == 23'd0) && + (f1_exp__h486464 != 8'd255 || f1_sfd__h486465 != 23'd0) && + (f1_exp__h486464 != 8'd0 || f1_sfd__h486465 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 | - ((f2_exp__h525636 != 8'd255 || f2_sfd__h525637 == 23'd0) && - (f2_exp__h525636 != 8'd255 || f2_sfd__h525637 != 23'd0) && - (f2_exp__h525636 != 8'd0 || f2_sfd__h525637 != 23'd0) && + ((f2_exp__h525458 != 8'd255 || f2_sfd__h525459 == 23'd0) && + (f2_exp__h525458 != 8'd255 || f2_sfd__h525459 != 23'd0) && + (f2_exp__h525458 != 8'd0 || f2_sfd__h525459 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 = - !f1_sfd__h486643[21] && !f1_sfd__h486643[20] && - !f1_sfd__h486643[19] && - !f1_sfd__h486643[18] && - !f1_sfd__h486643[17] && - !f1_sfd__h486643[16] && - !f1_sfd__h486643[15] && - !f1_sfd__h486643[14] && - !f1_sfd__h486643[13] && - !f1_sfd__h486643[12] && - !f1_sfd__h486643[11] && - !f1_sfd__h486643[10] && - !f1_sfd__h486643[9] && - !f1_sfd__h486643[8] && - !f1_sfd__h486643[7] && - !f1_sfd__h486643[6] && - !f1_sfd__h486643[5] && - !f1_sfd__h486643[4] && - !f1_sfd__h486643[3] && - !f1_sfd__h486643[2] && - !f1_sfd__h486643[1] && - !f1_sfd__h486643[0] ; + !f1_sfd__h486465[21] && !f1_sfd__h486465[20] && + !f1_sfd__h486465[19] && + !f1_sfd__h486465[18] && + !f1_sfd__h486465[17] && + !f1_sfd__h486465[16] && + !f1_sfd__h486465[15] && + !f1_sfd__h486465[14] && + !f1_sfd__h486465[13] && + !f1_sfd__h486465[12] && + !f1_sfd__h486465[11] && + !f1_sfd__h486465[10] && + !f1_sfd__h486465[9] && + !f1_sfd__h486465[8] && + !f1_sfd__h486465[7] && + !f1_sfd__h486465[6] && + !f1_sfd__h486465[5] && + !f1_sfd__h486465[4] && + !f1_sfd__h486465[3] && + !f1_sfd__h486465[2] && + !f1_sfd__h486465[1] && + !f1_sfd__h486465[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 = - !f3_sfd__h564941[21] && !f3_sfd__h564941[20] && - !f3_sfd__h564941[19] && - !f3_sfd__h564941[18] && - !f3_sfd__h564941[17] && - !f3_sfd__h564941[16] && - !f3_sfd__h564941[15] && - !f3_sfd__h564941[14] && - !f3_sfd__h564941[13] && - !f3_sfd__h564941[12] && - !f3_sfd__h564941[11] && - !f3_sfd__h564941[10] && - !f3_sfd__h564941[9] && - !f3_sfd__h564941[8] && - !f3_sfd__h564941[7] && - !f3_sfd__h564941[6] && - !f3_sfd__h564941[5] && - !f3_sfd__h564941[4] && - !f3_sfd__h564941[3] && - !f3_sfd__h564941[2] && - !f3_sfd__h564941[1] && - !f3_sfd__h564941[0] ; + !f3_sfd__h564763[21] && !f3_sfd__h564763[20] && + !f3_sfd__h564763[19] && + !f3_sfd__h564763[18] && + !f3_sfd__h564763[17] && + !f3_sfd__h564763[16] && + !f3_sfd__h564763[15] && + !f3_sfd__h564763[14] && + !f3_sfd__h564763[13] && + !f3_sfd__h564763[12] && + !f3_sfd__h564763[11] && + !f3_sfd__h564763[10] && + !f3_sfd__h564763[9] && + !f3_sfd__h564763[8] && + !f3_sfd__h564763[7] && + !f3_sfd__h564763[6] && + !f3_sfd__h564763[5] && + !f3_sfd__h564763[4] && + !f3_sfd__h564763[3] && + !f3_sfd__h564763[2] && + !f3_sfd__h564763[1] && + !f3_sfd__h564763[0] ; assign NOT_IF_rob_deqPort_0_deq_data__4363_BITS_97_TO_ETC___d14849 = - next_pc__h715420 != + next_pc__h715242 != rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13511 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__346_ETC___d13509 && @@ -23416,8 +23168,8 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13355 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h659778 == 5'd0 && - imm__h659779 == 32'd0 || + rs1__h659600 == 5'd0 && + imm__h659601 == 32'd0 || IF_fetchStage_pipelines_0_first__2863_BIT_173__ETC___d13116[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13456 = @@ -23484,7 +23236,7 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign NOT_fetchStage_pipelines_0_first__2863_BITS_32_ETC___d14106 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h668013 ; + fallthrough_pc__h667835 ; assign NOT_fetchStage_pipelines_0_first__2863_BIT_68__ETC___d13504 = !fetchStage$pipelines_0_first[68] && !checkForException___d13089[4] && @@ -23566,7 +23318,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[173] ; assign NOT_fetchStage_pipelines_1_first__2872_BITS_32_ETC___d14271 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h683505 ; + fallthrough_pc__h683327 ; assign NOT_fetchStage_pipelines_1_first__2872_BIT_68__ETC___d14214 = !fetchStage$pipelines_1_first[68] && !checkForException___d13706[4] && @@ -23693,10 +23445,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage_pipelines_1_first__2872_BIT_68_3583_ETC___d13972 ; - assign NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_RDY_ETC___d14917 = + assign NOT_rob_deqPort_0_canDeq__4878_4879_OR_regRena_ETC___d14917 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4885_BIT_25_4886_4_ETC___d14914) ; @@ -23737,7 +23489,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d13995 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__3436__ETC___d13861 || @@ -23767,22 +23519,22 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - x__h295278 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15219 = + x__h295100 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15216 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15175 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15172 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15184 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15175, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15181 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15172, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15193 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15184, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15190 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15181, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ; assign SEL_ARR_fetchStage_pipelines_0_canDeq__2861_AN_ETC___d13806 = @@ -23792,8 +23544,8 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2872_BITS_199_TO_ETC___d13803 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 = - { {4{f2_exp25636_MINUS_127__q168[7]}}, - f2_exp25636_MINUS_127__q168 } ; + { {4{f2_exp25458_MINUS_127__q168[7]}}, + f2_exp25458_MINUS_127__q168 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^ 12'h800) <= @@ -23803,12 +23555,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187 = - b__h607636 * b__h607712 ; + b__h607458 * b__h607534 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200 = - b__h607636 * b__h607825 ; + b__h607458 * b__h607647 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 = - { {4{f1_exp86642_MINUS_127__q128[7]}}, - f1_exp86642_MINUS_127__q128 } ; + { {4{f1_exp86464_MINUS_127__q128[7]}}, + f1_exp86464_MINUS_127__q128 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^ 12'h800) <= @@ -23818,8 +23570,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 = - { {4{f3_exp64940_MINUS_127__q145[7]}}, - f3_exp64940_MINUS_127__q145 } ; + { {4{f3_exp64762_MINUS_127__q145[7]}}, + f3_exp64762_MINUS_127__q145 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^ 12'h800) <= @@ -23904,15 +23656,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 = { 3'd0, - _theResult___fst_exp__h357962 == 8'd0 && - (sfdin__h357956[56:34] == 23'd0 || guard__h349861 != 2'b0), + _theResult___fst_exp__h357784 == 8'd0 && + (sfdin__h357778[56:34] == 23'd0 || guard__h349683 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h358559 == 8'd255 && - _theResult___fst_sfd__h358560 == 23'd0, + _theResult___fst_exp__h358381 == 8'd255 && + _theResult___fst_sfd__h358382 == 23'd0, 1'd0, - _theResult___fst_exp__h357962 != 8'd255 && - guard__h349861 != 2'b0 } ; + _theResult___fst_exp__h357784 != 8'd255 && + guard__h349683 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^ @@ -23920,15 +23672,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 = { 3'd0, - _theResult___fst_exp__h403659 == 8'd0 && - (sfdin__h403653[56:34] == 23'd0 || guard__h395560 != 2'b0), + _theResult___fst_exp__h403481 == 8'd0 && + (sfdin__h403475[56:34] == 23'd0 || guard__h395382 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h404256 == 8'd255 && - _theResult___fst_sfd__h404257 == 23'd0, + _theResult___fst_exp__h404078 == 8'd255 && + _theResult___fst_sfd__h404079 == 23'd0, 1'd0, - _theResult___fst_exp__h403659 != 8'd255 && - guard__h395560 != 2'b0 } ; + _theResult___fst_exp__h403481 != 8'd255 && + guard__h395382 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^ @@ -23936,15 +23688,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 = { 3'd0, - _theResult___fst_exp__h449354 == 8'd0 && - (sfdin__h449348[56:34] == 23'd0 || guard__h441255 != 2'b0), + _theResult___fst_exp__h449176 == 8'd0 && + (sfdin__h449170[56:34] == 23'd0 || guard__h441077 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h449951 == 8'd255 && - _theResult___fst_sfd__h449952 == 23'd0, + _theResult___fst_exp__h449773 == 8'd255 && + _theResult___fst_sfd__h449774 == 23'd0, 1'd0, - _theResult___fst_exp__h449354 != 8'd255 && - guard__h441255 != 2'b0 } ; + _theResult___fst_exp__h449176 != 8'd255 && + guard__h441077 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ^ @@ -23952,37 +23704,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869 = { 3'd0, - _theResult___fst_exp__h515607 == 11'd0 && - (sfdin__h515601[56:5] == 52'd0 || guard__h507381 != 2'b0), + _theResult___fst_exp__h515429 == 11'd0 && + (sfdin__h515423[56:5] == 52'd0 || guard__h507203 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h516439 == 11'd2047 && - _theResult___fst_sfd__h516440 == 52'd0, + _theResult___fst_exp__h516261 == 11'd2047 && + _theResult___fst_sfd__h516262 == 52'd0, 1'd0, - _theResult___fst_exp__h515607 != 11'd2047 && - guard__h507381 != 2'b0 } ; + _theResult___fst_exp__h515429 != 11'd2047 && + guard__h507203 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910 = { 3'd0, - _theResult___fst_exp__h554460 == 11'd0 && - (sfdin__h554454[56:5] == 52'd0 || guard__h546234 != 2'b0), + _theResult___fst_exp__h554282 == 11'd0 && + (sfdin__h554276[56:5] == 52'd0 || guard__h546056 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h555292 == 11'd2047 && - _theResult___fst_sfd__h555293 == 52'd0, + _theResult___fst_exp__h555114 == 11'd2047 && + _theResult___fst_sfd__h555115 == 52'd0, 1'd0, - _theResult___fst_exp__h554460 != 11'd2047 && - guard__h546234 != 2'b0 } ; + _theResult___fst_exp__h554282 != 11'd2047 && + guard__h546056 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954 = { 3'd0, - _theResult___fst_exp__h593764 == 11'd0 && - (sfdin__h593758[56:5] == 52'd0 || guard__h585538 != 2'b0), + _theResult___fst_exp__h593586 == 11'd0 && + (sfdin__h593580[56:5] == 52'd0 || guard__h585360 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h594596 == 11'd2047 && - _theResult___fst_sfd__h594597 == 52'd0, + _theResult___fst_exp__h594418 == 11'd2047 && + _theResult___fst_sfd__h594419 == 52'd0, 1'd0, - _theResult___fst_exp__h593764 != 11'd2047 && - guard__h585538 != 2'b0 } ; + _theResult___fst_exp__h593586 != 11'd2047 && + guard__h585360 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ^ @@ -24000,15 +23752,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 = { 3'd0, - _theResult___fst_exp__h375728 == 8'd0 && - (sfdin__h375722[56:34] == 23'd0 || guard__h367500 != 2'b0), + _theResult___fst_exp__h375550 == 8'd0 && + (sfdin__h375544[56:34] == 23'd0 || guard__h367322 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h376325 == 8'd255 && - _theResult___fst_sfd__h376326 == 23'd0, + _theResult___fst_exp__h376147 == 8'd255 && + _theResult___fst_sfd__h376148 == 23'd0, 1'd0, - _theResult___fst_exp__h375728 != 8'd255 && - guard__h367500 != 2'b0 } ; + _theResult___fst_exp__h375550 != 8'd255 && + guard__h367322 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^ @@ -24016,15 +23768,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 = { 3'd0, - _theResult___fst_exp__h421425 == 8'd0 && - (sfdin__h421419[56:34] == 23'd0 || guard__h413197 != 2'b0), + _theResult___fst_exp__h421247 == 8'd0 && + (sfdin__h421241[56:34] == 23'd0 || guard__h413019 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h422022 == 8'd255 && - _theResult___fst_sfd__h422023 == 23'd0, + _theResult___fst_exp__h421844 == 8'd255 && + _theResult___fst_sfd__h421845 == 23'd0, 1'd0, - _theResult___fst_exp__h421425 != 8'd255 && - guard__h413197 != 2'b0 } ; + _theResult___fst_exp__h421247 != 8'd255 && + guard__h413019 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^ @@ -24032,15 +23784,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 = { 3'd0, - _theResult___fst_exp__h467120 == 8'd0 && - (sfdin__h467114[56:34] == 23'd0 || guard__h458892 != 2'b0), + _theResult___fst_exp__h466942 == 8'd0 && + (sfdin__h466936[56:34] == 23'd0 || guard__h458714 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h467717 == 8'd255 && - _theResult___fst_sfd__h467718 == 23'd0, + _theResult___fst_exp__h467539 == 8'd255 && + _theResult___fst_sfd__h467540 == 23'd0, 1'd0, - _theResult___fst_exp__h467120 != 8'd255 && - guard__h458892 != 2'b0 } ; + _theResult___fst_exp__h466942 != 8'd255 && + guard__h458714 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^ @@ -24054,37 +23806,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852 = { 3'd0, - _theResult___fst_exp__h506030 == 11'd0 && - guard__h498069 != 2'b0, + _theResult___fst_exp__h505852 == 11'd0 && + guard__h497891 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h506788 == 11'd2047 && - _theResult___fst_sfd__h506789 == 52'd0, + _theResult___fst_exp__h506610 == 11'd2047 && + _theResult___fst_sfd__h506611 == 52'd0, 1'd0, - _theResult___fst_exp__h506030 != 11'd2047 && - guard__h498069 != 2'b0 } ; + _theResult___fst_exp__h505852 != 11'd2047 && + guard__h497891 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893 = { 3'd0, - _theResult___fst_exp__h544883 == 11'd0 && - guard__h536922 != 2'b0, + _theResult___fst_exp__h544705 == 11'd0 && + guard__h536744 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h545641 == 11'd2047 && - _theResult___fst_sfd__h545642 == 52'd0, + _theResult___fst_exp__h545463 == 11'd2047 && + _theResult___fst_sfd__h545464 == 52'd0, 1'd0, - _theResult___fst_exp__h544883 != 11'd2047 && - guard__h536922 != 2'b0 } ; + _theResult___fst_exp__h544705 != 11'd2047 && + guard__h536744 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937 = { 3'd0, - _theResult___fst_exp__h584187 == 11'd0 && - guard__h576226 != 2'b0, + _theResult___fst_exp__h584009 == 11'd0 && + guard__h576048 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h584945 == 11'd2047 && - _theResult___fst_sfd__h584946 == 52'd0, + _theResult___fst_exp__h584767 == 11'd2047 && + _theResult___fst_sfd__h584768 == 52'd0, 1'd0, - _theResult___fst_exp__h584187 != 11'd2047 && - guard__h576226 != 2'b0 } ; + _theResult___fst_exp__h584009 != 11'd2047 && + guard__h576048 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^ @@ -24120,15 +23872,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 = { 3'd0, - _theResult___fst_exp__h366618 == 8'd0 && - guard__h358570 != 2'b0, + _theResult___fst_exp__h366440 == 8'd0 && + guard__h358392 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h367141 == 8'd255 && - _theResult___fst_sfd__h367142 == 23'd0, + _theResult___fst_exp__h366963 == 8'd255 && + _theResult___fst_sfd__h366964 == 23'd0, 1'd0, - _theResult___fst_exp__h366618 != 8'd255 && - guard__h358570 != 2'b0 } ; + _theResult___fst_exp__h366440 != 8'd255 && + guard__h358392 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^ @@ -24142,15 +23894,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 = { 3'd0, - _theResult___fst_exp__h412315 == 8'd0 && - guard__h404267 != 2'b0, + _theResult___fst_exp__h412137 == 8'd0 && + guard__h404089 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h412838 == 8'd255 && - _theResult___fst_sfd__h412839 == 23'd0, + _theResult___fst_exp__h412660 == 8'd255 && + _theResult___fst_sfd__h412661 == 23'd0, 1'd0, - _theResult___fst_exp__h412315 != 8'd255 && - guard__h404267 != 2'b0 } ; + _theResult___fst_exp__h412137 != 8'd255 && + guard__h404089 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^ @@ -24164,21 +23916,21 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 = { 3'd0, - _theResult___fst_exp__h458010 == 8'd0 && - guard__h449962 != 2'b0, + _theResult___fst_exp__h457832 == 8'd0 && + guard__h449784 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h458533 == 8'd255 && - _theResult___fst_sfd__h458534 == 23'd0, + _theResult___fst_exp__h458355 == 8'd255 && + _theResult___fst_sfd__h458356 == 23'd0, 1'd0, - _theResult___fst_exp__h458010 != 8'd255 && - guard__h449962 != 2'b0 } ; + _theResult___fst_exp__h457832 != 8'd255 && + guard__h449784 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 = - b__h607813 * b__h607825 ; + b__h607635 * b__h607647 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__2863_BI_ETC___d13923 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k71653_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k71475_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2872_BI_ETC___d14008 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -24190,33 +23942,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2872_BITS_199_TO_ETC___d13803 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 = - sfd__h525998 >> + sfd__h525820 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764 = - sfd__h487004 >> + sfd__h486826 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479 = - sfd__h565302 >> + sfd__h565124 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 = - sfd__h342246 >> + sfd__h342068 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 = - sfd__h387948 >> + sfd__h387770 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 = - sfd__h433643 >> + sfd__h433465 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1815_1816_ETC___d14540 = - medeleg_csr__read__h616285[i__h704826] ; + medeleg_csr__read__h616107[i__h704648] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1823_1824_ETC___d14521 = - mideleg_csr__read__h616380[i__h704986] ; + mideleg_csr__read__h616202[i__h704808] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24622,51 +24374,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 = 12'd3970 - { 7'd0, - f2_sfd__h525637[22] ? + f2_sfd__h525459[22] ? 5'd0 : - (f2_sfd__h525637[21] ? + (f2_sfd__h525459[21] ? 5'd1 : - (f2_sfd__h525637[20] ? + (f2_sfd__h525459[20] ? 5'd2 : - (f2_sfd__h525637[19] ? + (f2_sfd__h525459[19] ? 5'd3 : - (f2_sfd__h525637[18] ? + (f2_sfd__h525459[18] ? 5'd4 : - (f2_sfd__h525637[17] ? + (f2_sfd__h525459[17] ? 5'd5 : - (f2_sfd__h525637[16] ? + (f2_sfd__h525459[16] ? 5'd6 : - (f2_sfd__h525637[15] ? + (f2_sfd__h525459[15] ? 5'd7 : - (f2_sfd__h525637[14] ? + (f2_sfd__h525459[14] ? 5'd8 : - (f2_sfd__h525637[13] ? + (f2_sfd__h525459[13] ? 5'd9 : - (f2_sfd__h525637[12] ? + (f2_sfd__h525459[12] ? 5'd10 : - (f2_sfd__h525637[11] ? + (f2_sfd__h525459[11] ? 5'd11 : - (f2_sfd__h525637[10] ? + (f2_sfd__h525459[10] ? 5'd12 : - (f2_sfd__h525637[9] ? + (f2_sfd__h525459[9] ? 5'd13 : - (f2_sfd__h525637[8] ? + (f2_sfd__h525459[8] ? 5'd14 : - (f2_sfd__h525637[7] ? + (f2_sfd__h525459[7] ? 5'd15 : - (f2_sfd__h525637[6] ? + (f2_sfd__h525459[6] ? 5'd16 : - (f2_sfd__h525637[5] ? + (f2_sfd__h525459[5] ? 5'd17 : - (f2_sfd__h525637[4] ? + (f2_sfd__h525459[4] ? 5'd18 : - (f2_sfd__h525637[3] ? + (f2_sfd__h525459[3] ? 5'd19 : - (f2_sfd__h525637[2] ? + (f2_sfd__h525459[2] ? 5'd20 : - (f2_sfd__h525637[1] ? + (f2_sfd__h525459[1] ? 5'd21 : - (f2_sfd__h525637[0] ? + (f2_sfd__h525459[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 = @@ -24680,51 +24432,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 = 12'd3970 - { 7'd0, - f1_sfd__h486643[22] ? + f1_sfd__h486465[22] ? 5'd0 : - (f1_sfd__h486643[21] ? + (f1_sfd__h486465[21] ? 5'd1 : - (f1_sfd__h486643[20] ? + (f1_sfd__h486465[20] ? 5'd2 : - (f1_sfd__h486643[19] ? + (f1_sfd__h486465[19] ? 5'd3 : - (f1_sfd__h486643[18] ? + (f1_sfd__h486465[18] ? 5'd4 : - (f1_sfd__h486643[17] ? + (f1_sfd__h486465[17] ? 5'd5 : - (f1_sfd__h486643[16] ? + (f1_sfd__h486465[16] ? 5'd6 : - (f1_sfd__h486643[15] ? + (f1_sfd__h486465[15] ? 5'd7 : - (f1_sfd__h486643[14] ? + (f1_sfd__h486465[14] ? 5'd8 : - (f1_sfd__h486643[13] ? + (f1_sfd__h486465[13] ? 5'd9 : - (f1_sfd__h486643[12] ? + (f1_sfd__h486465[12] ? 5'd10 : - (f1_sfd__h486643[11] ? + (f1_sfd__h486465[11] ? 5'd11 : - (f1_sfd__h486643[10] ? + (f1_sfd__h486465[10] ? 5'd12 : - (f1_sfd__h486643[9] ? + (f1_sfd__h486465[9] ? 5'd13 : - (f1_sfd__h486643[8] ? + (f1_sfd__h486465[8] ? 5'd14 : - (f1_sfd__h486643[7] ? + (f1_sfd__h486465[7] ? 5'd15 : - (f1_sfd__h486643[6] ? + (f1_sfd__h486465[6] ? 5'd16 : - (f1_sfd__h486643[5] ? + (f1_sfd__h486465[5] ? 5'd17 : - (f1_sfd__h486643[4] ? + (f1_sfd__h486465[4] ? 5'd18 : - (f1_sfd__h486643[3] ? + (f1_sfd__h486465[3] ? 5'd19 : - (f1_sfd__h486643[2] ? + (f1_sfd__h486465[2] ? 5'd20 : - (f1_sfd__h486643[1] ? + (f1_sfd__h486465[1] ? 5'd21 : - (f1_sfd__h486643[0] ? + (f1_sfd__h486465[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 = @@ -24738,51 +24490,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 = 12'd3970 - { 7'd0, - f3_sfd__h564941[22] ? + f3_sfd__h564763[22] ? 5'd0 : - (f3_sfd__h564941[21] ? + (f3_sfd__h564763[21] ? 5'd1 : - (f3_sfd__h564941[20] ? + (f3_sfd__h564763[20] ? 5'd2 : - (f3_sfd__h564941[19] ? + (f3_sfd__h564763[19] ? 5'd3 : - (f3_sfd__h564941[18] ? + (f3_sfd__h564763[18] ? 5'd4 : - (f3_sfd__h564941[17] ? + (f3_sfd__h564763[17] ? 5'd5 : - (f3_sfd__h564941[16] ? + (f3_sfd__h564763[16] ? 5'd6 : - (f3_sfd__h564941[15] ? + (f3_sfd__h564763[15] ? 5'd7 : - (f3_sfd__h564941[14] ? + (f3_sfd__h564763[14] ? 5'd8 : - (f3_sfd__h564941[13] ? + (f3_sfd__h564763[13] ? 5'd9 : - (f3_sfd__h564941[12] ? + (f3_sfd__h564763[12] ? 5'd10 : - (f3_sfd__h564941[11] ? + (f3_sfd__h564763[11] ? 5'd11 : - (f3_sfd__h564941[10] ? + (f3_sfd__h564763[10] ? 5'd12 : - (f3_sfd__h564941[9] ? + (f3_sfd__h564763[9] ? 5'd13 : - (f3_sfd__h564941[8] ? + (f3_sfd__h564763[8] ? 5'd14 : - (f3_sfd__h564941[7] ? + (f3_sfd__h564763[7] ? 5'd15 : - (f3_sfd__h564941[6] ? + (f3_sfd__h564763[6] ? 5'd16 : - (f3_sfd__h564941[5] ? + (f3_sfd__h564763[5] ? 5'd17 : - (f3_sfd__h564941[4] ? + (f3_sfd__h564763[4] ? 5'd18 : - (f3_sfd__h564941[3] ? + (f3_sfd__h564763[3] ? 5'd19 : - (f3_sfd__h564941[2] ? + (f3_sfd__h564763[2] ? 5'd20 : - (f3_sfd__h564941[1] ? + (f3_sfd__h564763[1] ? 5'd21 : - (f3_sfd__h564941[0] ? + (f3_sfd__h564763[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 = @@ -24811,7 +24563,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d14284 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h671653 == 1'd0 && + k__h671475 == 1'd0 && fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14085 || fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14203 == 1'd0 && @@ -24918,1421 +24670,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h300288 = + assign _theResult_____2__h300110 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ? - next_deqP___1__h300567 : + next_deqP___1__h300389 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h308284 = + assign _theResult_____2__h308106 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ? - next_deqP___1__h308563 : + next_deqP___1__h308385 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h314278 = + assign _theResult_____2__h314100 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ? - next_deqP___1__h314844 : + next_deqP___1__h314666 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h322132 = + assign _theResult_____2__h321954 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ? - next_deqP___1__h322698 : + next_deqP___1__h322520 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h332476 = + assign _theResult_____2__h332298 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ? - next_deqP___1__h332755 : + next_deqP___1__h332577 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h335701 = + assign _theResult_____2__h335523 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ? - next_deqP___1__h335980 : + next_deqP___1__h335802 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h349851 = - (value__h350473 == 54'd0) ? sfd__h342246 : 57'd1 ; - assign _theResult____h367490 = + assign _theResult____h349673 = + (value__h350295 == 54'd0) ? sfd__h342068 : 57'd1 ; + assign _theResult____h367312 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^ 12'h800) < 12'd2105) ? - result__h368103 : - _theResult____h349851 ; - assign _theResult____h395550 = - (value__h396170 == 54'd0) ? sfd__h387948 : 57'd1 ; - assign _theResult____h413187 = + result__h367925 : + _theResult____h349673 ; + assign _theResult____h395372 = + (value__h395992 == 54'd0) ? sfd__h387770 : 57'd1 ; + assign _theResult____h413009 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^ 12'h800) < 12'd2105) ? - result__h413800 : - _theResult____h395550 ; - assign _theResult____h441245 = - (value__h441865 == 54'd0) ? sfd__h433643 : 57'd1 ; - assign _theResult____h458882 = + result__h413622 : + _theResult____h395372 ; + assign _theResult____h441067 = + (value__h441687 == 54'd0) ? sfd__h433465 : 57'd1 ; + assign _theResult____h458704 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^ 12'h800) < 12'd2105) ? - result__h459495 : - _theResult____h441245 ; - assign _theResult____h507371 = + result__h459317 : + _theResult____h441067 ; + assign _theResult____h507193 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ^ 12'h800) < 12'd2105) ? - result__h507984 : - ((value__h491587 == 25'd0) ? sfd__h487004 : 57'd1) ; - assign _theResult____h546224 = + result__h507806 : + ((value__h491409 == 25'd0) ? sfd__h486826 : 57'd1) ; + assign _theResult____h546046 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ^ 12'h800) < 12'd2105) ? - result__h546837 : - ((value__h530440 == 25'd0) ? sfd__h525998 : 57'd1) ; - assign _theResult____h585528 = + result__h546659 : + ((value__h530262 == 25'd0) ? sfd__h525820 : 57'd1) ; + assign _theResult____h585350 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ^ 12'h800) < 12'd2105) ? - result__h586141 : - ((value__h569744 == 25'd0) ? sfd__h565302 : 57'd1) ; - assign _theResult____h655999 = + result__h585963 : + ((value__h569566 == 25'd0) ? sfd__h565124 : 57'd1) ; + assign _theResult____h655821 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h656412 : + enabled_ints___1__h656234 : 12'd0 ; - assign _theResult___exp__h358478 = - sfd__h358054[24] ? - ((_theResult___fst_exp__h357962 == 8'd254) ? + assign _theResult___exp__h358300 = + sfd__h357876[24] ? + ((_theResult___fst_exp__h357784 == 8'd254) ? 8'd255 : - din_inc___2_exp__h384995) : - ((_theResult___fst_exp__h357962 == 8'd0 && - sfd__h358054[24:23] == 2'b01) ? + din_inc___2_exp__h384817) : + ((_theResult___fst_exp__h357784 == 8'd0 && + sfd__h357876[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h357962) ; - assign _theResult___exp__h367060 = - sfd__h366636[24] ? - ((_theResult___fst_exp__h366618 == 8'd254) ? + _theResult___fst_exp__h357784) ; + assign _theResult___exp__h366882 = + sfd__h366458[24] ? + ((_theResult___fst_exp__h366440 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385019) : - ((_theResult___fst_exp__h366618 == 8'd0 && - sfd__h366636[24:23] == 2'b01) ? + din_inc___2_exp__h384841) : + ((_theResult___fst_exp__h366440 == 8'd0 && + sfd__h366458[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h366618) ; - assign _theResult___exp__h376244 = - sfd__h375820[24] ? - ((_theResult___fst_exp__h375728 == 8'd254) ? + _theResult___fst_exp__h366440) ; + assign _theResult___exp__h376066 = + sfd__h375642[24] ? + ((_theResult___fst_exp__h375550 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385049) : - ((_theResult___fst_exp__h375728 == 8'd0 && - sfd__h375820[24:23] == 2'b01) ? + din_inc___2_exp__h384871) : + ((_theResult___fst_exp__h375550 == 8'd0 && + sfd__h375642[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h375728) ; - assign _theResult___exp__h384880 = - sfd__h384432[24] ? - ((_theResult___fst_exp__h384413 == 8'd254) ? + _theResult___fst_exp__h375550) ; + assign _theResult___exp__h384702 = + sfd__h384254[24] ? + ((_theResult___fst_exp__h384235 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385073) : - ((_theResult___fst_exp__h384413 == 8'd0 && - sfd__h384432[24:23] == 2'b01) ? + din_inc___2_exp__h384895) : + ((_theResult___fst_exp__h384235 == 8'd0 && + sfd__h384254[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h384413) ; - assign _theResult___exp__h384982 = + _theResult___fst_exp__h384235) ; + assign _theResult___exp__h384804 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h384973 ; - assign _theResult___exp__h404175 = - sfd__h403751[24] ? - ((_theResult___fst_exp__h403659 == 8'd254) ? + _theResult___fst_exp__h384795 ; + assign _theResult___exp__h403997 = + sfd__h403573[24] ? + ((_theResult___fst_exp__h403481 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430692) : - ((_theResult___fst_exp__h403659 == 8'd0 && - sfd__h403751[24:23] == 2'b01) ? + din_inc___2_exp__h430514) : + ((_theResult___fst_exp__h403481 == 8'd0 && + sfd__h403573[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h403659) ; - assign _theResult___exp__h412757 = - sfd__h412333[24] ? - ((_theResult___fst_exp__h412315 == 8'd254) ? + _theResult___fst_exp__h403481) ; + assign _theResult___exp__h412579 = + sfd__h412155[24] ? + ((_theResult___fst_exp__h412137 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430716) : - ((_theResult___fst_exp__h412315 == 8'd0 && - sfd__h412333[24:23] == 2'b01) ? + din_inc___2_exp__h430538) : + ((_theResult___fst_exp__h412137 == 8'd0 && + sfd__h412155[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h412315) ; - assign _theResult___exp__h421941 = - sfd__h421517[24] ? - ((_theResult___fst_exp__h421425 == 8'd254) ? + _theResult___fst_exp__h412137) ; + assign _theResult___exp__h421763 = + sfd__h421339[24] ? + ((_theResult___fst_exp__h421247 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430746) : - ((_theResult___fst_exp__h421425 == 8'd0 && - sfd__h421517[24:23] == 2'b01) ? + din_inc___2_exp__h430568) : + ((_theResult___fst_exp__h421247 == 8'd0 && + sfd__h421339[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h421425) ; - assign _theResult___exp__h430577 = - sfd__h430129[24] ? - ((_theResult___fst_exp__h430110 == 8'd254) ? + _theResult___fst_exp__h421247) ; + assign _theResult___exp__h430399 = + sfd__h429951[24] ? + ((_theResult___fst_exp__h429932 == 8'd254) ? 8'd255 : - din_inc___2_exp__h430770) : - ((_theResult___fst_exp__h430110 == 8'd0 && - sfd__h430129[24:23] == 2'b01) ? + din_inc___2_exp__h430592) : + ((_theResult___fst_exp__h429932 == 8'd0 && + sfd__h429951[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h430110) ; - assign _theResult___exp__h430679 = + _theResult___fst_exp__h429932) ; + assign _theResult___exp__h430501 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h430670 ; - assign _theResult___exp__h449870 = - sfd__h449446[24] ? - ((_theResult___fst_exp__h449354 == 8'd254) ? + _theResult___fst_exp__h430492 ; + assign _theResult___exp__h449692 = + sfd__h449268[24] ? + ((_theResult___fst_exp__h449176 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476387) : - ((_theResult___fst_exp__h449354 == 8'd0 && - sfd__h449446[24:23] == 2'b01) ? + din_inc___2_exp__h476209) : + ((_theResult___fst_exp__h449176 == 8'd0 && + sfd__h449268[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h449354) ; - assign _theResult___exp__h458452 = - sfd__h458028[24] ? - ((_theResult___fst_exp__h458010 == 8'd254) ? + _theResult___fst_exp__h449176) ; + assign _theResult___exp__h458274 = + sfd__h457850[24] ? + ((_theResult___fst_exp__h457832 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476411) : - ((_theResult___fst_exp__h458010 == 8'd0 && - sfd__h458028[24:23] == 2'b01) ? + din_inc___2_exp__h476233) : + ((_theResult___fst_exp__h457832 == 8'd0 && + sfd__h457850[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h458010) ; - assign _theResult___exp__h467636 = - sfd__h467212[24] ? - ((_theResult___fst_exp__h467120 == 8'd254) ? + _theResult___fst_exp__h457832) ; + assign _theResult___exp__h467458 = + sfd__h467034[24] ? + ((_theResult___fst_exp__h466942 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476441) : - ((_theResult___fst_exp__h467120 == 8'd0 && - sfd__h467212[24:23] == 2'b01) ? + din_inc___2_exp__h476263) : + ((_theResult___fst_exp__h466942 == 8'd0 && + sfd__h467034[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h467120) ; - assign _theResult___exp__h476272 = - sfd__h475824[24] ? - ((_theResult___fst_exp__h475805 == 8'd254) ? + _theResult___fst_exp__h466942) ; + assign _theResult___exp__h476094 = + sfd__h475646[24] ? + ((_theResult___fst_exp__h475627 == 8'd254) ? 8'd255 : - din_inc___2_exp__h476465) : - ((_theResult___fst_exp__h475805 == 8'd0 && - sfd__h475824[24:23] == 2'b01) ? + din_inc___2_exp__h476287) : + ((_theResult___fst_exp__h475627 == 8'd0 && + sfd__h475646[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h475805) ; - assign _theResult___exp__h476374 = + _theResult___fst_exp__h475627) ; + assign _theResult___exp__h476196 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h476365 ; - assign _theResult___exp__h506685 = - sfd__h506048[53] ? - ((_theResult___fst_exp__h506030 == 11'd2046) ? + _theResult___fst_exp__h476187 ; + assign _theResult___exp__h506507 = + sfd__h505870[53] ? + ((_theResult___fst_exp__h505852 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525280) : - ((_theResult___fst_exp__h506030 == 11'd0 && - sfd__h506048[53:52] == 2'b01) ? + din_inc___2_exp__h525102) : + ((_theResult___fst_exp__h505852 == 11'd0 && + sfd__h505870[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h506030) ; - assign _theResult___exp__h516336 = - sfd__h515699[53] ? - ((_theResult___fst_exp__h515607 == 11'd2046) ? + _theResult___fst_exp__h505852) ; + assign _theResult___exp__h516158 = + sfd__h515521[53] ? + ((_theResult___fst_exp__h515429 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525315) : - ((_theResult___fst_exp__h515607 == 11'd0 && - sfd__h515699[53:52] == 2'b01) ? + din_inc___2_exp__h525137) : + ((_theResult___fst_exp__h515429 == 11'd0 && + sfd__h515521[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h515607) ; - assign _theResult___exp__h525120 = - sfd__h524459[53] ? - ((_theResult___fst_exp__h524440 == 11'd2046) ? + _theResult___fst_exp__h515429) ; + assign _theResult___exp__h524942 = + sfd__h524281[53] ? + ((_theResult___fst_exp__h524262 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525341) : - ((_theResult___fst_exp__h524440 == 11'd0 && - sfd__h524459[53:52] == 2'b01) ? + din_inc___2_exp__h525163) : + ((_theResult___fst_exp__h524262 == 11'd0 && + sfd__h524281[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h524440) ; - assign _theResult___exp__h545538 = - sfd__h544901[53] ? - ((_theResult___fst_exp__h544883 == 11'd2046) ? + _theResult___fst_exp__h524262) ; + assign _theResult___exp__h545360 = + sfd__h544723[53] ? + ((_theResult___fst_exp__h544705 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564133) : - ((_theResult___fst_exp__h544883 == 11'd0 && - sfd__h544901[53:52] == 2'b01) ? + din_inc___2_exp__h563955) : + ((_theResult___fst_exp__h544705 == 11'd0 && + sfd__h544723[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h544883) ; - assign _theResult___exp__h555189 = - sfd__h554552[53] ? - ((_theResult___fst_exp__h554460 == 11'd2046) ? + _theResult___fst_exp__h544705) ; + assign _theResult___exp__h555011 = + sfd__h554374[53] ? + ((_theResult___fst_exp__h554282 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564168) : - ((_theResult___fst_exp__h554460 == 11'd0 && - sfd__h554552[53:52] == 2'b01) ? + din_inc___2_exp__h563990) : + ((_theResult___fst_exp__h554282 == 11'd0 && + sfd__h554374[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h554460) ; - assign _theResult___exp__h563973 = - sfd__h563312[53] ? - ((_theResult___fst_exp__h563293 == 11'd2046) ? + _theResult___fst_exp__h554282) ; + assign _theResult___exp__h563795 = + sfd__h563134[53] ? + ((_theResult___fst_exp__h563115 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564194) : - ((_theResult___fst_exp__h563293 == 11'd0 && - sfd__h563312[53:52] == 2'b01) ? + din_inc___2_exp__h564016) : + ((_theResult___fst_exp__h563115 == 11'd0 && + sfd__h563134[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h563293) ; - assign _theResult___exp__h584842 = - sfd__h584205[53] ? - ((_theResult___fst_exp__h584187 == 11'd2046) ? + _theResult___fst_exp__h563115) ; + assign _theResult___exp__h584664 = + sfd__h584027[53] ? + ((_theResult___fst_exp__h584009 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603437) : - ((_theResult___fst_exp__h584187 == 11'd0 && - sfd__h584205[53:52] == 2'b01) ? + din_inc___2_exp__h603259) : + ((_theResult___fst_exp__h584009 == 11'd0 && + sfd__h584027[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h584187) ; - assign _theResult___exp__h594493 = - sfd__h593856[53] ? - ((_theResult___fst_exp__h593764 == 11'd2046) ? + _theResult___fst_exp__h584009) ; + assign _theResult___exp__h594315 = + sfd__h593678[53] ? + ((_theResult___fst_exp__h593586 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603472) : - ((_theResult___fst_exp__h593764 == 11'd0 && - sfd__h593856[53:52] == 2'b01) ? + din_inc___2_exp__h603294) : + ((_theResult___fst_exp__h593586 == 11'd0 && + sfd__h593678[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h593764) ; - assign _theResult___exp__h603277 = - sfd__h602616[53] ? - ((_theResult___fst_exp__h602597 == 11'd2046) ? + _theResult___fst_exp__h593586) ; + assign _theResult___exp__h603099 = + sfd__h602438[53] ? + ((_theResult___fst_exp__h602419 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603498) : - ((_theResult___fst_exp__h602597 == 11'd0 && - sfd__h602616[53:52] == 2'b01) ? + din_inc___2_exp__h603320) : + ((_theResult___fst_exp__h602419 == 11'd0 && + sfd__h602438[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h602597) ; - assign _theResult___fst__h608036 = - a__h607488[63] ? a___1__h608041 : a__h607488 ; - assign _theResult___fst_exp__h357962 = - _theResult____h349851[56] ? + _theResult___fst_exp__h602419) ; + assign _theResult___fst__h607858 = + a__h607310[63] ? a___1__h607863 : a__h607310 ; + assign _theResult___fst_exp__h357784 = + _theResult____h349673[56] ? 8'd2 : - _theResult___fst_exp__h358036 ; - assign _theResult___fst_exp__h358027 = + _theResult___fst_exp__h357858 ; + assign _theResult___fst_exp__h357849 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ; - assign _theResult___fst_exp__h358033 = - (!_theResult____h349851[56] && !_theResult____h349851[55] && - !_theResult____h349851[54] && - !_theResult____h349851[53] && - !_theResult____h349851[52] && - !_theResult____h349851[51] && - !_theResult____h349851[50] && - !_theResult____h349851[49] && - !_theResult____h349851[48] && - !_theResult____h349851[47] && - !_theResult____h349851[46] && - !_theResult____h349851[45] && - !_theResult____h349851[44] && - !_theResult____h349851[43] && - !_theResult____h349851[42] && - !_theResult____h349851[41] && - !_theResult____h349851[40] && - !_theResult____h349851[39] && - !_theResult____h349851[38] && - !_theResult____h349851[37] && - !_theResult____h349851[36] && - !_theResult____h349851[35] && - !_theResult____h349851[34] && - !_theResult____h349851[33] && - !_theResult____h349851[32] && - !_theResult____h349851[31] && - !_theResult____h349851[30] && - !_theResult____h349851[29] && - !_theResult____h349851[28] && - !_theResult____h349851[27] && - !_theResult____h349851[26] && - !_theResult____h349851[25] && - !_theResult____h349851[24] && - !_theResult____h349851[23] && - !_theResult____h349851[22] && - !_theResult____h349851[21] && - !_theResult____h349851[20] && - !_theResult____h349851[19] && - !_theResult____h349851[18] && - !_theResult____h349851[17] && - !_theResult____h349851[16] && - !_theResult____h349851[15] && - !_theResult____h349851[14] && - !_theResult____h349851[13] && - !_theResult____h349851[12] && - !_theResult____h349851[11] && - !_theResult____h349851[10] && - !_theResult____h349851[9] && - !_theResult____h349851[8] && - !_theResult____h349851[7] && - !_theResult____h349851[6] && - !_theResult____h349851[5] && - !_theResult____h349851[4] && - !_theResult____h349851[3] && - !_theResult____h349851[2] && - !_theResult____h349851[1] && - !_theResult____h349851[0] || + assign _theResult___fst_exp__h357855 = + (!_theResult____h349673[56] && !_theResult____h349673[55] && + !_theResult____h349673[54] && + !_theResult____h349673[53] && + !_theResult____h349673[52] && + !_theResult____h349673[51] && + !_theResult____h349673[50] && + !_theResult____h349673[49] && + !_theResult____h349673[48] && + !_theResult____h349673[47] && + !_theResult____h349673[46] && + !_theResult____h349673[45] && + !_theResult____h349673[44] && + !_theResult____h349673[43] && + !_theResult____h349673[42] && + !_theResult____h349673[41] && + !_theResult____h349673[40] && + !_theResult____h349673[39] && + !_theResult____h349673[38] && + !_theResult____h349673[37] && + !_theResult____h349673[36] && + !_theResult____h349673[35] && + !_theResult____h349673[34] && + !_theResult____h349673[33] && + !_theResult____h349673[32] && + !_theResult____h349673[31] && + !_theResult____h349673[30] && + !_theResult____h349673[29] && + !_theResult____h349673[28] && + !_theResult____h349673[27] && + !_theResult____h349673[26] && + !_theResult____h349673[25] && + !_theResult____h349673[24] && + !_theResult____h349673[23] && + !_theResult____h349673[22] && + !_theResult____h349673[21] && + !_theResult____h349673[20] && + !_theResult____h349673[19] && + !_theResult____h349673[18] && + !_theResult____h349673[17] && + !_theResult____h349673[16] && + !_theResult____h349673[15] && + !_theResult____h349673[14] && + !_theResult____h349673[13] && + !_theResult____h349673[12] && + !_theResult____h349673[11] && + !_theResult____h349673[10] && + !_theResult____h349673[9] && + !_theResult____h349673[8] && + !_theResult____h349673[7] && + !_theResult____h349673[6] && + !_theResult____h349673[5] && + !_theResult____h349673[4] && + !_theResult____h349673[3] && + !_theResult____h349673[2] && + !_theResult____h349673[1] && + !_theResult____h349673[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ? 8'd0 : - _theResult___fst_exp__h358027 ; - assign _theResult___fst_exp__h358036 = - (!_theResult____h349851[56] && _theResult____h349851[55]) ? + _theResult___fst_exp__h357849 ; + assign _theResult___fst_exp__h357858 = + (!_theResult____h349673[56] && _theResult____h349673[55]) ? 8'd1 : - _theResult___fst_exp__h358033 ; - assign _theResult___fst_exp__h358559 = - (_theResult___fst_exp__h357962 == 8'd255) ? - _theResult___fst_exp__h357962 : - _theResult___fst_exp__h358556 ; - assign _theResult___fst_exp__h366609 = + _theResult___fst_exp__h357855 ; + assign _theResult___fst_exp__h358381 = + (_theResult___fst_exp__h357784 == 8'd255) ? + _theResult___fst_exp__h357784 : + _theResult___fst_exp__h358378 ; + assign _theResult___fst_exp__h366431 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h366615 = + assign _theResult___fst_exp__h366437 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ? 8'd0 : - _theResult___fst_exp__h366609 ; - assign _theResult___fst_exp__h366618 = + _theResult___fst_exp__h366431 ; + assign _theResult___fst_exp__h366440 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h366615 : + _theResult___fst_exp__h366437 : 8'd129 ; - assign _theResult___fst_exp__h367141 = - (_theResult___fst_exp__h366618 == 8'd255) ? - _theResult___fst_exp__h366618 : - _theResult___fst_exp__h367138 ; - assign _theResult___fst_exp__h375728 = - _theResult____h367490[56] ? + assign _theResult___fst_exp__h366963 = + (_theResult___fst_exp__h366440 == 8'd255) ? + _theResult___fst_exp__h366440 : + _theResult___fst_exp__h366960 ; + assign _theResult___fst_exp__h375550 = + _theResult____h367312[56] ? 8'd2 : - _theResult___fst_exp__h375802 ; - assign _theResult___fst_exp__h375793 = + _theResult___fst_exp__h375624 ; + assign _theResult___fst_exp__h375615 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ; - assign _theResult___fst_exp__h375799 = - (!_theResult____h367490[56] && !_theResult____h367490[55] && - !_theResult____h367490[54] && - !_theResult____h367490[53] && - !_theResult____h367490[52] && - !_theResult____h367490[51] && - !_theResult____h367490[50] && - !_theResult____h367490[49] && - !_theResult____h367490[48] && - !_theResult____h367490[47] && - !_theResult____h367490[46] && - !_theResult____h367490[45] && - !_theResult____h367490[44] && - !_theResult____h367490[43] && - !_theResult____h367490[42] && - !_theResult____h367490[41] && - !_theResult____h367490[40] && - !_theResult____h367490[39] && - !_theResult____h367490[38] && - !_theResult____h367490[37] && - !_theResult____h367490[36] && - !_theResult____h367490[35] && - !_theResult____h367490[34] && - !_theResult____h367490[33] && - !_theResult____h367490[32] && - !_theResult____h367490[31] && - !_theResult____h367490[30] && - !_theResult____h367490[29] && - !_theResult____h367490[28] && - !_theResult____h367490[27] && - !_theResult____h367490[26] && - !_theResult____h367490[25] && - !_theResult____h367490[24] && - !_theResult____h367490[23] && - !_theResult____h367490[22] && - !_theResult____h367490[21] && - !_theResult____h367490[20] && - !_theResult____h367490[19] && - !_theResult____h367490[18] && - !_theResult____h367490[17] && - !_theResult____h367490[16] && - !_theResult____h367490[15] && - !_theResult____h367490[14] && - !_theResult____h367490[13] && - !_theResult____h367490[12] && - !_theResult____h367490[11] && - !_theResult____h367490[10] && - !_theResult____h367490[9] && - !_theResult____h367490[8] && - !_theResult____h367490[7] && - !_theResult____h367490[6] && - !_theResult____h367490[5] && - !_theResult____h367490[4] && - !_theResult____h367490[3] && - !_theResult____h367490[2] && - !_theResult____h367490[1] && - !_theResult____h367490[0] || + assign _theResult___fst_exp__h375621 = + (!_theResult____h367312[56] && !_theResult____h367312[55] && + !_theResult____h367312[54] && + !_theResult____h367312[53] && + !_theResult____h367312[52] && + !_theResult____h367312[51] && + !_theResult____h367312[50] && + !_theResult____h367312[49] && + !_theResult____h367312[48] && + !_theResult____h367312[47] && + !_theResult____h367312[46] && + !_theResult____h367312[45] && + !_theResult____h367312[44] && + !_theResult____h367312[43] && + !_theResult____h367312[42] && + !_theResult____h367312[41] && + !_theResult____h367312[40] && + !_theResult____h367312[39] && + !_theResult____h367312[38] && + !_theResult____h367312[37] && + !_theResult____h367312[36] && + !_theResult____h367312[35] && + !_theResult____h367312[34] && + !_theResult____h367312[33] && + !_theResult____h367312[32] && + !_theResult____h367312[31] && + !_theResult____h367312[30] && + !_theResult____h367312[29] && + !_theResult____h367312[28] && + !_theResult____h367312[27] && + !_theResult____h367312[26] && + !_theResult____h367312[25] && + !_theResult____h367312[24] && + !_theResult____h367312[23] && + !_theResult____h367312[22] && + !_theResult____h367312[21] && + !_theResult____h367312[20] && + !_theResult____h367312[19] && + !_theResult____h367312[18] && + !_theResult____h367312[17] && + !_theResult____h367312[16] && + !_theResult____h367312[15] && + !_theResult____h367312[14] && + !_theResult____h367312[13] && + !_theResult____h367312[12] && + !_theResult____h367312[11] && + !_theResult____h367312[10] && + !_theResult____h367312[9] && + !_theResult____h367312[8] && + !_theResult____h367312[7] && + !_theResult____h367312[6] && + !_theResult____h367312[5] && + !_theResult____h367312[4] && + !_theResult____h367312[3] && + !_theResult____h367312[2] && + !_theResult____h367312[1] && + !_theResult____h367312[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ? 8'd0 : - _theResult___fst_exp__h375793 ; - assign _theResult___fst_exp__h375802 = - (!_theResult____h367490[56] && _theResult____h367490[55]) ? + _theResult___fst_exp__h375615 ; + assign _theResult___fst_exp__h375624 = + (!_theResult____h367312[56] && _theResult____h367312[55]) ? 8'd1 : - _theResult___fst_exp__h375799 ; - assign _theResult___fst_exp__h376325 = - (_theResult___fst_exp__h375728 == 8'd255) ? - _theResult___fst_exp__h375728 : - _theResult___fst_exp__h376322 ; - assign _theResult___fst_exp__h384365 = + _theResult___fst_exp__h375621 ; + assign _theResult___fst_exp__h376147 = + (_theResult___fst_exp__h375550 == 8'd255) ? + _theResult___fst_exp__h375550 : + _theResult___fst_exp__h376144 ; + assign _theResult___fst_exp__h384187 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; - assign _theResult___fst_exp__h384404 = + assign _theResult___fst_exp__h384226 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h384410 = + assign _theResult___fst_exp__h384232 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ? 8'd0 : - _theResult___fst_exp__h384404 ; - assign _theResult___fst_exp__h384413 = + _theResult___fst_exp__h384226 ; + assign _theResult___fst_exp__h384235 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h384410 : - _theResult___fst_exp__h384365 ; - assign _theResult___fst_exp__h384961 = - (_theResult___fst_exp__h384413 == 8'd255) ? - _theResult___fst_exp__h384413 : - _theResult___fst_exp__h384958 ; - assign _theResult___fst_exp__h384970 = + _theResult___fst_exp__h384232 : + _theResult___fst_exp__h384187 ; + assign _theResult___fst_exp__h384783 = + (_theResult___fst_exp__h384235 == 8'd255) ? + _theResult___fst_exp__h384235 : + _theResult___fst_exp__h384780 ; + assign _theResult___fst_exp__h384792 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_exp__h367144 : - _theResult___fst_exp__h349833) : + _theResult___snd_fst_exp__h366966 : + _theResult___fst_exp__h349655) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_exp__h384964 : - _theResult___fst_exp__h349833) ; - assign _theResult___fst_exp__h384973 = + _theResult___snd_fst_exp__h384786 : + _theResult___fst_exp__h349655) ; + assign _theResult___fst_exp__h384795 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h384970 ; - assign _theResult___fst_exp__h403659 = - _theResult____h395550[56] ? + _theResult___fst_exp__h384792 ; + assign _theResult___fst_exp__h403481 = + _theResult____h395372[56] ? 8'd2 : - _theResult___fst_exp__h403733 ; - assign _theResult___fst_exp__h403724 = + _theResult___fst_exp__h403555 ; + assign _theResult___fst_exp__h403546 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ; - assign _theResult___fst_exp__h403730 = - (!_theResult____h395550[56] && !_theResult____h395550[55] && - !_theResult____h395550[54] && - !_theResult____h395550[53] && - !_theResult____h395550[52] && - !_theResult____h395550[51] && - !_theResult____h395550[50] && - !_theResult____h395550[49] && - !_theResult____h395550[48] && - !_theResult____h395550[47] && - !_theResult____h395550[46] && - !_theResult____h395550[45] && - !_theResult____h395550[44] && - !_theResult____h395550[43] && - !_theResult____h395550[42] && - !_theResult____h395550[41] && - !_theResult____h395550[40] && - !_theResult____h395550[39] && - !_theResult____h395550[38] && - !_theResult____h395550[37] && - !_theResult____h395550[36] && - !_theResult____h395550[35] && - !_theResult____h395550[34] && - !_theResult____h395550[33] && - !_theResult____h395550[32] && - !_theResult____h395550[31] && - !_theResult____h395550[30] && - !_theResult____h395550[29] && - !_theResult____h395550[28] && - !_theResult____h395550[27] && - !_theResult____h395550[26] && - !_theResult____h395550[25] && - !_theResult____h395550[24] && - !_theResult____h395550[23] && - !_theResult____h395550[22] && - !_theResult____h395550[21] && - !_theResult____h395550[20] && - !_theResult____h395550[19] && - !_theResult____h395550[18] && - !_theResult____h395550[17] && - !_theResult____h395550[16] && - !_theResult____h395550[15] && - !_theResult____h395550[14] && - !_theResult____h395550[13] && - !_theResult____h395550[12] && - !_theResult____h395550[11] && - !_theResult____h395550[10] && - !_theResult____h395550[9] && - !_theResult____h395550[8] && - !_theResult____h395550[7] && - !_theResult____h395550[6] && - !_theResult____h395550[5] && - !_theResult____h395550[4] && - !_theResult____h395550[3] && - !_theResult____h395550[2] && - !_theResult____h395550[1] && - !_theResult____h395550[0] || + assign _theResult___fst_exp__h403552 = + (!_theResult____h395372[56] && !_theResult____h395372[55] && + !_theResult____h395372[54] && + !_theResult____h395372[53] && + !_theResult____h395372[52] && + !_theResult____h395372[51] && + !_theResult____h395372[50] && + !_theResult____h395372[49] && + !_theResult____h395372[48] && + !_theResult____h395372[47] && + !_theResult____h395372[46] && + !_theResult____h395372[45] && + !_theResult____h395372[44] && + !_theResult____h395372[43] && + !_theResult____h395372[42] && + !_theResult____h395372[41] && + !_theResult____h395372[40] && + !_theResult____h395372[39] && + !_theResult____h395372[38] && + !_theResult____h395372[37] && + !_theResult____h395372[36] && + !_theResult____h395372[35] && + !_theResult____h395372[34] && + !_theResult____h395372[33] && + !_theResult____h395372[32] && + !_theResult____h395372[31] && + !_theResult____h395372[30] && + !_theResult____h395372[29] && + !_theResult____h395372[28] && + !_theResult____h395372[27] && + !_theResult____h395372[26] && + !_theResult____h395372[25] && + !_theResult____h395372[24] && + !_theResult____h395372[23] && + !_theResult____h395372[22] && + !_theResult____h395372[21] && + !_theResult____h395372[20] && + !_theResult____h395372[19] && + !_theResult____h395372[18] && + !_theResult____h395372[17] && + !_theResult____h395372[16] && + !_theResult____h395372[15] && + !_theResult____h395372[14] && + !_theResult____h395372[13] && + !_theResult____h395372[12] && + !_theResult____h395372[11] && + !_theResult____h395372[10] && + !_theResult____h395372[9] && + !_theResult____h395372[8] && + !_theResult____h395372[7] && + !_theResult____h395372[6] && + !_theResult____h395372[5] && + !_theResult____h395372[4] && + !_theResult____h395372[3] && + !_theResult____h395372[2] && + !_theResult____h395372[1] && + !_theResult____h395372[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ? 8'd0 : - _theResult___fst_exp__h403724 ; - assign _theResult___fst_exp__h403733 = - (!_theResult____h395550[56] && _theResult____h395550[55]) ? + _theResult___fst_exp__h403546 ; + assign _theResult___fst_exp__h403555 = + (!_theResult____h395372[56] && _theResult____h395372[55]) ? 8'd1 : - _theResult___fst_exp__h403730 ; - assign _theResult___fst_exp__h404256 = - (_theResult___fst_exp__h403659 == 8'd255) ? - _theResult___fst_exp__h403659 : - _theResult___fst_exp__h404253 ; - assign _theResult___fst_exp__h412306 = + _theResult___fst_exp__h403552 ; + assign _theResult___fst_exp__h404078 = + (_theResult___fst_exp__h403481 == 8'd255) ? + _theResult___fst_exp__h403481 : + _theResult___fst_exp__h404075 ; + assign _theResult___fst_exp__h412128 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h412312 = + assign _theResult___fst_exp__h412134 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ? 8'd0 : - _theResult___fst_exp__h412306 ; - assign _theResult___fst_exp__h412315 = + _theResult___fst_exp__h412128 ; + assign _theResult___fst_exp__h412137 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h412312 : + _theResult___fst_exp__h412134 : 8'd129 ; - assign _theResult___fst_exp__h412838 = - (_theResult___fst_exp__h412315 == 8'd255) ? - _theResult___fst_exp__h412315 : - _theResult___fst_exp__h412835 ; - assign _theResult___fst_exp__h421425 = - _theResult____h413187[56] ? + assign _theResult___fst_exp__h412660 = + (_theResult___fst_exp__h412137 == 8'd255) ? + _theResult___fst_exp__h412137 : + _theResult___fst_exp__h412657 ; + assign _theResult___fst_exp__h421247 = + _theResult____h413009[56] ? 8'd2 : - _theResult___fst_exp__h421499 ; - assign _theResult___fst_exp__h421490 = + _theResult___fst_exp__h421321 ; + assign _theResult___fst_exp__h421312 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ; - assign _theResult___fst_exp__h421496 = - (!_theResult____h413187[56] && !_theResult____h413187[55] && - !_theResult____h413187[54] && - !_theResult____h413187[53] && - !_theResult____h413187[52] && - !_theResult____h413187[51] && - !_theResult____h413187[50] && - !_theResult____h413187[49] && - !_theResult____h413187[48] && - !_theResult____h413187[47] && - !_theResult____h413187[46] && - !_theResult____h413187[45] && - !_theResult____h413187[44] && - !_theResult____h413187[43] && - !_theResult____h413187[42] && - !_theResult____h413187[41] && - !_theResult____h413187[40] && - !_theResult____h413187[39] && - !_theResult____h413187[38] && - !_theResult____h413187[37] && - !_theResult____h413187[36] && - !_theResult____h413187[35] && - !_theResult____h413187[34] && - !_theResult____h413187[33] && - !_theResult____h413187[32] && - !_theResult____h413187[31] && - !_theResult____h413187[30] && - !_theResult____h413187[29] && - !_theResult____h413187[28] && - !_theResult____h413187[27] && - !_theResult____h413187[26] && - !_theResult____h413187[25] && - !_theResult____h413187[24] && - !_theResult____h413187[23] && - !_theResult____h413187[22] && - !_theResult____h413187[21] && - !_theResult____h413187[20] && - !_theResult____h413187[19] && - !_theResult____h413187[18] && - !_theResult____h413187[17] && - !_theResult____h413187[16] && - !_theResult____h413187[15] && - !_theResult____h413187[14] && - !_theResult____h413187[13] && - !_theResult____h413187[12] && - !_theResult____h413187[11] && - !_theResult____h413187[10] && - !_theResult____h413187[9] && - !_theResult____h413187[8] && - !_theResult____h413187[7] && - !_theResult____h413187[6] && - !_theResult____h413187[5] && - !_theResult____h413187[4] && - !_theResult____h413187[3] && - !_theResult____h413187[2] && - !_theResult____h413187[1] && - !_theResult____h413187[0] || + assign _theResult___fst_exp__h421318 = + (!_theResult____h413009[56] && !_theResult____h413009[55] && + !_theResult____h413009[54] && + !_theResult____h413009[53] && + !_theResult____h413009[52] && + !_theResult____h413009[51] && + !_theResult____h413009[50] && + !_theResult____h413009[49] && + !_theResult____h413009[48] && + !_theResult____h413009[47] && + !_theResult____h413009[46] && + !_theResult____h413009[45] && + !_theResult____h413009[44] && + !_theResult____h413009[43] && + !_theResult____h413009[42] && + !_theResult____h413009[41] && + !_theResult____h413009[40] && + !_theResult____h413009[39] && + !_theResult____h413009[38] && + !_theResult____h413009[37] && + !_theResult____h413009[36] && + !_theResult____h413009[35] && + !_theResult____h413009[34] && + !_theResult____h413009[33] && + !_theResult____h413009[32] && + !_theResult____h413009[31] && + !_theResult____h413009[30] && + !_theResult____h413009[29] && + !_theResult____h413009[28] && + !_theResult____h413009[27] && + !_theResult____h413009[26] && + !_theResult____h413009[25] && + !_theResult____h413009[24] && + !_theResult____h413009[23] && + !_theResult____h413009[22] && + !_theResult____h413009[21] && + !_theResult____h413009[20] && + !_theResult____h413009[19] && + !_theResult____h413009[18] && + !_theResult____h413009[17] && + !_theResult____h413009[16] && + !_theResult____h413009[15] && + !_theResult____h413009[14] && + !_theResult____h413009[13] && + !_theResult____h413009[12] && + !_theResult____h413009[11] && + !_theResult____h413009[10] && + !_theResult____h413009[9] && + !_theResult____h413009[8] && + !_theResult____h413009[7] && + !_theResult____h413009[6] && + !_theResult____h413009[5] && + !_theResult____h413009[4] && + !_theResult____h413009[3] && + !_theResult____h413009[2] && + !_theResult____h413009[1] && + !_theResult____h413009[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ? 8'd0 : - _theResult___fst_exp__h421490 ; - assign _theResult___fst_exp__h421499 = - (!_theResult____h413187[56] && _theResult____h413187[55]) ? + _theResult___fst_exp__h421312 ; + assign _theResult___fst_exp__h421321 = + (!_theResult____h413009[56] && _theResult____h413009[55]) ? 8'd1 : - _theResult___fst_exp__h421496 ; - assign _theResult___fst_exp__h422022 = - (_theResult___fst_exp__h421425 == 8'd255) ? - _theResult___fst_exp__h421425 : - _theResult___fst_exp__h422019 ; - assign _theResult___fst_exp__h430062 = + _theResult___fst_exp__h421318 ; + assign _theResult___fst_exp__h421844 = + (_theResult___fst_exp__h421247 == 8'd255) ? + _theResult___fst_exp__h421247 : + _theResult___fst_exp__h421841 ; + assign _theResult___fst_exp__h429884 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ; - assign _theResult___fst_exp__h430101 = + assign _theResult___fst_exp__h429923 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h430107 = + assign _theResult___fst_exp__h429929 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ? 8'd0 : - _theResult___fst_exp__h430101 ; - assign _theResult___fst_exp__h430110 = + _theResult___fst_exp__h429923 ; + assign _theResult___fst_exp__h429932 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h430107 : - _theResult___fst_exp__h430062 ; - assign _theResult___fst_exp__h430658 = - (_theResult___fst_exp__h430110 == 8'd255) ? - _theResult___fst_exp__h430110 : - _theResult___fst_exp__h430655 ; - assign _theResult___fst_exp__h430667 = + _theResult___fst_exp__h429929 : + _theResult___fst_exp__h429884 ; + assign _theResult___fst_exp__h430480 = + (_theResult___fst_exp__h429932 == 8'd255) ? + _theResult___fst_exp__h429932 : + _theResult___fst_exp__h430477 ; + assign _theResult___fst_exp__h430489 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_exp__h412841 : - _theResult___fst_exp__h395532) : + _theResult___snd_fst_exp__h412663 : + _theResult___fst_exp__h395354) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_exp__h430661 : - _theResult___fst_exp__h395532) ; - assign _theResult___fst_exp__h430670 = + _theResult___snd_fst_exp__h430483 : + _theResult___fst_exp__h395354) ; + assign _theResult___fst_exp__h430492 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h430667 ; - assign _theResult___fst_exp__h449354 = - _theResult____h441245[56] ? + _theResult___fst_exp__h430489 ; + assign _theResult___fst_exp__h449176 = + _theResult____h441067[56] ? 8'd2 : - _theResult___fst_exp__h449428 ; - assign _theResult___fst_exp__h449419 = + _theResult___fst_exp__h449250 ; + assign _theResult___fst_exp__h449241 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ; - assign _theResult___fst_exp__h449425 = - (!_theResult____h441245[56] && !_theResult____h441245[55] && - !_theResult____h441245[54] && - !_theResult____h441245[53] && - !_theResult____h441245[52] && - !_theResult____h441245[51] && - !_theResult____h441245[50] && - !_theResult____h441245[49] && - !_theResult____h441245[48] && - !_theResult____h441245[47] && - !_theResult____h441245[46] && - !_theResult____h441245[45] && - !_theResult____h441245[44] && - !_theResult____h441245[43] && - !_theResult____h441245[42] && - !_theResult____h441245[41] && - !_theResult____h441245[40] && - !_theResult____h441245[39] && - !_theResult____h441245[38] && - !_theResult____h441245[37] && - !_theResult____h441245[36] && - !_theResult____h441245[35] && - !_theResult____h441245[34] && - !_theResult____h441245[33] && - !_theResult____h441245[32] && - !_theResult____h441245[31] && - !_theResult____h441245[30] && - !_theResult____h441245[29] && - !_theResult____h441245[28] && - !_theResult____h441245[27] && - !_theResult____h441245[26] && - !_theResult____h441245[25] && - !_theResult____h441245[24] && - !_theResult____h441245[23] && - !_theResult____h441245[22] && - !_theResult____h441245[21] && - !_theResult____h441245[20] && - !_theResult____h441245[19] && - !_theResult____h441245[18] && - !_theResult____h441245[17] && - !_theResult____h441245[16] && - !_theResult____h441245[15] && - !_theResult____h441245[14] && - !_theResult____h441245[13] && - !_theResult____h441245[12] && - !_theResult____h441245[11] && - !_theResult____h441245[10] && - !_theResult____h441245[9] && - !_theResult____h441245[8] && - !_theResult____h441245[7] && - !_theResult____h441245[6] && - !_theResult____h441245[5] && - !_theResult____h441245[4] && - !_theResult____h441245[3] && - !_theResult____h441245[2] && - !_theResult____h441245[1] && - !_theResult____h441245[0] || + assign _theResult___fst_exp__h449247 = + (!_theResult____h441067[56] && !_theResult____h441067[55] && + !_theResult____h441067[54] && + !_theResult____h441067[53] && + !_theResult____h441067[52] && + !_theResult____h441067[51] && + !_theResult____h441067[50] && + !_theResult____h441067[49] && + !_theResult____h441067[48] && + !_theResult____h441067[47] && + !_theResult____h441067[46] && + !_theResult____h441067[45] && + !_theResult____h441067[44] && + !_theResult____h441067[43] && + !_theResult____h441067[42] && + !_theResult____h441067[41] && + !_theResult____h441067[40] && + !_theResult____h441067[39] && + !_theResult____h441067[38] && + !_theResult____h441067[37] && + !_theResult____h441067[36] && + !_theResult____h441067[35] && + !_theResult____h441067[34] && + !_theResult____h441067[33] && + !_theResult____h441067[32] && + !_theResult____h441067[31] && + !_theResult____h441067[30] && + !_theResult____h441067[29] && + !_theResult____h441067[28] && + !_theResult____h441067[27] && + !_theResult____h441067[26] && + !_theResult____h441067[25] && + !_theResult____h441067[24] && + !_theResult____h441067[23] && + !_theResult____h441067[22] && + !_theResult____h441067[21] && + !_theResult____h441067[20] && + !_theResult____h441067[19] && + !_theResult____h441067[18] && + !_theResult____h441067[17] && + !_theResult____h441067[16] && + !_theResult____h441067[15] && + !_theResult____h441067[14] && + !_theResult____h441067[13] && + !_theResult____h441067[12] && + !_theResult____h441067[11] && + !_theResult____h441067[10] && + !_theResult____h441067[9] && + !_theResult____h441067[8] && + !_theResult____h441067[7] && + !_theResult____h441067[6] && + !_theResult____h441067[5] && + !_theResult____h441067[4] && + !_theResult____h441067[3] && + !_theResult____h441067[2] && + !_theResult____h441067[1] && + !_theResult____h441067[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ? 8'd0 : - _theResult___fst_exp__h449419 ; - assign _theResult___fst_exp__h449428 = - (!_theResult____h441245[56] && _theResult____h441245[55]) ? + _theResult___fst_exp__h449241 ; + assign _theResult___fst_exp__h449250 = + (!_theResult____h441067[56] && _theResult____h441067[55]) ? 8'd1 : - _theResult___fst_exp__h449425 ; - assign _theResult___fst_exp__h449951 = - (_theResult___fst_exp__h449354 == 8'd255) ? - _theResult___fst_exp__h449354 : - _theResult___fst_exp__h449948 ; - assign _theResult___fst_exp__h458001 = + _theResult___fst_exp__h449247 ; + assign _theResult___fst_exp__h449773 = + (_theResult___fst_exp__h449176 == 8'd255) ? + _theResult___fst_exp__h449176 : + _theResult___fst_exp__h449770 ; + assign _theResult___fst_exp__h457823 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h458007 = + assign _theResult___fst_exp__h457829 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ? 8'd0 : - _theResult___fst_exp__h458001 ; - assign _theResult___fst_exp__h458010 = + _theResult___fst_exp__h457823 ; + assign _theResult___fst_exp__h457832 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h458007 : + _theResult___fst_exp__h457829 : 8'd129 ; - assign _theResult___fst_exp__h458533 = - (_theResult___fst_exp__h458010 == 8'd255) ? - _theResult___fst_exp__h458010 : - _theResult___fst_exp__h458530 ; - assign _theResult___fst_exp__h467120 = - _theResult____h458882[56] ? + assign _theResult___fst_exp__h458355 = + (_theResult___fst_exp__h457832 == 8'd255) ? + _theResult___fst_exp__h457832 : + _theResult___fst_exp__h458352 ; + assign _theResult___fst_exp__h466942 = + _theResult____h458704[56] ? 8'd2 : - _theResult___fst_exp__h467194 ; - assign _theResult___fst_exp__h467185 = + _theResult___fst_exp__h467016 ; + assign _theResult___fst_exp__h467007 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ; - assign _theResult___fst_exp__h467191 = - (!_theResult____h458882[56] && !_theResult____h458882[55] && - !_theResult____h458882[54] && - !_theResult____h458882[53] && - !_theResult____h458882[52] && - !_theResult____h458882[51] && - !_theResult____h458882[50] && - !_theResult____h458882[49] && - !_theResult____h458882[48] && - !_theResult____h458882[47] && - !_theResult____h458882[46] && - !_theResult____h458882[45] && - !_theResult____h458882[44] && - !_theResult____h458882[43] && - !_theResult____h458882[42] && - !_theResult____h458882[41] && - !_theResult____h458882[40] && - !_theResult____h458882[39] && - !_theResult____h458882[38] && - !_theResult____h458882[37] && - !_theResult____h458882[36] && - !_theResult____h458882[35] && - !_theResult____h458882[34] && - !_theResult____h458882[33] && - !_theResult____h458882[32] && - !_theResult____h458882[31] && - !_theResult____h458882[30] && - !_theResult____h458882[29] && - !_theResult____h458882[28] && - !_theResult____h458882[27] && - !_theResult____h458882[26] && - !_theResult____h458882[25] && - !_theResult____h458882[24] && - !_theResult____h458882[23] && - !_theResult____h458882[22] && - !_theResult____h458882[21] && - !_theResult____h458882[20] && - !_theResult____h458882[19] && - !_theResult____h458882[18] && - !_theResult____h458882[17] && - !_theResult____h458882[16] && - !_theResult____h458882[15] && - !_theResult____h458882[14] && - !_theResult____h458882[13] && - !_theResult____h458882[12] && - !_theResult____h458882[11] && - !_theResult____h458882[10] && - !_theResult____h458882[9] && - !_theResult____h458882[8] && - !_theResult____h458882[7] && - !_theResult____h458882[6] && - !_theResult____h458882[5] && - !_theResult____h458882[4] && - !_theResult____h458882[3] && - !_theResult____h458882[2] && - !_theResult____h458882[1] && - !_theResult____h458882[0] || + assign _theResult___fst_exp__h467013 = + (!_theResult____h458704[56] && !_theResult____h458704[55] && + !_theResult____h458704[54] && + !_theResult____h458704[53] && + !_theResult____h458704[52] && + !_theResult____h458704[51] && + !_theResult____h458704[50] && + !_theResult____h458704[49] && + !_theResult____h458704[48] && + !_theResult____h458704[47] && + !_theResult____h458704[46] && + !_theResult____h458704[45] && + !_theResult____h458704[44] && + !_theResult____h458704[43] && + !_theResult____h458704[42] && + !_theResult____h458704[41] && + !_theResult____h458704[40] && + !_theResult____h458704[39] && + !_theResult____h458704[38] && + !_theResult____h458704[37] && + !_theResult____h458704[36] && + !_theResult____h458704[35] && + !_theResult____h458704[34] && + !_theResult____h458704[33] && + !_theResult____h458704[32] && + !_theResult____h458704[31] && + !_theResult____h458704[30] && + !_theResult____h458704[29] && + !_theResult____h458704[28] && + !_theResult____h458704[27] && + !_theResult____h458704[26] && + !_theResult____h458704[25] && + !_theResult____h458704[24] && + !_theResult____h458704[23] && + !_theResult____h458704[22] && + !_theResult____h458704[21] && + !_theResult____h458704[20] && + !_theResult____h458704[19] && + !_theResult____h458704[18] && + !_theResult____h458704[17] && + !_theResult____h458704[16] && + !_theResult____h458704[15] && + !_theResult____h458704[14] && + !_theResult____h458704[13] && + !_theResult____h458704[12] && + !_theResult____h458704[11] && + !_theResult____h458704[10] && + !_theResult____h458704[9] && + !_theResult____h458704[8] && + !_theResult____h458704[7] && + !_theResult____h458704[6] && + !_theResult____h458704[5] && + !_theResult____h458704[4] && + !_theResult____h458704[3] && + !_theResult____h458704[2] && + !_theResult____h458704[1] && + !_theResult____h458704[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ? 8'd0 : - _theResult___fst_exp__h467185 ; - assign _theResult___fst_exp__h467194 = - (!_theResult____h458882[56] && _theResult____h458882[55]) ? + _theResult___fst_exp__h467007 ; + assign _theResult___fst_exp__h467016 = + (!_theResult____h458704[56] && _theResult____h458704[55]) ? 8'd1 : - _theResult___fst_exp__h467191 ; - assign _theResult___fst_exp__h467717 = - (_theResult___fst_exp__h467120 == 8'd255) ? - _theResult___fst_exp__h467120 : - _theResult___fst_exp__h467714 ; - assign _theResult___fst_exp__h475757 = + _theResult___fst_exp__h467013 ; + assign _theResult___fst_exp__h467539 = + (_theResult___fst_exp__h466942 == 8'd255) ? + _theResult___fst_exp__h466942 : + _theResult___fst_exp__h467536 ; + assign _theResult___fst_exp__h475579 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ; - assign _theResult___fst_exp__h475796 = + assign _theResult___fst_exp__h475618 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h475802 = + assign _theResult___fst_exp__h475624 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ? 8'd0 : - _theResult___fst_exp__h475796 ; - assign _theResult___fst_exp__h475805 = + _theResult___fst_exp__h475618 ; + assign _theResult___fst_exp__h475627 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h475802 : - _theResult___fst_exp__h475757 ; - assign _theResult___fst_exp__h476353 = - (_theResult___fst_exp__h475805 == 8'd255) ? - _theResult___fst_exp__h475805 : - _theResult___fst_exp__h476350 ; - assign _theResult___fst_exp__h476362 = + _theResult___fst_exp__h475624 : + _theResult___fst_exp__h475579 ; + assign _theResult___fst_exp__h476175 = + (_theResult___fst_exp__h475627 == 8'd255) ? + _theResult___fst_exp__h475627 : + _theResult___fst_exp__h476172 ; + assign _theResult___fst_exp__h476184 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_exp__h458536 : - _theResult___fst_exp__h441227) : + _theResult___snd_fst_exp__h458358 : + _theResult___fst_exp__h441049) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_exp__h476356 : - _theResult___fst_exp__h441227) ; - assign _theResult___fst_exp__h476365 = + _theResult___snd_fst_exp__h476178 : + _theResult___fst_exp__h441049) ; + assign _theResult___fst_exp__h476187 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h476362 ; - assign _theResult___fst_exp__h490957 = + _theResult___fst_exp__h476184 ; + assign _theResult___fst_exp__h490779 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h506021 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; + assign _theResult___fst_exp__h505843 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h506027 = - (f1_exp__h486642 == 8'd0 && !f1_sfd__h486643[22] && + assign _theResult___fst_exp__h505849 = + (f1_exp__h486464 == 8'd0 && !f1_sfd__h486465[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696) ? 11'd0 : - _theResult___fst_exp__h506021 ; - assign _theResult___fst_exp__h506030 = - (f1_exp__h486642 == 8'd0) ? - _theResult___fst_exp__h506027 : + _theResult___fst_exp__h505843 ; + assign _theResult___fst_exp__h505852 = + (f1_exp__h486464 == 8'd0) ? + _theResult___fst_exp__h505849 : 11'd897 ; - assign _theResult___fst_exp__h506785 = + assign _theResult___fst_exp__h506607 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q136 : + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 ; - assign _theResult___fst_exp__h506788 = - (_theResult___fst_exp__h506030 == 11'd2047) ? - _theResult___fst_exp__h506030 : - _theResult___fst_exp__h506785 ; - assign _theResult___fst_exp__h515607 = - _theResult____h507371[56] ? + assign _theResult___fst_exp__h506610 = + (_theResult___fst_exp__h505852 == 11'd2047) ? + _theResult___fst_exp__h505852 : + _theResult___fst_exp__h506607 ; + assign _theResult___fst_exp__h515429 = + _theResult____h507193[56] ? 11'd2 : - _theResult___fst_exp__h515681 ; - assign _theResult___fst_exp__h515672 = + _theResult___fst_exp__h515503 ; + assign _theResult___fst_exp__h515494 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ; - assign _theResult___fst_exp__h515678 = - (!_theResult____h507371[56] && !_theResult____h507371[55] && - !_theResult____h507371[54] && - !_theResult____h507371[53] && - !_theResult____h507371[52] && - !_theResult____h507371[51] && - !_theResult____h507371[50] && - !_theResult____h507371[49] && - !_theResult____h507371[48] && - !_theResult____h507371[47] && - !_theResult____h507371[46] && - !_theResult____h507371[45] && - !_theResult____h507371[44] && - !_theResult____h507371[43] && - !_theResult____h507371[42] && - !_theResult____h507371[41] && - !_theResult____h507371[40] && - !_theResult____h507371[39] && - !_theResult____h507371[38] && - !_theResult____h507371[37] && - !_theResult____h507371[36] && - !_theResult____h507371[35] && - !_theResult____h507371[34] && - !_theResult____h507371[33] && - !_theResult____h507371[32] && - !_theResult____h507371[31] && - !_theResult____h507371[30] && - !_theResult____h507371[29] && - !_theResult____h507371[28] && - !_theResult____h507371[27] && - !_theResult____h507371[26] && - !_theResult____h507371[25] && - !_theResult____h507371[24] && - !_theResult____h507371[23] && - !_theResult____h507371[22] && - !_theResult____h507371[21] && - !_theResult____h507371[20] && - !_theResult____h507371[19] && - !_theResult____h507371[18] && - !_theResult____h507371[17] && - !_theResult____h507371[16] && - !_theResult____h507371[15] && - !_theResult____h507371[14] && - !_theResult____h507371[13] && - !_theResult____h507371[12] && - !_theResult____h507371[11] && - !_theResult____h507371[10] && - !_theResult____h507371[9] && - !_theResult____h507371[8] && - !_theResult____h507371[7] && - !_theResult____h507371[6] && - !_theResult____h507371[5] && - !_theResult____h507371[4] && - !_theResult____h507371[3] && - !_theResult____h507371[2] && - !_theResult____h507371[1] && - !_theResult____h507371[0] || + assign _theResult___fst_exp__h515500 = + (!_theResult____h507193[56] && !_theResult____h507193[55] && + !_theResult____h507193[54] && + !_theResult____h507193[53] && + !_theResult____h507193[52] && + !_theResult____h507193[51] && + !_theResult____h507193[50] && + !_theResult____h507193[49] && + !_theResult____h507193[48] && + !_theResult____h507193[47] && + !_theResult____h507193[46] && + !_theResult____h507193[45] && + !_theResult____h507193[44] && + !_theResult____h507193[43] && + !_theResult____h507193[42] && + !_theResult____h507193[41] && + !_theResult____h507193[40] && + !_theResult____h507193[39] && + !_theResult____h507193[38] && + !_theResult____h507193[37] && + !_theResult____h507193[36] && + !_theResult____h507193[35] && + !_theResult____h507193[34] && + !_theResult____h507193[33] && + !_theResult____h507193[32] && + !_theResult____h507193[31] && + !_theResult____h507193[30] && + !_theResult____h507193[29] && + !_theResult____h507193[28] && + !_theResult____h507193[27] && + !_theResult____h507193[26] && + !_theResult____h507193[25] && + !_theResult____h507193[24] && + !_theResult____h507193[23] && + !_theResult____h507193[22] && + !_theResult____h507193[21] && + !_theResult____h507193[20] && + !_theResult____h507193[19] && + !_theResult____h507193[18] && + !_theResult____h507193[17] && + !_theResult____h507193[16] && + !_theResult____h507193[15] && + !_theResult____h507193[14] && + !_theResult____h507193[13] && + !_theResult____h507193[12] && + !_theResult____h507193[11] && + !_theResult____h507193[10] && + !_theResult____h507193[9] && + !_theResult____h507193[8] && + !_theResult____h507193[7] && + !_theResult____h507193[6] && + !_theResult____h507193[5] && + !_theResult____h507193[4] && + !_theResult____h507193[3] && + !_theResult____h507193[2] && + !_theResult____h507193[1] && + !_theResult____h507193[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008) ? 11'd0 : - _theResult___fst_exp__h515672 ; - assign _theResult___fst_exp__h515681 = - (!_theResult____h507371[56] && _theResult____h507371[55]) ? + _theResult___fst_exp__h515494 ; + assign _theResult___fst_exp__h515503 = + (!_theResult____h507193[56] && _theResult____h507193[55]) ? 11'd1 : - _theResult___fst_exp__h515678 ; - assign _theResult___fst_exp__h516436 = + _theResult___fst_exp__h515500 ; + assign _theResult___fst_exp__h516258 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q204 : + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 ; - assign _theResult___fst_exp__h516439 = - (_theResult___fst_exp__h515607 == 11'd2047) ? - _theResult___fst_exp__h515607 : - _theResult___fst_exp__h516436 ; - assign _theResult___fst_exp__h524392 = + assign _theResult___fst_exp__h516261 = + (_theResult___fst_exp__h515429 == 11'd2047) ? + _theResult___fst_exp__h515429 : + _theResult___fst_exp__h516258 ; + assign _theResult___fst_exp__h524214 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ; - assign _theResult___fst_exp__h524431 = + assign _theResult___fst_exp__h524253 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h524437 = - (f1_exp__h486642 == 8'd0 && !f1_sfd__h486643[22] && + assign _theResult___fst_exp__h524259 = + (f1_exp__h486464 == 8'd0 && !f1_sfd__h486465[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058) ? 11'd0 : - _theResult___fst_exp__h524431 ; - assign _theResult___fst_exp__h524440 = - (f1_exp__h486642 == 8'd0) ? - _theResult___fst_exp__h524437 : - _theResult___fst_exp__h524392 ; - assign _theResult___fst_exp__h525220 = + _theResult___fst_exp__h524253 ; + assign _theResult___fst_exp__h524262 = + (f1_exp__h486464 == 8'd0) ? + _theResult___fst_exp__h524259 : + _theResult___fst_exp__h524214 ; + assign _theResult___fst_exp__h525042 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q206 : + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 ; - assign _theResult___fst_exp__h525223 = - (_theResult___fst_exp__h524440 == 11'd2047) ? - _theResult___fst_exp__h524440 : - _theResult___fst_exp__h525220 ; - assign _theResult___fst_exp__h525232 = - (f1_exp__h486642 == 8'd0) ? + assign _theResult___fst_exp__h525045 = + (_theResult___fst_exp__h524262 == 11'd2047) ? + _theResult___fst_exp__h524262 : + _theResult___fst_exp__h525042 ; + assign _theResult___fst_exp__h525054 = + (f1_exp__h486464 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_exp__h506791 : - _theResult___fst_exp__h490957) : + _theResult___snd_fst_exp__h506613 : + _theResult___fst_exp__h490779) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_exp__h525226 : - _theResult___fst_exp__h490957) ; - assign _theResult___fst_exp__h525235 = - (f1_exp__h486642 == 8'd0 && f1_sfd__h486643 == 23'd0) ? + _theResult___snd_fst_exp__h525048 : + _theResult___fst_exp__h490779) ; + assign _theResult___fst_exp__h525057 = + (f1_exp__h486464 == 8'd0 && f1_sfd__h486465 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h525232 ; - assign _theResult___fst_exp__h529810 = + _theResult___fst_exp__h525054 ; + assign _theResult___fst_exp__h529632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_exp__h544874 = + assign _theResult___fst_exp__h544696 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h544880 = - (f2_exp__h525636 == 8'd0 && !f2_sfd__h525637[22] && + assign _theResult___fst_exp__h544702 = + (f2_exp__h525458 == 8'd0 && !f2_sfd__h525459[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196) ? 11'd0 : - _theResult___fst_exp__h544874 ; - assign _theResult___fst_exp__h544883 = - (f2_exp__h525636 == 8'd0) ? - _theResult___fst_exp__h544880 : + _theResult___fst_exp__h544696 ; + assign _theResult___fst_exp__h544705 = + (f2_exp__h525458 == 8'd0) ? + _theResult___fst_exp__h544702 : 11'd897 ; - assign _theResult___fst_exp__h545638 = + assign _theResult___fst_exp__h545460 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q176 : + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 ; - assign _theResult___fst_exp__h545641 = - (_theResult___fst_exp__h544883 == 11'd2047) ? - _theResult___fst_exp__h544883 : - _theResult___fst_exp__h545638 ; - assign _theResult___fst_exp__h554460 = - _theResult____h546224[56] ? + assign _theResult___fst_exp__h545463 = + (_theResult___fst_exp__h544705 == 11'd2047) ? + _theResult___fst_exp__h544705 : + _theResult___fst_exp__h545460 ; + assign _theResult___fst_exp__h554282 = + _theResult____h546046[56] ? 11'd2 : - _theResult___fst_exp__h554534 ; - assign _theResult___fst_exp__h554525 = + _theResult___fst_exp__h554356 ; + assign _theResult___fst_exp__h554347 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ; - assign _theResult___fst_exp__h554531 = - (!_theResult____h546224[56] && !_theResult____h546224[55] && - !_theResult____h546224[54] && - !_theResult____h546224[53] && - !_theResult____h546224[52] && - !_theResult____h546224[51] && - !_theResult____h546224[50] && - !_theResult____h546224[49] && - !_theResult____h546224[48] && - !_theResult____h546224[47] && - !_theResult____h546224[46] && - !_theResult____h546224[45] && - !_theResult____h546224[44] && - !_theResult____h546224[43] && - !_theResult____h546224[42] && - !_theResult____h546224[41] && - !_theResult____h546224[40] && - !_theResult____h546224[39] && - !_theResult____h546224[38] && - !_theResult____h546224[37] && - !_theResult____h546224[36] && - !_theResult____h546224[35] && - !_theResult____h546224[34] && - !_theResult____h546224[33] && - !_theResult____h546224[32] && - !_theResult____h546224[31] && - !_theResult____h546224[30] && - !_theResult____h546224[29] && - !_theResult____h546224[28] && - !_theResult____h546224[27] && - !_theResult____h546224[26] && - !_theResult____h546224[25] && - !_theResult____h546224[24] && - !_theResult____h546224[23] && - !_theResult____h546224[22] && - !_theResult____h546224[21] && - !_theResult____h546224[20] && - !_theResult____h546224[19] && - !_theResult____h546224[18] && - !_theResult____h546224[17] && - !_theResult____h546224[16] && - !_theResult____h546224[15] && - !_theResult____h546224[14] && - !_theResult____h546224[13] && - !_theResult____h546224[12] && - !_theResult____h546224[11] && - !_theResult____h546224[10] && - !_theResult____h546224[9] && - !_theResult____h546224[8] && - !_theResult____h546224[7] && - !_theResult____h546224[6] && - !_theResult____h546224[5] && - !_theResult____h546224[4] && - !_theResult____h546224[3] && - !_theResult____h546224[2] && - !_theResult____h546224[1] && - !_theResult____h546224[0] || + assign _theResult___fst_exp__h554353 = + (!_theResult____h546046[56] && !_theResult____h546046[55] && + !_theResult____h546046[54] && + !_theResult____h546046[53] && + !_theResult____h546046[52] && + !_theResult____h546046[51] && + !_theResult____h546046[50] && + !_theResult____h546046[49] && + !_theResult____h546046[48] && + !_theResult____h546046[47] && + !_theResult____h546046[46] && + !_theResult____h546046[45] && + !_theResult____h546046[44] && + !_theResult____h546046[43] && + !_theResult____h546046[42] && + !_theResult____h546046[41] && + !_theResult____h546046[40] && + !_theResult____h546046[39] && + !_theResult____h546046[38] && + !_theResult____h546046[37] && + !_theResult____h546046[36] && + !_theResult____h546046[35] && + !_theResult____h546046[34] && + !_theResult____h546046[33] && + !_theResult____h546046[32] && + !_theResult____h546046[31] && + !_theResult____h546046[30] && + !_theResult____h546046[29] && + !_theResult____h546046[28] && + !_theResult____h546046[27] && + !_theResult____h546046[26] && + !_theResult____h546046[25] && + !_theResult____h546046[24] && + !_theResult____h546046[23] && + !_theResult____h546046[22] && + !_theResult____h546046[21] && + !_theResult____h546046[20] && + !_theResult____h546046[19] && + !_theResult____h546046[18] && + !_theResult____h546046[17] && + !_theResult____h546046[16] && + !_theResult____h546046[15] && + !_theResult____h546046[14] && + !_theResult____h546046[13] && + !_theResult____h546046[12] && + !_theResult____h546046[11] && + !_theResult____h546046[10] && + !_theResult____h546046[9] && + !_theResult____h546046[8] && + !_theResult____h546046[7] && + !_theResult____h546046[6] && + !_theResult____h546046[5] && + !_theResult____h546046[4] && + !_theResult____h546046[3] && + !_theResult____h546046[2] && + !_theResult____h546046[1] && + !_theResult____h546046[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493) ? 11'd0 : - _theResult___fst_exp__h554525 ; - assign _theResult___fst_exp__h554534 = - (!_theResult____h546224[56] && _theResult____h546224[55]) ? + _theResult___fst_exp__h554347 ; + assign _theResult___fst_exp__h554356 = + (!_theResult____h546046[56] && _theResult____h546046[55]) ? 11'd1 : - _theResult___fst_exp__h554531 ; - assign _theResult___fst_exp__h555289 = + _theResult___fst_exp__h554353 ; + assign _theResult___fst_exp__h555111 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q180 : + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 ; - assign _theResult___fst_exp__h555292 = - (_theResult___fst_exp__h554460 == 11'd2047) ? - _theResult___fst_exp__h554460 : - _theResult___fst_exp__h555289 ; - assign _theResult___fst_exp__h563245 = + assign _theResult___fst_exp__h555114 = + (_theResult___fst_exp__h554282 == 11'd2047) ? + _theResult___fst_exp__h554282 : + _theResult___fst_exp__h555111 ; + assign _theResult___fst_exp__h563067 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ; - assign _theResult___fst_exp__h563284 = + assign _theResult___fst_exp__h563106 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h563290 = - (f2_exp__h525636 == 8'd0 && !f2_sfd__h525637[22] && + assign _theResult___fst_exp__h563112 = + (f2_exp__h525458 == 8'd0 && !f2_sfd__h525459[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543) ? 11'd0 : - _theResult___fst_exp__h563284 ; - assign _theResult___fst_exp__h563293 = - (f2_exp__h525636 == 8'd0) ? - _theResult___fst_exp__h563290 : - _theResult___fst_exp__h563245 ; - assign _theResult___fst_exp__h564073 = + _theResult___fst_exp__h563106 ; + assign _theResult___fst_exp__h563115 = + (f2_exp__h525458 == 8'd0) ? + _theResult___fst_exp__h563112 : + _theResult___fst_exp__h563067 ; + assign _theResult___fst_exp__h563895 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q178 : + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 ; - assign _theResult___fst_exp__h564076 = - (_theResult___fst_exp__h563293 == 11'd2047) ? - _theResult___fst_exp__h563293 : - _theResult___fst_exp__h564073 ; - assign _theResult___fst_exp__h564085 = - (f2_exp__h525636 == 8'd0) ? + assign _theResult___fst_exp__h563898 = + (_theResult___fst_exp__h563115 == 11'd2047) ? + _theResult___fst_exp__h563115 : + _theResult___fst_exp__h563895 ; + assign _theResult___fst_exp__h563907 = + (f2_exp__h525458 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_exp__h545644 : - _theResult___fst_exp__h529810) : + _theResult___snd_fst_exp__h545466 : + _theResult___fst_exp__h529632) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_exp__h564079 : - _theResult___fst_exp__h529810) ; - assign _theResult___fst_exp__h564088 = - (f2_exp__h525636 == 8'd0 && f2_sfd__h525637 == 23'd0) ? + _theResult___snd_fst_exp__h563901 : + _theResult___fst_exp__h529632) ; + assign _theResult___fst_exp__h563910 = + (f2_exp__h525458 == 8'd0 && f2_sfd__h525459 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h564085 ; - assign _theResult___fst_exp__h569114 = + _theResult___fst_exp__h563907 ; + assign _theResult___fst_exp__h568936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_exp__h584178 = + assign _theResult___fst_exp__h584000 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h584184 = - (f3_exp__h564940 == 8'd0 && !f3_sfd__h564941[22] && + assign _theResult___fst_exp__h584006 = + (f3_exp__h564762 == 8'd0 && !f3_sfd__h564763[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426) ? 11'd0 : - _theResult___fst_exp__h584178 ; - assign _theResult___fst_exp__h584187 = - (f3_exp__h564940 == 8'd0) ? - _theResult___fst_exp__h584184 : + _theResult___fst_exp__h584000 ; + assign _theResult___fst_exp__h584009 = + (f3_exp__h564762 == 8'd0) ? + _theResult___fst_exp__h584006 : 11'd897 ; - assign _theResult___fst_exp__h584942 = + assign _theResult___fst_exp__h584764 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q153 : + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 ; - assign _theResult___fst_exp__h584945 = - (_theResult___fst_exp__h584187 == 11'd2047) ? - _theResult___fst_exp__h584187 : - _theResult___fst_exp__h584942 ; - assign _theResult___fst_exp__h593764 = - _theResult____h585528[56] ? + assign _theResult___fst_exp__h584767 = + (_theResult___fst_exp__h584009 == 11'd2047) ? + _theResult___fst_exp__h584009 : + _theResult___fst_exp__h584764 ; + assign _theResult___fst_exp__h593586 = + _theResult____h585350[56] ? 11'd2 : - _theResult___fst_exp__h593838 ; - assign _theResult___fst_exp__h593829 = + _theResult___fst_exp__h593660 ; + assign _theResult___fst_exp__h593651 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ; - assign _theResult___fst_exp__h593835 = - (!_theResult____h585528[56] && !_theResult____h585528[55] && - !_theResult____h585528[54] && - !_theResult____h585528[53] && - !_theResult____h585528[52] && - !_theResult____h585528[51] && - !_theResult____h585528[50] && - !_theResult____h585528[49] && - !_theResult____h585528[48] && - !_theResult____h585528[47] && - !_theResult____h585528[46] && - !_theResult____h585528[45] && - !_theResult____h585528[44] && - !_theResult____h585528[43] && - !_theResult____h585528[42] && - !_theResult____h585528[41] && - !_theResult____h585528[40] && - !_theResult____h585528[39] && - !_theResult____h585528[38] && - !_theResult____h585528[37] && - !_theResult____h585528[36] && - !_theResult____h585528[35] && - !_theResult____h585528[34] && - !_theResult____h585528[33] && - !_theResult____h585528[32] && - !_theResult____h585528[31] && - !_theResult____h585528[30] && - !_theResult____h585528[29] && - !_theResult____h585528[28] && - !_theResult____h585528[27] && - !_theResult____h585528[26] && - !_theResult____h585528[25] && - !_theResult____h585528[24] && - !_theResult____h585528[23] && - !_theResult____h585528[22] && - !_theResult____h585528[21] && - !_theResult____h585528[20] && - !_theResult____h585528[19] && - !_theResult____h585528[18] && - !_theResult____h585528[17] && - !_theResult____h585528[16] && - !_theResult____h585528[15] && - !_theResult____h585528[14] && - !_theResult____h585528[13] && - !_theResult____h585528[12] && - !_theResult____h585528[11] && - !_theResult____h585528[10] && - !_theResult____h585528[9] && - !_theResult____h585528[8] && - !_theResult____h585528[7] && - !_theResult____h585528[6] && - !_theResult____h585528[5] && - !_theResult____h585528[4] && - !_theResult____h585528[3] && - !_theResult____h585528[2] && - !_theResult____h585528[1] && - !_theResult____h585528[0] || + assign _theResult___fst_exp__h593657 = + (!_theResult____h585350[56] && !_theResult____h585350[55] && + !_theResult____h585350[54] && + !_theResult____h585350[53] && + !_theResult____h585350[52] && + !_theResult____h585350[51] && + !_theResult____h585350[50] && + !_theResult____h585350[49] && + !_theResult____h585350[48] && + !_theResult____h585350[47] && + !_theResult____h585350[46] && + !_theResult____h585350[45] && + !_theResult____h585350[44] && + !_theResult____h585350[43] && + !_theResult____h585350[42] && + !_theResult____h585350[41] && + !_theResult____h585350[40] && + !_theResult____h585350[39] && + !_theResult____h585350[38] && + !_theResult____h585350[37] && + !_theResult____h585350[36] && + !_theResult____h585350[35] && + !_theResult____h585350[34] && + !_theResult____h585350[33] && + !_theResult____h585350[32] && + !_theResult____h585350[31] && + !_theResult____h585350[30] && + !_theResult____h585350[29] && + !_theResult____h585350[28] && + !_theResult____h585350[27] && + !_theResult____h585350[26] && + !_theResult____h585350[25] && + !_theResult____h585350[24] && + !_theResult____h585350[23] && + !_theResult____h585350[22] && + !_theResult____h585350[21] && + !_theResult____h585350[20] && + !_theResult____h585350[19] && + !_theResult____h585350[18] && + !_theResult____h585350[17] && + !_theResult____h585350[16] && + !_theResult____h585350[15] && + !_theResult____h585350[14] && + !_theResult____h585350[13] && + !_theResult____h585350[12] && + !_theResult____h585350[11] && + !_theResult____h585350[10] && + !_theResult____h585350[9] && + !_theResult____h585350[8] && + !_theResult____h585350[7] && + !_theResult____h585350[6] && + !_theResult____h585350[5] && + !_theResult____h585350[4] && + !_theResult____h585350[3] && + !_theResult____h585350[2] && + !_theResult____h585350[1] && + !_theResult____h585350[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723) ? 11'd0 : - _theResult___fst_exp__h593829 ; - assign _theResult___fst_exp__h593838 = - (!_theResult____h585528[56] && _theResult____h585528[55]) ? + _theResult___fst_exp__h593651 ; + assign _theResult___fst_exp__h593660 = + (!_theResult____h585350[56] && _theResult____h585350[55]) ? 11'd1 : - _theResult___fst_exp__h593835 ; - assign _theResult___fst_exp__h594593 = + _theResult___fst_exp__h593657 ; + assign _theResult___fst_exp__h594415 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q182 : + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 ; - assign _theResult___fst_exp__h594596 = - (_theResult___fst_exp__h593764 == 11'd2047) ? - _theResult___fst_exp__h593764 : - _theResult___fst_exp__h594593 ; - assign _theResult___fst_exp__h602549 = + assign _theResult___fst_exp__h594418 = + (_theResult___fst_exp__h593586 == 11'd2047) ? + _theResult___fst_exp__h593586 : + _theResult___fst_exp__h594415 ; + assign _theResult___fst_exp__h602371 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ; - assign _theResult___fst_exp__h602588 = + assign _theResult___fst_exp__h602410 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h602594 = - (f3_exp__h564940 == 8'd0 && !f3_sfd__h564941[22] && + assign _theResult___fst_exp__h602416 = + (f3_exp__h564762 == 8'd0 && !f3_sfd__h564763[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773) ? 11'd0 : - _theResult___fst_exp__h602588 ; - assign _theResult___fst_exp__h602597 = - (f3_exp__h564940 == 8'd0) ? - _theResult___fst_exp__h602594 : - _theResult___fst_exp__h602549 ; - assign _theResult___fst_exp__h603377 = + _theResult___fst_exp__h602410 ; + assign _theResult___fst_exp__h602419 = + (f3_exp__h564762 == 8'd0) ? + _theResult___fst_exp__h602416 : + _theResult___fst_exp__h602371 ; + assign _theResult___fst_exp__h603199 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q184 : + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 ; - assign _theResult___fst_exp__h603380 = - (_theResult___fst_exp__h602597 == 11'd2047) ? - _theResult___fst_exp__h602597 : - _theResult___fst_exp__h603377 ; - assign _theResult___fst_exp__h603389 = - (f3_exp__h564940 == 8'd0) ? + assign _theResult___fst_exp__h603202 = + (_theResult___fst_exp__h602419 == 11'd2047) ? + _theResult___fst_exp__h602419 : + _theResult___fst_exp__h603199 ; + assign _theResult___fst_exp__h603211 = + (f3_exp__h564762 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_exp__h584948 : - _theResult___fst_exp__h569114) : + _theResult___snd_fst_exp__h584770 : + _theResult___fst_exp__h568936) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_exp__h603383 : - _theResult___fst_exp__h569114) ; - assign _theResult___fst_exp__h603392 = - (f3_exp__h564940 == 8'd0 && f3_sfd__h564941 == 23'd0) ? + _theResult___snd_fst_exp__h603205 : + _theResult___fst_exp__h568936) ; + assign _theResult___fst_exp__h603214 = + (f3_exp__h564762 == 8'd0 && f3_sfd__h564763 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h603389 ; - assign _theResult___fst_sfd__h358560 = - (_theResult___fst_exp__h357962 == 8'd255) ? - sfdin__h357956[56:34] : - _theResult___fst_sfd__h358557 ; - assign _theResult___fst_sfd__h367142 = - (_theResult___fst_exp__h366618 == 8'd255) ? - _theResult___snd__h366569[56:34] : - _theResult___fst_sfd__h367139 ; - assign _theResult___fst_sfd__h376326 = - (_theResult___fst_exp__h375728 == 8'd255) ? - sfdin__h375722[56:34] : - _theResult___fst_sfd__h376323 ; - assign _theResult___fst_sfd__h384962 = - (_theResult___fst_exp__h384413 == 8'd255) ? - _theResult___snd__h384359[56:34] : - _theResult___fst_sfd__h384959 ; - assign _theResult___fst_sfd__h384971 = + _theResult___fst_exp__h603211 ; + assign _theResult___fst_sfd__h358382 = + (_theResult___fst_exp__h357784 == 8'd255) ? + sfdin__h357778[56:34] : + _theResult___fst_sfd__h358379 ; + assign _theResult___fst_sfd__h366964 = + (_theResult___fst_exp__h366440 == 8'd255) ? + _theResult___snd__h366391[56:34] : + _theResult___fst_sfd__h366961 ; + assign _theResult___fst_sfd__h376148 = + (_theResult___fst_exp__h375550 == 8'd255) ? + sfdin__h375544[56:34] : + _theResult___fst_sfd__h376145 ; + assign _theResult___fst_sfd__h384784 = + (_theResult___fst_exp__h384235 == 8'd255) ? + _theResult___snd__h384181[56:34] : + _theResult___fst_sfd__h384781 ; + assign _theResult___fst_sfd__h384793 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_sfd__h367145 : - _theResult___fst_sfd__h349834) : + _theResult___snd_fst_sfd__h366967 : + _theResult___fst_sfd__h349656) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_sfd__h384965 : - _theResult___fst_sfd__h349834) ; - assign _theResult___fst_sfd__h384977 = + _theResult___snd_fst_sfd__h384787 : + _theResult___fst_sfd__h349656) ; + assign _theResult___fst_sfd__h384799 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -26340,33 +26092,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h384971 ; - assign _theResult___fst_sfd__h404257 = - (_theResult___fst_exp__h403659 == 8'd255) ? - sfdin__h403653[56:34] : - _theResult___fst_sfd__h404254 ; - assign _theResult___fst_sfd__h412839 = - (_theResult___fst_exp__h412315 == 8'd255) ? - _theResult___snd__h412266[56:34] : - _theResult___fst_sfd__h412836 ; - assign _theResult___fst_sfd__h422023 = - (_theResult___fst_exp__h421425 == 8'd255) ? - sfdin__h421419[56:34] : - _theResult___fst_sfd__h422020 ; - assign _theResult___fst_sfd__h430659 = - (_theResult___fst_exp__h430110 == 8'd255) ? - _theResult___snd__h430056[56:34] : - _theResult___fst_sfd__h430656 ; - assign _theResult___fst_sfd__h430668 = + _theResult___fst_sfd__h384793 ; + assign _theResult___fst_sfd__h404079 = + (_theResult___fst_exp__h403481 == 8'd255) ? + sfdin__h403475[56:34] : + _theResult___fst_sfd__h404076 ; + assign _theResult___fst_sfd__h412661 = + (_theResult___fst_exp__h412137 == 8'd255) ? + _theResult___snd__h412088[56:34] : + _theResult___fst_sfd__h412658 ; + assign _theResult___fst_sfd__h421845 = + (_theResult___fst_exp__h421247 == 8'd255) ? + sfdin__h421241[56:34] : + _theResult___fst_sfd__h421842 ; + assign _theResult___fst_sfd__h430481 = + (_theResult___fst_exp__h429932 == 8'd255) ? + _theResult___snd__h429878[56:34] : + _theResult___fst_sfd__h430478 ; + assign _theResult___fst_sfd__h430490 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_sfd__h412842 : - _theResult___fst_sfd__h395533) : + _theResult___snd_fst_sfd__h412664 : + _theResult___fst_sfd__h395355) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_sfd__h430662 : - _theResult___fst_sfd__h395533) ; - assign _theResult___fst_sfd__h430674 = + _theResult___snd_fst_sfd__h430484 : + _theResult___fst_sfd__h395355) ; + assign _theResult___fst_sfd__h430496 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -26374,33 +26126,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h430668 ; - assign _theResult___fst_sfd__h449952 = - (_theResult___fst_exp__h449354 == 8'd255) ? - sfdin__h449348[56:34] : - _theResult___fst_sfd__h449949 ; - assign _theResult___fst_sfd__h458534 = - (_theResult___fst_exp__h458010 == 8'd255) ? - _theResult___snd__h457961[56:34] : - _theResult___fst_sfd__h458531 ; - assign _theResult___fst_sfd__h467718 = - (_theResult___fst_exp__h467120 == 8'd255) ? - sfdin__h467114[56:34] : - _theResult___fst_sfd__h467715 ; - assign _theResult___fst_sfd__h476354 = - (_theResult___fst_exp__h475805 == 8'd255) ? - _theResult___snd__h475751[56:34] : - _theResult___fst_sfd__h476351 ; - assign _theResult___fst_sfd__h476363 = + _theResult___fst_sfd__h430490 ; + assign _theResult___fst_sfd__h449774 = + (_theResult___fst_exp__h449176 == 8'd255) ? + sfdin__h449170[56:34] : + _theResult___fst_sfd__h449771 ; + assign _theResult___fst_sfd__h458356 = + (_theResult___fst_exp__h457832 == 8'd255) ? + _theResult___snd__h457783[56:34] : + _theResult___fst_sfd__h458353 ; + assign _theResult___fst_sfd__h467540 = + (_theResult___fst_exp__h466942 == 8'd255) ? + sfdin__h466936[56:34] : + _theResult___fst_sfd__h467537 ; + assign _theResult___fst_sfd__h476176 = + (_theResult___fst_exp__h475627 == 8'd255) ? + _theResult___snd__h475573[56:34] : + _theResult___fst_sfd__h476173 ; + assign _theResult___fst_sfd__h476185 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_sfd__h458537 : - _theResult___fst_sfd__h441228) : + _theResult___snd_fst_sfd__h458359 : + _theResult___fst_sfd__h441050) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_sfd__h476357 : - _theResult___fst_sfd__h441228) ; - assign _theResult___fst_sfd__h476369 = + _theResult___snd_fst_sfd__h476179 : + _theResult___fst_sfd__h441050) ; + assign _theResult___fst_sfd__h476191 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -26408,1312 +26160,1312 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h476363 ; - assign _theResult___fst_sfd__h490958 = + _theResult___fst_sfd__h476185 ; + assign _theResult___fst_sfd__h490780 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_sfd__h506786 = + assign _theResult___fst_sfd__h506608 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q208 : + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ; - assign _theResult___fst_sfd__h506789 = - (_theResult___fst_exp__h506030 == 11'd2047) ? - _theResult___snd__h505981[56:5] : - _theResult___fst_sfd__h506786 ; - assign _theResult___fst_sfd__h516437 = + assign _theResult___fst_sfd__h506611 = + (_theResult___fst_exp__h505852 == 11'd2047) ? + _theResult___snd__h505803[56:5] : + _theResult___fst_sfd__h506608 ; + assign _theResult___fst_sfd__h516259 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ; - assign _theResult___fst_sfd__h516440 = - (_theResult___fst_exp__h515607 == 11'd2047) ? - sfdin__h515601[56:5] : - _theResult___fst_sfd__h516437 ; - assign _theResult___fst_sfd__h525221 = + assign _theResult___fst_sfd__h516262 = + (_theResult___fst_exp__h515429 == 11'd2047) ? + sfdin__h515423[56:5] : + _theResult___fst_sfd__h516259 ; + assign _theResult___fst_sfd__h525043 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q212 : + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 ; - assign _theResult___fst_sfd__h525224 = - (_theResult___fst_exp__h524440 == 11'd2047) ? - _theResult___snd__h524386[56:5] : - _theResult___fst_sfd__h525221 ; - assign _theResult___fst_sfd__h525233 = - (f1_exp__h486642 == 8'd0) ? + assign _theResult___fst_sfd__h525046 = + (_theResult___fst_exp__h524262 == 11'd2047) ? + _theResult___snd__h524208[56:5] : + _theResult___fst_sfd__h525043 ; + assign _theResult___fst_sfd__h525055 = + (f1_exp__h486464 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_sfd__h506792 : - _theResult___fst_sfd__h490958) : + _theResult___snd_fst_sfd__h506614 : + _theResult___fst_sfd__h490780) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_sfd__h525227 : - _theResult___fst_sfd__h490958) ; - assign _theResult___fst_sfd__h525239 = - ((f1_exp__h486642 == 8'd255 || f1_exp__h486642 == 8'd0) && - f1_sfd__h486643 == 23'd0) ? + _theResult___snd_fst_sfd__h525049 : + _theResult___fst_sfd__h490780) ; + assign _theResult___fst_sfd__h525061 = + ((f1_exp__h486464 == 8'd255 || f1_exp__h486464 == 8'd0) && + f1_sfd__h486465 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h525233 ; - assign _theResult___fst_sfd__h529811 = + _theResult___fst_sfd__h525055 ; + assign _theResult___fst_sfd__h529633 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_sfd__h545639 = + assign _theResult___fst_sfd__h545461 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q198 : + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 ; - assign _theResult___fst_sfd__h545642 = - (_theResult___fst_exp__h544883 == 11'd2047) ? - _theResult___snd__h544834[56:5] : - _theResult___fst_sfd__h545639 ; - assign _theResult___fst_sfd__h555290 = + assign _theResult___fst_sfd__h545464 = + (_theResult___fst_exp__h544705 == 11'd2047) ? + _theResult___snd__h544656[56:5] : + _theResult___fst_sfd__h545461 ; + assign _theResult___fst_sfd__h555112 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 ; - assign _theResult___fst_sfd__h555293 = - (_theResult___fst_exp__h554460 == 11'd2047) ? - sfdin__h554454[56:5] : - _theResult___fst_sfd__h555290 ; - assign _theResult___fst_sfd__h564074 = + assign _theResult___fst_sfd__h555115 = + (_theResult___fst_exp__h554282 == 11'd2047) ? + sfdin__h554276[56:5] : + _theResult___fst_sfd__h555112 ; + assign _theResult___fst_sfd__h563896 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q202 : + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 ; - assign _theResult___fst_sfd__h564077 = - (_theResult___fst_exp__h563293 == 11'd2047) ? - _theResult___snd__h563239[56:5] : - _theResult___fst_sfd__h564074 ; - assign _theResult___fst_sfd__h564086 = - (f2_exp__h525636 == 8'd0) ? + assign _theResult___fst_sfd__h563899 = + (_theResult___fst_exp__h563115 == 11'd2047) ? + _theResult___snd__h563061[56:5] : + _theResult___fst_sfd__h563896 ; + assign _theResult___fst_sfd__h563908 = + (f2_exp__h525458 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_sfd__h545645 : - _theResult___fst_sfd__h529811) : + _theResult___snd_fst_sfd__h545467 : + _theResult___fst_sfd__h529633) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_sfd__h564080 : - _theResult___fst_sfd__h529811) ; - assign _theResult___fst_sfd__h564092 = - ((f2_exp__h525636 == 8'd255 || f2_exp__h525636 == 8'd0) && - f2_sfd__h525637 == 23'd0) ? + _theResult___snd_fst_sfd__h563902 : + _theResult___fst_sfd__h529633) ; + assign _theResult___fst_sfd__h563914 = + ((f2_exp__h525458 == 8'd255 || f2_exp__h525458 == 8'd0) && + f2_sfd__h525459 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h564086 ; - assign _theResult___fst_sfd__h569115 = + _theResult___fst_sfd__h563908 ; + assign _theResult___fst_sfd__h568937 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ; - assign _theResult___fst_sfd__h584943 = + assign _theResult___fst_sfd__h584765 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q214 : + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 ; - assign _theResult___fst_sfd__h584946 = - (_theResult___fst_exp__h584187 == 11'd2047) ? - _theResult___snd__h584138[56:5] : - _theResult___fst_sfd__h584943 ; - assign _theResult___fst_sfd__h594594 = + assign _theResult___fst_sfd__h584768 = + (_theResult___fst_exp__h584009 == 11'd2047) ? + _theResult___snd__h583960[56:5] : + _theResult___fst_sfd__h584765 ; + assign _theResult___fst_sfd__h594416 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 ; - assign _theResult___fst_sfd__h594597 = - (_theResult___fst_exp__h593764 == 11'd2047) ? - sfdin__h593758[56:5] : - _theResult___fst_sfd__h594594 ; - assign _theResult___fst_sfd__h603378 = + assign _theResult___fst_sfd__h594419 = + (_theResult___fst_exp__h593586 == 11'd2047) ? + sfdin__h593580[56:5] : + _theResult___fst_sfd__h594416 ; + assign _theResult___fst_sfd__h603200 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q218 : + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 ; - assign _theResult___fst_sfd__h603381 = - (_theResult___fst_exp__h602597 == 11'd2047) ? - _theResult___snd__h602543[56:5] : - _theResult___fst_sfd__h603378 ; - assign _theResult___fst_sfd__h603390 = - (f3_exp__h564940 == 8'd0) ? + assign _theResult___fst_sfd__h603203 = + (_theResult___fst_exp__h602419 == 11'd2047) ? + _theResult___snd__h602365[56:5] : + _theResult___fst_sfd__h603200 ; + assign _theResult___fst_sfd__h603212 = + (f3_exp__h564762 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_sfd__h584949 : - _theResult___fst_sfd__h569115) : + _theResult___snd_fst_sfd__h584771 : + _theResult___fst_sfd__h568937) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_sfd__h603384 : - _theResult___fst_sfd__h569115) ; - assign _theResult___fst_sfd__h603396 = - ((f3_exp__h564940 == 8'd255 || f3_exp__h564940 == 8'd0) && - f3_sfd__h564941 == 23'd0) ? + _theResult___snd_fst_sfd__h603206 : + _theResult___fst_sfd__h568937) ; + assign _theResult___fst_sfd__h603218 = + ((f3_exp__h564762 == 8'd255 || f3_exp__h564762 == 8'd0) && + f3_sfd__h564763 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h603390 ; - assign _theResult___sfd__h358479 = - sfd__h358054[24] ? - ((_theResult___fst_exp__h357962 == 8'd254) ? + _theResult___fst_sfd__h603212 ; + assign _theResult___sfd__h358301 = + sfd__h357876[24] ? + ((_theResult___fst_exp__h357784 == 8'd254) ? 23'd0 : - sfd__h358054[23:1]) : - sfd__h358054[22:0] ; - assign _theResult___sfd__h367061 = - sfd__h366636[24] ? - ((_theResult___fst_exp__h366618 == 8'd254) ? + sfd__h357876[23:1]) : + sfd__h357876[22:0] ; + assign _theResult___sfd__h366883 = + sfd__h366458[24] ? + ((_theResult___fst_exp__h366440 == 8'd254) ? 23'd0 : - sfd__h366636[23:1]) : - sfd__h366636[22:0] ; - assign _theResult___sfd__h376245 = - sfd__h375820[24] ? - ((_theResult___fst_exp__h375728 == 8'd254) ? + sfd__h366458[23:1]) : + sfd__h366458[22:0] ; + assign _theResult___sfd__h376067 = + sfd__h375642[24] ? + ((_theResult___fst_exp__h375550 == 8'd254) ? 23'd0 : - sfd__h375820[23:1]) : - sfd__h375820[22:0] ; - assign _theResult___sfd__h384881 = - sfd__h384432[24] ? - ((_theResult___fst_exp__h384413 == 8'd254) ? + sfd__h375642[23:1]) : + sfd__h375642[22:0] ; + assign _theResult___sfd__h384703 = + sfd__h384254[24] ? + ((_theResult___fst_exp__h384235 == 8'd254) ? 23'd0 : - sfd__h384432[23:1]) : - sfd__h384432[22:0] ; - assign _theResult___sfd__h384983 = + sfd__h384254[23:1]) : + sfd__h384254[22:0] ; + assign _theResult___sfd__h384805 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h342196 : - _theResult___fst_sfd__h384977 ; - assign _theResult___sfd__h404176 = - sfd__h403751[24] ? - ((_theResult___fst_exp__h403659 == 8'd254) ? + _theResult___snd_fst_sfd__h342018 : + _theResult___fst_sfd__h384799 ; + assign _theResult___sfd__h403998 = + sfd__h403573[24] ? + ((_theResult___fst_exp__h403481 == 8'd254) ? 23'd0 : - sfd__h403751[23:1]) : - sfd__h403751[22:0] ; - assign _theResult___sfd__h412758 = - sfd__h412333[24] ? - ((_theResult___fst_exp__h412315 == 8'd254) ? + sfd__h403573[23:1]) : + sfd__h403573[22:0] ; + assign _theResult___sfd__h412580 = + sfd__h412155[24] ? + ((_theResult___fst_exp__h412137 == 8'd254) ? 23'd0 : - sfd__h412333[23:1]) : - sfd__h412333[22:0] ; - assign _theResult___sfd__h421942 = - sfd__h421517[24] ? - ((_theResult___fst_exp__h421425 == 8'd254) ? + sfd__h412155[23:1]) : + sfd__h412155[22:0] ; + assign _theResult___sfd__h421764 = + sfd__h421339[24] ? + ((_theResult___fst_exp__h421247 == 8'd254) ? 23'd0 : - sfd__h421517[23:1]) : - sfd__h421517[22:0] ; - assign _theResult___sfd__h430578 = - sfd__h430129[24] ? - ((_theResult___fst_exp__h430110 == 8'd254) ? + sfd__h421339[23:1]) : + sfd__h421339[22:0] ; + assign _theResult___sfd__h430400 = + sfd__h429951[24] ? + ((_theResult___fst_exp__h429932 == 8'd254) ? 23'd0 : - sfd__h430129[23:1]) : - sfd__h430129[22:0] ; - assign _theResult___sfd__h430680 = + sfd__h429951[23:1]) : + sfd__h429951[22:0] ; + assign _theResult___sfd__h430502 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h387898 : - _theResult___fst_sfd__h430674 ; - assign _theResult___sfd__h449871 = - sfd__h449446[24] ? - ((_theResult___fst_exp__h449354 == 8'd254) ? + _theResult___snd_fst_sfd__h387720 : + _theResult___fst_sfd__h430496 ; + assign _theResult___sfd__h449693 = + sfd__h449268[24] ? + ((_theResult___fst_exp__h449176 == 8'd254) ? 23'd0 : - sfd__h449446[23:1]) : - sfd__h449446[22:0] ; - assign _theResult___sfd__h458453 = - sfd__h458028[24] ? - ((_theResult___fst_exp__h458010 == 8'd254) ? + sfd__h449268[23:1]) : + sfd__h449268[22:0] ; + assign _theResult___sfd__h458275 = + sfd__h457850[24] ? + ((_theResult___fst_exp__h457832 == 8'd254) ? 23'd0 : - sfd__h458028[23:1]) : - sfd__h458028[22:0] ; - assign _theResult___sfd__h467637 = - sfd__h467212[24] ? - ((_theResult___fst_exp__h467120 == 8'd254) ? + sfd__h457850[23:1]) : + sfd__h457850[22:0] ; + assign _theResult___sfd__h467459 = + sfd__h467034[24] ? + ((_theResult___fst_exp__h466942 == 8'd254) ? 23'd0 : - sfd__h467212[23:1]) : - sfd__h467212[22:0] ; - assign _theResult___sfd__h476273 = - sfd__h475824[24] ? - ((_theResult___fst_exp__h475805 == 8'd254) ? + sfd__h467034[23:1]) : + sfd__h467034[22:0] ; + assign _theResult___sfd__h476095 = + sfd__h475646[24] ? + ((_theResult___fst_exp__h475627 == 8'd254) ? 23'd0 : - sfd__h475824[23:1]) : - sfd__h475824[22:0] ; - assign _theResult___sfd__h476375 = + sfd__h475646[23:1]) : + sfd__h475646[22:0] ; + assign _theResult___sfd__h476197 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h433593 : - _theResult___fst_sfd__h476369 ; - assign _theResult___sfd__h506686 = - sfd__h506048[53] ? - ((_theResult___fst_exp__h506030 == 11'd2046) ? + _theResult___snd_fst_sfd__h433415 : + _theResult___fst_sfd__h476191 ; + assign _theResult___sfd__h506508 = + sfd__h505870[53] ? + ((_theResult___fst_exp__h505852 == 11'd2046) ? 52'd0 : - sfd__h506048[52:1]) : - sfd__h506048[51:0] ; - assign _theResult___sfd__h516337 = - sfd__h515699[53] ? - ((_theResult___fst_exp__h515607 == 11'd2046) ? + sfd__h505870[52:1]) : + sfd__h505870[51:0] ; + assign _theResult___sfd__h516159 = + sfd__h515521[53] ? + ((_theResult___fst_exp__h515429 == 11'd2046) ? 52'd0 : - sfd__h515699[52:1]) : - sfd__h515699[51:0] ; - assign _theResult___sfd__h525121 = - sfd__h524459[53] ? - ((_theResult___fst_exp__h524440 == 11'd2046) ? + sfd__h515521[52:1]) : + sfd__h515521[51:0] ; + assign _theResult___sfd__h524943 = + sfd__h524281[53] ? + ((_theResult___fst_exp__h524262 == 11'd2046) ? 52'd0 : - sfd__h524459[52:1]) : - sfd__h524459[51:0] ; - assign _theResult___sfd__h545539 = - sfd__h544901[53] ? - ((_theResult___fst_exp__h544883 == 11'd2046) ? + sfd__h524281[52:1]) : + sfd__h524281[51:0] ; + assign _theResult___sfd__h545361 = + sfd__h544723[53] ? + ((_theResult___fst_exp__h544705 == 11'd2046) ? 52'd0 : - sfd__h544901[52:1]) : - sfd__h544901[51:0] ; - assign _theResult___sfd__h555190 = - sfd__h554552[53] ? - ((_theResult___fst_exp__h554460 == 11'd2046) ? + sfd__h544723[52:1]) : + sfd__h544723[51:0] ; + assign _theResult___sfd__h555012 = + sfd__h554374[53] ? + ((_theResult___fst_exp__h554282 == 11'd2046) ? 52'd0 : - sfd__h554552[52:1]) : - sfd__h554552[51:0] ; - assign _theResult___sfd__h563974 = - sfd__h563312[53] ? - ((_theResult___fst_exp__h563293 == 11'd2046) ? + sfd__h554374[52:1]) : + sfd__h554374[51:0] ; + assign _theResult___sfd__h563796 = + sfd__h563134[53] ? + ((_theResult___fst_exp__h563115 == 11'd2046) ? 52'd0 : - sfd__h563312[52:1]) : - sfd__h563312[51:0] ; - assign _theResult___sfd__h584843 = - sfd__h584205[53] ? - ((_theResult___fst_exp__h584187 == 11'd2046) ? + sfd__h563134[52:1]) : + sfd__h563134[51:0] ; + assign _theResult___sfd__h584665 = + sfd__h584027[53] ? + ((_theResult___fst_exp__h584009 == 11'd2046) ? 52'd0 : - sfd__h584205[52:1]) : - sfd__h584205[51:0] ; - assign _theResult___sfd__h594494 = - sfd__h593856[53] ? - ((_theResult___fst_exp__h593764 == 11'd2046) ? + sfd__h584027[52:1]) : + sfd__h584027[51:0] ; + assign _theResult___sfd__h594316 = + sfd__h593678[53] ? + ((_theResult___fst_exp__h593586 == 11'd2046) ? 52'd0 : - sfd__h593856[52:1]) : - sfd__h593856[51:0] ; - assign _theResult___sfd__h603278 = - sfd__h602616[53] ? - ((_theResult___fst_exp__h602597 == 11'd2046) ? + sfd__h593678[52:1]) : + sfd__h593678[51:0] ; + assign _theResult___sfd__h603100 = + sfd__h602438[53] ? + ((_theResult___fst_exp__h602419 == 11'd2046) ? 52'd0 : - sfd__h602616[52:1]) : - sfd__h602616[51:0] ; - assign _theResult___snd__h357973 = { _theResult____h349851[55:0], 1'd0 } ; - assign _theResult___snd__h357984 = - (!_theResult____h349851[56] && _theResult____h349851[55]) ? - _theResult___snd__h357986 : - _theResult___snd__h357996 ; - assign _theResult___snd__h357986 = { _theResult____h349851[54:0], 2'd0 } ; - assign _theResult___snd__h357996 = - (!_theResult____h349851[56] && !_theResult____h349851[55] && - !_theResult____h349851[54] && - !_theResult____h349851[53] && - !_theResult____h349851[52] && - !_theResult____h349851[51] && - !_theResult____h349851[50] && - !_theResult____h349851[49] && - !_theResult____h349851[48] && - !_theResult____h349851[47] && - !_theResult____h349851[46] && - !_theResult____h349851[45] && - !_theResult____h349851[44] && - !_theResult____h349851[43] && - !_theResult____h349851[42] && - !_theResult____h349851[41] && - !_theResult____h349851[40] && - !_theResult____h349851[39] && - !_theResult____h349851[38] && - !_theResult____h349851[37] && - !_theResult____h349851[36] && - !_theResult____h349851[35] && - !_theResult____h349851[34] && - !_theResult____h349851[33] && - !_theResult____h349851[32] && - !_theResult____h349851[31] && - !_theResult____h349851[30] && - !_theResult____h349851[29] && - !_theResult____h349851[28] && - !_theResult____h349851[27] && - !_theResult____h349851[26] && - !_theResult____h349851[25] && - !_theResult____h349851[24] && - !_theResult____h349851[23] && - !_theResult____h349851[22] && - !_theResult____h349851[21] && - !_theResult____h349851[20] && - !_theResult____h349851[19] && - !_theResult____h349851[18] && - !_theResult____h349851[17] && - !_theResult____h349851[16] && - !_theResult____h349851[15] && - !_theResult____h349851[14] && - !_theResult____h349851[13] && - !_theResult____h349851[12] && - !_theResult____h349851[11] && - !_theResult____h349851[10] && - !_theResult____h349851[9] && - !_theResult____h349851[8] && - !_theResult____h349851[7] && - !_theResult____h349851[6] && - !_theResult____h349851[5] && - !_theResult____h349851[4] && - !_theResult____h349851[3] && - !_theResult____h349851[2] && - !_theResult____h349851[1] && - !_theResult____h349851[0]) ? - _theResult____h349851 : - _theResult___snd__h358002 ; - assign _theResult___snd__h358002 = + sfd__h602438[52:1]) : + sfd__h602438[51:0] ; + assign _theResult___snd__h357795 = { _theResult____h349673[55:0], 1'd0 } ; + assign _theResult___snd__h357806 = + (!_theResult____h349673[56] && _theResult____h349673[55]) ? + _theResult___snd__h357808 : + _theResult___snd__h357818 ; + assign _theResult___snd__h357808 = { _theResult____h349673[54:0], 2'd0 } ; + assign _theResult___snd__h357818 = + (!_theResult____h349673[56] && !_theResult____h349673[55] && + !_theResult____h349673[54] && + !_theResult____h349673[53] && + !_theResult____h349673[52] && + !_theResult____h349673[51] && + !_theResult____h349673[50] && + !_theResult____h349673[49] && + !_theResult____h349673[48] && + !_theResult____h349673[47] && + !_theResult____h349673[46] && + !_theResult____h349673[45] && + !_theResult____h349673[44] && + !_theResult____h349673[43] && + !_theResult____h349673[42] && + !_theResult____h349673[41] && + !_theResult____h349673[40] && + !_theResult____h349673[39] && + !_theResult____h349673[38] && + !_theResult____h349673[37] && + !_theResult____h349673[36] && + !_theResult____h349673[35] && + !_theResult____h349673[34] && + !_theResult____h349673[33] && + !_theResult____h349673[32] && + !_theResult____h349673[31] && + !_theResult____h349673[30] && + !_theResult____h349673[29] && + !_theResult____h349673[28] && + !_theResult____h349673[27] && + !_theResult____h349673[26] && + !_theResult____h349673[25] && + !_theResult____h349673[24] && + !_theResult____h349673[23] && + !_theResult____h349673[22] && + !_theResult____h349673[21] && + !_theResult____h349673[20] && + !_theResult____h349673[19] && + !_theResult____h349673[18] && + !_theResult____h349673[17] && + !_theResult____h349673[16] && + !_theResult____h349673[15] && + !_theResult____h349673[14] && + !_theResult____h349673[13] && + !_theResult____h349673[12] && + !_theResult____h349673[11] && + !_theResult____h349673[10] && + !_theResult____h349673[9] && + !_theResult____h349673[8] && + !_theResult____h349673[7] && + !_theResult____h349673[6] && + !_theResult____h349673[5] && + !_theResult____h349673[4] && + !_theResult____h349673[3] && + !_theResult____h349673[2] && + !_theResult____h349673[1] && + !_theResult____h349673[0]) ? + _theResult____h349673 : + _theResult___snd__h357824 ; + assign _theResult___snd__h357824 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; - assign _theResult___snd__h358025 = - _theResult____h349851 << + assign _theResult___snd__h357847 = + _theResult____h349673 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ; - assign _theResult___snd__h366569 = + assign _theResult___snd__h366391 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h366578 : - _theResult___snd__h366571 ; - assign _theResult___snd__h366571 = + _theResult___snd__h366400 : + _theResult___snd__h366393 ; + assign _theResult___snd__h366393 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h366578 = + assign _theResult___snd__h366400 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h342246 : - _theResult___snd__h366584 ; - assign _theResult___snd__h366584 = + sfd__h342068 : + _theResult___snd__h366406 ; + assign _theResult___snd__h366406 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; - assign _theResult___snd__h366607 = - sfd__h342246 << + assign _theResult___snd__h366429 = + sfd__h342068 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ; - assign _theResult___snd__h375739 = { _theResult____h367490[55:0], 1'd0 } ; - assign _theResult___snd__h375750 = - (!_theResult____h367490[56] && _theResult____h367490[55]) ? - _theResult___snd__h375752 : - _theResult___snd__h375762 ; - assign _theResult___snd__h375752 = { _theResult____h367490[54:0], 2'd0 } ; - assign _theResult___snd__h375762 = - (!_theResult____h367490[56] && !_theResult____h367490[55] && - !_theResult____h367490[54] && - !_theResult____h367490[53] && - !_theResult____h367490[52] && - !_theResult____h367490[51] && - !_theResult____h367490[50] && - !_theResult____h367490[49] && - !_theResult____h367490[48] && - !_theResult____h367490[47] && - !_theResult____h367490[46] && - !_theResult____h367490[45] && - !_theResult____h367490[44] && - !_theResult____h367490[43] && - !_theResult____h367490[42] && - !_theResult____h367490[41] && - !_theResult____h367490[40] && - !_theResult____h367490[39] && - !_theResult____h367490[38] && - !_theResult____h367490[37] && - !_theResult____h367490[36] && - !_theResult____h367490[35] && - !_theResult____h367490[34] && - !_theResult____h367490[33] && - !_theResult____h367490[32] && - !_theResult____h367490[31] && - !_theResult____h367490[30] && - !_theResult____h367490[29] && - !_theResult____h367490[28] && - !_theResult____h367490[27] && - !_theResult____h367490[26] && - !_theResult____h367490[25] && - !_theResult____h367490[24] && - !_theResult____h367490[23] && - !_theResult____h367490[22] && - !_theResult____h367490[21] && - !_theResult____h367490[20] && - !_theResult____h367490[19] && - !_theResult____h367490[18] && - !_theResult____h367490[17] && - !_theResult____h367490[16] && - !_theResult____h367490[15] && - !_theResult____h367490[14] && - !_theResult____h367490[13] && - !_theResult____h367490[12] && - !_theResult____h367490[11] && - !_theResult____h367490[10] && - !_theResult____h367490[9] && - !_theResult____h367490[8] && - !_theResult____h367490[7] && - !_theResult____h367490[6] && - !_theResult____h367490[5] && - !_theResult____h367490[4] && - !_theResult____h367490[3] && - !_theResult____h367490[2] && - !_theResult____h367490[1] && - !_theResult____h367490[0]) ? - _theResult____h367490 : - _theResult___snd__h375768 ; - assign _theResult___snd__h375768 = + assign _theResult___snd__h375561 = { _theResult____h367312[55:0], 1'd0 } ; + assign _theResult___snd__h375572 = + (!_theResult____h367312[56] && _theResult____h367312[55]) ? + _theResult___snd__h375574 : + _theResult___snd__h375584 ; + assign _theResult___snd__h375574 = { _theResult____h367312[54:0], 2'd0 } ; + assign _theResult___snd__h375584 = + (!_theResult____h367312[56] && !_theResult____h367312[55] && + !_theResult____h367312[54] && + !_theResult____h367312[53] && + !_theResult____h367312[52] && + !_theResult____h367312[51] && + !_theResult____h367312[50] && + !_theResult____h367312[49] && + !_theResult____h367312[48] && + !_theResult____h367312[47] && + !_theResult____h367312[46] && + !_theResult____h367312[45] && + !_theResult____h367312[44] && + !_theResult____h367312[43] && + !_theResult____h367312[42] && + !_theResult____h367312[41] && + !_theResult____h367312[40] && + !_theResult____h367312[39] && + !_theResult____h367312[38] && + !_theResult____h367312[37] && + !_theResult____h367312[36] && + !_theResult____h367312[35] && + !_theResult____h367312[34] && + !_theResult____h367312[33] && + !_theResult____h367312[32] && + !_theResult____h367312[31] && + !_theResult____h367312[30] && + !_theResult____h367312[29] && + !_theResult____h367312[28] && + !_theResult____h367312[27] && + !_theResult____h367312[26] && + !_theResult____h367312[25] && + !_theResult____h367312[24] && + !_theResult____h367312[23] && + !_theResult____h367312[22] && + !_theResult____h367312[21] && + !_theResult____h367312[20] && + !_theResult____h367312[19] && + !_theResult____h367312[18] && + !_theResult____h367312[17] && + !_theResult____h367312[16] && + !_theResult____h367312[15] && + !_theResult____h367312[14] && + !_theResult____h367312[13] && + !_theResult____h367312[12] && + !_theResult____h367312[11] && + !_theResult____h367312[10] && + !_theResult____h367312[9] && + !_theResult____h367312[8] && + !_theResult____h367312[7] && + !_theResult____h367312[6] && + !_theResult____h367312[5] && + !_theResult____h367312[4] && + !_theResult____h367312[3] && + !_theResult____h367312[2] && + !_theResult____h367312[1] && + !_theResult____h367312[0]) ? + _theResult____h367312 : + _theResult___snd__h375590 ; + assign _theResult___snd__h375590 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h375791 = - _theResult____h367490 << + assign _theResult___snd__h375613 = + _theResult____h367312 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ; - assign _theResult___snd__h384359 = + assign _theResult___snd__h384181 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h384373 : - _theResult___snd__h366571 ; - assign _theResult___snd__h384373 = + _theResult___snd__h384195 : + _theResult___snd__h366393 ; + assign _theResult___snd__h384195 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h342246 : - _theResult___snd__h384379 ; - assign _theResult___snd__h384379 = + sfd__h342068 : + _theResult___snd__h384201 ; + assign _theResult___snd__h384201 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0], 2'd0 } ; - assign _theResult___snd__h384397 = - sfd__h342246 << + assign _theResult___snd__h384219 = + sfd__h342068 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ; - assign _theResult___snd__h403670 = { _theResult____h395550[55:0], 1'd0 } ; - assign _theResult___snd__h403681 = - (!_theResult____h395550[56] && _theResult____h395550[55]) ? - _theResult___snd__h403683 : - _theResult___snd__h403693 ; - assign _theResult___snd__h403683 = { _theResult____h395550[54:0], 2'd0 } ; - assign _theResult___snd__h403693 = - (!_theResult____h395550[56] && !_theResult____h395550[55] && - !_theResult____h395550[54] && - !_theResult____h395550[53] && - !_theResult____h395550[52] && - !_theResult____h395550[51] && - !_theResult____h395550[50] && - !_theResult____h395550[49] && - !_theResult____h395550[48] && - !_theResult____h395550[47] && - !_theResult____h395550[46] && - !_theResult____h395550[45] && - !_theResult____h395550[44] && - !_theResult____h395550[43] && - !_theResult____h395550[42] && - !_theResult____h395550[41] && - !_theResult____h395550[40] && - !_theResult____h395550[39] && - !_theResult____h395550[38] && - !_theResult____h395550[37] && - !_theResult____h395550[36] && - !_theResult____h395550[35] && - !_theResult____h395550[34] && - !_theResult____h395550[33] && - !_theResult____h395550[32] && - !_theResult____h395550[31] && - !_theResult____h395550[30] && - !_theResult____h395550[29] && - !_theResult____h395550[28] && - !_theResult____h395550[27] && - !_theResult____h395550[26] && - !_theResult____h395550[25] && - !_theResult____h395550[24] && - !_theResult____h395550[23] && - !_theResult____h395550[22] && - !_theResult____h395550[21] && - !_theResult____h395550[20] && - !_theResult____h395550[19] && - !_theResult____h395550[18] && - !_theResult____h395550[17] && - !_theResult____h395550[16] && - !_theResult____h395550[15] && - !_theResult____h395550[14] && - !_theResult____h395550[13] && - !_theResult____h395550[12] && - !_theResult____h395550[11] && - !_theResult____h395550[10] && - !_theResult____h395550[9] && - !_theResult____h395550[8] && - !_theResult____h395550[7] && - !_theResult____h395550[6] && - !_theResult____h395550[5] && - !_theResult____h395550[4] && - !_theResult____h395550[3] && - !_theResult____h395550[2] && - !_theResult____h395550[1] && - !_theResult____h395550[0]) ? - _theResult____h395550 : - _theResult___snd__h403699 ; - assign _theResult___snd__h403699 = + assign _theResult___snd__h403492 = { _theResult____h395372[55:0], 1'd0 } ; + assign _theResult___snd__h403503 = + (!_theResult____h395372[56] && _theResult____h395372[55]) ? + _theResult___snd__h403505 : + _theResult___snd__h403515 ; + assign _theResult___snd__h403505 = { _theResult____h395372[54:0], 2'd0 } ; + assign _theResult___snd__h403515 = + (!_theResult____h395372[56] && !_theResult____h395372[55] && + !_theResult____h395372[54] && + !_theResult____h395372[53] && + !_theResult____h395372[52] && + !_theResult____h395372[51] && + !_theResult____h395372[50] && + !_theResult____h395372[49] && + !_theResult____h395372[48] && + !_theResult____h395372[47] && + !_theResult____h395372[46] && + !_theResult____h395372[45] && + !_theResult____h395372[44] && + !_theResult____h395372[43] && + !_theResult____h395372[42] && + !_theResult____h395372[41] && + !_theResult____h395372[40] && + !_theResult____h395372[39] && + !_theResult____h395372[38] && + !_theResult____h395372[37] && + !_theResult____h395372[36] && + !_theResult____h395372[35] && + !_theResult____h395372[34] && + !_theResult____h395372[33] && + !_theResult____h395372[32] && + !_theResult____h395372[31] && + !_theResult____h395372[30] && + !_theResult____h395372[29] && + !_theResult____h395372[28] && + !_theResult____h395372[27] && + !_theResult____h395372[26] && + !_theResult____h395372[25] && + !_theResult____h395372[24] && + !_theResult____h395372[23] && + !_theResult____h395372[22] && + !_theResult____h395372[21] && + !_theResult____h395372[20] && + !_theResult____h395372[19] && + !_theResult____h395372[18] && + !_theResult____h395372[17] && + !_theResult____h395372[16] && + !_theResult____h395372[15] && + !_theResult____h395372[14] && + !_theResult____h395372[13] && + !_theResult____h395372[12] && + !_theResult____h395372[11] && + !_theResult____h395372[10] && + !_theResult____h395372[9] && + !_theResult____h395372[8] && + !_theResult____h395372[7] && + !_theResult____h395372[6] && + !_theResult____h395372[5] && + !_theResult____h395372[4] && + !_theResult____h395372[3] && + !_theResult____h395372[2] && + !_theResult____h395372[1] && + !_theResult____h395372[0]) ? + _theResult____h395372 : + _theResult___snd__h403521 ; + assign _theResult___snd__h403521 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h403722 = - _theResult____h395550 << + assign _theResult___snd__h403544 = + _theResult____h395372 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ; - assign _theResult___snd__h412266 = + assign _theResult___snd__h412088 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h412275 : - _theResult___snd__h412268 ; - assign _theResult___snd__h412268 = + _theResult___snd__h412097 : + _theResult___snd__h412090 ; + assign _theResult___snd__h412090 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h412275 = + assign _theResult___snd__h412097 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h387948 : - _theResult___snd__h412281 ; - assign _theResult___snd__h412281 = + sfd__h387770 : + _theResult___snd__h412103 ; + assign _theResult___snd__h412103 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0], 2'd0 } ; - assign _theResult___snd__h412304 = - sfd__h387948 << + assign _theResult___snd__h412126 = + sfd__h387770 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ; - assign _theResult___snd__h421436 = { _theResult____h413187[55:0], 1'd0 } ; - assign _theResult___snd__h421447 = - (!_theResult____h413187[56] && _theResult____h413187[55]) ? - _theResult___snd__h421449 : - _theResult___snd__h421459 ; - assign _theResult___snd__h421449 = { _theResult____h413187[54:0], 2'd0 } ; - assign _theResult___snd__h421459 = - (!_theResult____h413187[56] && !_theResult____h413187[55] && - !_theResult____h413187[54] && - !_theResult____h413187[53] && - !_theResult____h413187[52] && - !_theResult____h413187[51] && - !_theResult____h413187[50] && - !_theResult____h413187[49] && - !_theResult____h413187[48] && - !_theResult____h413187[47] && - !_theResult____h413187[46] && - !_theResult____h413187[45] && - !_theResult____h413187[44] && - !_theResult____h413187[43] && - !_theResult____h413187[42] && - !_theResult____h413187[41] && - !_theResult____h413187[40] && - !_theResult____h413187[39] && - !_theResult____h413187[38] && - !_theResult____h413187[37] && - !_theResult____h413187[36] && - !_theResult____h413187[35] && - !_theResult____h413187[34] && - !_theResult____h413187[33] && - !_theResult____h413187[32] && - !_theResult____h413187[31] && - !_theResult____h413187[30] && - !_theResult____h413187[29] && - !_theResult____h413187[28] && - !_theResult____h413187[27] && - !_theResult____h413187[26] && - !_theResult____h413187[25] && - !_theResult____h413187[24] && - !_theResult____h413187[23] && - !_theResult____h413187[22] && - !_theResult____h413187[21] && - !_theResult____h413187[20] && - !_theResult____h413187[19] && - !_theResult____h413187[18] && - !_theResult____h413187[17] && - !_theResult____h413187[16] && - !_theResult____h413187[15] && - !_theResult____h413187[14] && - !_theResult____h413187[13] && - !_theResult____h413187[12] && - !_theResult____h413187[11] && - !_theResult____h413187[10] && - !_theResult____h413187[9] && - !_theResult____h413187[8] && - !_theResult____h413187[7] && - !_theResult____h413187[6] && - !_theResult____h413187[5] && - !_theResult____h413187[4] && - !_theResult____h413187[3] && - !_theResult____h413187[2] && - !_theResult____h413187[1] && - !_theResult____h413187[0]) ? - _theResult____h413187 : - _theResult___snd__h421465 ; - assign _theResult___snd__h421465 = + assign _theResult___snd__h421258 = { _theResult____h413009[55:0], 1'd0 } ; + assign _theResult___snd__h421269 = + (!_theResult____h413009[56] && _theResult____h413009[55]) ? + _theResult___snd__h421271 : + _theResult___snd__h421281 ; + assign _theResult___snd__h421271 = { _theResult____h413009[54:0], 2'd0 } ; + assign _theResult___snd__h421281 = + (!_theResult____h413009[56] && !_theResult____h413009[55] && + !_theResult____h413009[54] && + !_theResult____h413009[53] && + !_theResult____h413009[52] && + !_theResult____h413009[51] && + !_theResult____h413009[50] && + !_theResult____h413009[49] && + !_theResult____h413009[48] && + !_theResult____h413009[47] && + !_theResult____h413009[46] && + !_theResult____h413009[45] && + !_theResult____h413009[44] && + !_theResult____h413009[43] && + !_theResult____h413009[42] && + !_theResult____h413009[41] && + !_theResult____h413009[40] && + !_theResult____h413009[39] && + !_theResult____h413009[38] && + !_theResult____h413009[37] && + !_theResult____h413009[36] && + !_theResult____h413009[35] && + !_theResult____h413009[34] && + !_theResult____h413009[33] && + !_theResult____h413009[32] && + !_theResult____h413009[31] && + !_theResult____h413009[30] && + !_theResult____h413009[29] && + !_theResult____h413009[28] && + !_theResult____h413009[27] && + !_theResult____h413009[26] && + !_theResult____h413009[25] && + !_theResult____h413009[24] && + !_theResult____h413009[23] && + !_theResult____h413009[22] && + !_theResult____h413009[21] && + !_theResult____h413009[20] && + !_theResult____h413009[19] && + !_theResult____h413009[18] && + !_theResult____h413009[17] && + !_theResult____h413009[16] && + !_theResult____h413009[15] && + !_theResult____h413009[14] && + !_theResult____h413009[13] && + !_theResult____h413009[12] && + !_theResult____h413009[11] && + !_theResult____h413009[10] && + !_theResult____h413009[9] && + !_theResult____h413009[8] && + !_theResult____h413009[7] && + !_theResult____h413009[6] && + !_theResult____h413009[5] && + !_theResult____h413009[4] && + !_theResult____h413009[3] && + !_theResult____h413009[2] && + !_theResult____h413009[1] && + !_theResult____h413009[0]) ? + _theResult____h413009 : + _theResult___snd__h421287 ; + assign _theResult___snd__h421287 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h421488 = - _theResult____h413187 << + assign _theResult___snd__h421310 = + _theResult____h413009 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ; - assign _theResult___snd__h430056 = + assign _theResult___snd__h429878 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h430070 : - _theResult___snd__h412268 ; - assign _theResult___snd__h430070 = + _theResult___snd__h429892 : + _theResult___snd__h412090 ; + assign _theResult___snd__h429892 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h387948 : - _theResult___snd__h430076 ; - assign _theResult___snd__h430076 = + sfd__h387770 : + _theResult___snd__h429898 ; + assign _theResult___snd__h429898 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0], 2'd0 } ; - assign _theResult___snd__h430094 = - sfd__h387948 << + assign _theResult___snd__h429916 = + sfd__h387770 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ; - assign _theResult___snd__h449365 = { _theResult____h441245[55:0], 1'd0 } ; - assign _theResult___snd__h449376 = - (!_theResult____h441245[56] && _theResult____h441245[55]) ? - _theResult___snd__h449378 : - _theResult___snd__h449388 ; - assign _theResult___snd__h449378 = { _theResult____h441245[54:0], 2'd0 } ; - assign _theResult___snd__h449388 = - (!_theResult____h441245[56] && !_theResult____h441245[55] && - !_theResult____h441245[54] && - !_theResult____h441245[53] && - !_theResult____h441245[52] && - !_theResult____h441245[51] && - !_theResult____h441245[50] && - !_theResult____h441245[49] && - !_theResult____h441245[48] && - !_theResult____h441245[47] && - !_theResult____h441245[46] && - !_theResult____h441245[45] && - !_theResult____h441245[44] && - !_theResult____h441245[43] && - !_theResult____h441245[42] && - !_theResult____h441245[41] && - !_theResult____h441245[40] && - !_theResult____h441245[39] && - !_theResult____h441245[38] && - !_theResult____h441245[37] && - !_theResult____h441245[36] && - !_theResult____h441245[35] && - !_theResult____h441245[34] && - !_theResult____h441245[33] && - !_theResult____h441245[32] && - !_theResult____h441245[31] && - !_theResult____h441245[30] && - !_theResult____h441245[29] && - !_theResult____h441245[28] && - !_theResult____h441245[27] && - !_theResult____h441245[26] && - !_theResult____h441245[25] && - !_theResult____h441245[24] && - !_theResult____h441245[23] && - !_theResult____h441245[22] && - !_theResult____h441245[21] && - !_theResult____h441245[20] && - !_theResult____h441245[19] && - !_theResult____h441245[18] && - !_theResult____h441245[17] && - !_theResult____h441245[16] && - !_theResult____h441245[15] && - !_theResult____h441245[14] && - !_theResult____h441245[13] && - !_theResult____h441245[12] && - !_theResult____h441245[11] && - !_theResult____h441245[10] && - !_theResult____h441245[9] && - !_theResult____h441245[8] && - !_theResult____h441245[7] && - !_theResult____h441245[6] && - !_theResult____h441245[5] && - !_theResult____h441245[4] && - !_theResult____h441245[3] && - !_theResult____h441245[2] && - !_theResult____h441245[1] && - !_theResult____h441245[0]) ? - _theResult____h441245 : - _theResult___snd__h449394 ; - assign _theResult___snd__h449394 = + assign _theResult___snd__h449187 = { _theResult____h441067[55:0], 1'd0 } ; + assign _theResult___snd__h449198 = + (!_theResult____h441067[56] && _theResult____h441067[55]) ? + _theResult___snd__h449200 : + _theResult___snd__h449210 ; + assign _theResult___snd__h449200 = { _theResult____h441067[54:0], 2'd0 } ; + assign _theResult___snd__h449210 = + (!_theResult____h441067[56] && !_theResult____h441067[55] && + !_theResult____h441067[54] && + !_theResult____h441067[53] && + !_theResult____h441067[52] && + !_theResult____h441067[51] && + !_theResult____h441067[50] && + !_theResult____h441067[49] && + !_theResult____h441067[48] && + !_theResult____h441067[47] && + !_theResult____h441067[46] && + !_theResult____h441067[45] && + !_theResult____h441067[44] && + !_theResult____h441067[43] && + !_theResult____h441067[42] && + !_theResult____h441067[41] && + !_theResult____h441067[40] && + !_theResult____h441067[39] && + !_theResult____h441067[38] && + !_theResult____h441067[37] && + !_theResult____h441067[36] && + !_theResult____h441067[35] && + !_theResult____h441067[34] && + !_theResult____h441067[33] && + !_theResult____h441067[32] && + !_theResult____h441067[31] && + !_theResult____h441067[30] && + !_theResult____h441067[29] && + !_theResult____h441067[28] && + !_theResult____h441067[27] && + !_theResult____h441067[26] && + !_theResult____h441067[25] && + !_theResult____h441067[24] && + !_theResult____h441067[23] && + !_theResult____h441067[22] && + !_theResult____h441067[21] && + !_theResult____h441067[20] && + !_theResult____h441067[19] && + !_theResult____h441067[18] && + !_theResult____h441067[17] && + !_theResult____h441067[16] && + !_theResult____h441067[15] && + !_theResult____h441067[14] && + !_theResult____h441067[13] && + !_theResult____h441067[12] && + !_theResult____h441067[11] && + !_theResult____h441067[10] && + !_theResult____h441067[9] && + !_theResult____h441067[8] && + !_theResult____h441067[7] && + !_theResult____h441067[6] && + !_theResult____h441067[5] && + !_theResult____h441067[4] && + !_theResult____h441067[3] && + !_theResult____h441067[2] && + !_theResult____h441067[1] && + !_theResult____h441067[0]) ? + _theResult____h441067 : + _theResult___snd__h449216 ; + assign _theResult___snd__h449216 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h449417 = - _theResult____h441245 << + assign _theResult___snd__h449239 = + _theResult____h441067 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ; - assign _theResult___snd__h457961 = + assign _theResult___snd__h457783 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h457970 : - _theResult___snd__h457963 ; - assign _theResult___snd__h457963 = + _theResult___snd__h457792 : + _theResult___snd__h457785 ; + assign _theResult___snd__h457785 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h457970 = + assign _theResult___snd__h457792 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h433643 : - _theResult___snd__h457976 ; - assign _theResult___snd__h457976 = + sfd__h433465 : + _theResult___snd__h457798 ; + assign _theResult___snd__h457798 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0], 2'd0 } ; - assign _theResult___snd__h457999 = - sfd__h433643 << + assign _theResult___snd__h457821 = + sfd__h433465 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ; - assign _theResult___snd__h467131 = { _theResult____h458882[55:0], 1'd0 } ; - assign _theResult___snd__h467142 = - (!_theResult____h458882[56] && _theResult____h458882[55]) ? - _theResult___snd__h467144 : - _theResult___snd__h467154 ; - assign _theResult___snd__h467144 = { _theResult____h458882[54:0], 2'd0 } ; - assign _theResult___snd__h467154 = - (!_theResult____h458882[56] && !_theResult____h458882[55] && - !_theResult____h458882[54] && - !_theResult____h458882[53] && - !_theResult____h458882[52] && - !_theResult____h458882[51] && - !_theResult____h458882[50] && - !_theResult____h458882[49] && - !_theResult____h458882[48] && - !_theResult____h458882[47] && - !_theResult____h458882[46] && - !_theResult____h458882[45] && - !_theResult____h458882[44] && - !_theResult____h458882[43] && - !_theResult____h458882[42] && - !_theResult____h458882[41] && - !_theResult____h458882[40] && - !_theResult____h458882[39] && - !_theResult____h458882[38] && - !_theResult____h458882[37] && - !_theResult____h458882[36] && - !_theResult____h458882[35] && - !_theResult____h458882[34] && - !_theResult____h458882[33] && - !_theResult____h458882[32] && - !_theResult____h458882[31] && - !_theResult____h458882[30] && - !_theResult____h458882[29] && - !_theResult____h458882[28] && - !_theResult____h458882[27] && - !_theResult____h458882[26] && - !_theResult____h458882[25] && - !_theResult____h458882[24] && - !_theResult____h458882[23] && - !_theResult____h458882[22] && - !_theResult____h458882[21] && - !_theResult____h458882[20] && - !_theResult____h458882[19] && - !_theResult____h458882[18] && - !_theResult____h458882[17] && - !_theResult____h458882[16] && - !_theResult____h458882[15] && - !_theResult____h458882[14] && - !_theResult____h458882[13] && - !_theResult____h458882[12] && - !_theResult____h458882[11] && - !_theResult____h458882[10] && - !_theResult____h458882[9] && - !_theResult____h458882[8] && - !_theResult____h458882[7] && - !_theResult____h458882[6] && - !_theResult____h458882[5] && - !_theResult____h458882[4] && - !_theResult____h458882[3] && - !_theResult____h458882[2] && - !_theResult____h458882[1] && - !_theResult____h458882[0]) ? - _theResult____h458882 : - _theResult___snd__h467160 ; - assign _theResult___snd__h467160 = + assign _theResult___snd__h466953 = { _theResult____h458704[55:0], 1'd0 } ; + assign _theResult___snd__h466964 = + (!_theResult____h458704[56] && _theResult____h458704[55]) ? + _theResult___snd__h466966 : + _theResult___snd__h466976 ; + assign _theResult___snd__h466966 = { _theResult____h458704[54:0], 2'd0 } ; + assign _theResult___snd__h466976 = + (!_theResult____h458704[56] && !_theResult____h458704[55] && + !_theResult____h458704[54] && + !_theResult____h458704[53] && + !_theResult____h458704[52] && + !_theResult____h458704[51] && + !_theResult____h458704[50] && + !_theResult____h458704[49] && + !_theResult____h458704[48] && + !_theResult____h458704[47] && + !_theResult____h458704[46] && + !_theResult____h458704[45] && + !_theResult____h458704[44] && + !_theResult____h458704[43] && + !_theResult____h458704[42] && + !_theResult____h458704[41] && + !_theResult____h458704[40] && + !_theResult____h458704[39] && + !_theResult____h458704[38] && + !_theResult____h458704[37] && + !_theResult____h458704[36] && + !_theResult____h458704[35] && + !_theResult____h458704[34] && + !_theResult____h458704[33] && + !_theResult____h458704[32] && + !_theResult____h458704[31] && + !_theResult____h458704[30] && + !_theResult____h458704[29] && + !_theResult____h458704[28] && + !_theResult____h458704[27] && + !_theResult____h458704[26] && + !_theResult____h458704[25] && + !_theResult____h458704[24] && + !_theResult____h458704[23] && + !_theResult____h458704[22] && + !_theResult____h458704[21] && + !_theResult____h458704[20] && + !_theResult____h458704[19] && + !_theResult____h458704[18] && + !_theResult____h458704[17] && + !_theResult____h458704[16] && + !_theResult____h458704[15] && + !_theResult____h458704[14] && + !_theResult____h458704[13] && + !_theResult____h458704[12] && + !_theResult____h458704[11] && + !_theResult____h458704[10] && + !_theResult____h458704[9] && + !_theResult____h458704[8] && + !_theResult____h458704[7] && + !_theResult____h458704[6] && + !_theResult____h458704[5] && + !_theResult____h458704[4] && + !_theResult____h458704[3] && + !_theResult____h458704[2] && + !_theResult____h458704[1] && + !_theResult____h458704[0]) ? + _theResult____h458704 : + _theResult___snd__h466982 ; + assign _theResult___snd__h466982 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h467183 = - _theResult____h458882 << + assign _theResult___snd__h467005 = + _theResult____h458704 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ; - assign _theResult___snd__h475751 = + assign _theResult___snd__h475573 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h475765 : - _theResult___snd__h457963 ; - assign _theResult___snd__h475765 = + _theResult___snd__h475587 : + _theResult___snd__h457785 ; + assign _theResult___snd__h475587 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h433643 : - _theResult___snd__h475771 ; - assign _theResult___snd__h475771 = + sfd__h433465 : + _theResult___snd__h475593 ; + assign _theResult___snd__h475593 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0], 2'd0 } ; - assign _theResult___snd__h475789 = - sfd__h433643 << + assign _theResult___snd__h475611 = + sfd__h433465 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ; - assign _theResult___snd__h505981 = - (f1_exp__h486642 == 8'd0) ? - _theResult___snd__h505990 : - _theResult___snd__h505983 ; - assign _theResult___snd__h505983 = { f1_sfd__h486643, 34'd0 } ; - assign _theResult___snd__h505990 = - (f1_exp__h486642 == 8'd0 && !f1_sfd__h486643[22] && + assign _theResult___snd__h505803 = + (f1_exp__h486464 == 8'd0) ? + _theResult___snd__h505812 : + _theResult___snd__h505805 ; + assign _theResult___snd__h505805 = { f1_sfd__h486465, 34'd0 } ; + assign _theResult___snd__h505812 = + (f1_exp__h486464 == 8'd0 && !f1_sfd__h486465[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487004 : - _theResult___snd__h505996 ; - assign _theResult___snd__h505996 = + sfd__h486826 : + _theResult___snd__h505818 ; + assign _theResult___snd__h505818 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h506019 = - sfd__h487004 << + assign _theResult___snd__h505841 = + sfd__h486826 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 ; - assign _theResult___snd__h515618 = { _theResult____h507371[55:0], 1'd0 } ; - assign _theResult___snd__h515629 = - (!_theResult____h507371[56] && _theResult____h507371[55]) ? - _theResult___snd__h515631 : - _theResult___snd__h515641 ; - assign _theResult___snd__h515631 = { _theResult____h507371[54:0], 2'd0 } ; - assign _theResult___snd__h515641 = - (!_theResult____h507371[56] && !_theResult____h507371[55] && - !_theResult____h507371[54] && - !_theResult____h507371[53] && - !_theResult____h507371[52] && - !_theResult____h507371[51] && - !_theResult____h507371[50] && - !_theResult____h507371[49] && - !_theResult____h507371[48] && - !_theResult____h507371[47] && - !_theResult____h507371[46] && - !_theResult____h507371[45] && - !_theResult____h507371[44] && - !_theResult____h507371[43] && - !_theResult____h507371[42] && - !_theResult____h507371[41] && - !_theResult____h507371[40] && - !_theResult____h507371[39] && - !_theResult____h507371[38] && - !_theResult____h507371[37] && - !_theResult____h507371[36] && - !_theResult____h507371[35] && - !_theResult____h507371[34] && - !_theResult____h507371[33] && - !_theResult____h507371[32] && - !_theResult____h507371[31] && - !_theResult____h507371[30] && - !_theResult____h507371[29] && - !_theResult____h507371[28] && - !_theResult____h507371[27] && - !_theResult____h507371[26] && - !_theResult____h507371[25] && - !_theResult____h507371[24] && - !_theResult____h507371[23] && - !_theResult____h507371[22] && - !_theResult____h507371[21] && - !_theResult____h507371[20] && - !_theResult____h507371[19] && - !_theResult____h507371[18] && - !_theResult____h507371[17] && - !_theResult____h507371[16] && - !_theResult____h507371[15] && - !_theResult____h507371[14] && - !_theResult____h507371[13] && - !_theResult____h507371[12] && - !_theResult____h507371[11] && - !_theResult____h507371[10] && - !_theResult____h507371[9] && - !_theResult____h507371[8] && - !_theResult____h507371[7] && - !_theResult____h507371[6] && - !_theResult____h507371[5] && - !_theResult____h507371[4] && - !_theResult____h507371[3] && - !_theResult____h507371[2] && - !_theResult____h507371[1] && - !_theResult____h507371[0]) ? - _theResult____h507371 : - _theResult___snd__h515647 ; - assign _theResult___snd__h515647 = + assign _theResult___snd__h515440 = { _theResult____h507193[55:0], 1'd0 } ; + assign _theResult___snd__h515451 = + (!_theResult____h507193[56] && _theResult____h507193[55]) ? + _theResult___snd__h515453 : + _theResult___snd__h515463 ; + assign _theResult___snd__h515453 = { _theResult____h507193[54:0], 2'd0 } ; + assign _theResult___snd__h515463 = + (!_theResult____h507193[56] && !_theResult____h507193[55] && + !_theResult____h507193[54] && + !_theResult____h507193[53] && + !_theResult____h507193[52] && + !_theResult____h507193[51] && + !_theResult____h507193[50] && + !_theResult____h507193[49] && + !_theResult____h507193[48] && + !_theResult____h507193[47] && + !_theResult____h507193[46] && + !_theResult____h507193[45] && + !_theResult____h507193[44] && + !_theResult____h507193[43] && + !_theResult____h507193[42] && + !_theResult____h507193[41] && + !_theResult____h507193[40] && + !_theResult____h507193[39] && + !_theResult____h507193[38] && + !_theResult____h507193[37] && + !_theResult____h507193[36] && + !_theResult____h507193[35] && + !_theResult____h507193[34] && + !_theResult____h507193[33] && + !_theResult____h507193[32] && + !_theResult____h507193[31] && + !_theResult____h507193[30] && + !_theResult____h507193[29] && + !_theResult____h507193[28] && + !_theResult____h507193[27] && + !_theResult____h507193[26] && + !_theResult____h507193[25] && + !_theResult____h507193[24] && + !_theResult____h507193[23] && + !_theResult____h507193[22] && + !_theResult____h507193[21] && + !_theResult____h507193[20] && + !_theResult____h507193[19] && + !_theResult____h507193[18] && + !_theResult____h507193[17] && + !_theResult____h507193[16] && + !_theResult____h507193[15] && + !_theResult____h507193[14] && + !_theResult____h507193[13] && + !_theResult____h507193[12] && + !_theResult____h507193[11] && + !_theResult____h507193[10] && + !_theResult____h507193[9] && + !_theResult____h507193[8] && + !_theResult____h507193[7] && + !_theResult____h507193[6] && + !_theResult____h507193[5] && + !_theResult____h507193[4] && + !_theResult____h507193[3] && + !_theResult____h507193[2] && + !_theResult____h507193[1] && + !_theResult____h507193[0]) ? + _theResult____h507193 : + _theResult___snd__h515469 ; + assign _theResult___snd__h515469 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h515670 = - _theResult____h507371 << + assign _theResult___snd__h515492 = + _theResult____h507193 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 ; - assign _theResult___snd__h524386 = - (f1_exp__h486642 == 8'd0) ? - _theResult___snd__h524400 : - _theResult___snd__h505983 ; - assign _theResult___snd__h524400 = - (f1_exp__h486642 == 8'd0 && !f1_sfd__h486643[22] && + assign _theResult___snd__h524208 = + (f1_exp__h486464 == 8'd0) ? + _theResult___snd__h524222 : + _theResult___snd__h505805 ; + assign _theResult___snd__h524222 = + (f1_exp__h486464 == 8'd0 && !f1_sfd__h486465[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487004 : - _theResult___snd__h524406 ; - assign _theResult___snd__h524406 = + sfd__h486826 : + _theResult___snd__h524228 ; + assign _theResult___snd__h524228 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h524424 = - sfd__h487004 << + assign _theResult___snd__h524246 = + sfd__h486826 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ; - assign _theResult___snd__h544834 = - (f2_exp__h525636 == 8'd0) ? - _theResult___snd__h544843 : - _theResult___snd__h544836 ; - assign _theResult___snd__h544836 = { f2_sfd__h525637, 34'd0 } ; - assign _theResult___snd__h544843 = - (f2_exp__h525636 == 8'd0 && !f2_sfd__h525637[22] && + assign _theResult___snd__h544656 = + (f2_exp__h525458 == 8'd0) ? + _theResult___snd__h544665 : + _theResult___snd__h544658 ; + assign _theResult___snd__h544658 = { f2_sfd__h525459, 34'd0 } ; + assign _theResult___snd__h544665 = + (f2_exp__h525458 == 8'd0 && !f2_sfd__h525459[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h525998 : - _theResult___snd__h544849 ; - assign _theResult___snd__h544849 = + sfd__h525820 : + _theResult___snd__h544671 ; + assign _theResult___snd__h544671 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h544872 = - sfd__h525998 << + assign _theResult___snd__h544694 = + sfd__h525820 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 ; - assign _theResult___snd__h554471 = { _theResult____h546224[55:0], 1'd0 } ; - assign _theResult___snd__h554482 = - (!_theResult____h546224[56] && _theResult____h546224[55]) ? - _theResult___snd__h554484 : - _theResult___snd__h554494 ; - assign _theResult___snd__h554484 = { _theResult____h546224[54:0], 2'd0 } ; - assign _theResult___snd__h554494 = - (!_theResult____h546224[56] && !_theResult____h546224[55] && - !_theResult____h546224[54] && - !_theResult____h546224[53] && - !_theResult____h546224[52] && - !_theResult____h546224[51] && - !_theResult____h546224[50] && - !_theResult____h546224[49] && - !_theResult____h546224[48] && - !_theResult____h546224[47] && - !_theResult____h546224[46] && - !_theResult____h546224[45] && - !_theResult____h546224[44] && - !_theResult____h546224[43] && - !_theResult____h546224[42] && - !_theResult____h546224[41] && - !_theResult____h546224[40] && - !_theResult____h546224[39] && - !_theResult____h546224[38] && - !_theResult____h546224[37] && - !_theResult____h546224[36] && - !_theResult____h546224[35] && - !_theResult____h546224[34] && - !_theResult____h546224[33] && - !_theResult____h546224[32] && - !_theResult____h546224[31] && - !_theResult____h546224[30] && - !_theResult____h546224[29] && - !_theResult____h546224[28] && - !_theResult____h546224[27] && - !_theResult____h546224[26] && - !_theResult____h546224[25] && - !_theResult____h546224[24] && - !_theResult____h546224[23] && - !_theResult____h546224[22] && - !_theResult____h546224[21] && - !_theResult____h546224[20] && - !_theResult____h546224[19] && - !_theResult____h546224[18] && - !_theResult____h546224[17] && - !_theResult____h546224[16] && - !_theResult____h546224[15] && - !_theResult____h546224[14] && - !_theResult____h546224[13] && - !_theResult____h546224[12] && - !_theResult____h546224[11] && - !_theResult____h546224[10] && - !_theResult____h546224[9] && - !_theResult____h546224[8] && - !_theResult____h546224[7] && - !_theResult____h546224[6] && - !_theResult____h546224[5] && - !_theResult____h546224[4] && - !_theResult____h546224[3] && - !_theResult____h546224[2] && - !_theResult____h546224[1] && - !_theResult____h546224[0]) ? - _theResult____h546224 : - _theResult___snd__h554500 ; - assign _theResult___snd__h554500 = + assign _theResult___snd__h554293 = { _theResult____h546046[55:0], 1'd0 } ; + assign _theResult___snd__h554304 = + (!_theResult____h546046[56] && _theResult____h546046[55]) ? + _theResult___snd__h554306 : + _theResult___snd__h554316 ; + assign _theResult___snd__h554306 = { _theResult____h546046[54:0], 2'd0 } ; + assign _theResult___snd__h554316 = + (!_theResult____h546046[56] && !_theResult____h546046[55] && + !_theResult____h546046[54] && + !_theResult____h546046[53] && + !_theResult____h546046[52] && + !_theResult____h546046[51] && + !_theResult____h546046[50] && + !_theResult____h546046[49] && + !_theResult____h546046[48] && + !_theResult____h546046[47] && + !_theResult____h546046[46] && + !_theResult____h546046[45] && + !_theResult____h546046[44] && + !_theResult____h546046[43] && + !_theResult____h546046[42] && + !_theResult____h546046[41] && + !_theResult____h546046[40] && + !_theResult____h546046[39] && + !_theResult____h546046[38] && + !_theResult____h546046[37] && + !_theResult____h546046[36] && + !_theResult____h546046[35] && + !_theResult____h546046[34] && + !_theResult____h546046[33] && + !_theResult____h546046[32] && + !_theResult____h546046[31] && + !_theResult____h546046[30] && + !_theResult____h546046[29] && + !_theResult____h546046[28] && + !_theResult____h546046[27] && + !_theResult____h546046[26] && + !_theResult____h546046[25] && + !_theResult____h546046[24] && + !_theResult____h546046[23] && + !_theResult____h546046[22] && + !_theResult____h546046[21] && + !_theResult____h546046[20] && + !_theResult____h546046[19] && + !_theResult____h546046[18] && + !_theResult____h546046[17] && + !_theResult____h546046[16] && + !_theResult____h546046[15] && + !_theResult____h546046[14] && + !_theResult____h546046[13] && + !_theResult____h546046[12] && + !_theResult____h546046[11] && + !_theResult____h546046[10] && + !_theResult____h546046[9] && + !_theResult____h546046[8] && + !_theResult____h546046[7] && + !_theResult____h546046[6] && + !_theResult____h546046[5] && + !_theResult____h546046[4] && + !_theResult____h546046[3] && + !_theResult____h546046[2] && + !_theResult____h546046[1] && + !_theResult____h546046[0]) ? + _theResult____h546046 : + _theResult___snd__h554322 ; + assign _theResult___snd__h554322 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h554523 = - _theResult____h546224 << + assign _theResult___snd__h554345 = + _theResult____h546046 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 ; - assign _theResult___snd__h563239 = - (f2_exp__h525636 == 8'd0) ? - _theResult___snd__h563253 : - _theResult___snd__h544836 ; - assign _theResult___snd__h563253 = - (f2_exp__h525636 == 8'd0 && !f2_sfd__h525637[22] && + assign _theResult___snd__h563061 = + (f2_exp__h525458 == 8'd0) ? + _theResult___snd__h563075 : + _theResult___snd__h544658 ; + assign _theResult___snd__h563075 = + (f2_exp__h525458 == 8'd0 && !f2_sfd__h525459[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h525998 : - _theResult___snd__h563259 ; - assign _theResult___snd__h563259 = + sfd__h525820 : + _theResult___snd__h563081 ; + assign _theResult___snd__h563081 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h563277 = - sfd__h525998 << + assign _theResult___snd__h563099 = + sfd__h525820 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ; - assign _theResult___snd__h584138 = - (f3_exp__h564940 == 8'd0) ? - _theResult___snd__h584147 : - _theResult___snd__h584140 ; - assign _theResult___snd__h584140 = { f3_sfd__h564941, 34'd0 } ; - assign _theResult___snd__h584147 = - (f3_exp__h564940 == 8'd0 && !f3_sfd__h564941[22] && + assign _theResult___snd__h583960 = + (f3_exp__h564762 == 8'd0) ? + _theResult___snd__h583969 : + _theResult___snd__h583962 ; + assign _theResult___snd__h583962 = { f3_sfd__h564763, 34'd0 } ; + assign _theResult___snd__h583969 = + (f3_exp__h564762 == 8'd0 && !f3_sfd__h564763[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h565302 : - _theResult___snd__h584153 ; - assign _theResult___snd__h584153 = + sfd__h565124 : + _theResult___snd__h583975 ; + assign _theResult___snd__h583975 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h584176 = - sfd__h565302 << + assign _theResult___snd__h583998 = + sfd__h565124 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 ; - assign _theResult___snd__h593775 = { _theResult____h585528[55:0], 1'd0 } ; - assign _theResult___snd__h593786 = - (!_theResult____h585528[56] && _theResult____h585528[55]) ? - _theResult___snd__h593788 : - _theResult___snd__h593798 ; - assign _theResult___snd__h593788 = { _theResult____h585528[54:0], 2'd0 } ; - assign _theResult___snd__h593798 = - (!_theResult____h585528[56] && !_theResult____h585528[55] && - !_theResult____h585528[54] && - !_theResult____h585528[53] && - !_theResult____h585528[52] && - !_theResult____h585528[51] && - !_theResult____h585528[50] && - !_theResult____h585528[49] && - !_theResult____h585528[48] && - !_theResult____h585528[47] && - !_theResult____h585528[46] && - !_theResult____h585528[45] && - !_theResult____h585528[44] && - !_theResult____h585528[43] && - !_theResult____h585528[42] && - !_theResult____h585528[41] && - !_theResult____h585528[40] && - !_theResult____h585528[39] && - !_theResult____h585528[38] && - !_theResult____h585528[37] && - !_theResult____h585528[36] && - !_theResult____h585528[35] && - !_theResult____h585528[34] && - !_theResult____h585528[33] && - !_theResult____h585528[32] && - !_theResult____h585528[31] && - !_theResult____h585528[30] && - !_theResult____h585528[29] && - !_theResult____h585528[28] && - !_theResult____h585528[27] && - !_theResult____h585528[26] && - !_theResult____h585528[25] && - !_theResult____h585528[24] && - !_theResult____h585528[23] && - !_theResult____h585528[22] && - !_theResult____h585528[21] && - !_theResult____h585528[20] && - !_theResult____h585528[19] && - !_theResult____h585528[18] && - !_theResult____h585528[17] && - !_theResult____h585528[16] && - !_theResult____h585528[15] && - !_theResult____h585528[14] && - !_theResult____h585528[13] && - !_theResult____h585528[12] && - !_theResult____h585528[11] && - !_theResult____h585528[10] && - !_theResult____h585528[9] && - !_theResult____h585528[8] && - !_theResult____h585528[7] && - !_theResult____h585528[6] && - !_theResult____h585528[5] && - !_theResult____h585528[4] && - !_theResult____h585528[3] && - !_theResult____h585528[2] && - !_theResult____h585528[1] && - !_theResult____h585528[0]) ? - _theResult____h585528 : - _theResult___snd__h593804 ; - assign _theResult___snd__h593804 = + assign _theResult___snd__h593597 = { _theResult____h585350[55:0], 1'd0 } ; + assign _theResult___snd__h593608 = + (!_theResult____h585350[56] && _theResult____h585350[55]) ? + _theResult___snd__h593610 : + _theResult___snd__h593620 ; + assign _theResult___snd__h593610 = { _theResult____h585350[54:0], 2'd0 } ; + assign _theResult___snd__h593620 = + (!_theResult____h585350[56] && !_theResult____h585350[55] && + !_theResult____h585350[54] && + !_theResult____h585350[53] && + !_theResult____h585350[52] && + !_theResult____h585350[51] && + !_theResult____h585350[50] && + !_theResult____h585350[49] && + !_theResult____h585350[48] && + !_theResult____h585350[47] && + !_theResult____h585350[46] && + !_theResult____h585350[45] && + !_theResult____h585350[44] && + !_theResult____h585350[43] && + !_theResult____h585350[42] && + !_theResult____h585350[41] && + !_theResult____h585350[40] && + !_theResult____h585350[39] && + !_theResult____h585350[38] && + !_theResult____h585350[37] && + !_theResult____h585350[36] && + !_theResult____h585350[35] && + !_theResult____h585350[34] && + !_theResult____h585350[33] && + !_theResult____h585350[32] && + !_theResult____h585350[31] && + !_theResult____h585350[30] && + !_theResult____h585350[29] && + !_theResult____h585350[28] && + !_theResult____h585350[27] && + !_theResult____h585350[26] && + !_theResult____h585350[25] && + !_theResult____h585350[24] && + !_theResult____h585350[23] && + !_theResult____h585350[22] && + !_theResult____h585350[21] && + !_theResult____h585350[20] && + !_theResult____h585350[19] && + !_theResult____h585350[18] && + !_theResult____h585350[17] && + !_theResult____h585350[16] && + !_theResult____h585350[15] && + !_theResult____h585350[14] && + !_theResult____h585350[13] && + !_theResult____h585350[12] && + !_theResult____h585350[11] && + !_theResult____h585350[10] && + !_theResult____h585350[9] && + !_theResult____h585350[8] && + !_theResult____h585350[7] && + !_theResult____h585350[6] && + !_theResult____h585350[5] && + !_theResult____h585350[4] && + !_theResult____h585350[3] && + !_theResult____h585350[2] && + !_theResult____h585350[1] && + !_theResult____h585350[0]) ? + _theResult____h585350 : + _theResult___snd__h593626 ; + assign _theResult___snd__h593626 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h593827 = - _theResult____h585528 << + assign _theResult___snd__h593649 = + _theResult____h585350 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 ; - assign _theResult___snd__h602543 = - (f3_exp__h564940 == 8'd0) ? - _theResult___snd__h602557 : - _theResult___snd__h584140 ; - assign _theResult___snd__h602557 = - (f3_exp__h564940 == 8'd0 && !f3_sfd__h564941[22] && + assign _theResult___snd__h602365 = + (f3_exp__h564762 == 8'd0) ? + _theResult___snd__h602379 : + _theResult___snd__h583962 ; + assign _theResult___snd__h602379 = + (f3_exp__h564762 == 8'd0 && !f3_sfd__h564763[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h565302 : - _theResult___snd__h602563 ; - assign _theResult___snd__h602563 = + sfd__h565124 : + _theResult___snd__h602385 ; + assign _theResult___snd__h602385 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h602581 = - sfd__h565302 << + assign _theResult___snd__h602403 = + sfd__h565124 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ; - assign _theResult___snd__h608037 = - b__h607489[63] ? b___1__h608102 : b__h607489 ; - assign _theResult___snd_fst_exp__h367144 = + assign _theResult___snd__h607859 = + b__h607311[63] ? b___1__h607924 : b__h607311 ; + assign _theResult___snd_fst_exp__h366966 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_exp__h358559 : - _theResult___fst_exp__h367141 ; - assign _theResult___snd_fst_exp__h384964 = + _theResult___fst_exp__h358381 : + _theResult___fst_exp__h366963 ; + assign _theResult___snd_fst_exp__h384786 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_exp__h376325 : - _theResult___fst_exp__h384961 ; - assign _theResult___snd_fst_exp__h412841 = + _theResult___fst_exp__h376147 : + _theResult___fst_exp__h384783 ; + assign _theResult___snd_fst_exp__h412663 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_exp__h404256 : - _theResult___fst_exp__h412838 ; - assign _theResult___snd_fst_exp__h430661 = + _theResult___fst_exp__h404078 : + _theResult___fst_exp__h412660 ; + assign _theResult___snd_fst_exp__h430483 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_exp__h422022 : - _theResult___fst_exp__h430658 ; - assign _theResult___snd_fst_exp__h458536 = + _theResult___fst_exp__h421844 : + _theResult___fst_exp__h430480 ; + assign _theResult___snd_fst_exp__h458358 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_exp__h449951 : - _theResult___fst_exp__h458533 ; - assign _theResult___snd_fst_exp__h476356 = + _theResult___fst_exp__h449773 : + _theResult___fst_exp__h458355 ; + assign _theResult___snd_fst_exp__h476178 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_exp__h467717 : - _theResult___fst_exp__h476353 ; - assign _theResult___snd_fst_exp__h506791 = + _theResult___fst_exp__h467539 : + _theResult___fst_exp__h476175 ; + assign _theResult___snd_fst_exp__h506613 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 11'd0 : - _theResult___fst_exp__h506788 ; - assign _theResult___snd_fst_exp__h525226 = + _theResult___fst_exp__h506610 ; + assign _theResult___snd_fst_exp__h525048 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_exp__h516439 : - _theResult___fst_exp__h525223 ; - assign _theResult___snd_fst_exp__h545644 = + _theResult___fst_exp__h516261 : + _theResult___fst_exp__h525045 ; + assign _theResult___snd_fst_exp__h545466 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 11'd0 : - _theResult___fst_exp__h545641 ; - assign _theResult___snd_fst_exp__h564079 = + _theResult___fst_exp__h545463 ; + assign _theResult___snd_fst_exp__h563901 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_exp__h555292 : - _theResult___fst_exp__h564076 ; - assign _theResult___snd_fst_exp__h584948 = + _theResult___fst_exp__h555114 : + _theResult___fst_exp__h563898 ; + assign _theResult___snd_fst_exp__h584770 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 11'd0 : - _theResult___fst_exp__h584945 ; - assign _theResult___snd_fst_exp__h603383 = + _theResult___fst_exp__h584767 ; + assign _theResult___snd_fst_exp__h603205 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_exp__h594596 : - _theResult___fst_exp__h603380 ; - assign _theResult___snd_fst_sfd__h342196 = + _theResult___fst_exp__h594418 : + _theResult___fst_exp__h603202 ; + assign _theResult___snd_fst_sfd__h342018 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h367145 = + assign _theResult___snd_fst_sfd__h366967 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_sfd__h358560 : - _theResult___fst_sfd__h367142 ; - assign _theResult___snd_fst_sfd__h384965 = + _theResult___fst_sfd__h358382 : + _theResult___fst_sfd__h366964 ; + assign _theResult___snd_fst_sfd__h384787 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_sfd__h376326 : - _theResult___fst_sfd__h384962 ; - assign _theResult___snd_fst_sfd__h387898 = + _theResult___fst_sfd__h376148 : + _theResult___fst_sfd__h384784 ; + assign _theResult___snd_fst_sfd__h387720 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h412842 = + assign _theResult___snd_fst_sfd__h412664 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_sfd__h404257 : - _theResult___fst_sfd__h412839 ; - assign _theResult___snd_fst_sfd__h430662 = + _theResult___fst_sfd__h404079 : + _theResult___fst_sfd__h412661 ; + assign _theResult___snd_fst_sfd__h430484 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_sfd__h422023 : - _theResult___fst_sfd__h430659 ; - assign _theResult___snd_fst_sfd__h433593 = + _theResult___fst_sfd__h421845 : + _theResult___fst_sfd__h430481 ; + assign _theResult___snd_fst_sfd__h433415 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h458537 = + assign _theResult___snd_fst_sfd__h458359 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_sfd__h449952 : - _theResult___fst_sfd__h458534 ; - assign _theResult___snd_fst_sfd__h476357 = + _theResult___fst_sfd__h449774 : + _theResult___fst_sfd__h458356 ; + assign _theResult___snd_fst_sfd__h476179 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_sfd__h467718 : - _theResult___fst_sfd__h476354 ; - assign _theResult___snd_fst_sfd__h486958 = - (f1_sfd__h486643 == 23'd0) ? + _theResult___fst_sfd__h467540 : + _theResult___fst_sfd__h476176 ; + assign _theResult___snd_fst_sfd__h486780 = + (f1_sfd__h486465 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h486706 ; - assign _theResult___snd_fst_sfd__h506792 = + out___1_sfd__h486528 ; + assign _theResult___snd_fst_sfd__h506614 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 52'd0 : - _theResult___fst_sfd__h506789 ; - assign _theResult___snd_fst_sfd__h525227 = + _theResult___fst_sfd__h506611 ; + assign _theResult___snd_fst_sfd__h525049 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_sfd__h516440 : - _theResult___fst_sfd__h525224 ; - assign _theResult___snd_fst_sfd__h525952 = - (f2_sfd__h525637 == 23'd0) ? + _theResult___fst_sfd__h516262 : + _theResult___fst_sfd__h525046 ; + assign _theResult___snd_fst_sfd__h525774 = + (f2_sfd__h525459 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h525700 ; - assign _theResult___snd_fst_sfd__h545645 = + out___1_sfd__h525522 ; + assign _theResult___snd_fst_sfd__h545467 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 52'd0 : - _theResult___fst_sfd__h545642 ; - assign _theResult___snd_fst_sfd__h564080 = + _theResult___fst_sfd__h545464 ; + assign _theResult___snd_fst_sfd__h563902 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_sfd__h555293 : - _theResult___fst_sfd__h564077 ; - assign _theResult___snd_fst_sfd__h565256 = - (f3_sfd__h564941 == 23'd0) ? + _theResult___fst_sfd__h555115 : + _theResult___fst_sfd__h563899 ; + assign _theResult___snd_fst_sfd__h565078 = + (f3_sfd__h564763 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h565004 ; - assign _theResult___snd_fst_sfd__h584949 = + out___1_sfd__h564826 ; + assign _theResult___snd_fst_sfd__h584771 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 52'd0 : - _theResult___fst_sfd__h584946 ; - assign _theResult___snd_fst_sfd__h603384 = + _theResult___fst_sfd__h584768 ; + assign _theResult___snd_fst_sfd__h603206 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_sfd__h594597 : - _theResult___fst_sfd__h603381 ; - assign a___1__h607650 = + _theResult___fst_sfd__h594419 : + _theResult___fst_sfd__h603203 ; + assign a___1__h607472 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ; - assign a___1__h608041 = 64'd0 - a__h607488 ; - assign a__h607488 = + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q4[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q4 } ; + assign a___1__h607863 = 64'd0 - a__h607310 ; + assign a__h607310 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h607650 : + a___1__h607472 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h607651 = + assign b___1__h607473 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } : + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h608102 = 64'd0 - b__h607489 ; - assign b__h607489 = + assign b___1__h607924 = 64'd0 - b__h607311 ; + assign b__h607311 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h607651 : + b___1__h607473 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h607636 = { {64{a__h607488[63]}}, a__h607488 } ; - assign b__h607712 = { {64{b__h607489[63]}}, b__h607489 } ; - assign b__h607813 = { 64'd0, a__h607488 } ; - assign b__h607825 = { 64'd0, b__h607489 } ; - assign base__h707397 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h707600 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h704811 = - commitStage_commitTrap[4] ? i__h704986 : i__h704826 ; + assign b__h607458 = { {64{a__h607310[63]}}, a__h607310 } ; + assign b__h607534 = { {64{b__h607311[63]}}, b__h607311 } ; + assign b__h607635 = { 64'd0, a__h607310 } ; + assign b__h607647 = { 64'd0, b__h607311 } ; + assign base__h707219 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h707422 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h704633 = + commitStage_commitTrap[4] ? i__h704808 : i__h704648 ; assign coreFix_aluExe_0_bypassWire_0_wget__2326_BITS__ETC___d12328 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27900,9 +27652,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 | - ((f3_exp__h564940 != 8'd255 || f3_sfd__h564941 == 23'd0) && - (f3_exp__h564940 != 8'd255 || f3_sfd__h564941 != 23'd0) && - (f3_exp__h564940 != 8'd0 || f3_sfd__h564941 != 23'd0) && + ((f3_exp__h564762 != 8'd255 || f3_sfd__h564763 == 23'd0) && + (f3_exp__h564762 != 8'd255 || f3_sfd__h564763 != 23'd0) && + (f3_exp__h564762 != 8'd0 || f3_sfd__h564763 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27910,9 +27662,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 | - ((f3_exp__h564940 != 8'd255 || f3_sfd__h564941 == 23'd0) && - (f3_exp__h564940 != 8'd255 || f3_sfd__h564941 != 23'd0) && - (f3_exp__h564940 != 8'd0 || f3_sfd__h564941 != 23'd0) && + ((f3_exp__h564762 != 8'd255 || f3_sfd__h564763 == 23'd0) && + (f3_exp__h564762 != 8'd255 || f3_sfd__h564763 != 23'd0) && + (f3_exp__h564762 != 8'd0 || f3_sfd__h564763 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27920,9 +27672,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 | - ((f3_exp__h564940 != 8'd255 || f3_sfd__h564941 == 23'd0) && - (f3_exp__h564940 != 8'd255 || f3_sfd__h564941 != 23'd0) && - (f3_exp__h564940 != 8'd0 || f3_sfd__h564941 != 23'd0) && + ((f3_exp__h564762 != 8'd255 || f3_sfd__h564763 == 23'd0) && + (f3_exp__h564762 != 8'd255 || f3_sfd__h564763 != 23'd0) && + (f3_exp__h564762 != 8'd0 || f3_sfd__h564763 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27930,9 +27682,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 | - ((f3_exp__h564940 != 8'd255 || f3_sfd__h564941 == 23'd0) && - (f3_exp__h564940 != 8'd255 || f3_sfd__h564941 != 23'd0) && - (f3_exp__h564940 != 8'd0 || f3_sfd__h564941 != 23'd0) && + ((f3_exp__h564762 != 8'd255 || f3_sfd__h564763 == 23'd0) && + (f3_exp__h564762 != 8'd255 || f3_sfd__h564763 != 23'd0) && + (f3_exp__h564762 != 8'd0 || f3_sfd__h564763 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27940,13 +27692,13 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 | - ((f3_exp__h564940 != 8'd255 || f3_sfd__h564941 == 23'd0) && - (f3_exp__h564940 != 8'd255 || f3_sfd__h564941 != 23'd0) && - (f3_exp__h564940 != 8'd0 || f3_sfd__h564941 != 23'd0) && + ((f3_exp__h564762 != 8'd255 || f3_sfd__h564763 == 23'd0) && + (f3_exp__h564762 != 8'd255 || f3_sfd__h564763 != 23'd0) && + (f3_exp__h564762 != 8'd0 || f3_sfd__h564763 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126) ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 = + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 = + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q4 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14015 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && @@ -27988,7 +27740,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h257551 ; + y__h257373 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 || @@ -28341,9 +28093,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14679 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4363_BITS_186_TO_1_ETC___d14674 ; @@ -28403,95 +28155,103 @@ module mkCore(CLK, assign csrf_prv_reg_read__2891_ULT_IF_fetchStage_pipe_ETC___d13121 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2863_BIT_173__ETC___d13116[9:8] ; - assign data78377_BITS_31_TO_0__q2 = data__h478377[31:0] ; - assign data79309_BITS_31_TO_0__q7 = data__h479309[31:0] ; - assign data___1__h478889 = - { {32{data78377_BITS_31_TO_0__q2[31]}}, - data78377_BITS_31_TO_0__q2 } ; - assign data___1__h479821 = - { {32{data79309_BITS_31_TO_0__q7[31]}}, - data79309_BITS_31_TO_0__q7 } ; - assign data__h478377 = + assign data78199_BITS_31_TO_0__q2 = data__h478199[31:0] ; + assign data79131_BITS_31_TO_0__q6 = data__h479131[31:0] ; + assign data___1__h478711 = + { {32{data78199_BITS_31_TO_0__q2[31]}}, + data78199_BITS_31_TO_0__q2 } ; + assign data___1__h479643 = + { {32{data79131_BITS_31_TO_0__q6[31]}}, + data79131_BITS_31_TO_0__q6 } ; + assign data__h478199 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h479309 = + assign data__h479131 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h479073 : - x_remainder__h479074 ; - assign din_inc___2_exp__h384995 = _theResult___fst_exp__h357962 + 8'd1 ; - assign din_inc___2_exp__h385019 = _theResult___fst_exp__h366618 + 8'd1 ; - assign din_inc___2_exp__h385049 = _theResult___fst_exp__h375728 + 8'd1 ; - assign din_inc___2_exp__h385073 = _theResult___fst_exp__h384413 + 8'd1 ; - assign din_inc___2_exp__h430692 = _theResult___fst_exp__h403659 + 8'd1 ; - assign din_inc___2_exp__h430716 = _theResult___fst_exp__h412315 + 8'd1 ; - assign din_inc___2_exp__h430746 = _theResult___fst_exp__h421425 + 8'd1 ; - assign din_inc___2_exp__h430770 = _theResult___fst_exp__h430110 + 8'd1 ; - assign din_inc___2_exp__h476387 = _theResult___fst_exp__h449354 + 8'd1 ; - assign din_inc___2_exp__h476411 = _theResult___fst_exp__h458010 + 8'd1 ; - assign din_inc___2_exp__h476441 = _theResult___fst_exp__h467120 + 8'd1 ; - assign din_inc___2_exp__h476465 = _theResult___fst_exp__h475805 + 8'd1 ; - assign din_inc___2_exp__h525280 = _theResult___fst_exp__h506030 + 11'd1 ; - assign din_inc___2_exp__h525315 = _theResult___fst_exp__h515607 + 11'd1 ; - assign din_inc___2_exp__h525341 = _theResult___fst_exp__h524440 + 11'd1 ; - assign din_inc___2_exp__h564133 = _theResult___fst_exp__h544883 + 11'd1 ; - assign din_inc___2_exp__h564168 = _theResult___fst_exp__h554460 + 11'd1 ; - assign din_inc___2_exp__h564194 = _theResult___fst_exp__h563293 + 11'd1 ; - assign din_inc___2_exp__h603437 = _theResult___fst_exp__h584187 + 11'd1 ; - assign din_inc___2_exp__h603472 = _theResult___fst_exp__h593764 + 11'd1 ; - assign din_inc___2_exp__h603498 = _theResult___fst_exp__h602597 + 11'd1 ; - assign enabled_ints___1__h656412 = pend_ints__h655997 & y__h656424 ; - assign enabled_ints__h656459 = - pend_ints__h655997 & - { r1__read_BITS_9_TO_0___h656435, csrf_mideleg_1_0_reg } ; - assign f1_exp86642_MINUS_127__q128 = f1_exp__h486642 - 8'd127 ; - assign f1_exp__h486642 = + x_quotient__h478895 : + x_remainder__h478896 ; + assign din_inc___2_exp__h384817 = _theResult___fst_exp__h357784 + 8'd1 ; + assign din_inc___2_exp__h384841 = _theResult___fst_exp__h366440 + 8'd1 ; + assign din_inc___2_exp__h384871 = _theResult___fst_exp__h375550 + 8'd1 ; + assign din_inc___2_exp__h384895 = _theResult___fst_exp__h384235 + 8'd1 ; + assign din_inc___2_exp__h430514 = _theResult___fst_exp__h403481 + 8'd1 ; + assign din_inc___2_exp__h430538 = _theResult___fst_exp__h412137 + 8'd1 ; + assign din_inc___2_exp__h430568 = _theResult___fst_exp__h421247 + 8'd1 ; + assign din_inc___2_exp__h430592 = _theResult___fst_exp__h429932 + 8'd1 ; + assign din_inc___2_exp__h476209 = _theResult___fst_exp__h449176 + 8'd1 ; + assign din_inc___2_exp__h476233 = _theResult___fst_exp__h457832 + 8'd1 ; + assign din_inc___2_exp__h476263 = _theResult___fst_exp__h466942 + 8'd1 ; + assign din_inc___2_exp__h476287 = _theResult___fst_exp__h475627 + 8'd1 ; + assign din_inc___2_exp__h525102 = _theResult___fst_exp__h505852 + 11'd1 ; + assign din_inc___2_exp__h525137 = _theResult___fst_exp__h515429 + 11'd1 ; + assign din_inc___2_exp__h525163 = _theResult___fst_exp__h524262 + 11'd1 ; + assign din_inc___2_exp__h563955 = _theResult___fst_exp__h544705 + 11'd1 ; + assign din_inc___2_exp__h563990 = _theResult___fst_exp__h554282 + 11'd1 ; + assign din_inc___2_exp__h564016 = _theResult___fst_exp__h563115 + 11'd1 ; + assign din_inc___2_exp__h603259 = _theResult___fst_exp__h584009 + 11'd1 ; + assign din_inc___2_exp__h603294 = _theResult___fst_exp__h593586 + 11'd1 ; + assign din_inc___2_exp__h603320 = _theResult___fst_exp__h602419 + 11'd1 ; + assign enabled_ints___1__h656234 = pend_ints__h655819 & y__h656246 ; + assign enabled_ints__h656281 = + pend_ints__h655819 & + { r1__read_BITS_9_TO_0___h656257, csrf_mideleg_1_0_reg } ; + assign f1_exp86464_MINUS_127__q128 = f1_exp__h486464 - 8'd127 ; + assign f1_exp__h486464 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h486643 = + assign f1_sfd__h486465 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp25636_MINUS_127__q168 = f2_exp__h525636 - 8'd127 ; - assign f2_exp__h525636 = + assign f2_exp25458_MINUS_127__q168 = f2_exp__h525458 - 8'd127 ; + assign f2_exp__h525458 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h525637 = + assign f2_sfd__h525459 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp64940_MINUS_127__q145 = f3_exp__h564940 - 8'd127 ; - assign f3_exp__h564940 = + assign f3_exp64762_MINUS_127__q145 = f3_exp__h564762 - 8'd127 ; + assign f3_exp__h564762 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h564941 = + assign f3_sfd__h564763 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign fallthrough_pc__h668013 = + assign fallthrough_pc__h667835 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h683505 = + assign fallthrough_pc__h683327 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h615293 = { 56'd0, x__h617953 } ; + assign fcsr_csr__read__h615115 = { 56'd0, x__h617775 } ; assign fetchStage_RDY_pipelines_0_first__2860_AND_NOT_ETC___d13459 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13456 ; + assign fetchStage_RDY_pipelines_0_first__2860_AND_epo_ETC___d13333 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__2860_AND_fet_ETC___d13525 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -28499,12 +28259,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2860_AND__ETC___d13463 ; - assign fetchStage_RDY_pipelines_1_deq__2875_AND_NOT_f_ETC___d14064 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d14060) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__2861_AND_NOT_fe_ETC___d14006 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28582,8 +28336,8 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13119 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h659778 != 5'd0 || - imm__h659779 != 32'd0) && + rs1__h659600 != 5'd0 || + imm__h659601 != 32'd0) && IF_fetchStage_pipelines_0_first__2863_BIT_173__ETC___d13116[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13750 = @@ -28707,82 +28461,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13957 ; - assign fflags__h719327 = + assign fflags__h719149 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_fst__h719274 : + y_avValue_fst__h719096 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 ; - assign fflags_csr__read__h615268 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h615279 = { 61'd0, csrf_frm_reg } ; - assign guard__h349861 = - { IF_sfdin57956_BIT_33_THEN_2_ELSE_0__q22[1], - { sfdin__h357956[32:0], 23'd0 } != 56'd0 } ; - assign guard__h358570 = - { IF_theResult___snd66569_BIT_33_THEN_2_ELSE_0__q24[1], - { _theResult___snd__h366569[32:0], 23'd0 } != 56'd0 } ; - assign guard__h367500 = - { IF_sfdin75722_BIT_33_THEN_2_ELSE_0__q32[1], - { sfdin__h375722[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368098 = x__h368200 != 57'd0 ; - assign guard__h376336 = - { IF_theResult___snd84359_BIT_33_THEN_2_ELSE_0__q37[1], - { _theResult___snd__h384359[32:0], 23'd0 } != 56'd0 } ; - assign guard__h395560 = - { IF_sfdin03653_BIT_33_THEN_2_ELSE_0__q57[1], - { sfdin__h403653[32:0], 23'd0 } != 56'd0 } ; - assign guard__h404267 = - { IF_theResult___snd12266_BIT_33_THEN_2_ELSE_0__q59[1], - { _theResult___snd__h412266[32:0], 23'd0 } != 56'd0 } ; - assign guard__h413197 = - { IF_sfdin21419_BIT_33_THEN_2_ELSE_0__q67[1], - { sfdin__h421419[32:0], 23'd0 } != 56'd0 } ; - assign guard__h413795 = x__h413897 != 57'd0 ; - assign guard__h422033 = - { IF_theResult___snd30056_BIT_33_THEN_2_ELSE_0__q72[1], - { _theResult___snd__h430056[32:0], 23'd0 } != 56'd0 } ; - assign guard__h441255 = - { IF_sfdin49348_BIT_33_THEN_2_ELSE_0__q92[1], - { sfdin__h449348[32:0], 23'd0 } != 56'd0 } ; - assign guard__h449962 = - { IF_theResult___snd57961_BIT_33_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h457961[32:0], 23'd0 } != 56'd0 } ; - assign guard__h458892 = - { IF_sfdin67114_BIT_33_THEN_2_ELSE_0__q102[1], - { sfdin__h467114[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459490 = x__h459592 != 57'd0 ; - assign guard__h467728 = - { IF_theResult___snd75751_BIT_33_THEN_2_ELSE_0__q107[1], - { _theResult___snd__h475751[32:0], 23'd0 } != 56'd0 } ; - assign guard__h498069 = - { IF_theResult___snd05981_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h505981[3:0], 52'd0 } != 56'd0 } ; - assign guard__h507381 = - { IF_sfdin15601_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h515601[3:0], 52'd0 } != 56'd0 } ; - assign guard__h507979 = x__h508079 != 57'd0 ; - assign guard__h516450 = - { IF_theResult___snd24386_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h524386[3:0], 52'd0 } != 56'd0 } ; - assign guard__h536922 = - { IF_theResult___snd44834_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h544834[3:0], 52'd0 } != 56'd0 } ; - assign guard__h546234 = - { IF_sfdin54454_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h554454[3:0], 52'd0 } != 56'd0 } ; - assign guard__h546832 = x__h546932 != 57'd0 ; - assign guard__h555303 = - { IF_theResult___snd63239_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h563239[3:0], 52'd0 } != 56'd0 } ; - assign guard__h576226 = - { IF_theResult___snd84138_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h584138[3:0], 52'd0 } != 56'd0 } ; - assign guard__h585538 = - { IF_sfdin93758_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h593758[3:0], 52'd0 } != 56'd0 } ; - assign guard__h586136 = x__h586236 != 57'd0 ; - assign guard__h594607 = - { IF_theResult___snd02543_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h602543[3:0], 52'd0 } != 56'd0 } ; - assign idx__h686994 = + assign fflags_csr__read__h615090 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h615101 = { 61'd0, csrf_frm_reg } ; + assign guard__h349683 = + { IF_sfdin57778_BIT_33_THEN_2_ELSE_0__q22[1], + { sfdin__h357778[32:0], 23'd0 } != 56'd0 } ; + assign guard__h358392 = + { IF_theResult___snd66391_BIT_33_THEN_2_ELSE_0__q24[1], + { _theResult___snd__h366391[32:0], 23'd0 } != 56'd0 } ; + assign guard__h367322 = + { IF_sfdin75544_BIT_33_THEN_2_ELSE_0__q32[1], + { sfdin__h375544[32:0], 23'd0 } != 56'd0 } ; + assign guard__h367920 = x__h368022 != 57'd0 ; + assign guard__h376158 = + { IF_theResult___snd84181_BIT_33_THEN_2_ELSE_0__q37[1], + { _theResult___snd__h384181[32:0], 23'd0 } != 56'd0 } ; + assign guard__h395382 = + { IF_sfdin03475_BIT_33_THEN_2_ELSE_0__q57[1], + { sfdin__h403475[32:0], 23'd0 } != 56'd0 } ; + assign guard__h404089 = + { IF_theResult___snd12088_BIT_33_THEN_2_ELSE_0__q59[1], + { _theResult___snd__h412088[32:0], 23'd0 } != 56'd0 } ; + assign guard__h413019 = + { IF_sfdin21241_BIT_33_THEN_2_ELSE_0__q67[1], + { sfdin__h421241[32:0], 23'd0 } != 56'd0 } ; + assign guard__h413617 = x__h413719 != 57'd0 ; + assign guard__h421855 = + { IF_theResult___snd29878_BIT_33_THEN_2_ELSE_0__q72[1], + { _theResult___snd__h429878[32:0], 23'd0 } != 56'd0 } ; + assign guard__h441077 = + { IF_sfdin49170_BIT_33_THEN_2_ELSE_0__q92[1], + { sfdin__h449170[32:0], 23'd0 } != 56'd0 } ; + assign guard__h449784 = + { IF_theResult___snd57783_BIT_33_THEN_2_ELSE_0__q94[1], + { _theResult___snd__h457783[32:0], 23'd0 } != 56'd0 } ; + assign guard__h458714 = + { IF_sfdin66936_BIT_33_THEN_2_ELSE_0__q102[1], + { sfdin__h466936[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459312 = x__h459414 != 57'd0 ; + assign guard__h467550 = + { IF_theResult___snd75573_BIT_33_THEN_2_ELSE_0__q107[1], + { _theResult___snd__h475573[32:0], 23'd0 } != 56'd0 } ; + assign guard__h497891 = + { IF_theResult___snd05803_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h505803[3:0], 52'd0 } != 56'd0 } ; + assign guard__h507203 = + { IF_sfdin15423_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h515423[3:0], 52'd0 } != 56'd0 } ; + assign guard__h507801 = x__h507901 != 57'd0 ; + assign guard__h516272 = + { IF_theResult___snd24208_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h524208[3:0], 52'd0 } != 56'd0 } ; + assign guard__h536744 = + { IF_theResult___snd44656_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h544656[3:0], 52'd0 } != 56'd0 } ; + assign guard__h546056 = + { IF_sfdin54276_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h554276[3:0], 52'd0 } != 56'd0 } ; + assign guard__h546654 = x__h546754 != 57'd0 ; + assign guard__h555125 = + { IF_theResult___snd63061_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h563061[3:0], 52'd0 } != 56'd0 } ; + assign guard__h576048 = + { IF_theResult___snd83960_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h583960[3:0], 52'd0 } != 56'd0 } ; + assign guard__h585360 = + { IF_sfdin93580_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h593580[3:0], 52'd0 } != 56'd0 } ; + assign guard__h585958 = x__h586058 != 57'd0 ; + assign guard__h594429 = + { IF_theResult___snd02365_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h602365[3:0], 52'd0 } != 56'd0 } ; + assign idx__h686816 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13751 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28790,26 +28544,26 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13771) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3470__ETC___d13472 ; - assign imm__h659779 = + assign imm__h659601 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h671653 = + assign k__h671475 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3470__ETC___d13472 ; - assign mcause_csr__read__h616933 = - { r1__read__h619474, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h616678 = - { r1__read__h619461, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h616285 = - { r1__read__h619304, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h616380 = - { r1__read__h619321, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h616504 = - { r1__read__h619345, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h617166 = - { r1__read__h619480, csrf_software_int_pend_vec_0 } ; + assign mcause_csr__read__h616755 = + { r1__read__h619296, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h616500 = + { r1__read__h619283, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h616107 = + { r1__read__h619126, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h616202 = + { r1__read__h619143, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h616326 = + { r1__read__h619167, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h616988 = + { r1__read__h619302, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28885,423 +28639,415 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h75651 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h616137 = { r1__read__h619179, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h616586 = - { r1__read__h619456, csrf_mtvec_mode_low_reg } ; - assign n___1__h200866 = + assign msip__h75472 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h615959 = { r1__read__h619001, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h616408 = + { r1__read__h619278, csrf_mtvec_mode_low_reg } ; + assign n___1__h200688 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h199463[63:56], + x__h199285[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h199463[55:48], + x__h199285[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h199463[47:40], + x__h199285[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h199463[39:32], + x__h199285[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h199463[31:24], + x__h199285[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h199463[23:16], + x__h199285[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h199463[15:8], + x__h199285[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h199463[7:0] } ; - assign n__read__h617270 = + x__h199285[7:0] } ; + assign n__read__h617092 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h617461 = + assign n__read__h617283 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6352 = + assign n__read__h6174 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6466 : + rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h716179 = + assign n__read__h716001 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h300567 = + assign next_deqP___1__h300389 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h308563 = + assign next_deqP___1__h308385 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h314844 = + assign next_deqP___1__h314666 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h322698 = + assign next_deqP___1__h322520 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h332755 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h335980 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h715420 = + assign next_deqP___1__h332577 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h335802 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h715242 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 ; - assign out___1_sfd__h486706 = { f1_sfd__h486643, 29'd0 } ; - assign out___1_sfd__h525700 = { f2_sfd__h525637, 29'd0 } ; - assign out___1_sfd__h565004 = { f3_sfd__h564941, 29'd0 } ; - assign out_exp__h358481 = - sfdin__h357956[34] ? - _theResult___exp__h358478 : - _theResult___fst_exp__h357962 ; - assign out_exp__h367063 = - _theResult___snd__h366569[34] ? - _theResult___exp__h367060 : - _theResult___fst_exp__h366618 ; - assign out_exp__h376247 = - sfdin__h375722[34] ? - _theResult___exp__h376244 : - _theResult___fst_exp__h375728 ; - assign out_exp__h384883 = - _theResult___snd__h384359[34] ? - _theResult___exp__h384880 : - _theResult___fst_exp__h384413 ; - assign out_exp__h404178 = - sfdin__h403653[34] ? - _theResult___exp__h404175 : - _theResult___fst_exp__h403659 ; - assign out_exp__h412760 = - _theResult___snd__h412266[34] ? - _theResult___exp__h412757 : - _theResult___fst_exp__h412315 ; - assign out_exp__h421944 = - sfdin__h421419[34] ? - _theResult___exp__h421941 : - _theResult___fst_exp__h421425 ; - assign out_exp__h430580 = - _theResult___snd__h430056[34] ? - _theResult___exp__h430577 : - _theResult___fst_exp__h430110 ; - assign out_exp__h449873 = - sfdin__h449348[34] ? - _theResult___exp__h449870 : - _theResult___fst_exp__h449354 ; - assign out_exp__h458455 = - _theResult___snd__h457961[34] ? - _theResult___exp__h458452 : - _theResult___fst_exp__h458010 ; - assign out_exp__h467639 = - sfdin__h467114[34] ? - _theResult___exp__h467636 : - _theResult___fst_exp__h467120 ; - assign out_exp__h476275 = - _theResult___snd__h475751[34] ? - _theResult___exp__h476272 : - _theResult___fst_exp__h475805 ; - assign out_exp__h506688 = - _theResult___snd__h505981[5] ? - _theResult___exp__h506685 : - _theResult___fst_exp__h506030 ; - assign out_exp__h516339 = - sfdin__h515601[5] ? - _theResult___exp__h516336 : - _theResult___fst_exp__h515607 ; - assign out_exp__h525123 = - _theResult___snd__h524386[5] ? - _theResult___exp__h525120 : - _theResult___fst_exp__h524440 ; - assign out_exp__h545541 = - _theResult___snd__h544834[5] ? - _theResult___exp__h545538 : - _theResult___fst_exp__h544883 ; - assign out_exp__h555192 = - sfdin__h554454[5] ? - _theResult___exp__h555189 : - _theResult___fst_exp__h554460 ; - assign out_exp__h563976 = - _theResult___snd__h563239[5] ? - _theResult___exp__h563973 : - _theResult___fst_exp__h563293 ; - assign out_exp__h584845 = - _theResult___snd__h584138[5] ? - _theResult___exp__h584842 : - _theResult___fst_exp__h584187 ; - assign out_exp__h594496 = - sfdin__h593758[5] ? - _theResult___exp__h594493 : - _theResult___fst_exp__h593764 ; - assign out_exp__h603280 = - _theResult___snd__h602543[5] ? - _theResult___exp__h603277 : - _theResult___fst_exp__h602597 ; - assign out_f_exp__h385259 = - (_theResult___exp__h384982 == 8'd255 && - _theResult___sfd__h384983 != 23'd0 || + assign out___1_sfd__h486528 = { f1_sfd__h486465, 29'd0 } ; + assign out___1_sfd__h525522 = { f2_sfd__h525459, 29'd0 } ; + assign out___1_sfd__h564826 = { f3_sfd__h564763, 29'd0 } ; + assign out_exp__h358303 = + sfdin__h357778[34] ? + _theResult___exp__h358300 : + _theResult___fst_exp__h357784 ; + assign out_exp__h366885 = + _theResult___snd__h366391[34] ? + _theResult___exp__h366882 : + _theResult___fst_exp__h366440 ; + assign out_exp__h376069 = + sfdin__h375544[34] ? + _theResult___exp__h376066 : + _theResult___fst_exp__h375550 ; + assign out_exp__h384705 = + _theResult___snd__h384181[34] ? + _theResult___exp__h384702 : + _theResult___fst_exp__h384235 ; + assign out_exp__h404000 = + sfdin__h403475[34] ? + _theResult___exp__h403997 : + _theResult___fst_exp__h403481 ; + assign out_exp__h412582 = + _theResult___snd__h412088[34] ? + _theResult___exp__h412579 : + _theResult___fst_exp__h412137 ; + assign out_exp__h421766 = + sfdin__h421241[34] ? + _theResult___exp__h421763 : + _theResult___fst_exp__h421247 ; + assign out_exp__h430402 = + _theResult___snd__h429878[34] ? + _theResult___exp__h430399 : + _theResult___fst_exp__h429932 ; + assign out_exp__h449695 = + sfdin__h449170[34] ? + _theResult___exp__h449692 : + _theResult___fst_exp__h449176 ; + assign out_exp__h458277 = + _theResult___snd__h457783[34] ? + _theResult___exp__h458274 : + _theResult___fst_exp__h457832 ; + assign out_exp__h467461 = + sfdin__h466936[34] ? + _theResult___exp__h467458 : + _theResult___fst_exp__h466942 ; + assign out_exp__h476097 = + _theResult___snd__h475573[34] ? + _theResult___exp__h476094 : + _theResult___fst_exp__h475627 ; + assign out_exp__h506510 = + _theResult___snd__h505803[5] ? + _theResult___exp__h506507 : + _theResult___fst_exp__h505852 ; + assign out_exp__h516161 = + sfdin__h515423[5] ? + _theResult___exp__h516158 : + _theResult___fst_exp__h515429 ; + assign out_exp__h524945 = + _theResult___snd__h524208[5] ? + _theResult___exp__h524942 : + _theResult___fst_exp__h524262 ; + assign out_exp__h545363 = + _theResult___snd__h544656[5] ? + _theResult___exp__h545360 : + _theResult___fst_exp__h544705 ; + assign out_exp__h555014 = + sfdin__h554276[5] ? + _theResult___exp__h555011 : + _theResult___fst_exp__h554282 ; + assign out_exp__h563798 = + _theResult___snd__h563061[5] ? + _theResult___exp__h563795 : + _theResult___fst_exp__h563115 ; + assign out_exp__h584667 = + _theResult___snd__h583960[5] ? + _theResult___exp__h584664 : + _theResult___fst_exp__h584009 ; + assign out_exp__h594318 = + sfdin__h593580[5] ? + _theResult___exp__h594315 : + _theResult___fst_exp__h593586 ; + assign out_exp__h603102 = + _theResult___snd__h602365[5] ? + _theResult___exp__h603099 : + _theResult___fst_exp__h602419 ; + assign out_f_exp__h385081 = + (_theResult___exp__h384804 == 8'd255 && + _theResult___sfd__h384805 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h384973 ; - assign out_f_exp__h430956 = - (_theResult___exp__h430679 == 8'd255 && - _theResult___sfd__h430680 != 23'd0 || + _theResult___fst_exp__h384795 ; + assign out_f_exp__h430778 = + (_theResult___exp__h430501 == 8'd255 && + _theResult___sfd__h430502 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h430670 ; - assign out_f_exp__h476651 = - (_theResult___exp__h476374 == 8'd255 && - _theResult___sfd__h476375 != 23'd0 || + _theResult___fst_exp__h430492 ; + assign out_f_exp__h476473 = + (_theResult___exp__h476196 == 8'd255 && + _theResult___sfd__h476197 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h476365 ; - assign out_f_sfd__h385260 = - (_theResult___exp__h384982 == 8'd255 && - _theResult___sfd__h384983 != 23'd0) ? + _theResult___fst_exp__h476187 ; + assign out_f_sfd__h385082 = + (_theResult___exp__h384804 == 8'd255 && + _theResult___sfd__h384805 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h384983 ; - assign out_f_sfd__h430957 = - (_theResult___exp__h430679 == 8'd255 && - _theResult___sfd__h430680 != 23'd0) ? + _theResult___sfd__h384805 ; + assign out_f_sfd__h430779 = + (_theResult___exp__h430501 == 8'd255 && + _theResult___sfd__h430502 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h430680 ; - assign out_f_sfd__h476652 = - (_theResult___exp__h476374 == 8'd255 && - _theResult___sfd__h476375 != 23'd0) ? + _theResult___sfd__h430502 ; + assign out_f_sfd__h476474 = + (_theResult___exp__h476196 == 8'd255 && + _theResult___sfd__h476197 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h476375 ; - assign out_sfd__h358482 = - sfdin__h357956[34] ? - _theResult___sfd__h358479 : - sfdin__h357956[56:34] ; - assign out_sfd__h367064 = - _theResult___snd__h366569[34] ? - _theResult___sfd__h367061 : - _theResult___snd__h366569[56:34] ; - assign out_sfd__h376248 = - sfdin__h375722[34] ? - _theResult___sfd__h376245 : - sfdin__h375722[56:34] ; - assign out_sfd__h384884 = - _theResult___snd__h384359[34] ? - _theResult___sfd__h384881 : - _theResult___snd__h384359[56:34] ; - assign out_sfd__h404179 = - sfdin__h403653[34] ? - _theResult___sfd__h404176 : - sfdin__h403653[56:34] ; - assign out_sfd__h412761 = - _theResult___snd__h412266[34] ? - _theResult___sfd__h412758 : - _theResult___snd__h412266[56:34] ; - assign out_sfd__h421945 = - sfdin__h421419[34] ? - _theResult___sfd__h421942 : - sfdin__h421419[56:34] ; - assign out_sfd__h430581 = - _theResult___snd__h430056[34] ? - _theResult___sfd__h430578 : - _theResult___snd__h430056[56:34] ; - assign out_sfd__h449874 = - sfdin__h449348[34] ? - _theResult___sfd__h449871 : - sfdin__h449348[56:34] ; - assign out_sfd__h458456 = - _theResult___snd__h457961[34] ? - _theResult___sfd__h458453 : - _theResult___snd__h457961[56:34] ; - assign out_sfd__h467640 = - sfdin__h467114[34] ? - _theResult___sfd__h467637 : - sfdin__h467114[56:34] ; - assign out_sfd__h476276 = - _theResult___snd__h475751[34] ? - _theResult___sfd__h476273 : - _theResult___snd__h475751[56:34] ; - assign out_sfd__h506689 = - _theResult___snd__h505981[5] ? - _theResult___sfd__h506686 : - _theResult___snd__h505981[56:5] ; - assign out_sfd__h516340 = - sfdin__h515601[5] ? - _theResult___sfd__h516337 : - sfdin__h515601[56:5] ; - assign out_sfd__h525124 = - _theResult___snd__h524386[5] ? - _theResult___sfd__h525121 : - _theResult___snd__h524386[56:5] ; - assign out_sfd__h545542 = - _theResult___snd__h544834[5] ? - _theResult___sfd__h545539 : - _theResult___snd__h544834[56:5] ; - assign out_sfd__h555193 = - sfdin__h554454[5] ? - _theResult___sfd__h555190 : - sfdin__h554454[56:5] ; - assign out_sfd__h563977 = - _theResult___snd__h563239[5] ? - _theResult___sfd__h563974 : - _theResult___snd__h563239[56:5] ; - assign out_sfd__h584846 = - _theResult___snd__h584138[5] ? - _theResult___sfd__h584843 : - _theResult___snd__h584138[56:5] ; - assign out_sfd__h594497 = - sfdin__h593758[5] ? - _theResult___sfd__h594494 : - sfdin__h593758[56:5] ; - assign out_sfd__h603281 = - _theResult___snd__h602543[5] ? - _theResult___sfd__h603278 : - _theResult___snd__h602543[56:5] ; - assign pend_ints__h655997 = + _theResult___sfd__h476197 ; + assign out_sfd__h358304 = + sfdin__h357778[34] ? + _theResult___sfd__h358301 : + sfdin__h357778[56:34] ; + assign out_sfd__h366886 = + _theResult___snd__h366391[34] ? + _theResult___sfd__h366883 : + _theResult___snd__h366391[56:34] ; + assign out_sfd__h376070 = + sfdin__h375544[34] ? + _theResult___sfd__h376067 : + sfdin__h375544[56:34] ; + assign out_sfd__h384706 = + _theResult___snd__h384181[34] ? + _theResult___sfd__h384703 : + _theResult___snd__h384181[56:34] ; + assign out_sfd__h404001 = + sfdin__h403475[34] ? + _theResult___sfd__h403998 : + sfdin__h403475[56:34] ; + assign out_sfd__h412583 = + _theResult___snd__h412088[34] ? + _theResult___sfd__h412580 : + _theResult___snd__h412088[56:34] ; + assign out_sfd__h421767 = + sfdin__h421241[34] ? + _theResult___sfd__h421764 : + sfdin__h421241[56:34] ; + assign out_sfd__h430403 = + _theResult___snd__h429878[34] ? + _theResult___sfd__h430400 : + _theResult___snd__h429878[56:34] ; + assign out_sfd__h449696 = + sfdin__h449170[34] ? + _theResult___sfd__h449693 : + sfdin__h449170[56:34] ; + assign out_sfd__h458278 = + _theResult___snd__h457783[34] ? + _theResult___sfd__h458275 : + _theResult___snd__h457783[56:34] ; + assign out_sfd__h467462 = + sfdin__h466936[34] ? + _theResult___sfd__h467459 : + sfdin__h466936[56:34] ; + assign out_sfd__h476098 = + _theResult___snd__h475573[34] ? + _theResult___sfd__h476095 : + _theResult___snd__h475573[56:34] ; + assign out_sfd__h506511 = + _theResult___snd__h505803[5] ? + _theResult___sfd__h506508 : + _theResult___snd__h505803[56:5] ; + assign out_sfd__h516162 = + sfdin__h515423[5] ? + _theResult___sfd__h516159 : + sfdin__h515423[56:5] ; + assign out_sfd__h524946 = + _theResult___snd__h524208[5] ? + _theResult___sfd__h524943 : + _theResult___snd__h524208[56:5] ; + assign out_sfd__h545364 = + _theResult___snd__h544656[5] ? + _theResult___sfd__h545361 : + _theResult___snd__h544656[56:5] ; + assign out_sfd__h555015 = + sfdin__h554276[5] ? + _theResult___sfd__h555012 : + sfdin__h554276[56:5] ; + assign out_sfd__h563799 = + _theResult___snd__h563061[5] ? + _theResult___sfd__h563796 : + _theResult___snd__h563061[56:5] ; + assign out_sfd__h584668 = + _theResult___snd__h583960[5] ? + _theResult___sfd__h584665 : + _theResult___snd__h583960[56:5] ; + assign out_sfd__h594319 = + sfdin__h593580[5] ? + _theResult___sfd__h594316 : + sfdin__h593580[56:5] ; + assign out_sfd__h603103 = + _theResult___snd__h602365[5] ? + _theResult___sfd__h603100 : + _theResult___snd__h602365[56:5] ; + assign pend_ints__h655819 = { csrf_external_int_en_vec_3_read__1834_AND_csrf_ETC___d12904, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h720841 = csrf_prv_reg ; - assign prv__h720885 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h479896 = + assign prv__h720663 = csrf_prv_reg ; + assign prv__h720707 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h479718 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_12___h659647 = csrf_fs_reg ; - assign r1__read_BITS_9_TO_0___h656435 = + assign r1__read_BITS_13_TO_12___h659469 = csrf_fs_reg ; + assign r1__read_BITS_9_TO_0___h656257 = { csrf_mideleg_11_reg, 1'b0, csrf_mideleg_9_7_reg, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BIT_20___h660275 = csrf_tw_reg ; - assign r1__read__h617968 = { r1__read__h617970, csrf_ie_vec_1 } ; - assign r1__read__h617970 = { r1__read__h617972, 2'b0 } ; - assign r1__read__h617972 = { r1__read__h617974, csrf_prev_ie_vec_0 } ; - assign r1__read__h617974 = { r1__read__h617976, csrf_prev_ie_vec_1 } ; - assign r1__read__h617976 = { r1__read__h617978, 2'b0 } ; - assign r1__read__h617978 = { r1__read__h617980, csrf_spp_reg } ; - assign r1__read__h617980 = { r1__read__h617982, 4'b0 } ; - assign r1__read__h617982 = { r1__read__h617984, csrf_fs_reg } ; - assign r1__read__h617984 = { r1__read__h617986, 2'd0 } ; - assign r1__read__h617986 = { r1__read__h617988, 1'b0 } ; - assign r1__read__h617988 = { r1__read__h617990, csrf_sum_reg } ; - assign r1__read__h617990 = { r1__read__h617992, csrf_mxr_reg } ; - assign r1__read__h617992 = { r1__read__h617994, 12'b0 } ; - assign r1__read__h617994 = { r1__read__h617996, 2'b10 } ; - assign r1__read__h617996 = { r__h618000, 29'b0 } ; - assign r1__read__h618372 = - { r1__read__h618374, csrf_software_int_en_vec_1 } ; - assign r1__read__h618374 = { r1__read__h618376, 2'b0 } ; - assign r1__read__h618376 = { r1__read__h618378, csrf_timer_int_en_vec_0 } ; - assign r1__read__h618378 = { r1__read__h618380, csrf_timer_int_en_vec_1 } ; - assign r1__read__h618380 = { r1__read__h618382, 2'b0 } ; - assign r1__read__h618382 = - { r1__read__h618384, csrf_external_int_en_vec_0 } ; - assign r1__read__h618384 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h618902 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h618907 = { r1__read__h618909, csrf_scounteren_tm_reg } ; - assign r1__read__h618909 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h618920 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h618926 = - { r1__read__h618928, csrf_software_int_pend_vec_1 } ; - assign r1__read__h618928 = { r1__read__h618930, 2'b0 } ; - assign r1__read__h618930 = - { r1__read__h618932, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h618932 = - { r1__read__h618934, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h618934 = { r1__read__h618936, 2'b0 } ; - assign r1__read__h618936 = - { r1__read__h618938, csrf_external_int_pend_vec_0 } ; - assign r1__read__h618938 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h619156 = { vm_mode_reg__read__h619162, 16'd0 } ; - assign r1__read__h619179 = { r1__read__h619181, csrf_ie_vec_1 } ; - assign r1__read__h619181 = { r1__read__h619183, 1'b0 } ; - assign r1__read__h619183 = { r1__read__h619185, csrf_ie_vec_3 } ; - assign r1__read__h619185 = { r1__read__h619187, csrf_prev_ie_vec_0 } ; - assign r1__read__h619187 = { r1__read__h619189, csrf_prev_ie_vec_1 } ; - assign r1__read__h619189 = { r1__read__h619191, 1'b0 } ; - assign r1__read__h619191 = { r1__read__h619193, csrf_prev_ie_vec_3 } ; - assign r1__read__h619193 = { r1__read__h619195, csrf_spp_reg } ; - assign r1__read__h619195 = { r1__read__h619197, 2'b0 } ; - assign r1__read__h619197 = { r1__read__h619199, csrf_mpp_reg } ; - assign r1__read__h619199 = { r1__read__h619201, csrf_fs_reg } ; - assign r1__read__h619201 = { r1__read__h619203, 2'd0 } ; - assign r1__read__h619203 = { r1__read__h619205, csrf_mprv_reg } ; - assign r1__read__h619205 = { r1__read__h619207, csrf_sum_reg } ; - assign r1__read__h619207 = { r1__read__h619209, csrf_mxr_reg } ; - assign r1__read__h619209 = { r1__read__h619211, csrf_tvm_reg } ; - assign r1__read__h619211 = { r1__read__h619213, csrf_tw_reg } ; - assign r1__read__h619213 = { r1__read__h619215, csrf_tsr_reg } ; - assign r1__read__h619215 = { r1__read__h619217, 9'b0 } ; - assign r1__read__h619217 = { r1__read__h619219, 2'b10 } ; - assign r1__read__h619219 = { r1__read__h619221, 2'b10 } ; - assign r1__read__h619221 = { r__h618000, 27'b0 } ; + assign r1__read_BIT_20___h660097 = csrf_tw_reg ; + assign r1__read__h617790 = { r1__read__h617792, csrf_ie_vec_1 } ; + assign r1__read__h617792 = { r1__read__h617794, 2'b0 } ; + assign r1__read__h617794 = { r1__read__h617796, csrf_prev_ie_vec_0 } ; + assign r1__read__h617796 = { r1__read__h617798, csrf_prev_ie_vec_1 } ; + assign r1__read__h617798 = { r1__read__h617800, 2'b0 } ; + assign r1__read__h617800 = { r1__read__h617802, csrf_spp_reg } ; + assign r1__read__h617802 = { r1__read__h617804, 4'b0 } ; + assign r1__read__h617804 = { r1__read__h617806, csrf_fs_reg } ; + assign r1__read__h617806 = { r1__read__h617808, 2'd0 } ; + assign r1__read__h617808 = { r1__read__h617810, 1'b0 } ; + assign r1__read__h617810 = { r1__read__h617812, csrf_sum_reg } ; + assign r1__read__h617812 = { r1__read__h617814, csrf_mxr_reg } ; + assign r1__read__h617814 = { r1__read__h617816, 12'b0 } ; + assign r1__read__h617816 = { r1__read__h617818, 2'b10 } ; + assign r1__read__h617818 = { r__h617822, 29'b0 } ; + assign r1__read__h618194 = + { r1__read__h618196, csrf_software_int_en_vec_1 } ; + assign r1__read__h618196 = { r1__read__h618198, 2'b0 } ; + assign r1__read__h618198 = { r1__read__h618200, csrf_timer_int_en_vec_0 } ; + assign r1__read__h618200 = { r1__read__h618202, csrf_timer_int_en_vec_1 } ; + assign r1__read__h618202 = { r1__read__h618204, 2'b0 } ; + assign r1__read__h618204 = + { r1__read__h618206, csrf_external_int_en_vec_0 } ; + assign r1__read__h618206 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h618724 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h618729 = { r1__read__h618731, csrf_scounteren_tm_reg } ; + assign r1__read__h618731 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h618742 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h618748 = + { r1__read__h618750, csrf_software_int_pend_vec_1 } ; + assign r1__read__h618750 = { r1__read__h618752, 2'b0 } ; + assign r1__read__h618752 = + { r1__read__h618754, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h618754 = + { r1__read__h618756, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h618756 = { r1__read__h618758, 2'b0 } ; + assign r1__read__h618758 = + { r1__read__h618760, csrf_external_int_pend_vec_0 } ; + assign r1__read__h618760 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h618978 = { vm_mode_reg__read__h618984, 16'd0 } ; + assign r1__read__h619001 = { r1__read__h619003, csrf_ie_vec_1 } ; + assign r1__read__h619003 = { r1__read__h619005, 1'b0 } ; + assign r1__read__h619005 = { r1__read__h619007, csrf_ie_vec_3 } ; + assign r1__read__h619007 = { r1__read__h619009, csrf_prev_ie_vec_0 } ; + assign r1__read__h619009 = { r1__read__h619011, csrf_prev_ie_vec_1 } ; + assign r1__read__h619011 = { r1__read__h619013, 1'b0 } ; + assign r1__read__h619013 = { r1__read__h619015, csrf_prev_ie_vec_3 } ; + assign r1__read__h619015 = { r1__read__h619017, csrf_spp_reg } ; + assign r1__read__h619017 = { r1__read__h619019, 2'b0 } ; + assign r1__read__h619019 = { r1__read__h619021, csrf_mpp_reg } ; + assign r1__read__h619021 = { r1__read__h619023, csrf_fs_reg } ; + assign r1__read__h619023 = { r1__read__h619025, 2'd0 } ; + assign r1__read__h619025 = { r1__read__h619027, csrf_mprv_reg } ; + assign r1__read__h619027 = { r1__read__h619029, csrf_sum_reg } ; + assign r1__read__h619029 = { r1__read__h619031, csrf_mxr_reg } ; + assign r1__read__h619031 = { r1__read__h619033, csrf_tvm_reg } ; + assign r1__read__h619033 = { r1__read__h619035, csrf_tw_reg } ; + assign r1__read__h619035 = { r1__read__h619037, csrf_tsr_reg } ; + assign r1__read__h619037 = { r1__read__h619039, 9'b0 } ; + assign r1__read__h619039 = { r1__read__h619041, 2'b10 } ; + assign r1__read__h619041 = { r1__read__h619043, 2'b10 } ; + assign r1__read__h619043 = { r__h617822, 27'b0 } ; + assign r1__read__h619126 = { r1__read__h619128, 1'b0 } ; + assign r1__read__h619128 = { r1__read__h619130, csrf_medeleg_13_11_reg } ; + assign r1__read__h619130 = { r1__read__h619132, 1'b0 } ; + assign r1__read__h619132 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h619143 = { r1__read__h619145, 1'b0 } ; + assign r1__read__h619145 = { r1__read__h619147, csrf_mideleg_5_3_reg } ; + assign r1__read__h619147 = { r1__read__h619149, 1'b0 } ; + assign r1__read__h619149 = { r1__read__h619151, csrf_mideleg_9_7_reg } ; + assign r1__read__h619151 = { r1__read__h619153, 1'b0 } ; + assign r1__read__h619153 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h619167 = + { r1__read__h619169, csrf_software_int_en_vec_1 } ; + assign r1__read__h619169 = { r1__read__h619171, 1'b0 } ; + assign r1__read__h619171 = + { r1__read__h619173, csrf_software_int_en_vec_3 } ; + assign r1__read__h619173 = { r1__read__h619175, csrf_timer_int_en_vec_0 } ; + assign r1__read__h619175 = { r1__read__h619177, csrf_timer_int_en_vec_1 } ; + assign r1__read__h619177 = { r1__read__h619179, 1'b0 } ; + assign r1__read__h619179 = { r1__read__h619181, csrf_timer_int_en_vec_3 } ; + assign r1__read__h619181 = + { r1__read__h619183, csrf_external_int_en_vec_0 } ; + assign r1__read__h619183 = + { r1__read__h619185, csrf_external_int_en_vec_1 } ; + assign r1__read__h619185 = { r1__read__h619187, 1'b0 } ; + assign r1__read__h619187 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h619278 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h619283 = { r1__read__h619285, csrf_mcounteren_tm_reg } ; + assign r1__read__h619285 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h619296 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h619302 = + { r1__read__h619304, csrf_software_int_pend_vec_1 } ; assign r1__read__h619304 = { r1__read__h619306, 1'b0 } ; - assign r1__read__h619306 = { r1__read__h619308, csrf_medeleg_13_11_reg } ; - assign r1__read__h619308 = { r1__read__h619310, 1'b0 } ; - assign r1__read__h619310 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h619321 = { r1__read__h619323, 1'b0 } ; - assign r1__read__h619323 = { r1__read__h619325, csrf_mideleg_5_3_reg } ; - assign r1__read__h619325 = { r1__read__h619327, 1'b0 } ; - assign r1__read__h619327 = { r1__read__h619329, csrf_mideleg_9_7_reg } ; - assign r1__read__h619329 = { r1__read__h619331, 1'b0 } ; - assign r1__read__h619331 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h619345 = - { r1__read__h619347, csrf_software_int_en_vec_1 } ; - assign r1__read__h619347 = { r1__read__h619349, 1'b0 } ; - assign r1__read__h619349 = - { r1__read__h619351, csrf_software_int_en_vec_3 } ; - assign r1__read__h619351 = { r1__read__h619353, csrf_timer_int_en_vec_0 } ; - assign r1__read__h619353 = { r1__read__h619355, csrf_timer_int_en_vec_1 } ; - assign r1__read__h619355 = { r1__read__h619357, 1'b0 } ; - assign r1__read__h619357 = { r1__read__h619359, csrf_timer_int_en_vec_3 } ; - assign r1__read__h619359 = - { r1__read__h619361, csrf_external_int_en_vec_0 } ; - assign r1__read__h619361 = - { r1__read__h619363, csrf_external_int_en_vec_1 } ; - assign r1__read__h619363 = { r1__read__h619365, 1'b0 } ; - assign r1__read__h619365 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h619456 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h619461 = { r1__read__h619463, csrf_mcounteren_tm_reg } ; - assign r1__read__h619463 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h619474 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h619480 = - { r1__read__h619482, csrf_software_int_pend_vec_1 } ; - assign r1__read__h619482 = { r1__read__h619484, 1'b0 } ; - assign r1__read__h619484 = - { r1__read__h619486, csrf_software_int_pend_vec_3 } ; - assign r1__read__h619486 = - { r1__read__h619488, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h619488 = - { r1__read__h619490, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h619490 = { r1__read__h619492, 1'b0 } ; - assign r1__read__h619492 = - { r1__read__h619494, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h619494 = - { r1__read__h619496, csrf_external_int_pend_vec_0 } ; - assign r1__read__h619496 = - { r1__read__h619498, csrf_external_int_pend_vec_1 } ; - assign r1__read__h619498 = { r1__read__h619500, 1'b0 } ; - assign r1__read__h619500 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign rVal1__h486258 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h486259 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h479923 = + assign r1__read__h619306 = + { r1__read__h619308, csrf_software_int_pend_vec_3 } ; + assign r1__read__h619308 = + { r1__read__h619310, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h619310 = + { r1__read__h619312, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h619312 = { r1__read__h619314, 1'b0 } ; + assign r1__read__h619314 = + { r1__read__h619316, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h619316 = + { r1__read__h619318, csrf_external_int_pend_vec_0 } ; + assign r1__read__h619318 = + { r1__read__h619320, csrf_external_int_pend_vec_1 } ; + assign r1__read__h619320 = { r1__read__h619322, 1'b0 } ; + assign r1__read__h619322 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign rVal1__h486080 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h486081 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h479745 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h618000 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13333 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign r__h617822 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3324__ETC___d13936 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -29444,12 +29190,12 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2861_2862_O_ETC___d14284 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160] ; - assign renaming_spec_bits__h686863 = + assign renaming_spec_bits__h686685 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h683629 : + y_avValue_snd_fst__h683451 : specTagManager$currentSpecBits ; - assign res_data__h341635 = { 32'hFFFFFFFF, x__h341650 } ; - assign res_data__h341640 = + assign res_data__h341457 = { 32'hFFFFFFFF, x__h341472 } ; + assign res_data__h341462 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -29462,8 +29208,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h387337 = { 32'hFFFFFFFF, x__h387352 } ; - assign res_data__h387342 = + assign res_data__h387159 = { 32'hFFFFFFFF, x__h387174 } ; + assign res_data__h387164 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -29476,8 +29222,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h433032 = { 32'hFFFFFFFF, x__h433047 } ; - assign res_data__h433037 = + assign res_data__h432854 = { 32'hFFFFFFFF, x__h432869 } ; + assign res_data__h432859 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -29490,7 +29236,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h341636 = + assign res_fflags__h341458 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -29558,7 +29304,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ; - assign res_fflags__h387338 = + assign res_fflags__h387160 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -29626,7 +29372,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ; - assign res_fflags__h433033 = + assign res_fflags__h432855 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -29637,7 +29383,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h450620 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8082, @@ -29649,7 +29396,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h450620 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8093, @@ -29661,7 +29409,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h450620 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8109, @@ -29673,7 +29422,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h450620 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8122, @@ -29685,39 +29435,46 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h450620 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ; - assign resp_addr__h295744 = + assign resp_addr__h295566 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h368103 = + assign result__h367925 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] | - guard__h368098 } ; - assign result__h413800 = + guard__h367920 } ; + assign result__h413622 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] | - guard__h413795 } ; - assign result__h459495 = + guard__h413617 } ; + assign result__h459317 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] | - guard__h459490 } ; - assign result__h507984 = + guard__h459312 } ; + assign result__h507806 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[0] | - guard__h507979 } ; - assign result__h546837 = + guard__h507801 } ; + assign result__h546659 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[0] | - guard__h546832 } ; - assign result__h586141 = + guard__h546654 } ; + assign result__h585963 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[0] | - guard__h586136 } ; - assign result__h651706 = w__h651701 & y__h651735 ; - assign result__h651757 = ~x__h651756 ; + guard__h585958 } ; + assign result__h651528 = w__h651523 & y__h651557 ; + assign result__h651579 = ~x__h651578 ; + assign rob_RDY_enqPort_1_enq__4056_AND_NOT_fetchStage_ETC___d14064 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3434_3519_OR_NOT__ETC___d14060) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4363_BITS_282_TO_219_4_ETC___d14846 = rob$deqPort_0_deq_data[282:219] + 64'd4 ; assign rob_enqPort_1_canEnq__3735_AND_epochManager_ch_ETC___d13740 = @@ -29743,481 +29500,471 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13887) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h659778 = + assign rs1__h659600 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h615994 = { r1__read__h619156, csrf_ppn_reg } ; - assign sbIdx__h158499 = + assign satp_csr__read__h615816 = { r1__read__h618978, csrf_ppn_reg } ; + assign sbIdx__h158320 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h615792 = - { r1__read__h618920, csrf_scause_code_reg } ; - assign scounteren_csr__read__h615654 = - { r1__read__h618907, csrf_scounteren_cy_reg } ; - assign sfd__h342246 = { value__h350473, 3'd0 } ; - assign sfd__h358054 = + assign scause_csr__read__h615614 = + { r1__read__h618742, csrf_scause_code_reg } ; + assign scounteren_csr__read__h615476 = + { r1__read__h618729, csrf_scounteren_cy_reg } ; + assign sfd__h342068 = { value__h350295, 3'd0 } ; + assign sfd__h357876 = { 1'b0, - _theResult___fst_exp__h357962 != 8'd0, - sfdin__h357956[56:34] } + + _theResult___fst_exp__h357784 != 8'd0, + sfdin__h357778[56:34] } + 25'd1 ; - assign sfd__h366636 = + assign sfd__h366458 = { 1'b0, - _theResult___fst_exp__h366618 != 8'd0, - _theResult___snd__h366569[56:34] } + + _theResult___fst_exp__h366440 != 8'd0, + _theResult___snd__h366391[56:34] } + 25'd1 ; - assign sfd__h375820 = + assign sfd__h375642 = { 1'b0, - _theResult___fst_exp__h375728 != 8'd0, - sfdin__h375722[56:34] } + + _theResult___fst_exp__h375550 != 8'd0, + sfdin__h375544[56:34] } + 25'd1 ; - assign sfd__h384432 = + assign sfd__h384254 = { 1'b0, - _theResult___fst_exp__h384413 != 8'd0, - _theResult___snd__h384359[56:34] } + + _theResult___fst_exp__h384235 != 8'd0, + _theResult___snd__h384181[56:34] } + 25'd1 ; - assign sfd__h387948 = { value__h396170, 3'd0 } ; - assign sfd__h403751 = + assign sfd__h387770 = { value__h395992, 3'd0 } ; + assign sfd__h403573 = { 1'b0, - _theResult___fst_exp__h403659 != 8'd0, - sfdin__h403653[56:34] } + + _theResult___fst_exp__h403481 != 8'd0, + sfdin__h403475[56:34] } + 25'd1 ; - assign sfd__h412333 = + assign sfd__h412155 = { 1'b0, - _theResult___fst_exp__h412315 != 8'd0, - _theResult___snd__h412266[56:34] } + + _theResult___fst_exp__h412137 != 8'd0, + _theResult___snd__h412088[56:34] } + 25'd1 ; - assign sfd__h421517 = + assign sfd__h421339 = { 1'b0, - _theResult___fst_exp__h421425 != 8'd0, - sfdin__h421419[56:34] } + + _theResult___fst_exp__h421247 != 8'd0, + sfdin__h421241[56:34] } + 25'd1 ; - assign sfd__h430129 = + assign sfd__h429951 = { 1'b0, - _theResult___fst_exp__h430110 != 8'd0, - _theResult___snd__h430056[56:34] } + + _theResult___fst_exp__h429932 != 8'd0, + _theResult___snd__h429878[56:34] } + 25'd1 ; - assign sfd__h433643 = { value__h441865, 3'd0 } ; - assign sfd__h449446 = + assign sfd__h433465 = { value__h441687, 3'd0 } ; + assign sfd__h449268 = { 1'b0, - _theResult___fst_exp__h449354 != 8'd0, - sfdin__h449348[56:34] } + + _theResult___fst_exp__h449176 != 8'd0, + sfdin__h449170[56:34] } + 25'd1 ; - assign sfd__h458028 = + assign sfd__h457850 = { 1'b0, - _theResult___fst_exp__h458010 != 8'd0, - _theResult___snd__h457961[56:34] } + + _theResult___fst_exp__h457832 != 8'd0, + _theResult___snd__h457783[56:34] } + 25'd1 ; - assign sfd__h467212 = + assign sfd__h467034 = { 1'b0, - _theResult___fst_exp__h467120 != 8'd0, - sfdin__h467114[56:34] } + + _theResult___fst_exp__h466942 != 8'd0, + sfdin__h466936[56:34] } + 25'd1 ; - assign sfd__h475824 = + assign sfd__h475646 = { 1'b0, - _theResult___fst_exp__h475805 != 8'd0, - _theResult___snd__h475751[56:34] } + + _theResult___fst_exp__h475627 != 8'd0, + _theResult___snd__h475573[56:34] } + 25'd1 ; - assign sfd__h487004 = { value__h491587, 32'd0 } ; - assign sfd__h506048 = + assign sfd__h486826 = { value__h491409, 32'd0 } ; + assign sfd__h505870 = { 1'b0, - _theResult___fst_exp__h506030 != 11'd0, - _theResult___snd__h505981[56:5] } + + _theResult___fst_exp__h505852 != 11'd0, + _theResult___snd__h505803[56:5] } + 54'd1 ; - assign sfd__h515699 = + assign sfd__h515521 = { 1'b0, - _theResult___fst_exp__h515607 != 11'd0, - sfdin__h515601[56:5] } + + _theResult___fst_exp__h515429 != 11'd0, + sfdin__h515423[56:5] } + 54'd1 ; - assign sfd__h524459 = + assign sfd__h524281 = { 1'b0, - _theResult___fst_exp__h524440 != 11'd0, - _theResult___snd__h524386[56:5] } + + _theResult___fst_exp__h524262 != 11'd0, + _theResult___snd__h524208[56:5] } + 54'd1 ; - assign sfd__h525998 = { value__h530440, 32'd0 } ; - assign sfd__h544901 = + assign sfd__h525820 = { value__h530262, 32'd0 } ; + assign sfd__h544723 = { 1'b0, - _theResult___fst_exp__h544883 != 11'd0, - _theResult___snd__h544834[56:5] } + + _theResult___fst_exp__h544705 != 11'd0, + _theResult___snd__h544656[56:5] } + 54'd1 ; - assign sfd__h554552 = + assign sfd__h554374 = { 1'b0, - _theResult___fst_exp__h554460 != 11'd0, - sfdin__h554454[56:5] } + + _theResult___fst_exp__h554282 != 11'd0, + sfdin__h554276[56:5] } + 54'd1 ; - assign sfd__h563312 = + assign sfd__h563134 = { 1'b0, - _theResult___fst_exp__h563293 != 11'd0, - _theResult___snd__h563239[56:5] } + + _theResult___fst_exp__h563115 != 11'd0, + _theResult___snd__h563061[56:5] } + 54'd1 ; - assign sfd__h565302 = { value__h569744, 32'd0 } ; - assign sfd__h584205 = + assign sfd__h565124 = { value__h569566, 32'd0 } ; + assign sfd__h584027 = { 1'b0, - _theResult___fst_exp__h584187 != 11'd0, - _theResult___snd__h584138[56:5] } + + _theResult___fst_exp__h584009 != 11'd0, + _theResult___snd__h583960[56:5] } + 54'd1 ; - assign sfd__h593856 = + assign sfd__h593678 = { 1'b0, - _theResult___fst_exp__h593764 != 11'd0, - sfdin__h593758[56:5] } + + _theResult___fst_exp__h593586 != 11'd0, + sfdin__h593580[56:5] } + 54'd1 ; - assign sfd__h602616 = + assign sfd__h602438 = { 1'b0, - _theResult___fst_exp__h602597 != 11'd0, - _theResult___snd__h602543[56:5] } + + _theResult___fst_exp__h602419 != 11'd0, + _theResult___snd__h602365[56:5] } + 54'd1 ; - assign sfdin__h357956 = - _theResult____h349851[56] ? - _theResult___snd__h357973 : - _theResult___snd__h357984 ; - assign sfdin__h375722 = - _theResult____h367490[56] ? - _theResult___snd__h375739 : - _theResult___snd__h375750 ; - assign sfdin__h403653 = - _theResult____h395550[56] ? - _theResult___snd__h403670 : - _theResult___snd__h403681 ; - assign sfdin__h421419 = - _theResult____h413187[56] ? - _theResult___snd__h421436 : - _theResult___snd__h421447 ; - assign sfdin__h449348 = - _theResult____h441245[56] ? - _theResult___snd__h449365 : - _theResult___snd__h449376 ; - assign sfdin__h467114 = - _theResult____h458882[56] ? - _theResult___snd__h467131 : - _theResult___snd__h467142 ; - assign sfdin__h515601 = - _theResult____h507371[56] ? - _theResult___snd__h515618 : - _theResult___snd__h515629 ; - assign sfdin__h554454 = - _theResult____h546224[56] ? - _theResult___snd__h554471 : - _theResult___snd__h554482 ; - assign sfdin__h593758 = - _theResult____h585528[56] ? - _theResult___snd__h593775 : - _theResult___snd__h593786 ; - assign shiftData__h184726 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184855 ; - assign sie_csr__read__h615558 = - { r1__read__h618372, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h615931 = - { r1__read__h618926, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h689958 = specTagManager$currentSpecBits | y__h689971 ; - assign sstatus_csr__read__h615489 = { r1__read__h617968, csrf_ie_vec_0 } ; - assign stvec_csr__read__h615601 = - { r1__read__h618902, csrf_stvec_mode_low_reg } ; - assign upd__h3857 = + assign sfdin__h357778 = + _theResult____h349673[56] ? + _theResult___snd__h357795 : + _theResult___snd__h357806 ; + assign sfdin__h375544 = + _theResult____h367312[56] ? + _theResult___snd__h375561 : + _theResult___snd__h375572 ; + assign sfdin__h403475 = + _theResult____h395372[56] ? + _theResult___snd__h403492 : + _theResult___snd__h403503 ; + assign sfdin__h421241 = + _theResult____h413009[56] ? + _theResult___snd__h421258 : + _theResult___snd__h421269 ; + assign sfdin__h449170 = + _theResult____h441067[56] ? + _theResult___snd__h449187 : + _theResult___snd__h449198 ; + assign sfdin__h466936 = + _theResult____h458704[56] ? + _theResult___snd__h466953 : + _theResult___snd__h466964 ; + assign sfdin__h515423 = + _theResult____h507193[56] ? + _theResult___snd__h515440 : + _theResult___snd__h515451 ; + assign sfdin__h554276 = + _theResult____h546046[56] ? + _theResult___snd__h554293 : + _theResult___snd__h554304 ; + assign sfdin__h593580 = + _theResult____h585350[56] ? + _theResult___snd__h593597 : + _theResult___snd__h593608 ; + assign shiftData__h184548 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184677 ; + assign sie_csr__read__h615380 = + { r1__read__h618194, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h615753 = + { r1__read__h618748, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h689780 = specTagManager$currentSpecBits | y__h689793 ; + assign sstatus_csr__read__h615311 = { r1__read__h617790, csrf_ie_vec_0 } ; + assign stvec_csr__read__h615423 = + { r1__read__h618724, csrf_stvec_mode_low_reg } ; + assign upd__h3679 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5174 = n__read__h6352 + 64'd1 ; - assign upd__h6466 = - MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? - rob$deqPort_0_deq_data[95:32] : - 64'd0 ; - assign upd__h716290 = - MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? - rob$deqPort_0_deq_data[95:32] : - 64'd0 ; - assign v__h299708 = + assign upd__h4996 = n__read__h6174 + 64'd1 ; + assign v__h299530 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ? - v__h299939 : + v__h299761 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h299939 = + assign v__h299761 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h303053 = + assign v__h302875 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ? - v__h303571 : + v__h303393 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h303571 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h313567 = + assign v__h303393 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h313389 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ? - v__h313798 : + v__h313620 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h313798 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h317443 = + assign v__h313620 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h317265 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ? - v__h317674 : + v__h317496 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h317674 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h332044 = + assign v__h317496 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h331866 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ? - v__h332275 : + v__h332097 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h332275 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h335269 = + assign v__h332097 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h335091 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ? - v__h335500 : + v__h335322 : coreFix_memExe_forwardQ_enqP ; - assign v__h335500 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h608735 = + assign v__h335322 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h608557 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h608745 : + v__h608567 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h608745 = + assign v__h608567 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h609803 = v__h608735 - 2'd1 ; - assign v__h613787 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h614958 ; - assign v__h638244 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h639264 ; - assign vaddr__h184721 = + assign v__h609625 = v__h608557 - 2'd1 ; + assign v__h613609 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h614780 ; + assign v__h638066 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h639086 ; + assign vaddr__h184543 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; - assign value_BIT_52___h450620 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 ; - assign value__h350473 = + assign value__h350295 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h396170 = + assign value__h395992 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h441865 = + assign value__h441687 = { 1'b0, - value_BIT_52___h450620, + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h491587 = { 1'b0, f1_exp__h486642 != 8'd0, f1_sfd__h486643 } ; - assign value__h530440 = { 1'b0, f2_exp__h525636 != 8'd0, f2_sfd__h525637 } ; - assign value__h569744 = { 1'b0, f3_exp__h564940 != 8'd0, f3_sfd__h564941 } ; - assign vm_mode_reg__read__h619162 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h651701 = + assign value__h491409 = { 1'b0, f1_exp__h486464 != 8'd0, f1_sfd__h486465 } ; + assign value__h530262 = { 1'b0, f2_exp__h525458 != 8'd0, f2_sfd__h525459 } ; + assign value__h569566 = { 1'b0, f3_exp__h564762 != 8'd0, f3_sfd__h564763 } ; + assign vm_mode_reg__read__h618984 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h651523 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h651757 : + result__h651579 : 12'd4095 ; - assign x__h155073 = + assign x__h154894 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155079 = + assign x__h154900 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158620 = { 3'd0, sbIdx__h158499 } ; - assign x__h158626 = + assign x__h158441 = { 3'd0, sbIdx__h158320 } ; + assign x__h158447 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161436 = + assign x__h161257 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161440 = + assign x__h161261 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163288 = + assign x__h163109 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h17914 = + assign x__h17735 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h184633 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183761 ; - assign x__h184634 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184480 ; - assign x__h184855 = { vaddr__h184721[2:0], 3'b0 } ; - assign x__h195183 = + assign x__h184455 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183583 ; + assign x__h184456 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184302 ; + assign x__h184677 = { vaddr__h184543[2:0], 3'b0 } ; + assign x__h195005 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h194420[63:32] : - curData__h194420[31:0] ; - assign x__h20452 = + curData__h194242[63:32] : + curData__h194242[31:0] ; + assign x__h20273 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h290941 = + assign x__h290763 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h290953 = + assign x__h290775 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h292807 = + assign x__h292629 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h305918 = + assign x__h305740 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h341650 = - { (_theResult___exp__h384982 != 8'd255 || - _theResult___sfd__h384983 == 23'd0) && + assign x__h341472 = + { (_theResult___exp__h384804 != 8'd255 || + _theResult___sfd__h384805 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236, - out_f_exp__h385259, - out_f_sfd__h385260 } ; - assign x__h368200 = - sfd__h342246 << (x__h368233[11] ? 12'hAAA : x__h368233) ; - assign x__h368233 = + out_f_exp__h385081, + out_f_sfd__h385082 } ; + assign x__h368022 = + sfd__h342068 << (x__h368055[11] ? 12'hAAA : x__h368055) ; + assign x__h368055 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ; - assign x__h387352 = - { (_theResult___exp__h430679 != 8'd255 || - _theResult___sfd__h430680 == 23'd0) && + assign x__h387174 = + { (_theResult___exp__h430501 != 8'd255 || + _theResult___sfd__h430502 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628, - out_f_exp__h430956, - out_f_sfd__h430957 } ; - assign x__h413897 = - sfd__h387948 << (x__h413930[11] ? 12'hAAA : x__h413930) ; - assign x__h413930 = + out_f_exp__h430778, + out_f_sfd__h430779 } ; + assign x__h413719 = + sfd__h387770 << (x__h413752[11] ? 12'hAAA : x__h413752) ; + assign x__h413752 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ; - assign x__h433047 = - { (_theResult___exp__h476374 != 8'd255 || - _theResult___sfd__h476375 == 23'd0) && + assign x__h432869 = + { (_theResult___exp__h476196 != 8'd255 || + _theResult___sfd__h476197 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020, - out_f_exp__h476651, - out_f_sfd__h476652 } ; - assign x__h45821 = + out_f_exp__h476473, + out_f_sfd__h476474 } ; + assign x__h45642 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h459592 = - sfd__h433643 << (x__h459625[11] ? 12'hAAA : x__h459625) ; - assign x__h459625 = + assign x__h459414 = + sfd__h433465 << (x__h459447[11] ? 12'hAAA : x__h459447) ; + assign x__h459447 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ; - assign x__h48357 = + assign x__h48178 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h486164 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483227 ; - assign x__h486165 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h483948 ; - assign x__h486166 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h484663 ; - assign x__h508079 = sfd__h487004 << x__h508112 ; - assign x__h508112 = + assign x__h485986 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483049 ; + assign x__h485987 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h483770 ; + assign x__h485988 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h484485 ; + assign x__h507901 = sfd__h486826 << x__h507934 ; + assign x__h507934 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; - assign x__h546932 = sfd__h525998 << x__h546965 ; - assign x__h546965 = + assign x__h546754 = sfd__h525820 << x__h546787 ; + assign x__h546787 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; - assign x__h586236 = sfd__h565302 << x__h586269 ; - assign x__h586269 = + assign x__h586058 = sfd__h565124 << x__h586091 ; + assign x__h586091 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; - assign x__h608025 = + assign x__h607847 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h608036 : - a__h607488 ; - assign x__h608051 = a__h607488[63] ^ b__h607489[63] ; - assign x__h608665 = + _theResult___fst__h607858 : + a__h607310 ; + assign x__h607873 = a__h607310[63] ^ b__h607311[63] ; + assign x__h608487 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 } ; - assign x__h617953 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h622251 = + assign x__h617775 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h622073 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h615015 : - v__h613787 ; - assign x__h622252 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h620293 ; - assign x__h644281 = + rVal1__h614837 : + v__h613609 ; + assign x__h622074 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h620115 ; + assign x__h644103 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h639319 : - v__h638244 ; - assign x__h644282 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h642333 ; - assign x__h651705 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h651756 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h701147 = + rVal1__h639141 : + v__h638066 ; + assign x__h644104 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h642155 ; + assign x__h651527 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h651578 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h700969 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h707412 = { cause_code__h704811, 2'b0 } ; - assign x__h715589 = { 1'b0, csrf_spp_reg } ; - assign x__h719574 = + assign x__h707234 = { cause_code__h704633, 2'b0 } ; + assign x__h715411 = { 1'b0, csrf_spp_reg } ; + assign x__h719396 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_snd_snd_snd_fst__h719397 : + y_avValue_snd_snd_snd_fst__h719219 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 ; - assign x__h75766 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h317841 = + assign x__h75587 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h317663 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65615 = + assign x_data__h65436 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h678934 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h694584 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h659462 = csrf_frm_reg ; - assign x_quotient__h479073 = + assign x_data_imm__h678756 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h694406 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h659284 = csrf_frm_reg ; + assign x_quotient__h478895 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h479896 : + q___1__h479718 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h615398 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h479074 = + assign x_reg_ifc__read__h615220 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h478896 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h479923 : + r___1__h479745 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h257551 = + assign y__h257373 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h625021 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h646758 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h651735 = ~x__h651705 ; - assign y__h656424 = + assign y__h624843 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h646580 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h651557 = ~x__h651527 ; + assign y__h656246 = { ~csrf_mideleg_11_reg, 1'd1, ~csrf_mideleg_9_7_reg, @@ -30225,60 +29972,60 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h689971 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h719350 = + assign y__h689793 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h719172 = NOT_rob_deqPort_0_canDeq__4878_4879_OR_rob_deq_ETC___d15070 ? - y_avValue_snd_snd_snd_snd_snd__h719403 : + y_avValue_snd_snd_snd_snd_snd__h719225 : IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 ; - assign y_avValue__h183761 = + assign y_avValue__h183583 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ; - assign y_avValue__h184480 = + assign y_avValue__h184302 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ; - assign y_avValue__h483227 = + assign y_avValue__h483049 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ; - assign y_avValue__h483948 = + assign y_avValue__h483770 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ; - assign y_avValue__h484663 = + assign y_avValue__h484485 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ; - assign y_avValue__h614958 = + assign y_avValue__h614780 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1502_1_ETC___d11529 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__150_ETC___d11918 ; - assign y_avValue__h620293 = + assign y_avValue__h620115 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1502_1_ETC___d11559 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__150_ETC___d11927 ; - assign y_avValue__h639264 = + assign y_avValue__h639086 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2325_2_ETC___d12352 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__232_ETC___d12560 ; - assign y_avValue__h642333 = + assign y_avValue__h642155 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2325_2_ETC___d12382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__232_ETC___d12569 ; - assign y_avValue__h705681 = + assign y_avValue__h705503 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h707397 + { 58'd0, x__h707412 } : - base__h707397 ; - assign y_avValue__h707434 = + base__h707219 + { 58'd0, x__h707234 } : + base__h707219 ; + assign y_avValue__h707256 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h707600 + { 58'd0, x__h707412 } : - base__h707600 ; - assign y_avValue_fst__h683355 = + base__h707422 + { 58'd0, x__h707234 } : + base__h707422 ; + assign y_avValue_fst__h683177 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h689958 : + spec_bits__h689780 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h718332 = + assign y_avValue_fst__h718154 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30292,10 +30039,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h719246 = + assign y_avValue_fst__h719068 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h719274 = + assign y_avValue_fst__h719096 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30308,19 +30055,19 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15076 : - y_avValue_fst__h719246 ; - assign y_avValue_snd_fst__h683629 = + y_avValue_fst__h719068 ; + assign y_avValue_snd_fst__h683451 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13456) ? - y_avValue_snd_fst__h683664 : + y_avValue_snd_fst__h683486 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h683664 = + assign y_avValue_snd_fst__h683486 = IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d13516 ? - y_avValue_fst__h683355 : + y_avValue_fst__h683177 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h718752 = + assign y_avValue_snd_snd_snd_fst__h718574 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30334,7 +30081,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h719397 = + assign y_avValue_snd_snd_snd_fst__h719219 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30347,11 +30094,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 : - y_avValue_snd_snd_snd_fst__h719426 ; - assign y_avValue_snd_snd_snd_fst__h719426 = + y_avValue_snd_snd_snd_fst__h719248 ; + assign y_avValue_snd_snd_snd_fst__h719248 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d15097 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h718758 = + assign y_avValue_snd_snd_snd_snd_snd__h718580 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -30365,7 +30112,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h719403 = + assign y_avValue_snd_snd_snd_snd_snd__h719225 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -30378,8 +30125,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 : - y_avValue_snd_snd_snd_snd_snd__h719432 ; - assign y_avValue_snd_snd_snd_snd_snd__h719432 = + y_avValue_snd_snd_snd_snd_snd__h719254 ; + assign y_avValue_snd_snd_snd_snd_snd__h719254 = IF_rob_deqPort_0_canDeq__4878_THEN_IF_NOT_rob__ETC___d14987 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -30398,28 +30145,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h199463 = + x__h199285 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -30435,28 +30182,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h289508 = + x__h289330 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -30466,10 +30213,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h293729 = + addr__h293551 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h293729 = + addr__h293551 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -30478,36 +30225,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h194420 = + curData__h194242 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h705834 = commitStage_commitTrap[132:69]; - default: trap_val__h705834 = + 4'd0, 4'd3: trap_val__h705656 = commitStage_commitTrap[132:69]; + default: trap_val__h705656 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -30522,268 +30269,268 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h295278 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h295100 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h295278 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h295100 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h615268 or - frm_csr__read__h615279 or - fcsr_csr__read__h615293 or - sstatus_csr__read__h615489 or - sie_csr__read__h615558 or - stvec_csr__read__h615601 or - scounteren_csr__read__h615654 or + fflags_csr__read__h615090 or + frm_csr__read__h615101 or + fcsr_csr__read__h615115 or + sstatus_csr__read__h615311 or + sie_csr__read__h615380 or + stvec_csr__read__h615423 or + scounteren_csr__read__h615476 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h615792 or + scause_csr__read__h615614 or csrf_stval_csr or - sip_csr__read__h615931 or - satp_csr__read__h615994 or - mstatus_csr__read__h616137 or - medeleg_csr__read__h616285 or - mideleg_csr__read__h616380 or - mie_csr__read__h616504 or - mtvec_csr__read__h616586 or - mcounteren_csr__read__h616678 or + sip_csr__read__h615753 or + satp_csr__read__h615816 or + mstatus_csr__read__h615959 or + medeleg_csr__read__h616107 or + mideleg_csr__read__h616202 or + mie_csr__read__h616326 or + mtvec_csr__read__h616408 or + mcounteren_csr__read__h616500 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h616933 or + mcause_csr__read__h616755 or csrf_mtval_csr or - mip_csr__read__h617166 or - x_reg_ifc__read__h615398 or - n__read__h617270 or n__read__h617461 or csrf_time_reg) + mip_csr__read__h616988 or + x_reg_ifc__read__h615220 or + n__read__h617092 or n__read__h617283 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h615015 = fflags_csr__read__h615268; - 12'd2: rVal1__h615015 = frm_csr__read__h615279; - 12'd3: rVal1__h615015 = fcsr_csr__read__h615293; - 12'd256: rVal1__h615015 = sstatus_csr__read__h615489; - 12'd260: rVal1__h615015 = sie_csr__read__h615558; - 12'd261: rVal1__h615015 = stvec_csr__read__h615601; - 12'd262: rVal1__h615015 = scounteren_csr__read__h615654; - 12'd320: rVal1__h615015 = csrf_sscratch_csr; - 12'd321: rVal1__h615015 = csrf_sepc_csr; - 12'd322: rVal1__h615015 = scause_csr__read__h615792; - 12'd323: rVal1__h615015 = csrf_stval_csr; - 12'd324: rVal1__h615015 = sip_csr__read__h615931; - 12'd384: rVal1__h615015 = satp_csr__read__h615994; - 12'd768: rVal1__h615015 = mstatus_csr__read__h616137; - 12'd769: rVal1__h615015 = 64'h800000000014112D; - 12'd770: rVal1__h615015 = medeleg_csr__read__h616285; - 12'd771: rVal1__h615015 = mideleg_csr__read__h616380; - 12'd772: rVal1__h615015 = mie_csr__read__h616504; - 12'd773: rVal1__h615015 = mtvec_csr__read__h616586; - 12'd774: rVal1__h615015 = mcounteren_csr__read__h616678; - 12'd832: rVal1__h615015 = csrf_mscratch_csr; - 12'd833: rVal1__h615015 = csrf_mepc_csr; - 12'd834: rVal1__h615015 = mcause_csr__read__h616933; - 12'd835: rVal1__h615015 = csrf_mtval_csr; - 12'd836: rVal1__h615015 = mip_csr__read__h617166; - 12'd2048: rVal1__h615015 = 64'd0; - 12'd2049: rVal1__h615015 = x_reg_ifc__read__h615398; - 12'd2816, 12'd3072: rVal1__h615015 = n__read__h617270; - 12'd2818, 12'd3074: rVal1__h615015 = n__read__h617461; - 12'd3073: rVal1__h615015 = csrf_time_reg; - default: rVal1__h615015 = 64'd0; + 12'd1: rVal1__h614837 = fflags_csr__read__h615090; + 12'd2: rVal1__h614837 = frm_csr__read__h615101; + 12'd3: rVal1__h614837 = fcsr_csr__read__h615115; + 12'd256: rVal1__h614837 = sstatus_csr__read__h615311; + 12'd260: rVal1__h614837 = sie_csr__read__h615380; + 12'd261: rVal1__h614837 = stvec_csr__read__h615423; + 12'd262: rVal1__h614837 = scounteren_csr__read__h615476; + 12'd320: rVal1__h614837 = csrf_sscratch_csr; + 12'd321: rVal1__h614837 = csrf_sepc_csr; + 12'd322: rVal1__h614837 = scause_csr__read__h615614; + 12'd323: rVal1__h614837 = csrf_stval_csr; + 12'd324: rVal1__h614837 = sip_csr__read__h615753; + 12'd384: rVal1__h614837 = satp_csr__read__h615816; + 12'd768: rVal1__h614837 = mstatus_csr__read__h615959; + 12'd769: rVal1__h614837 = 64'h800000000014112D; + 12'd770: rVal1__h614837 = medeleg_csr__read__h616107; + 12'd771: rVal1__h614837 = mideleg_csr__read__h616202; + 12'd772: rVal1__h614837 = mie_csr__read__h616326; + 12'd773: rVal1__h614837 = mtvec_csr__read__h616408; + 12'd774: rVal1__h614837 = mcounteren_csr__read__h616500; + 12'd832: rVal1__h614837 = csrf_mscratch_csr; + 12'd833: rVal1__h614837 = csrf_mepc_csr; + 12'd834: rVal1__h614837 = mcause_csr__read__h616755; + 12'd835: rVal1__h614837 = csrf_mtval_csr; + 12'd836: rVal1__h614837 = mip_csr__read__h616988; + 12'd2048: rVal1__h614837 = 64'd0; + 12'd2049: rVal1__h614837 = x_reg_ifc__read__h615220; + 12'd2816, 12'd3072: rVal1__h614837 = n__read__h617092; + 12'd2818, 12'd3074: rVal1__h614837 = n__read__h617283; + 12'd3073: rVal1__h614837 = csrf_time_reg; + default: rVal1__h614837 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h615268 or - frm_csr__read__h615279 or - fcsr_csr__read__h615293 or - sstatus_csr__read__h615489 or - sie_csr__read__h615558 or - stvec_csr__read__h615601 or - scounteren_csr__read__h615654 or + fflags_csr__read__h615090 or + frm_csr__read__h615101 or + fcsr_csr__read__h615115 or + sstatus_csr__read__h615311 or + sie_csr__read__h615380 or + stvec_csr__read__h615423 or + scounteren_csr__read__h615476 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h615792 or + scause_csr__read__h615614 or csrf_stval_csr or - sip_csr__read__h615931 or - satp_csr__read__h615994 or - mstatus_csr__read__h616137 or - medeleg_csr__read__h616285 or - mideleg_csr__read__h616380 or - mie_csr__read__h616504 or - mtvec_csr__read__h616586 or - mcounteren_csr__read__h616678 or + sip_csr__read__h615753 or + satp_csr__read__h615816 or + mstatus_csr__read__h615959 or + medeleg_csr__read__h616107 or + mideleg_csr__read__h616202 or + mie_csr__read__h616326 or + mtvec_csr__read__h616408 or + mcounteren_csr__read__h616500 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h616933 or + mcause_csr__read__h616755 or csrf_mtval_csr or - mip_csr__read__h617166 or - x_reg_ifc__read__h615398 or - n__read__h617270 or n__read__h617461 or csrf_time_reg) + mip_csr__read__h616988 or + x_reg_ifc__read__h615220 or + n__read__h617092 or n__read__h617283 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h639319 = fflags_csr__read__h615268; - 12'd2: rVal1__h639319 = frm_csr__read__h615279; - 12'd3: rVal1__h639319 = fcsr_csr__read__h615293; - 12'd256: rVal1__h639319 = sstatus_csr__read__h615489; - 12'd260: rVal1__h639319 = sie_csr__read__h615558; - 12'd261: rVal1__h639319 = stvec_csr__read__h615601; - 12'd262: rVal1__h639319 = scounteren_csr__read__h615654; - 12'd320: rVal1__h639319 = csrf_sscratch_csr; - 12'd321: rVal1__h639319 = csrf_sepc_csr; - 12'd322: rVal1__h639319 = scause_csr__read__h615792; - 12'd323: rVal1__h639319 = csrf_stval_csr; - 12'd324: rVal1__h639319 = sip_csr__read__h615931; - 12'd384: rVal1__h639319 = satp_csr__read__h615994; - 12'd768: rVal1__h639319 = mstatus_csr__read__h616137; - 12'd769: rVal1__h639319 = 64'h800000000014112D; - 12'd770: rVal1__h639319 = medeleg_csr__read__h616285; - 12'd771: rVal1__h639319 = mideleg_csr__read__h616380; - 12'd772: rVal1__h639319 = mie_csr__read__h616504; - 12'd773: rVal1__h639319 = mtvec_csr__read__h616586; - 12'd774: rVal1__h639319 = mcounteren_csr__read__h616678; - 12'd832: rVal1__h639319 = csrf_mscratch_csr; - 12'd833: rVal1__h639319 = csrf_mepc_csr; - 12'd834: rVal1__h639319 = mcause_csr__read__h616933; - 12'd835: rVal1__h639319 = csrf_mtval_csr; - 12'd836: rVal1__h639319 = mip_csr__read__h617166; - 12'd2048: rVal1__h639319 = 64'd0; - 12'd2049: rVal1__h639319 = x_reg_ifc__read__h615398; - 12'd2816, 12'd3072: rVal1__h639319 = n__read__h617270; - 12'd2818, 12'd3074: rVal1__h639319 = n__read__h617461; - 12'd3073: rVal1__h639319 = csrf_time_reg; - default: rVal1__h639319 = 64'd0; + 12'd1: rVal1__h639141 = fflags_csr__read__h615090; + 12'd2: rVal1__h639141 = frm_csr__read__h615101; + 12'd3: rVal1__h639141 = fcsr_csr__read__h615115; + 12'd256: rVal1__h639141 = sstatus_csr__read__h615311; + 12'd260: rVal1__h639141 = sie_csr__read__h615380; + 12'd261: rVal1__h639141 = stvec_csr__read__h615423; + 12'd262: rVal1__h639141 = scounteren_csr__read__h615476; + 12'd320: rVal1__h639141 = csrf_sscratch_csr; + 12'd321: rVal1__h639141 = csrf_sepc_csr; + 12'd322: rVal1__h639141 = scause_csr__read__h615614; + 12'd323: rVal1__h639141 = csrf_stval_csr; + 12'd324: rVal1__h639141 = sip_csr__read__h615753; + 12'd384: rVal1__h639141 = satp_csr__read__h615816; + 12'd768: rVal1__h639141 = mstatus_csr__read__h615959; + 12'd769: rVal1__h639141 = 64'h800000000014112D; + 12'd770: rVal1__h639141 = medeleg_csr__read__h616107; + 12'd771: rVal1__h639141 = mideleg_csr__read__h616202; + 12'd772: rVal1__h639141 = mie_csr__read__h616326; + 12'd773: rVal1__h639141 = mtvec_csr__read__h616408; + 12'd774: rVal1__h639141 = mcounteren_csr__read__h616500; + 12'd832: rVal1__h639141 = csrf_mscratch_csr; + 12'd833: rVal1__h639141 = csrf_mepc_csr; + 12'd834: rVal1__h639141 = mcause_csr__read__h616755; + 12'd835: rVal1__h639141 = csrf_mtval_csr; + 12'd836: rVal1__h639141 = mip_csr__read__h616988; + 12'd2048: rVal1__h639141 = 64'd0; + 12'd2049: rVal1__h639141 = x_reg_ifc__read__h615220; + 12'd2816, 12'd3072: rVal1__h639141 = n__read__h617092; + 12'd2818, 12'd3074: rVal1__h639141 = n__read__h617283; + 12'd3073: rVal1__h639141 = csrf_time_reg; + default: rVal1__h639141 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h441049 = 8'd255; + 3'd2: + _theResult___fst_exp__h441049 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h441049 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h441049 = 8'd254; + default: _theResult___fst_exp__h441049 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h349655 = 8'd255; + 3'd2: + _theResult___fst_exp__h349655 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h349655 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h349655 = 8'd254; + default: _theResult___fst_exp__h349655 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h349656 = 23'd0; + 3'd2: + _theResult___fst_sfd__h349656 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h349656 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h349656 = 23'd8388607; + default: _theResult___fst_sfd__h349656 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h395354 = 8'd255; + 3'd2: + _theResult___fst_exp__h395354 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h395354 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h395354 = 8'd254; + default: _theResult___fst_exp__h395354 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h395355 = 23'd0; + 3'd2: + _theResult___fst_sfd__h395355 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h395355 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h395355 = 23'd8388607; + default: _theResult___fst_sfd__h395355 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h441050 = 23'd0; + 3'd2: + _theResult___fst_sfd__h441050 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h441050 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h441050 = 23'd8388607; + default: _theResult___fst_sfd__h441050 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h349833 = 8'd255; - 3'd2: - _theResult___fst_exp__h349833 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h349833 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h349833 = 8'd254; - default: _theResult___fst_exp__h349833 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h349834 = 23'd0; - 3'd2: - _theResult___fst_sfd__h349834 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h349834 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h349834 = 23'd8388607; - default: _theResult___fst_sfd__h349834 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h395532 = 8'd255; - 3'd2: - _theResult___fst_exp__h395532 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h395532 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h395532 = 8'd254; - default: _theResult___fst_exp__h395532 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h395533 = 23'd0; - 3'd2: - _theResult___fst_sfd__h395533 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h395533 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h395533 = 23'd8388607; - default: _theResult___fst_sfd__h395533 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h441227 = 8'd255; - 3'd2: - _theResult___fst_exp__h441227 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h441227 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h441227 = 8'd254; - default: _theResult___fst_exp__h441227 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h441228 = 23'd0; - 3'd2: - _theResult___fst_sfd__h441228 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h441228 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h441228 = 23'd8388607; - default: _theResult___fst_sfd__h441228 = 23'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30913,16 +30660,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h704826 = commitStage_commitTrap[3:0]; - default: i__h704826 = 4'd15; + i__h704648 = commitStage_commitTrap[3:0]; + default: i__h704648 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9: - i__h704986 = commitStage_commitTrap[3:0]; - default: i__h704986 = 4'd11; + i__h704808 = commitStage_commitTrap[3:0]; + default: i__h704808 = 4'd11; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30994,6 +30741,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[15:0]; + 2'd1: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[31:16]; + 2'd2: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[47:32]; + 2'd3: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = + mmio_dataRespQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -31022,23 +30786,6 @@ module mkCore(CLK, mmio_dataRespQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[15:0]; - 2'd1: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[31:16]; - 2'd2: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[47:32]; - 2'd3: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 = - mmio_dataRespQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_dTlb$procResp) begin case (coreFix_memExe_dTlb$procResp[105:103]) @@ -31150,484 +30897,407 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h358570 or - _theResult___fst_exp__h366618 or - out_exp__h367063 or _theResult___exp__h367060) + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h358570) - 2'b0, 2'b01: - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25 = - _theResult___fst_exp__h366618; - 2'b10: - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25 = - out_exp__h367063; - 2'b11: - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25 = - _theResult___exp__h367060; + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h358570 or - _theResult___fst_exp__h366618 or _theResult___exp__h367060) + always@(guard__h358392 or + _theResult___fst_exp__h366440 or + out_exp__h366885 or _theResult___exp__h366882) begin - case (guard__h358570) + case (guard__h358392) + 2'b0, 2'b01: + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25 = + _theResult___fst_exp__h366440; + 2'b10: + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25 = + out_exp__h366885; + 2'b11: + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25 = + _theResult___exp__h366882; + endcase + end + always@(guard__h358392 or + _theResult___fst_exp__h366440 or _theResult___exp__h366882) + begin + case (guard__h358392) 2'b0: - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q26 = - _theResult___fst_exp__h366618; + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q26 = + _theResult___fst_exp__h366440; 2'b01, 2'b10, 2'b11: - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q26 = - _theResult___exp__h367060; + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q26 = + _theResult___exp__h366882; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25 or - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q26 or + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25 or + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q26 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h366618) + _theResult___fst_exp__h366440) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h367138 = - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q25; + _theResult___fst_exp__h366960 = + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q25; 3'd1: - _theResult___fst_exp__h367138 = - CASE_guard58570_0b0_theResult___fst_exp66618_0_ETC__q26; + _theResult___fst_exp__h366960 = + CASE_guard58392_0b0_theResult___fst_exp66440_0_ETC__q26; 3'd2: - _theResult___fst_exp__h367138 = + _theResult___fst_exp__h366960 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; 3'd3: - _theResult___fst_exp__h367138 = + _theResult___fst_exp__h366960 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h367138 = _theResult___fst_exp__h366618; - default: _theResult___fst_exp__h367138 = 8'd0; + 3'd4: _theResult___fst_exp__h366960 = _theResult___fst_exp__h366440; + default: _theResult___fst_exp__h366960 = 8'd0; endcase end - always@(guard__h349861 or - _theResult___fst_exp__h357962 or - out_exp__h358481 or _theResult___exp__h358478) + always@(guard__h349683 or + _theResult___fst_exp__h357784 or + out_exp__h358303 or _theResult___exp__h358300) begin - case (guard__h349861) + case (guard__h349683) 2'b0, 2'b01: - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27 = - _theResult___fst_exp__h357962; + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27 = + _theResult___fst_exp__h357784; 2'b10: - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27 = - out_exp__h358481; + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27 = + out_exp__h358303; 2'b11: - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27 = - _theResult___exp__h358478; + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27 = + _theResult___exp__h358300; endcase end - always@(guard__h349861 or - _theResult___fst_exp__h357962 or _theResult___exp__h358478) + always@(guard__h349683 or + _theResult___fst_exp__h357784 or _theResult___exp__h358300) begin - case (guard__h349861) + case (guard__h349683) 2'b0: - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q28 = - _theResult___fst_exp__h357962; + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q28 = + _theResult___fst_exp__h357784; 2'b01, 2'b10, 2'b11: - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q28 = - _theResult___exp__h358478; + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q28 = + _theResult___exp__h358300; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27 or - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q28 or + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27 or + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q28 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or - _theResult___fst_exp__h357962) + _theResult___fst_exp__h357784) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h358556 = - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q27; + _theResult___fst_exp__h358378 = + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q27; 3'd1: - _theResult___fst_exp__h358556 = - CASE_guard49861_0b0_theResult___fst_exp57962_0_ETC__q28; + _theResult___fst_exp__h358378 = + CASE_guard49683_0b0_theResult___fst_exp57784_0_ETC__q28; 3'd2: - _theResult___fst_exp__h358556 = + _theResult___fst_exp__h358378 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; 3'd3: - _theResult___fst_exp__h358556 = + _theResult___fst_exp__h358378 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; - 3'd4: _theResult___fst_exp__h358556 = _theResult___fst_exp__h357962; - default: _theResult___fst_exp__h358556 = 8'd0; + 3'd4: _theResult___fst_exp__h358378 = _theResult___fst_exp__h357784; + default: _theResult___fst_exp__h358378 = 8'd0; endcase end - always@(guard__h367500 or - _theResult___fst_exp__h375728 or - out_exp__h376247 or _theResult___exp__h376244) + always@(guard__h367322 or + _theResult___fst_exp__h375550 or + out_exp__h376069 or _theResult___exp__h376066) begin - case (guard__h367500) + case (guard__h367322) 2'b0, 2'b01: - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33 = - _theResult___fst_exp__h375728; + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33 = + _theResult___fst_exp__h375550; 2'b10: - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33 = - out_exp__h376247; + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33 = + out_exp__h376069; 2'b11: - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33 = - _theResult___exp__h376244; + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33 = + _theResult___exp__h376066; endcase end - always@(guard__h367500 or - _theResult___fst_exp__h375728 or _theResult___exp__h376244) + always@(guard__h367322 or + _theResult___fst_exp__h375550 or _theResult___exp__h376066) begin - case (guard__h367500) + case (guard__h367322) 2'b0: - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q34 = - _theResult___fst_exp__h375728; + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q34 = + _theResult___fst_exp__h375550; 2'b01, 2'b10, 2'b11: - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q34 = - _theResult___exp__h376244; + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q34 = + _theResult___exp__h376066; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33 or - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q34 or + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33 or + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q34 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or - _theResult___fst_exp__h375728) + _theResult___fst_exp__h375550) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h376322 = - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q33; + _theResult___fst_exp__h376144 = + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q33; 3'd1: - _theResult___fst_exp__h376322 = - CASE_guard67500_0b0_theResult___fst_exp75728_0_ETC__q34; + _theResult___fst_exp__h376144 = + CASE_guard67322_0b0_theResult___fst_exp75550_0_ETC__q34; 3'd2: - _theResult___fst_exp__h376322 = + _theResult___fst_exp__h376144 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; 3'd3: - _theResult___fst_exp__h376322 = + _theResult___fst_exp__h376144 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; - 3'd4: _theResult___fst_exp__h376322 = _theResult___fst_exp__h375728; - default: _theResult___fst_exp__h376322 = 8'd0; + 3'd4: _theResult___fst_exp__h376144 = _theResult___fst_exp__h375550; + default: _theResult___fst_exp__h376144 = 8'd0; endcase end - always@(guard__h376336 or - _theResult___fst_exp__h384413 or - out_exp__h384883 or _theResult___exp__h384880) + always@(guard__h376158 or + _theResult___fst_exp__h384235 or + out_exp__h384705 or _theResult___exp__h384702) begin - case (guard__h376336) + case (guard__h376158) 2'b0, 2'b01: - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38 = - _theResult___fst_exp__h384413; + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38 = + _theResult___fst_exp__h384235; 2'b10: - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38 = - out_exp__h384883; + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38 = + out_exp__h384705; 2'b11: - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38 = - _theResult___exp__h384880; + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38 = + _theResult___exp__h384702; endcase end - always@(guard__h376336 or - _theResult___fst_exp__h384413 or _theResult___exp__h384880) + always@(guard__h376158 or + _theResult___fst_exp__h384235 or _theResult___exp__h384702) begin - case (guard__h376336) + case (guard__h376158) 2'b0: - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q39 = - _theResult___fst_exp__h384413; + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q39 = + _theResult___fst_exp__h384235; 2'b01, 2'b10, 2'b11: - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q39 = - _theResult___exp__h384880; + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q39 = + _theResult___exp__h384702; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38 or - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q39 or + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38 or + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q39 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___fst_exp__h384413) + _theResult___fst_exp__h384235) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h384958 = - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q38; + _theResult___fst_exp__h384780 = + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q38; 3'd1: - _theResult___fst_exp__h384958 = - CASE_guard76336_0b0_theResult___fst_exp84413_0_ETC__q39; + _theResult___fst_exp__h384780 = + CASE_guard76158_0b0_theResult___fst_exp84235_0_ETC__q39; 3'd2: - _theResult___fst_exp__h384958 = + _theResult___fst_exp__h384780 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_exp__h384958 = + _theResult___fst_exp__h384780 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_exp__h384958 = _theResult___fst_exp__h384413; - default: _theResult___fst_exp__h384958 = 8'd0; + 3'd4: _theResult___fst_exp__h384780 = _theResult___fst_exp__h384235; + default: _theResult___fst_exp__h384780 = 8'd0; endcase end - always@(guard__h358570 or - _theResult___snd__h366569 or - out_sfd__h367064 or _theResult___sfd__h367061) + always@(guard__h358392 or + _theResult___snd__h366391 or + out_sfd__h366886 or _theResult___sfd__h366883) begin - case (guard__h358570) + case (guard__h358392) 2'b0, 2'b01: - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40 = - _theResult___snd__h366569[56:34]; + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40 = + _theResult___snd__h366391[56:34]; 2'b10: - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40 = - out_sfd__h367064; + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40 = + out_sfd__h366886; 2'b11: - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40 = - _theResult___sfd__h367061; + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40 = + _theResult___sfd__h366883; endcase end - always@(guard__h358570 or - _theResult___snd__h366569 or _theResult___sfd__h367061) + always@(guard__h358392 or + _theResult___snd__h366391 or _theResult___sfd__h366883) begin - case (guard__h358570) + case (guard__h358392) 2'b0: - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q41 = - _theResult___snd__h366569[56:34]; + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q41 = + _theResult___snd__h366391[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q41 = - _theResult___sfd__h367061; + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q41 = + _theResult___sfd__h366883; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40 or - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q41 or + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40 or + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q41 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or - _theResult___snd__h366569) + _theResult___snd__h366391) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h367139 = - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q40; + _theResult___fst_sfd__h366961 = + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q40; 3'd1: - _theResult___fst_sfd__h367139 = - CASE_guard58570_0b0_theResult___snd66569_BITS__ETC__q41; + _theResult___fst_sfd__h366961 = + CASE_guard58392_0b0_theResult___snd66391_BITS__ETC__q41; 3'd2: - _theResult___fst_sfd__h367139 = + _theResult___fst_sfd__h366961 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; 3'd3: - _theResult___fst_sfd__h367139 = + _theResult___fst_sfd__h366961 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; - 3'd4: _theResult___fst_sfd__h367139 = _theResult___snd__h366569[56:34]; - default: _theResult___fst_sfd__h367139 = 23'd0; + 3'd4: _theResult___fst_sfd__h366961 = _theResult___snd__h366391[56:34]; + default: _theResult___fst_sfd__h366961 = 23'd0; endcase end - always@(guard__h349861 or - sfdin__h357956 or out_sfd__h358482 or _theResult___sfd__h358479) + always@(guard__h349683 or + sfdin__h357778 or out_sfd__h358304 or _theResult___sfd__h358301) begin - case (guard__h349861) + case (guard__h349683) 2'b0, 2'b01: - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42 = - sfdin__h357956[56:34]; + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42 = + sfdin__h357778[56:34]; 2'b10: - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42 = - out_sfd__h358482; + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h358304; 2'b11: - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h358479; + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h358301; endcase end - always@(guard__h349861 or sfdin__h357956 or _theResult___sfd__h358479) + always@(guard__h349683 or sfdin__h357778 or _theResult___sfd__h358301) begin - case (guard__h349861) + case (guard__h349683) 2'b0: - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q43 = - sfdin__h357956[56:34]; + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q43 = + sfdin__h357778[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h358479; + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h358301; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42 or - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q43 or + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42 or + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q43 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h357956) + sfdin__h357778) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h358557 = - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h358379 = + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q42; 3'd1: - _theResult___fst_sfd__h358557 = - CASE_guard49861_0b0_sfdin57956_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h358379 = + CASE_guard49683_0b0_sfdin57778_BITS_56_TO_34_0_ETC__q43; 3'd2: - _theResult___fst_sfd__h358557 = + _theResult___fst_sfd__h358379 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; 3'd3: - _theResult___fst_sfd__h358557 = + _theResult___fst_sfd__h358379 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h358557 = sfdin__h357956[56:34]; - default: _theResult___fst_sfd__h358557 = 23'd0; + 3'd4: _theResult___fst_sfd__h358379 = sfdin__h357778[56:34]; + default: _theResult___fst_sfd__h358379 = 23'd0; endcase end - always@(guard__h367500 or - sfdin__h375722 or out_sfd__h376248 or _theResult___sfd__h376245) + always@(guard__h367322 or + sfdin__h375544 or out_sfd__h376070 or _theResult___sfd__h376067) begin - case (guard__h367500) + case (guard__h367322) 2'b0, 2'b01: - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44 = - sfdin__h375722[56:34]; + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44 = + sfdin__h375544[56:34]; 2'b10: - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44 = - out_sfd__h376248; + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44 = + out_sfd__h376070; 2'b11: - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h376245; + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h376067; endcase end - always@(guard__h367500 or sfdin__h375722 or _theResult___sfd__h376245) + always@(guard__h367322 or sfdin__h375544 or _theResult___sfd__h376067) begin - case (guard__h367500) + case (guard__h367322) 2'b0: - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q45 = - sfdin__h375722[56:34]; + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q45 = + sfdin__h375544[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q45 = - _theResult___sfd__h376245; + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q45 = + _theResult___sfd__h376067; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44 or - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q45 or + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44 or + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q45 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or - sfdin__h375722) + sfdin__h375544) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h376323 = - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h376145 = + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q44; 3'd1: - _theResult___fst_sfd__h376323 = - CASE_guard67500_0b0_sfdin75722_BITS_56_TO_34_0_ETC__q45; + _theResult___fst_sfd__h376145 = + CASE_guard67322_0b0_sfdin75544_BITS_56_TO_34_0_ETC__q45; 3'd2: - _theResult___fst_sfd__h376323 = + _theResult___fst_sfd__h376145 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; 3'd3: - _theResult___fst_sfd__h376323 = + _theResult___fst_sfd__h376145 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; - 3'd4: _theResult___fst_sfd__h376323 = sfdin__h375722[56:34]; - default: _theResult___fst_sfd__h376323 = 23'd0; + 3'd4: _theResult___fst_sfd__h376145 = sfdin__h375544[56:34]; + default: _theResult___fst_sfd__h376145 = 23'd0; endcase end - always@(guard__h376336 or - _theResult___snd__h384359 or - out_sfd__h384884 or _theResult___sfd__h384881) - begin - case (guard__h376336) - 2'b0, 2'b01: - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46 = - _theResult___snd__h384359[56:34]; - 2'b10: - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46 = - out_sfd__h384884; - 2'b11: - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46 = - _theResult___sfd__h384881; - endcase - end - always@(guard__h376336 or - _theResult___snd__h384359 or _theResult___sfd__h384881) - begin - case (guard__h376336) - 2'b0: - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q47 = - _theResult___snd__h384359[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q47 = - _theResult___sfd__h384881; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46 or - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q47 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h384359) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h384959 = - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q46; - 3'd1: - _theResult___fst_sfd__h384959 = - CASE_guard76336_0b0_theResult___snd84359_BITS__ETC__q47; - 3'd2: - _theResult___fst_sfd__h384959 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; - 3'd3: - _theResult___fst_sfd__h384959 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h384959 = _theResult___snd__h384359[56:34]; - default: _theResult___fst_sfd__h384959 = 23'd0; - endcase - end - always@(guard__h349861 or + always@(guard__h349683 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h349861) + case (guard__h349683) 2'b0, 2'b01, 2'b10: - CASE_guard49861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard49861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 = - guard__h349861 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard49861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 or - guard__h349861) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - CASE_guard49861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - (guard__h349861 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h349861 != 2'b01 && guard__h349861 != 2'b10 && - guard__h349861 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h349861 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h349861) - 2'b0, 2'b01, 2'b10: - CASE_guard49861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 = + CASE_guard49683_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard49861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 = - guard__h349861 == 2'b11 && + CASE_guard49683_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 = + guard__h349683 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard49861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 or - guard__h349861) + CASE_guard49683_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46 or + guard__h349683) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard49861_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49; + CASE_guard49683_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - (guard__h349861 == 2'b0) ? + (guard__h349683 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h349861 == 2'b01 || guard__h349861 == 2'b10 || - guard__h349861 == 2'b11) && + (guard__h349683 == 2'b01 || guard__h349683 == 2'b10 || + guard__h349683 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = @@ -31638,34 +31308,124 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h358570 or + always@(guard__h376158 or + _theResult___snd__h384181 or + out_sfd__h384706 or _theResult___sfd__h384703) + begin + case (guard__h376158) + 2'b0, 2'b01: + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47 = + _theResult___snd__h384181[56:34]; + 2'b10: + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47 = + out_sfd__h384706; + 2'b11: + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47 = + _theResult___sfd__h384703; + endcase + end + always@(guard__h376158 or + _theResult___snd__h384181 or _theResult___sfd__h384703) + begin + case (guard__h376158) + 2'b0: + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q48 = + _theResult___snd__h384181[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q48 = + _theResult___sfd__h384703; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47 or + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q48 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or + _theResult___snd__h384181) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h384781 = + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q47; + 3'd1: + _theResult___fst_sfd__h384781 = + CASE_guard76158_0b0_theResult___snd84181_BITS__ETC__q48; + 3'd2: + _theResult___fst_sfd__h384781 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; + 3'd3: + _theResult___fst_sfd__h384781 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; + 3'd4: _theResult___fst_sfd__h384781 = _theResult___snd__h384181[56:34]; + default: _theResult___fst_sfd__h384781 = 23'd0; + endcase + end + always@(guard__h349683 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h358570) + case (guard__h349683) 2'b0, 2'b01, 2'b10: - CASE_guard58570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + CASE_guard49683_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard49683_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h349683 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard49683_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h349683) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = + CASE_guard49683_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = + (guard__h349683 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + guard__h349683 != 2'b01 && guard__h349683 != 2'b10 && + guard__h349683 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h358392 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h358392) + 2'b0, 2'b01, 2'b10: + CASE_guard58392_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard58570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = - guard__h358570 == 2'b11 && + CASE_guard58392_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + guard__h358392 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard58570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or - guard__h358570) + CASE_guard58392_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or + guard__h358392) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - CASE_guard58570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; + CASE_guard58392_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - (guard__h358570 == 2'b0) ? + (guard__h358392 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h358570 == 2'b01 || guard__h358570 == 2'b10 || - guard__h358570 == 2'b11) && + (guard__h358392 == 2'b01 || guard__h358392 == 2'b10 || + guard__h358392 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = @@ -31676,34 +31436,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h358570 or + always@(guard__h358392 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h358570) + case (guard__h358392) 2'b0, 2'b01, 2'b10: - CASE_guard58570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + CASE_guard58392_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard58570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = - guard__h358570 != 2'b11 || + CASE_guard58392_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + guard__h358392 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard58570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or - guard__h358570) + CASE_guard58392_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or + guard__h358392) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - CASE_guard58570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; + CASE_guard58392_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - (guard__h358570 == 2'b0) ? + (guard__h358392 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h358570 != 2'b01 && guard__h358570 != 2'b10 && - guard__h358570 != 2'b11 || + guard__h358392 != 2'b01 && guard__h358392 != 2'b10 && + guard__h358392 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = @@ -31714,34 +31474,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h367500 or + always@(guard__h367322 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h367500) + case (guard__h367322) 2'b0, 2'b01, 2'b10: - CASE_guard67500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard67322_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard67500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h367500 == 2'b11 && + CASE_guard67322_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h367322 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard67500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h367500) + CASE_guard67322_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h367322) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - CASE_guard67500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard67322_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - (guard__h367500 == 2'b0) ? + (guard__h367322 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h367500 == 2'b01 || guard__h367500 == 2'b10 || - guard__h367500 == 2'b11) && + (guard__h367322 == 2'b01 || guard__h367322 == 2'b10 || + guard__h367322 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = @@ -31752,34 +31512,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h367500 or + always@(guard__h367322 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h367500) + case (guard__h367322) 2'b0, 2'b01, 2'b10: - CASE_guard67500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard67322_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard67500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h367500 != 2'b11 || + CASE_guard67322_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h367322 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard67500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h367500) + CASE_guard67322_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h367322) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard67500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard67322_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - (guard__h367500 == 2'b0) ? + (guard__h367322 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h367500 != 2'b01 && guard__h367500 != 2'b10 && - guard__h367500 != 2'b11 || + guard__h367322 != 2'b01 && guard__h367322 != 2'b10 && + guard__h367322 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = @@ -31790,34 +31550,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376336 or + always@(guard__h376158 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376336) + case (guard__h376158) 2'b0, 2'b01, 2'b10: - CASE_guard76336_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + CASE_guard76158_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76336_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = - guard__h376336 == 2'b11 && + CASE_guard76158_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h376158 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76336_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or - guard__h376336) + CASE_guard76158_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h376158) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard76336_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + CASE_guard76158_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h376336 == 2'b0) ? + (guard__h376158 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h376336 == 2'b01 || guard__h376336 == 2'b10 || - guard__h376336 == 2'b11) && + (guard__h376158 == 2'b01 || guard__h376158 == 2'b10 || + guard__h376158 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = @@ -31828,34 +31588,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376336 or + always@(guard__h376158 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376336) + case (guard__h376158) 2'b0, 2'b01, 2'b10: - CASE_guard76336_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + CASE_guard76158_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76336_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = - guard__h376336 != 2'b11 || + CASE_guard76158_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + guard__h376158 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76336_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or - guard__h376336) + CASE_guard76158_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or + guard__h376158) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - CASE_guard76336_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; + CASE_guard76158_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - (guard__h376336 == 2'b0) ? + (guard__h376158 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h376336 != 2'b01 && guard__h376336 != 2'b10 && - guard__h376336 != 2'b11 || + guard__h376158 != 2'b01 && guard__h376158 != 2'b10 && + guard__h376158 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = @@ -31866,19 +31626,6 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31892,446 +31639,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h404267 or - _theResult___fst_exp__h412315 or - out_exp__h412760 or _theResult___exp__h412757) + always@(guard__h404089 or + _theResult___fst_exp__h412137 or + out_exp__h412582 or _theResult___exp__h412579) begin - case (guard__h404267) + case (guard__h404089) 2'b0, 2'b01: - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60 = - _theResult___fst_exp__h412315; + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60 = + _theResult___fst_exp__h412137; 2'b10: - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60 = - out_exp__h412760; + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60 = + out_exp__h412582; 2'b11: - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60 = - _theResult___exp__h412757; + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60 = + _theResult___exp__h412579; endcase end - always@(guard__h404267 or - _theResult___fst_exp__h412315 or _theResult___exp__h412757) + always@(guard__h404089 or + _theResult___fst_exp__h412137 or _theResult___exp__h412579) begin - case (guard__h404267) + case (guard__h404089) 2'b0: - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q61 = - _theResult___fst_exp__h412315; + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q61 = + _theResult___fst_exp__h412137; 2'b01, 2'b10, 2'b11: - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q61 = - _theResult___exp__h412757; + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q61 = + _theResult___exp__h412579; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60 or - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q61 or + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60 or + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or - _theResult___fst_exp__h412315) + _theResult___fst_exp__h412137) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h412835 = - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q60; + _theResult___fst_exp__h412657 = + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q60; 3'd1: - _theResult___fst_exp__h412835 = - CASE_guard04267_0b0_theResult___fst_exp12315_0_ETC__q61; + _theResult___fst_exp__h412657 = + CASE_guard04089_0b0_theResult___fst_exp12137_0_ETC__q61; 3'd2: - _theResult___fst_exp__h412835 = + _theResult___fst_exp__h412657 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020; 3'd3: - _theResult___fst_exp__h412835 = + _theResult___fst_exp__h412657 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022; - 3'd4: _theResult___fst_exp__h412835 = _theResult___fst_exp__h412315; - default: _theResult___fst_exp__h412835 = 8'd0; + 3'd4: _theResult___fst_exp__h412657 = _theResult___fst_exp__h412137; + default: _theResult___fst_exp__h412657 = 8'd0; endcase end - always@(guard__h395560 or - _theResult___fst_exp__h403659 or - out_exp__h404178 or _theResult___exp__h404175) + always@(guard__h395382 or + _theResult___fst_exp__h403481 or + out_exp__h404000 or _theResult___exp__h403997) begin - case (guard__h395560) + case (guard__h395382) 2'b0, 2'b01: - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62 = - _theResult___fst_exp__h403659; + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62 = + _theResult___fst_exp__h403481; 2'b10: - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62 = - out_exp__h404178; + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62 = + out_exp__h404000; 2'b11: - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62 = - _theResult___exp__h404175; + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62 = + _theResult___exp__h403997; endcase end - always@(guard__h395560 or - _theResult___fst_exp__h403659 or _theResult___exp__h404175) + always@(guard__h395382 or + _theResult___fst_exp__h403481 or _theResult___exp__h403997) begin - case (guard__h395560) + case (guard__h395382) 2'b0: - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q63 = - _theResult___fst_exp__h403659; + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q63 = + _theResult___fst_exp__h403481; 2'b01, 2'b10, 2'b11: - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q63 = - _theResult___exp__h404175; + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q63 = + _theResult___exp__h403997; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62 or - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q63 or + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62 or + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q63 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or - _theResult___fst_exp__h403659) + _theResult___fst_exp__h403481) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h404253 = - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q62; + _theResult___fst_exp__h404075 = + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q62; 3'd1: - _theResult___fst_exp__h404253 = - CASE_guard95560_0b0_theResult___fst_exp03659_0_ETC__q63; + _theResult___fst_exp__h404075 = + CASE_guard95382_0b0_theResult___fst_exp03481_0_ETC__q63; 3'd2: - _theResult___fst_exp__h404253 = + _theResult___fst_exp__h404075 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798; 3'd3: - _theResult___fst_exp__h404253 = + _theResult___fst_exp__h404075 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801; - 3'd4: _theResult___fst_exp__h404253 = _theResult___fst_exp__h403659; - default: _theResult___fst_exp__h404253 = 8'd0; + 3'd4: _theResult___fst_exp__h404075 = _theResult___fst_exp__h403481; + default: _theResult___fst_exp__h404075 = 8'd0; endcase end - always@(guard__h413197 or - _theResult___fst_exp__h421425 or - out_exp__h421944 or _theResult___exp__h421941) + always@(guard__h413019 or + _theResult___fst_exp__h421247 or + out_exp__h421766 or _theResult___exp__h421763) begin - case (guard__h413197) + case (guard__h413019) 2'b0, 2'b01: - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68 = - _theResult___fst_exp__h421425; + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68 = + _theResult___fst_exp__h421247; 2'b10: - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68 = - out_exp__h421944; + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68 = + out_exp__h421766; 2'b11: - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68 = - _theResult___exp__h421941; + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68 = + _theResult___exp__h421763; endcase end - always@(guard__h413197 or - _theResult___fst_exp__h421425 or _theResult___exp__h421941) + always@(guard__h413019 or + _theResult___fst_exp__h421247 or _theResult___exp__h421763) begin - case (guard__h413197) + case (guard__h413019) 2'b0: - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q69 = - _theResult___fst_exp__h421425; + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q69 = + _theResult___fst_exp__h421247; 2'b01, 2'b10, 2'b11: - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q69 = - _theResult___exp__h421941; + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q69 = + _theResult___exp__h421763; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68 or - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q69 or + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68 or + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q69 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or - _theResult___fst_exp__h421425) + _theResult___fst_exp__h421247) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h422019 = - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q68; + _theResult___fst_exp__h421841 = + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q68; 3'd1: - _theResult___fst_exp__h422019 = - CASE_guard13197_0b0_theResult___fst_exp21425_0_ETC__q69; + _theResult___fst_exp__h421841 = + CASE_guard13019_0b0_theResult___fst_exp21247_0_ETC__q69; 3'd2: - _theResult___fst_exp__h422019 = + _theResult___fst_exp__h421841 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345; 3'd3: - _theResult___fst_exp__h422019 = + _theResult___fst_exp__h421841 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347; - 3'd4: _theResult___fst_exp__h422019 = _theResult___fst_exp__h421425; - default: _theResult___fst_exp__h422019 = 8'd0; + 3'd4: _theResult___fst_exp__h421841 = _theResult___fst_exp__h421247; + default: _theResult___fst_exp__h421841 = 8'd0; endcase end - always@(guard__h422033 or - _theResult___fst_exp__h430110 or - out_exp__h430580 or _theResult___exp__h430577) + always@(guard__h421855 or + _theResult___fst_exp__h429932 or + out_exp__h430402 or _theResult___exp__h430399) begin - case (guard__h422033) + case (guard__h421855) 2'b0, 2'b01: - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73 = - _theResult___fst_exp__h430110; + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73 = + _theResult___fst_exp__h429932; 2'b10: - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73 = - out_exp__h430580; + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73 = + out_exp__h430402; 2'b11: - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73 = - _theResult___exp__h430577; + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73 = + _theResult___exp__h430399; endcase end - always@(guard__h422033 or - _theResult___fst_exp__h430110 or _theResult___exp__h430577) + always@(guard__h421855 or + _theResult___fst_exp__h429932 or _theResult___exp__h430399) begin - case (guard__h422033) + case (guard__h421855) 2'b0: - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q74 = - _theResult___fst_exp__h430110; + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q74 = + _theResult___fst_exp__h429932; 2'b01, 2'b10, 2'b11: - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q74 = - _theResult___exp__h430577; + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q74 = + _theResult___exp__h430399; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73 or - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q74 or + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73 or + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q74 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___fst_exp__h430110) + _theResult___fst_exp__h429932) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h430655 = - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q73; + _theResult___fst_exp__h430477 = + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q73; 3'd1: - _theResult___fst_exp__h430655 = - CASE_guard22033_0b0_theResult___fst_exp30110_0_ETC__q74; + _theResult___fst_exp__h430477 = + CASE_guard21855_0b0_theResult___fst_exp29932_0_ETC__q74; 3'd2: - _theResult___fst_exp__h430655 = + _theResult___fst_exp__h430477 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_exp__h430655 = + _theResult___fst_exp__h430477 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_exp__h430655 = _theResult___fst_exp__h430110; - default: _theResult___fst_exp__h430655 = 8'd0; + 3'd4: _theResult___fst_exp__h430477 = _theResult___fst_exp__h429932; + default: _theResult___fst_exp__h430477 = 8'd0; endcase end - always@(guard__h395560 or - sfdin__h403653 or out_sfd__h404179 or _theResult___sfd__h404176) + always@(guard__h395382 or + sfdin__h403475 or out_sfd__h404001 or _theResult___sfd__h403998) begin - case (guard__h395560) + case (guard__h395382) 2'b0, 2'b01: - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75 = - sfdin__h403653[56:34]; + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75 = + sfdin__h403475[56:34]; 2'b10: - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75 = - out_sfd__h404179; + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75 = + out_sfd__h404001; 2'b11: - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75 = - _theResult___sfd__h404176; + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75 = + _theResult___sfd__h403998; endcase end - always@(guard__h395560 or sfdin__h403653 or _theResult___sfd__h404176) + always@(guard__h395382 or sfdin__h403475 or _theResult___sfd__h403998) begin - case (guard__h395560) + case (guard__h395382) 2'b0: - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q76 = - sfdin__h403653[56:34]; + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q76 = + sfdin__h403475[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h404176; + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h403998; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75 or - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q76 or + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75 or + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q76 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h403653) + sfdin__h403475) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h404254 = - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q75; + _theResult___fst_sfd__h404076 = + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q75; 3'd1: - _theResult___fst_sfd__h404254 = - CASE_guard95560_0b0_sfdin03653_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h404076 = + CASE_guard95382_0b0_sfdin03475_BITS_56_TO_34_0_ETC__q76; 3'd2: - _theResult___fst_sfd__h404254 = + _theResult___fst_sfd__h404076 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; 3'd3: - _theResult___fst_sfd__h404254 = + _theResult___fst_sfd__h404076 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h404254 = sfdin__h403653[56:34]; - default: _theResult___fst_sfd__h404254 = 23'd0; + 3'd4: _theResult___fst_sfd__h404076 = sfdin__h403475[56:34]; + default: _theResult___fst_sfd__h404076 = 23'd0; endcase end - always@(guard__h404267 or - _theResult___snd__h412266 or - out_sfd__h412761 or _theResult___sfd__h412758) + always@(guard__h404089 or + _theResult___snd__h412088 or + out_sfd__h412583 or _theResult___sfd__h412580) begin - case (guard__h404267) + case (guard__h404089) 2'b0, 2'b01: - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77 = - _theResult___snd__h412266[56:34]; + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77 = + _theResult___snd__h412088[56:34]; 2'b10: - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77 = - out_sfd__h412761; + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77 = + out_sfd__h412583; 2'b11: - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77 = - _theResult___sfd__h412758; + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77 = + _theResult___sfd__h412580; endcase end - always@(guard__h404267 or - _theResult___snd__h412266 or _theResult___sfd__h412758) + always@(guard__h404089 or + _theResult___snd__h412088 or _theResult___sfd__h412580) begin - case (guard__h404267) + case (guard__h404089) 2'b0: - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q78 = - _theResult___snd__h412266[56:34]; + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q78 = + _theResult___snd__h412088[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q78 = - _theResult___sfd__h412758; + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q78 = + _theResult___sfd__h412580; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77 or - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q78 or + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77 or + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q78 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or - _theResult___snd__h412266) + _theResult___snd__h412088) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h412836 = - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q77; + _theResult___fst_sfd__h412658 = + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q77; 3'd1: - _theResult___fst_sfd__h412836 = - CASE_guard04267_0b0_theResult___snd12266_BITS__ETC__q78; + _theResult___fst_sfd__h412658 = + CASE_guard04089_0b0_theResult___snd12088_BITS__ETC__q78; 3'd2: - _theResult___fst_sfd__h412836 = + _theResult___fst_sfd__h412658 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; 3'd3: - _theResult___fst_sfd__h412836 = + _theResult___fst_sfd__h412658 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; - 3'd4: _theResult___fst_sfd__h412836 = _theResult___snd__h412266[56:34]; - default: _theResult___fst_sfd__h412836 = 23'd0; + 3'd4: _theResult___fst_sfd__h412658 = _theResult___snd__h412088[56:34]; + default: _theResult___fst_sfd__h412658 = 23'd0; endcase end - always@(guard__h413197 or - sfdin__h421419 or out_sfd__h421945 or _theResult___sfd__h421942) + always@(guard__h413019 or + sfdin__h421241 or out_sfd__h421767 or _theResult___sfd__h421764) begin - case (guard__h413197) + case (guard__h413019) 2'b0, 2'b01: - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79 = - sfdin__h421419[56:34]; + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79 = + sfdin__h421241[56:34]; 2'b10: - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79 = - out_sfd__h421945; + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79 = + out_sfd__h421767; 2'b11: - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h421942; + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h421764; endcase end - always@(guard__h413197 or sfdin__h421419 or _theResult___sfd__h421942) + always@(guard__h413019 or sfdin__h421241 or _theResult___sfd__h421764) begin - case (guard__h413197) + case (guard__h413019) 2'b0: - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q80 = - sfdin__h421419[56:34]; + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q80 = + sfdin__h421241[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q80 = - _theResult___sfd__h421942; + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q80 = + _theResult___sfd__h421764; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79 or - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q80 or + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79 or + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q80 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or - sfdin__h421419) + sfdin__h421241) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h422020 = - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h421842 = + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q79; 3'd1: - _theResult___fst_sfd__h422020 = - CASE_guard13197_0b0_sfdin21419_BITS_56_TO_34_0_ETC__q80; + _theResult___fst_sfd__h421842 = + CASE_guard13019_0b0_sfdin21241_BITS_56_TO_34_0_ETC__q80; 3'd2: - _theResult___fst_sfd__h422020 = + _theResult___fst_sfd__h421842 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491; 3'd3: - _theResult___fst_sfd__h422020 = + _theResult___fst_sfd__h421842 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493; - 3'd4: _theResult___fst_sfd__h422020 = sfdin__h421419[56:34]; - default: _theResult___fst_sfd__h422020 = 23'd0; + 3'd4: _theResult___fst_sfd__h421842 = sfdin__h421241[56:34]; + default: _theResult___fst_sfd__h421842 = 23'd0; endcase end - always@(guard__h422033 or - _theResult___snd__h430056 or - out_sfd__h430581 or _theResult___sfd__h430578) + always@(guard__h421855 or + _theResult___snd__h429878 or + out_sfd__h430403 or _theResult___sfd__h430400) begin - case (guard__h422033) + case (guard__h421855) 2'b0, 2'b01: - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81 = - _theResult___snd__h430056[56:34]; + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81 = + _theResult___snd__h429878[56:34]; 2'b10: - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81 = - out_sfd__h430581; + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81 = + out_sfd__h430403; 2'b11: - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81 = - _theResult___sfd__h430578; + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81 = + _theResult___sfd__h430400; endcase end - always@(guard__h422033 or - _theResult___snd__h430056 or _theResult___sfd__h430578) + always@(guard__h421855 or + _theResult___snd__h429878 or _theResult___sfd__h430400) begin - case (guard__h422033) + case (guard__h421855) 2'b0: - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q82 = - _theResult___snd__h430056[56:34]; + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q82 = + _theResult___snd__h429878[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q82 = - _theResult___sfd__h430578; + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q82 = + _theResult___sfd__h430400; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81 or - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q82 or + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81 or + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or - _theResult___snd__h430056) + _theResult___snd__h429878) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h430656 = - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q81; + _theResult___fst_sfd__h430478 = + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q81; 3'd1: - _theResult___fst_sfd__h430656 = - CASE_guard22033_0b0_theResult___snd30056_BITS__ETC__q82; + _theResult___fst_sfd__h430478 = + CASE_guard21855_0b0_theResult___snd29878_BITS__ETC__q82; 3'd2: - _theResult___fst_sfd__h430656 = + _theResult___fst_sfd__h430478 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510; 3'd3: - _theResult___fst_sfd__h430656 = + _theResult___fst_sfd__h430478 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512; - 3'd4: _theResult___fst_sfd__h430656 = _theResult___snd__h430056[56:34]; - default: _theResult___fst_sfd__h430656 = 23'd0; + 3'd4: _theResult___fst_sfd__h430478 = _theResult___snd__h429878[56:34]; + default: _theResult___fst_sfd__h430478 = 23'd0; endcase end - always@(guard__h395560 or + always@(guard__h395382 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h395560) + case (guard__h395382) 2'b0, 2'b01, 2'b10: - CASE_guard95560_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + CASE_guard95382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard95560_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = - guard__h395560 == 2'b11 && + CASE_guard95382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + guard__h395382 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard95560_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or - guard__h395560) + CASE_guard95382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or + guard__h395382) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - CASE_guard95560_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; + CASE_guard95382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - (guard__h395560 == 2'b0) ? + (guard__h395382 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h395560 == 2'b01 || guard__h395560 == 2'b10 || - guard__h395560 == 2'b11) && + (guard__h395382 == 2'b01 || guard__h395382 == 2'b10 || + guard__h395382 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = @@ -32342,72 +32089,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404267 or + always@(guard__h395382 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404267) + case (guard__h395382) 2'b0, 2'b01, 2'b10: - CASE_guard04267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard04267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h404267 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h404267) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - CASE_guard04267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - (guard__h404267 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h404267 == 2'b01 || guard__h404267 == 2'b10 || - guard__h404267 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h395560 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h395560) - 2'b0, 2'b01, 2'b10: - CASE_guard95560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard95382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard95560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h395560 != 2'b11 || + CASE_guard95382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + guard__h395382 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard95560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h395560) + CASE_guard95382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or + guard__h395382) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - CASE_guard95560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + CASE_guard95382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - (guard__h395560 == 2'b0) ? + (guard__h395382 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h395560 != 2'b01 && guard__h395560 != 2'b10 && - guard__h395560 != 2'b11 || + guard__h395382 != 2'b01 && guard__h395382 != 2'b10 && + guard__h395382 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = @@ -32418,34 +32127,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404267 or + always@(guard__h404089 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404267) + case (guard__h404089) 2'b0, 2'b01, 2'b10: - CASE_guard04267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + CASE_guard04089_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard04089_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + guard__h404089 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard04089_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or + guard__h404089) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = + CASE_guard04089_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = + (guard__h404089 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + (guard__h404089 == 2'b01 || guard__h404089 == 2'b10 || + guard__h404089 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h404089 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h404089) + 2'b0, 2'b01, 2'b10: + CASE_guard04089_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard04267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = - guard__h404267 != 2'b11 || + CASE_guard04089_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + guard__h404089 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or - guard__h404267) + CASE_guard04089_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or + guard__h404089) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - CASE_guard04267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; + CASE_guard04089_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - (guard__h404267 == 2'b0) ? + (guard__h404089 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h404267 != 2'b01 && guard__h404267 != 2'b10 && - guard__h404267 != 2'b11 || + guard__h404089 != 2'b01 && guard__h404089 != 2'b10 && + guard__h404089 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = @@ -32456,34 +32203,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413197 or + always@(guard__h413019 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413197) + case (guard__h413019) 2'b0, 2'b01, 2'b10: - CASE_guard13197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + CASE_guard13019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard13197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = - guard__h413197 == 2'b11 && + CASE_guard13019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + guard__h413019 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or - guard__h413197) + CASE_guard13019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or + guard__h413019) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - CASE_guard13197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; + CASE_guard13019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - (guard__h413197 == 2'b0) ? + (guard__h413019 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h413197 == 2'b01 || guard__h413197 == 2'b10 || - guard__h413197 == 2'b11) && + (guard__h413019 == 2'b01 || guard__h413019 == 2'b10 || + guard__h413019 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = @@ -32494,72 +32241,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413197 or + always@(guard__h421855 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413197) + case (guard__h421855) 2'b0, 2'b01, 2'b10: - CASE_guard13197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard13197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = - guard__h413197 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or - guard__h413197) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - CASE_guard13197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - (guard__h413197 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h413197 != 2'b01 && guard__h413197 != 2'b10 && - guard__h413197 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h422033 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h422033) - 2'b0, 2'b01, 2'b10: - CASE_guard22033_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + CASE_guard21855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22033_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = - guard__h422033 == 2'b11 && + CASE_guard21855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + guard__h421855 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22033_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or - guard__h422033) + CASE_guard21855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + guard__h421855) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - CASE_guard22033_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; + CASE_guard21855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - (guard__h422033 == 2'b0) ? + (guard__h421855 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h422033 == 2'b01 || guard__h422033 == 2'b10 || - guard__h422033 == 2'b11) && + (guard__h421855 == 2'b01 || guard__h421855 == 2'b10 || + guard__h421855 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = @@ -32570,34 +32279,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422033 or + always@(guard__h413019 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422033) + case (guard__h413019) 2'b0, 2'b01, 2'b10: - CASE_guard22033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + CASE_guard13019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = - guard__h422033 != 2'b11 || + CASE_guard13019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + guard__h413019 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or - guard__h422033) + CASE_guard13019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or + guard__h413019) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = + CASE_guard13019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = + (guard__h413019 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h413019 != 2'b01 && guard__h413019 != 2'b10 && + guard__h413019 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h421855 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h421855) + 2'b0, 2'b01, 2'b10: + CASE_guard21855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard21855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + guard__h421855 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard21855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or + guard__h421855) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - CASE_guard22033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; + CASE_guard21855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - (guard__h422033 == 2'b0) ? + (guard__h421855 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h422033 != 2'b01 && guard__h422033 != 2'b10 && - guard__h422033 != 2'b11 || + guard__h421855 != 2'b01 && guard__h421855 != 2'b10 && + guard__h421855 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = @@ -32634,446 +32381,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h449962 or - _theResult___fst_exp__h458010 or - out_exp__h458455 or _theResult___exp__h458452) + always@(guard__h449784 or + _theResult___fst_exp__h457832 or + out_exp__h458277 or _theResult___exp__h458274) begin - case (guard__h449962) + case (guard__h449784) 2'b0, 2'b01: - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95 = - _theResult___fst_exp__h458010; + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95 = + _theResult___fst_exp__h457832; 2'b10: - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95 = - out_exp__h458455; + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95 = + out_exp__h458277; 2'b11: - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95 = - _theResult___exp__h458452; + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95 = + _theResult___exp__h458274; endcase end - always@(guard__h449962 or - _theResult___fst_exp__h458010 or _theResult___exp__h458452) + always@(guard__h449784 or + _theResult___fst_exp__h457832 or _theResult___exp__h458274) begin - case (guard__h449962) + case (guard__h449784) 2'b0: - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q96 = - _theResult___fst_exp__h458010; + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q96 = + _theResult___fst_exp__h457832; 2'b01, 2'b10, 2'b11: - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q96 = - _theResult___exp__h458452; + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q96 = + _theResult___exp__h458274; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95 or - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q96 or + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95 or + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q96 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or - _theResult___fst_exp__h458010) + _theResult___fst_exp__h457832) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h458530 = - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q95; + _theResult___fst_exp__h458352 = + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q95; 3'd1: - _theResult___fst_exp__h458530 = - CASE_guard49962_0b0_theResult___fst_exp58010_0_ETC__q96; + _theResult___fst_exp__h458352 = + CASE_guard49784_0b0_theResult___fst_exp57832_0_ETC__q96; 3'd2: - _theResult___fst_exp__h458530 = + _theResult___fst_exp__h458352 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412; 3'd3: - _theResult___fst_exp__h458530 = + _theResult___fst_exp__h458352 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414; - 3'd4: _theResult___fst_exp__h458530 = _theResult___fst_exp__h458010; - default: _theResult___fst_exp__h458530 = 8'd0; + 3'd4: _theResult___fst_exp__h458352 = _theResult___fst_exp__h457832; + default: _theResult___fst_exp__h458352 = 8'd0; endcase end - always@(guard__h441255 or - _theResult___fst_exp__h449354 or - out_exp__h449873 or _theResult___exp__h449870) + always@(guard__h441077 or + _theResult___fst_exp__h449176 or + out_exp__h449695 or _theResult___exp__h449692) begin - case (guard__h441255) + case (guard__h441077) 2'b0, 2'b01: - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97 = - _theResult___fst_exp__h449354; + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97 = + _theResult___fst_exp__h449176; 2'b10: - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97 = - out_exp__h449873; + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97 = + out_exp__h449695; 2'b11: - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97 = - _theResult___exp__h449870; + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97 = + _theResult___exp__h449692; endcase end - always@(guard__h441255 or - _theResult___fst_exp__h449354 or _theResult___exp__h449870) + always@(guard__h441077 or + _theResult___fst_exp__h449176 or _theResult___exp__h449692) begin - case (guard__h441255) + case (guard__h441077) 2'b0: - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q98 = - _theResult___fst_exp__h449354; + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q98 = + _theResult___fst_exp__h449176; 2'b01, 2'b10, 2'b11: - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q98 = - _theResult___exp__h449870; + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q98 = + _theResult___exp__h449692; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97 or - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q98 or + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97 or + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q98 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or - _theResult___fst_exp__h449354) + _theResult___fst_exp__h449176) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h449948 = - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q97; + _theResult___fst_exp__h449770 = + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q97; 3'd1: - _theResult___fst_exp__h449948 = - CASE_guard41255_0b0_theResult___fst_exp49354_0_ETC__q98; + _theResult___fst_exp__h449770 = + CASE_guard41077_0b0_theResult___fst_exp49176_0_ETC__q98; 3'd2: - _theResult___fst_exp__h449948 = + _theResult___fst_exp__h449770 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190; 3'd3: - _theResult___fst_exp__h449948 = + _theResult___fst_exp__h449770 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193; - 3'd4: _theResult___fst_exp__h449948 = _theResult___fst_exp__h449354; - default: _theResult___fst_exp__h449948 = 8'd0; + 3'd4: _theResult___fst_exp__h449770 = _theResult___fst_exp__h449176; + default: _theResult___fst_exp__h449770 = 8'd0; endcase end - always@(guard__h458892 or - _theResult___fst_exp__h467120 or - out_exp__h467639 or _theResult___exp__h467636) + always@(guard__h458714 or + _theResult___fst_exp__h466942 or + out_exp__h467461 or _theResult___exp__h467458) begin - case (guard__h458892) + case (guard__h458714) 2'b0, 2'b01: - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103 = - _theResult___fst_exp__h467120; + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103 = + _theResult___fst_exp__h466942; 2'b10: - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103 = - out_exp__h467639; + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103 = + out_exp__h467461; 2'b11: - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103 = - _theResult___exp__h467636; + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103 = + _theResult___exp__h467458; endcase end - always@(guard__h458892 or - _theResult___fst_exp__h467120 or _theResult___exp__h467636) + always@(guard__h458714 or + _theResult___fst_exp__h466942 or _theResult___exp__h467458) begin - case (guard__h458892) + case (guard__h458714) 2'b0: - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q104 = - _theResult___fst_exp__h467120; + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q104 = + _theResult___fst_exp__h466942; 2'b01, 2'b10, 2'b11: - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q104 = - _theResult___exp__h467636; + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q104 = + _theResult___exp__h467458; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103 or - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q104 or + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103 or + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q104 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or - _theResult___fst_exp__h467120) + _theResult___fst_exp__h466942) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h467714 = - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q103; + _theResult___fst_exp__h467536 = + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q103; 3'd1: - _theResult___fst_exp__h467714 = - CASE_guard58892_0b0_theResult___fst_exp67120_0_ETC__q104; + _theResult___fst_exp__h467536 = + CASE_guard58714_0b0_theResult___fst_exp66942_0_ETC__q104; 3'd2: - _theResult___fst_exp__h467714 = + _theResult___fst_exp__h467536 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737; 3'd3: - _theResult___fst_exp__h467714 = + _theResult___fst_exp__h467536 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739; - 3'd4: _theResult___fst_exp__h467714 = _theResult___fst_exp__h467120; - default: _theResult___fst_exp__h467714 = 8'd0; + 3'd4: _theResult___fst_exp__h467536 = _theResult___fst_exp__h466942; + default: _theResult___fst_exp__h467536 = 8'd0; endcase end - always@(guard__h467728 or - _theResult___fst_exp__h475805 or - out_exp__h476275 or _theResult___exp__h476272) + always@(guard__h467550 or + _theResult___fst_exp__h475627 or + out_exp__h476097 or _theResult___exp__h476094) begin - case (guard__h467728) + case (guard__h467550) 2'b0, 2'b01: - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108 = - _theResult___fst_exp__h475805; + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108 = + _theResult___fst_exp__h475627; 2'b10: - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108 = - out_exp__h476275; + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108 = + out_exp__h476097; 2'b11: - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108 = - _theResult___exp__h476272; + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108 = + _theResult___exp__h476094; endcase end - always@(guard__h467728 or - _theResult___fst_exp__h475805 or _theResult___exp__h476272) + always@(guard__h467550 or + _theResult___fst_exp__h475627 or _theResult___exp__h476094) begin - case (guard__h467728) + case (guard__h467550) 2'b0: - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q109 = - _theResult___fst_exp__h475805; + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q109 = + _theResult___fst_exp__h475627; 2'b01, 2'b10, 2'b11: - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q109 = - _theResult___exp__h476272; + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q109 = + _theResult___exp__h476094; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108 or - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q109 or + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108 or + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q109 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___fst_exp__h475805) + _theResult___fst_exp__h475627) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h476350 = - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q108; + _theResult___fst_exp__h476172 = + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q108; 3'd1: - _theResult___fst_exp__h476350 = - CASE_guard67728_0b0_theResult___fst_exp75805_0_ETC__q109; + _theResult___fst_exp__h476172 = + CASE_guard67550_0b0_theResult___fst_exp75627_0_ETC__q109; 3'd2: - _theResult___fst_exp__h476350 = + _theResult___fst_exp__h476172 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_exp__h476350 = + _theResult___fst_exp__h476172 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_exp__h476350 = _theResult___fst_exp__h475805; - default: _theResult___fst_exp__h476350 = 8'd0; + 3'd4: _theResult___fst_exp__h476172 = _theResult___fst_exp__h475627; + default: _theResult___fst_exp__h476172 = 8'd0; endcase end - always@(guard__h449962 or - _theResult___snd__h457961 or - out_sfd__h458456 or _theResult___sfd__h458453) + always@(guard__h449784 or + _theResult___snd__h457783 or + out_sfd__h458278 or _theResult___sfd__h458275) begin - case (guard__h449962) + case (guard__h449784) 2'b0, 2'b01: - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110 = - _theResult___snd__h457961[56:34]; + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110 = + _theResult___snd__h457783[56:34]; 2'b10: - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110 = - out_sfd__h458456; + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110 = + out_sfd__h458278; 2'b11: - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110 = - _theResult___sfd__h458453; + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110 = + _theResult___sfd__h458275; endcase end - always@(guard__h449962 or - _theResult___snd__h457961 or _theResult___sfd__h458453) + always@(guard__h449784 or + _theResult___snd__h457783 or _theResult___sfd__h458275) begin - case (guard__h449962) + case (guard__h449784) 2'b0: - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q111 = - _theResult___snd__h457961[56:34]; + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q111 = + _theResult___snd__h457783[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q111 = - _theResult___sfd__h458453; + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q111 = + _theResult___sfd__h458275; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110 or - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q111 or + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110 or + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q111 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or - _theResult___snd__h457961) + _theResult___snd__h457783) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h458531 = - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q110; + _theResult___fst_sfd__h458353 = + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q110; 3'd1: - _theResult___fst_sfd__h458531 = - CASE_guard49962_0b0_theResult___snd57961_BITS__ETC__q111; + _theResult___fst_sfd__h458353 = + CASE_guard49784_0b0_theResult___snd57783_BITS__ETC__q111; 3'd2: - _theResult___fst_sfd__h458531 = + _theResult___fst_sfd__h458353 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856; 3'd3: - _theResult___fst_sfd__h458531 = + _theResult___fst_sfd__h458353 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858; - 3'd4: _theResult___fst_sfd__h458531 = _theResult___snd__h457961[56:34]; - default: _theResult___fst_sfd__h458531 = 23'd0; + 3'd4: _theResult___fst_sfd__h458353 = _theResult___snd__h457783[56:34]; + default: _theResult___fst_sfd__h458353 = 23'd0; endcase end - always@(guard__h441255 or - sfdin__h449348 or out_sfd__h449874 or _theResult___sfd__h449871) + always@(guard__h441077 or + sfdin__h449170 or out_sfd__h449696 or _theResult___sfd__h449693) begin - case (guard__h441255) + case (guard__h441077) 2'b0, 2'b01: - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112 = - sfdin__h449348[56:34]; + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112 = + sfdin__h449170[56:34]; 2'b10: - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112 = - out_sfd__h449874; + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112 = + out_sfd__h449696; 2'b11: - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h449871; + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h449693; endcase end - always@(guard__h441255 or sfdin__h449348 or _theResult___sfd__h449871) + always@(guard__h441077 or sfdin__h449170 or _theResult___sfd__h449693) begin - case (guard__h441255) + case (guard__h441077) 2'b0: - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q113 = - sfdin__h449348[56:34]; + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q113 = + sfdin__h449170[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h449871; + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h449693; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112 or - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q113 or + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112 or + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q113 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or - sfdin__h449348) + sfdin__h449170) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h449949 = - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h449771 = + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q112; 3'd1: - _theResult___fst_sfd__h449949 = - CASE_guard41255_0b0_sfdin49348_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h449771 = + CASE_guard41077_0b0_sfdin49170_BITS_56_TO_34_0_ETC__q113; 3'd2: - _theResult___fst_sfd__h449949 = + _theResult___fst_sfd__h449771 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837; 3'd3: - _theResult___fst_sfd__h449949 = + _theResult___fst_sfd__h449771 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839; - 3'd4: _theResult___fst_sfd__h449949 = sfdin__h449348[56:34]; - default: _theResult___fst_sfd__h449949 = 23'd0; + 3'd4: _theResult___fst_sfd__h449771 = sfdin__h449170[56:34]; + default: _theResult___fst_sfd__h449771 = 23'd0; endcase end - always@(guard__h458892 or - sfdin__h467114 or out_sfd__h467640 or _theResult___sfd__h467637) + always@(guard__h458714 or + sfdin__h466936 or out_sfd__h467462 or _theResult___sfd__h467459) begin - case (guard__h458892) + case (guard__h458714) 2'b0, 2'b01: - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114 = - sfdin__h467114[56:34]; + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114 = + sfdin__h466936[56:34]; 2'b10: - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114 = - out_sfd__h467640; + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114 = + out_sfd__h467462; 2'b11: - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h467637; + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h467459; endcase end - always@(guard__h458892 or sfdin__h467114 or _theResult___sfd__h467637) + always@(guard__h458714 or sfdin__h466936 or _theResult___sfd__h467459) begin - case (guard__h458892) + case (guard__h458714) 2'b0: - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q115 = - sfdin__h467114[56:34]; + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q115 = + sfdin__h466936[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q115 = - _theResult___sfd__h467637; + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q115 = + _theResult___sfd__h467459; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114 or - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q115 or + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114 or + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q115 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or - sfdin__h467114) + sfdin__h466936) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h467715 = - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h467537 = + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q114; 3'd1: - _theResult___fst_sfd__h467715 = - CASE_guard58892_0b0_sfdin67114_BITS_56_TO_34_0_ETC__q115; + _theResult___fst_sfd__h467537 = + CASE_guard58714_0b0_sfdin66936_BITS_56_TO_34_0_ETC__q115; 3'd2: - _theResult___fst_sfd__h467715 = + _theResult___fst_sfd__h467537 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883; 3'd3: - _theResult___fst_sfd__h467715 = + _theResult___fst_sfd__h467537 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885; - 3'd4: _theResult___fst_sfd__h467715 = sfdin__h467114[56:34]; - default: _theResult___fst_sfd__h467715 = 23'd0; + 3'd4: _theResult___fst_sfd__h467537 = sfdin__h466936[56:34]; + default: _theResult___fst_sfd__h467537 = 23'd0; endcase end - always@(guard__h467728 or - _theResult___snd__h475751 or - out_sfd__h476276 or _theResult___sfd__h476273) + always@(guard__h467550 or + _theResult___snd__h475573 or + out_sfd__h476098 or _theResult___sfd__h476095) begin - case (guard__h467728) + case (guard__h467550) 2'b0, 2'b01: - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116 = - _theResult___snd__h475751[56:34]; + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116 = + _theResult___snd__h475573[56:34]; 2'b10: - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116 = - out_sfd__h476276; + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116 = + out_sfd__h476098; 2'b11: - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116 = - _theResult___sfd__h476273; + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116 = + _theResult___sfd__h476095; endcase end - always@(guard__h467728 or - _theResult___snd__h475751 or _theResult___sfd__h476273) + always@(guard__h467550 or + _theResult___snd__h475573 or _theResult___sfd__h476095) begin - case (guard__h467728) + case (guard__h467550) 2'b0: - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q117 = - _theResult___snd__h475751[56:34]; + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q117 = + _theResult___snd__h475573[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q117 = - _theResult___sfd__h476273; + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q117 = + _theResult___sfd__h476095; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116 or - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q117 or + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116 or + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or - _theResult___snd__h475751) + _theResult___snd__h475573) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h476351 = - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q116; + _theResult___fst_sfd__h476173 = + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q116; 3'd1: - _theResult___fst_sfd__h476351 = - CASE_guard67728_0b0_theResult___snd75751_BITS__ETC__q117; + _theResult___fst_sfd__h476173 = + CASE_guard67550_0b0_theResult___snd75573_BITS__ETC__q117; 3'd2: - _theResult___fst_sfd__h476351 = + _theResult___fst_sfd__h476173 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; 3'd3: - _theResult___fst_sfd__h476351 = + _theResult___fst_sfd__h476173 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; - 3'd4: _theResult___fst_sfd__h476351 = _theResult___snd__h475751[56:34]; - default: _theResult___fst_sfd__h476351 = 23'd0; + 3'd4: _theResult___fst_sfd__h476173 = _theResult___snd__h475573[56:34]; + default: _theResult___fst_sfd__h476173 = 23'd0; endcase end - always@(guard__h441255 or + always@(guard__h441077 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441255) + case (guard__h441077) 2'b0, 2'b01, 2'b10: - CASE_guard41255_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard41077_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41255_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = - guard__h441255 == 2'b11 && + CASE_guard41077_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + guard__h441077 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41255_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or - guard__h441255) + CASE_guard41077_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + guard__h441077) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard41255_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; + CASE_guard41077_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - (guard__h441255 == 2'b0) ? + (guard__h441077 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h441255 == 2'b01 || guard__h441255 == 2'b10 || - guard__h441255 == 2'b11) && + (guard__h441077 == 2'b01 || guard__h441077 == 2'b10 || + guard__h441077 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = @@ -33084,72 +32831,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h441255 or + always@(guard__h449784 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441255) + case (guard__h449784) 2'b0, 2'b01, 2'b10: - CASE_guard41255_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard41255_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - guard__h441255 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41255_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 or - guard__h441255) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard41255_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h441255 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h441255 != 2'b01 && guard__h441255 != 2'b10 && - guard__h441255 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h449962 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h449962) - 2'b0, 2'b01, 2'b10: - CASE_guard49962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + CASE_guard49784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard49962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = - guard__h449962 == 2'b11 && + CASE_guard49784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h449784 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard49962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or - guard__h449962) + CASE_guard49784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h449784) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard49962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; + CASE_guard49784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - (guard__h449962 == 2'b0) ? + (guard__h449784 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h449962 == 2'b01 || guard__h449962 == 2'b10 || - guard__h449962 == 2'b11) && + (guard__h449784 == 2'b01 || guard__h449784 == 2'b10 || + guard__h449784 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = @@ -33160,34 +32869,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h449962 or + always@(guard__h441077 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h449962) + case (guard__h441077) 2'b0, 2'b01, 2'b10: - CASE_guard49962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + CASE_guard41077_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard49962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = - guard__h449962 != 2'b11 || + CASE_guard41077_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h441077 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard49962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or - guard__h449962) + CASE_guard41077_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h441077) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + CASE_guard41077_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + (guard__h441077 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h441077 != 2'b01 && guard__h441077 != 2'b10 && + guard__h441077 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h449784 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h449784) + 2'b0, 2'b01, 2'b10: + CASE_guard49784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard49784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + guard__h449784 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard49784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or + guard__h449784) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - CASE_guard49962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; + CASE_guard49784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - (guard__h449962 == 2'b0) ? + (guard__h449784 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h449962 != 2'b01 && guard__h449962 != 2'b10 && - guard__h449962 != 2'b11 || + guard__h449784 != 2'b01 && guard__h449784 != 2'b10 && + guard__h449784 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = @@ -33198,34 +32945,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h458892 or + always@(guard__h458714 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h458892) + case (guard__h458714) 2'b0, 2'b01, 2'b10: - CASE_guard58892_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + CASE_guard58714_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard58892_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = - guard__h458892 == 2'b11 && + CASE_guard58714_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + guard__h458714 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard58892_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or - guard__h458892) + CASE_guard58714_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or + guard__h458714) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - CASE_guard58892_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; + CASE_guard58714_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - (guard__h458892 == 2'b0) ? + (guard__h458714 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h458892 == 2'b01 || guard__h458892 == 2'b10 || - guard__h458892 == 2'b11) && + (guard__h458714 == 2'b01 || guard__h458714 == 2'b10 || + guard__h458714 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = @@ -33236,34 +32983,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h458892 or + always@(guard__h458714 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h458892) + case (guard__h458714) 2'b0, 2'b01, 2'b10: - CASE_guard58892_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + CASE_guard58714_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard58892_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = - guard__h458892 != 2'b11 || + CASE_guard58714_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + guard__h458714 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard58892_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or - guard__h458892) + CASE_guard58714_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or + guard__h458714) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard58892_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; + CASE_guard58714_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - (guard__h458892 == 2'b0) ? + (guard__h458714 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h458892 != 2'b01 && guard__h458892 != 2'b10 && - guard__h458892 != 2'b11 || + guard__h458714 != 2'b01 && guard__h458714 != 2'b10 && + guard__h458714 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = @@ -33274,34 +33021,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h467728 or + always@(guard__h467550 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h467728) + case (guard__h467550) 2'b0, 2'b01, 2'b10: - CASE_guard67728_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + CASE_guard67550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67728_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = - guard__h467728 == 2'b11 && + CASE_guard67550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h467550 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67728_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or - guard__h467728) + CASE_guard67550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h467550) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard67728_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + CASE_guard67550_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h467728 == 2'b0) ? + (guard__h467550 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h467728 == 2'b01 || guard__h467728 == 2'b10 || - guard__h467728 == 2'b11) && + (guard__h467550 == 2'b01 || guard__h467550 == 2'b10 || + guard__h467550 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = @@ -33312,34 +33059,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h467728 or + always@(guard__h467550 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h467728) + case (guard__h467550) 2'b0, 2'b01, 2'b10: - CASE_guard67728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + CASE_guard67550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = - guard__h467728 != 2'b11 || + CASE_guard67550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h467550 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or - guard__h467728) + CASE_guard67550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h467550) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - CASE_guard67728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; + CASE_guard67550_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - (guard__h467728 == 2'b0) ? + (guard__h467550 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h467728 != 2'b01 && guard__h467728 != 2'b10 && - guard__h467728 != 2'b11 || + guard__h467550 != 2'b01 && guard__h467550 != 2'b10 && + guard__h467550 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = @@ -33396,28 +33143,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h498069 or - _theResult___fst_exp__h506030 or _theResult___exp__h506685) + always@(guard__h497891 or + _theResult___fst_exp__h505852 or _theResult___exp__h506507) begin - case (guard__h498069) + case (guard__h497891) 2'b0: - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q135 = - _theResult___fst_exp__h506030; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q135 = + _theResult___fst_exp__h505852; 2'b01, 2'b10, 2'b11: - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q135 = - _theResult___exp__h506685; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q135 = + _theResult___exp__h506507; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h506030 or + _theResult___fst_exp__h505852 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 or - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q135) + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - _theResult___fst_exp__h506030; + _theResult___fst_exp__h505852; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126; @@ -33426,44 +33173,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q135; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = 11'd0; endcase end - always@(guard__h498069 or - _theResult___fst_exp__h506030 or - out_exp__h506688 or _theResult___exp__h506685) + always@(guard__h497891 or + _theResult___fst_exp__h505852 or + out_exp__h506510 or _theResult___exp__h506507) begin - case (guard__h498069) + case (guard__h497891) 2'b0, 2'b01: - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q136 = - _theResult___fst_exp__h506030; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q136 = + _theResult___fst_exp__h505852; 2'b10: - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q136 = - out_exp__h506688; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q136 = + out_exp__h506510; 2'b11: - CASE_guard98069_0b0_theResult___fst_exp06030_0_ETC__q136 = - _theResult___exp__h506685; + CASE_guard97891_0b0_theResult___fst_exp05852_0_ETC__q136 = + _theResult___exp__h506507; endcase end - always@(guard__h498069 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h497891 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h498069) + case (guard__h497891) 2'b0, 2'b01, 2'b10: - CASE_guard98069_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard97891_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98069_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h498069 == 2'b11 && + CASE_guard97891_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h497891 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498069) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h497891) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33473,12 +33220,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h498069 == 2'b0) ? + (guard__h497891 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h498069 == 2'b01 || guard__h498069 == 2'b10 || - guard__h498069 == 2'b11) && + (guard__h497891 == 2'b01 || guard__h497891 == 2'b10 || + guard__h497891 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33489,23 +33236,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h507381 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h507203 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h507381) + case (guard__h507203) 2'b0, 2'b01, 2'b10: - CASE_guard07381_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard07203_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard07381_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h507381 == 2'b11 && + CASE_guard07203_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h507203 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507381) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33515,12 +33262,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h507381 == 2'b0) ? + (guard__h507203 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h507381 == 2'b01 || guard__h507381 == 2'b10 || - guard__h507381 == 2'b11) && + (guard__h507203 == 2'b01 || guard__h507203 == 2'b10 || + guard__h507203 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33531,23 +33278,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h516450 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h516272 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h516450) + case (guard__h516272) 2'b0, 2'b01, 2'b10: - CASE_guard16450_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard16272_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard16450_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h516450 == 2'b11 && + CASE_guard16272_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h516272 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516450) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516272) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33557,12 +33304,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h516450 == 2'b0) ? + (guard__h516272 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h516450 == 2'b01 || guard__h516450 == 2'b10 || - guard__h516450 == 2'b11) && + (guard__h516272 == 2'b01 || guard__h516272 == 2'b10 || + guard__h516272 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33573,28 +33320,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h576226 or - _theResult___fst_exp__h584187 or _theResult___exp__h584842) + always@(guard__h576048 or + _theResult___fst_exp__h584009 or _theResult___exp__h584664) begin - case (guard__h576226) + case (guard__h576048) 2'b0: - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q152 = - _theResult___fst_exp__h584187; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q152 = + _theResult___fst_exp__h584009; 2'b01, 2'b10, 2'b11: - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q152 = - _theResult___exp__h584842; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q152 = + _theResult___exp__h584664; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h584187 or + _theResult___fst_exp__h584009 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 or - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q152) + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - _theResult___fst_exp__h584187; + _theResult___fst_exp__h584009; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841; @@ -33603,42 +33350,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q152; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = 11'd0; endcase end - always@(guard__h576226 or - _theResult___fst_exp__h584187 or - out_exp__h584845 or _theResult___exp__h584842) + always@(guard__h576048 or + _theResult___fst_exp__h584009 or + out_exp__h584667 or _theResult___exp__h584664) begin - case (guard__h576226) + case (guard__h576048) 2'b0, 2'b01: - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q153 = - _theResult___fst_exp__h584187; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q153 = + _theResult___fst_exp__h584009; 2'b10: - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q153 = - out_exp__h584845; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q153 = + out_exp__h584667; 2'b11: - CASE_guard76226_0b0_theResult___fst_exp84187_0_ETC__q153 = - _theResult___exp__h584842; + CASE_guard76048_0b0_theResult___fst_exp84009_0_ETC__q153 = + _theResult___exp__h584664; endcase end - always@(guard__h576226 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576048 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576226) + case (guard__h576048) 2'b0, 2'b01, 2'b10: - CASE_guard76226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard76048_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h576226 == 2'b11 && + CASE_guard76048_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h576048 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576226) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576048) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33647,12 +33394,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h576226 == 2'b0) ? + (guard__h576048 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h576226 == 2'b01 || guard__h576226 == 2'b10 || - guard__h576226 == 2'b11) && + (guard__h576048 == 2'b01 || guard__h576048 == 2'b10 || + guard__h576048 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33663,21 +33410,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h594607 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h594429 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h594607) + case (guard__h594429) 2'b0, 2'b01, 2'b10: - CASE_guard94607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard94429_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard94607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h594607 == 2'b11 && + CASE_guard94429_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h594429 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h594607) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h594429) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33686,12 +33433,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h594607 == 2'b0) ? + (guard__h594429 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h594607 == 2'b01 || guard__h594607 == 2'b10 || - guard__h594607 == 2'b11) && + (guard__h594429 == 2'b01 || guard__h594429 == 2'b10 || + guard__h594429 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33702,21 +33449,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585538 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585360 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585538) + case (guard__h585360) 2'b0, 2'b01, 2'b10: - CASE_guard85538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard85360_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h585538 == 2'b11 && + CASE_guard85360_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h585360 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585538) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585360) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33725,12 +33472,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h585538 == 2'b0) ? + (guard__h585360 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h585538 == 2'b01 || guard__h585538 == 2'b10 || - guard__h585538 == 2'b11) && + (guard__h585360 == 2'b01 || guard__h585360 == 2'b10 || + guard__h585360 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33741,21 +33488,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585538 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585360 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585538) + case (guard__h585360) 2'b0, 2'b01, 2'b10: - CASE_guard85538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard85360_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h585538 != 2'b11 || + CASE_guard85360_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h585360 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585538) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585360) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33764,12 +33511,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h585538 == 2'b0) ? + (guard__h585360 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h585538 != 2'b01 && guard__h585538 != 2'b10 && - guard__h585538 != 2'b11 || + guard__h585360 != 2'b01 && guard__h585360 != 2'b10 && + guard__h585360 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33780,21 +33527,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h594607 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h594429 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h594607) + case (guard__h594429) 2'b0, 2'b01, 2'b10: - CASE_guard94607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard94429_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard94607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h594607 != 2'b11 || + CASE_guard94429_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h594429 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h594607) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h594429) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33803,12 +33550,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h594607 == 2'b0) ? + (guard__h594429 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h594607 != 2'b01 && guard__h594607 != 2'b10 && - guard__h594607 != 2'b11 || + guard__h594429 != 2'b01 && guard__h594429 != 2'b10 && + guard__h594429 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33819,21 +33566,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h576226 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576048 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576226) + case (guard__h576048) 2'b0, 2'b01, 2'b10: - CASE_guard76226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard76048_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h576226 != 2'b11 || + CASE_guard76048_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h576048 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576226) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576048) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33842,12 +33589,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h576226 == 2'b0) ? + (guard__h576048 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h576226 != 2'b01 && guard__h576226 != 2'b10 && - guard__h576226 != 2'b11 || + guard__h576048 != 2'b01 && guard__h576048 != 2'b10 && + guard__h576048 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33858,28 +33605,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h536922 or - _theResult___fst_exp__h544883 or _theResult___exp__h545538) + always@(guard__h536744 or + _theResult___fst_exp__h544705 or _theResult___exp__h545360) begin - case (guard__h536922) + case (guard__h536744) 2'b0: - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q175 = - _theResult___fst_exp__h544883; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q175 = + _theResult___fst_exp__h544705; 2'b01, 2'b10, 2'b11: - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q175 = - _theResult___exp__h545538; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q175 = + _theResult___exp__h545360; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h544883 or + _theResult___fst_exp__h544705 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 or - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q175) + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - _theResult___fst_exp__h544883; + _theResult___fst_exp__h544705; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611; @@ -33888,100 +33635,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q175; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = 11'd0; endcase end - always@(guard__h536922 or - _theResult___fst_exp__h544883 or - out_exp__h545541 or _theResult___exp__h545538) + always@(guard__h536744 or + _theResult___fst_exp__h544705 or + out_exp__h545363 or _theResult___exp__h545360) begin - case (guard__h536922) + case (guard__h536744) 2'b0, 2'b01: - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q176 = - _theResult___fst_exp__h544883; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q176 = + _theResult___fst_exp__h544705; 2'b10: - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q176 = - out_exp__h545541; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q176 = + out_exp__h545363; 2'b11: - CASE_guard36922_0b0_theResult___fst_exp44883_0_ETC__q176 = - _theResult___exp__h545538; + CASE_guard36744_0b0_theResult___fst_exp44705_0_ETC__q176 = + _theResult___exp__h545360; endcase end - always@(guard__h555303 or - _theResult___fst_exp__h563293 or _theResult___exp__h563973) + always@(guard__h546056 or + _theResult___fst_exp__h554282 or _theResult___exp__h555011) begin - case (guard__h555303) + case (guard__h546056) 2'b0: - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q177 = - _theResult___fst_exp__h563293; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q177 = + _theResult___fst_exp__h554282; 2'b01, 2'b10, 2'b11: - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q177 = - _theResult___exp__h563973; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q177 = + _theResult___exp__h555011; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h563293 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q177) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - _theResult___fst_exp__h563293; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q177; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - 11'd0; - endcase - end - always@(guard__h555303 or - _theResult___fst_exp__h563293 or - out_exp__h563976 or _theResult___exp__h563973) - begin - case (guard__h555303) - 2'b0, 2'b01: - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q178 = - _theResult___fst_exp__h563293; - 2'b10: - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q178 = - out_exp__h563976; - 2'b11: - CASE_guard55303_0b0_theResult___fst_exp63293_0_ETC__q178 = - _theResult___exp__h563973; - endcase - end - always@(guard__h546234 or - _theResult___fst_exp__h554460 or _theResult___exp__h555189) - begin - case (guard__h546234) - 2'b0: - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q179 = - _theResult___fst_exp__h554460; - 2'b01, 2'b10, 2'b11: - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q179 = - _theResult___exp__h555189; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h554460 or + _theResult___fst_exp__h554282 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 or - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q179) + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - _theResult___fst_exp__h554460; + _theResult___fst_exp__h554282; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649; @@ -33990,49 +33686,100 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q179; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = 11'd0; endcase end - always@(guard__h546234 or - _theResult___fst_exp__h554460 or - out_exp__h555192 or _theResult___exp__h555189) + always@(guard__h546056 or + _theResult___fst_exp__h554282 or + out_exp__h555014 or _theResult___exp__h555011) begin - case (guard__h546234) + case (guard__h546056) 2'b0, 2'b01: - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q180 = - _theResult___fst_exp__h554460; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q178 = + _theResult___fst_exp__h554282; 2'b10: - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q180 = - out_exp__h555192; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q178 = + out_exp__h555014; 2'b11: - CASE_guard46234_0b0_theResult___fst_exp54460_0_ETC__q180 = - _theResult___exp__h555189; + CASE_guard46056_0b0_theResult___fst_exp54282_0_ETC__q178 = + _theResult___exp__h555011; endcase end - always@(guard__h585538 or - _theResult___fst_exp__h593764 or _theResult___exp__h594493) + always@(guard__h555125 or + _theResult___fst_exp__h563115 or _theResult___exp__h563795) begin - case (guard__h585538) + case (guard__h555125) 2'b0: - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q181 = - _theResult___fst_exp__h593764; + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q179 = + _theResult___fst_exp__h563115; 2'b01, 2'b10, 2'b11: - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q181 = - _theResult___exp__h594493; + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q179 = + _theResult___exp__h563795; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h593764 or + _theResult___fst_exp__h563115 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q179) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = + _theResult___fst_exp__h563115; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q179; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = + 11'd0; + endcase + end + always@(guard__h555125 or + _theResult___fst_exp__h563115 or + out_exp__h563798 or _theResult___exp__h563795) + begin + case (guard__h555125) + 2'b0, 2'b01: + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q180 = + _theResult___fst_exp__h563115; + 2'b10: + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q180 = + out_exp__h563798; + 2'b11: + CASE_guard55125_0b0_theResult___fst_exp63115_0_ETC__q180 = + _theResult___exp__h563795; + endcase + end + always@(guard__h585360 or + _theResult___fst_exp__h593586 or _theResult___exp__h594315) + begin + case (guard__h585360) + 2'b0: + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q181 = + _theResult___fst_exp__h593586; + 2'b01, 2'b10, 2'b11: + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q181 = + _theResult___exp__h594315; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h593586 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q181) + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - _theResult___fst_exp__h593764; + _theResult___fst_exp__h593586; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879; @@ -34041,49 +33788,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q181; + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = 11'd0; endcase end - always@(guard__h585538 or - _theResult___fst_exp__h593764 or - out_exp__h594496 or _theResult___exp__h594493) + always@(guard__h585360 or + _theResult___fst_exp__h593586 or + out_exp__h594318 or _theResult___exp__h594315) begin - case (guard__h585538) + case (guard__h585360) 2'b0, 2'b01: - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q182 = - _theResult___fst_exp__h593764; + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q182 = + _theResult___fst_exp__h593586; 2'b10: - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q182 = - out_exp__h594496; + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q182 = + out_exp__h594318; 2'b11: - CASE_guard85538_0b0_theResult___fst_exp93764_0_ETC__q182 = - _theResult___exp__h594493; + CASE_guard85360_0b0_theResult___fst_exp93586_0_ETC__q182 = + _theResult___exp__h594315; endcase end - always@(guard__h594607 or - _theResult___fst_exp__h602597 or _theResult___exp__h603277) + always@(guard__h594429 or + _theResult___fst_exp__h602419 or _theResult___exp__h603099) begin - case (guard__h594607) + case (guard__h594429) 2'b0: - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q183 = - _theResult___fst_exp__h602597; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q183 = + _theResult___fst_exp__h602419; 2'b01, 2'b10, 2'b11: - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q183 = - _theResult___exp__h603277; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q183 = + _theResult___exp__h603099; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h602597 or + _theResult___fst_exp__h602419 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 or - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q183) + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - _theResult___fst_exp__h602597; + _theResult___fst_exp__h602419; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910; @@ -34092,44 +33839,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q183; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = 11'd0; endcase end - always@(guard__h594607 or - _theResult___fst_exp__h602597 or - out_exp__h603280 or _theResult___exp__h603277) + always@(guard__h594429 or + _theResult___fst_exp__h602419 or + out_exp__h603102 or _theResult___exp__h603099) begin - case (guard__h594607) + case (guard__h594429) 2'b0, 2'b01: - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q184 = - _theResult___fst_exp__h602597; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q184 = + _theResult___fst_exp__h602419; 2'b10: - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q184 = - out_exp__h603280; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q184 = + out_exp__h603102; 2'b11: - CASE_guard94607_0b0_theResult___fst_exp02597_0_ETC__q184 = - _theResult___exp__h603277; + CASE_guard94429_0b0_theResult___fst_exp02419_0_ETC__q184 = + _theResult___exp__h603099; endcase end - always@(guard__h536922 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h536744 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h536922) + case (guard__h536744) 2'b0, 2'b01, 2'b10: - CASE_guard36922_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard36744_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard36922_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h536922 == 2'b11 && + CASE_guard36744_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h536744 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536922) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536744) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34139,12 +33886,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h536922 == 2'b0) ? + (guard__h536744 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h536922 == 2'b01 || guard__h536922 == 2'b10 || - guard__h536922 == 2'b11) && + (guard__h536744 == 2'b01 || guard__h536744 == 2'b10 || + guard__h536744 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34155,23 +33902,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h546234 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555125 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546234) + case (guard__h555125) 2'b0, 2'b01, 2'b10: - CASE_guard46234_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46234_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h546234 == 2'b11 && + CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h555125 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546234) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555125) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34181,12 +33928,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h546234 == 2'b0) ? + (guard__h555125 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h546234 == 2'b01 || guard__h546234 == 2'b10 || - guard__h546234 == 2'b11) && + (guard__h555125 == 2'b01 || guard__h555125 == 2'b10 || + guard__h555125 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34197,23 +33944,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555303 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546056 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555303) + case (guard__h546056) 2'b0, 2'b01, 2'b10: - CASE_guard55303_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard46056_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55303_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h555303 == 2'b11 && + CASE_guard46056_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h546056 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555303) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546056) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34223,12 +33970,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h555303 == 2'b0) ? + (guard__h546056 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h555303 == 2'b01 || guard__h555303 == 2'b10 || - guard__h555303 == 2'b11) && + (guard__h546056 == 2'b01 || guard__h546056 == 2'b10 || + guard__h546056 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34239,23 +33986,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h546234 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546056 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546234) + case (guard__h546056) 2'b0, 2'b01, 2'b10: - CASE_guard46234_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard46056_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46234_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h546234 != 2'b11 || + CASE_guard46056_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h546056 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546234) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546056) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34265,12 +34012,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h546234 == 2'b0) ? + (guard__h546056 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h546234 != 2'b01 && guard__h546234 != 2'b10 && - guard__h546234 != 2'b11 || + guard__h546056 != 2'b01 && guard__h546056 != 2'b10 && + guard__h546056 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34281,23 +34028,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555303 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555125 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555303) + case (guard__h555125) 2'b0, 2'b01, 2'b10: - CASE_guard55303_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55303_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h555303 != 2'b11 || + CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h555125 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555303) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555125) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34307,12 +34054,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h555303 == 2'b0) ? + (guard__h555125 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h555303 != 2'b01 && guard__h555303 != 2'b10 && - guard__h555303 != 2'b11 || + guard__h555125 != 2'b01 && guard__h555125 != 2'b10 && + guard__h555125 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34323,23 +34070,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h536922 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h536744 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h536922) + case (guard__h536744) 2'b0, 2'b01, 2'b10: - CASE_guard36922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard36744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard36922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h536922 != 2'b11 || + CASE_guard36744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h536744 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536922) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h536744) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34349,12 +34096,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h536922 == 2'b0) ? + (guard__h536744 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h536922 != 2'b01 && guard__h536922 != 2'b10 && - guard__h536922 != 2'b11 || + guard__h536744 != 2'b01 && guard__h536744 != 2'b10 && + guard__h536744 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34365,28 +34112,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h536922 or - _theResult___snd__h544834 or _theResult___sfd__h545539) + always@(guard__h536744 or + _theResult___snd__h544656 or _theResult___sfd__h545361) begin - case (guard__h536922) + case (guard__h536744) 2'b0: - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q197 = - _theResult___snd__h544834[56:5]; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q197 = + _theResult___snd__h544656[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q197 = - _theResult___sfd__h545539; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q197 = + _theResult___sfd__h545361; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h544834 or + _theResult___snd__h544656 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 or - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q197) + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - _theResult___snd__h544834[56:5]; + _theResult___snd__h544656[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706; @@ -34395,98 +34142,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q197; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = 52'd0; endcase end - always@(guard__h536922 or - _theResult___snd__h544834 or - out_sfd__h545542 or _theResult___sfd__h545539) + always@(guard__h536744 or + _theResult___snd__h544656 or + out_sfd__h545364 or _theResult___sfd__h545361) begin - case (guard__h536922) + case (guard__h536744) 2'b0, 2'b01: - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q198 = - _theResult___snd__h544834[56:5]; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q198 = + _theResult___snd__h544656[56:5]; 2'b10: - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q198 = - out_sfd__h545542; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q198 = + out_sfd__h545364; 2'b11: - CASE_guard36922_0b0_theResult___snd44834_BITS__ETC__q198 = - _theResult___sfd__h545539; + CASE_guard36744_0b0_theResult___snd44656_BITS__ETC__q198 = + _theResult___sfd__h545361; endcase end - always@(guard__h546234 or sfdin__h554454 or _theResult___sfd__h555190) + always@(guard__h555125 or + _theResult___snd__h563061 or _theResult___sfd__h563796) begin - case (guard__h546234) + case (guard__h555125) 2'b0: - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h554454[56:5]; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q199 = + _theResult___snd__h563061[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h555190; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q199 = + _theResult___sfd__h563796; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h554454 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q199) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - sfdin__h554454[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q199; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - 52'd0; - endcase - end - always@(guard__h546234 or - sfdin__h554454 or out_sfd__h555193 or _theResult___sfd__h555190) - begin - case (guard__h546234) - 2'b0, 2'b01: - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h554454[56:5]; - 2'b10: - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h555193; - 2'b11: - CASE_guard46234_0b0_sfdin54454_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h555190; - endcase - end - always@(guard__h555303 or - _theResult___snd__h563239 or _theResult___sfd__h563974) - begin - case (guard__h555303) - 2'b0: - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q201 = - _theResult___snd__h563239[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q201 = - _theResult___sfd__h563974; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h563239 or + _theResult___snd__h563061 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 or - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q201) + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - _theResult___snd__h563239[56:5]; + _theResult___snd__h563061[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751; @@ -34495,49 +34193,98 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q201; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = 52'd0; endcase end - always@(guard__h555303 or - _theResult___snd__h563239 or - out_sfd__h563977 or _theResult___sfd__h563974) + always@(guard__h555125 or + _theResult___snd__h563061 or + out_sfd__h563799 or _theResult___sfd__h563796) begin - case (guard__h555303) + case (guard__h555125) 2'b0, 2'b01: - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q202 = - _theResult___snd__h563239[56:5]; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q200 = + _theResult___snd__h563061[56:5]; 2'b10: - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q202 = - out_sfd__h563977; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q200 = + out_sfd__h563799; 2'b11: - CASE_guard55303_0b0_theResult___snd63239_BITS__ETC__q202 = - _theResult___sfd__h563974; + CASE_guard55125_0b0_theResult___snd63061_BITS__ETC__q200 = + _theResult___sfd__h563796; endcase end - always@(guard__h507381 or - _theResult___fst_exp__h515607 or _theResult___exp__h516336) + always@(guard__h546056 or sfdin__h554276 or _theResult___sfd__h555012) begin - case (guard__h507381) + case (guard__h546056) 2'b0: - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q203 = - _theResult___fst_exp__h515607; + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q201 = + sfdin__h554276[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q203 = - _theResult___exp__h516336; + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q201 = + _theResult___sfd__h555012; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h515607 or + sfdin__h554276 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q201) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = + sfdin__h554276[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q201; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = + 52'd0; + endcase + end + always@(guard__h546056 or + sfdin__h554276 or out_sfd__h555015 or _theResult___sfd__h555012) + begin + case (guard__h546056) + 2'b0, 2'b01: + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q202 = + sfdin__h554276[56:5]; + 2'b10: + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q202 = + out_sfd__h555015; + 2'b11: + CASE_guard46056_0b0_sfdin54276_BITS_56_TO_5_0b_ETC__q202 = + _theResult___sfd__h555012; + endcase + end + always@(guard__h507203 or + _theResult___fst_exp__h515429 or _theResult___exp__h516158) + begin + case (guard__h507203) + 2'b0: + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q203 = + _theResult___fst_exp__h515429; + 2'b01, 2'b10, 2'b11: + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q203 = + _theResult___exp__h516158; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h515429 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 or - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q203) + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - _theResult___fst_exp__h515607; + _theResult___fst_exp__h515429; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169; @@ -34546,49 +34293,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q203; + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = 11'd0; endcase end - always@(guard__h507381 or - _theResult___fst_exp__h515607 or - out_exp__h516339 or _theResult___exp__h516336) + always@(guard__h507203 or + _theResult___fst_exp__h515429 or + out_exp__h516161 or _theResult___exp__h516158) begin - case (guard__h507381) + case (guard__h507203) 2'b0, 2'b01: - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q204 = - _theResult___fst_exp__h515607; + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q204 = + _theResult___fst_exp__h515429; 2'b10: - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q204 = - out_exp__h516339; + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q204 = + out_exp__h516161; 2'b11: - CASE_guard07381_0b0_theResult___fst_exp15607_0_ETC__q204 = - _theResult___exp__h516336; + CASE_guard07203_0b0_theResult___fst_exp15429_0_ETC__q204 = + _theResult___exp__h516158; endcase end - always@(guard__h516450 or - _theResult___fst_exp__h524440 or _theResult___exp__h525120) + always@(guard__h516272 or + _theResult___fst_exp__h524262 or _theResult___exp__h524942) begin - case (guard__h516450) + case (guard__h516272) 2'b0: - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q205 = - _theResult___fst_exp__h524440; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q205 = + _theResult___fst_exp__h524262; 2'b01, 2'b10, 2'b11: - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q205 = - _theResult___exp__h525120; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q205 = + _theResult___exp__h524942; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h524440 or + _theResult___fst_exp__h524262 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q205) + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - _theResult___fst_exp__h524440; + _theResult___fst_exp__h524262; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200; @@ -34597,99 +34344,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q205; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = 11'd0; endcase end - always@(guard__h516450 or - _theResult___fst_exp__h524440 or - out_exp__h525123 or _theResult___exp__h525120) + always@(guard__h516272 or + _theResult___fst_exp__h524262 or + out_exp__h524945 or _theResult___exp__h524942) begin - case (guard__h516450) + case (guard__h516272) 2'b0, 2'b01: - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q206 = - _theResult___fst_exp__h524440; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q206 = + _theResult___fst_exp__h524262; 2'b10: - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q206 = - out_exp__h525123; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q206 = + out_exp__h524945; 2'b11: - CASE_guard16450_0b0_theResult___fst_exp24440_0_ETC__q206 = - _theResult___exp__h525120; + CASE_guard16272_0b0_theResult___fst_exp24262_0_ETC__q206 = + _theResult___exp__h524942; endcase end - always@(guard__h498069 or - _theResult___snd__h505981 or _theResult___sfd__h506686) + always@(guard__h507203 or sfdin__h515423 or _theResult___sfd__h516159) begin - case (guard__h498069) + case (guard__h507203) 2'b0: - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q207 = - _theResult___snd__h505981[56:5]; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h515423[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q207 = - _theResult___sfd__h506686; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h516159; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h505981 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - _theResult___snd__h505981[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - 52'd0; - endcase - end - always@(guard__h498069 or - _theResult___snd__h505981 or - out_sfd__h506689 or _theResult___sfd__h506686) - begin - case (guard__h498069) - 2'b0, 2'b01: - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q208 = - _theResult___snd__h505981[56:5]; - 2'b10: - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q208 = - out_sfd__h506689; - 2'b11: - CASE_guard98069_0b0_theResult___snd05981_BITS__ETC__q208 = - _theResult___sfd__h506686; - endcase - end - always@(guard__h507381 or sfdin__h515601 or _theResult___sfd__h516337) - begin - case (guard__h507381) - 2'b0: - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q209 = - sfdin__h515601[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q209 = - _theResult___sfd__h516337; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h515601 or + sfdin__h515423 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q209) + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - sfdin__h515601[56:5]; + sfdin__h515423[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; @@ -34698,48 +34394,99 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q209; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = 52'd0; endcase end - always@(guard__h507381 or - sfdin__h515601 or out_sfd__h516340 or _theResult___sfd__h516337) + always@(guard__h507203 or + sfdin__h515423 or out_sfd__h516162 or _theResult___sfd__h516159) begin - case (guard__h507381) + case (guard__h507203) 2'b0, 2'b01: - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q210 = - sfdin__h515601[56:5]; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h515423[56:5]; 2'b10: - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q210 = - out_sfd__h516340; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h516162; 2'b11: - CASE_guard07381_0b0_sfdin15601_BITS_56_TO_5_0b_ETC__q210 = - _theResult___sfd__h516337; + CASE_guard07203_0b0_sfdin15423_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h516159; endcase end - always@(guard__h516450 or - _theResult___snd__h524386 or _theResult___sfd__h525121) + always@(guard__h497891 or + _theResult___snd__h505803 or _theResult___sfd__h506508) begin - case (guard__h516450) + case (guard__h497891) 2'b0: - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q211 = - _theResult___snd__h524386[56:5]; + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q209 = + _theResult___snd__h505803[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q211 = - _theResult___sfd__h525121; + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q209 = + _theResult___sfd__h506508; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h524386 or + _theResult___snd__h505803 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = + _theResult___snd__h505803[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = + 52'd0; + endcase + end + always@(guard__h497891 or + _theResult___snd__h505803 or + out_sfd__h506511 or _theResult___sfd__h506508) + begin + case (guard__h497891) + 2'b0, 2'b01: + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q210 = + _theResult___snd__h505803[56:5]; + 2'b10: + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q210 = + out_sfd__h506511; + 2'b11: + CASE_guard97891_0b0_theResult___snd05803_BITS__ETC__q210 = + _theResult___sfd__h506508; + endcase + end + always@(guard__h516272 or + _theResult___snd__h524208 or _theResult___sfd__h524943) + begin + case (guard__h516272) + 2'b0: + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q211 = + _theResult___snd__h524208[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q211 = + _theResult___sfd__h524943; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h524208 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 or - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q211) + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - _theResult___snd__h524386[56:5]; + _theResult___snd__h524208[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272; @@ -34748,49 +34495,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q211; + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = 52'd0; endcase end - always@(guard__h516450 or - _theResult___snd__h524386 or - out_sfd__h525124 or _theResult___sfd__h525121) + always@(guard__h516272 or + _theResult___snd__h524208 or + out_sfd__h524946 or _theResult___sfd__h524943) begin - case (guard__h516450) + case (guard__h516272) 2'b0, 2'b01: - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q212 = - _theResult___snd__h524386[56:5]; + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q212 = + _theResult___snd__h524208[56:5]; 2'b10: - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q212 = - out_sfd__h525124; + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q212 = + out_sfd__h524946; 2'b11: - CASE_guard16450_0b0_theResult___snd24386_BITS__ETC__q212 = - _theResult___sfd__h525121; + CASE_guard16272_0b0_theResult___snd24208_BITS__ETC__q212 = + _theResult___sfd__h524943; endcase end - always@(guard__h576226 or - _theResult___snd__h584138 or _theResult___sfd__h584843) + always@(guard__h576048 or + _theResult___snd__h583960 or _theResult___sfd__h584665) begin - case (guard__h576226) + case (guard__h576048) 2'b0: - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q213 = - _theResult___snd__h584138[56:5]; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q213 = + _theResult___snd__h583960[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q213 = - _theResult___sfd__h584843; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q213 = + _theResult___sfd__h584665; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h584138 or + _theResult___snd__h583960 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 or - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q213) + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - _theResult___snd__h584138[56:5]; + _theResult___snd__h583960[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936; @@ -34799,48 +34546,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q213; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = 52'd0; endcase end - always@(guard__h576226 or - _theResult___snd__h584138 or - out_sfd__h584846 or _theResult___sfd__h584843) + always@(guard__h576048 or + _theResult___snd__h583960 or + out_sfd__h584668 or _theResult___sfd__h584665) begin - case (guard__h576226) + case (guard__h576048) 2'b0, 2'b01: - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q214 = - _theResult___snd__h584138[56:5]; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q214 = + _theResult___snd__h583960[56:5]; 2'b10: - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q214 = - out_sfd__h584846; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q214 = + out_sfd__h584668; 2'b11: - CASE_guard76226_0b0_theResult___snd84138_BITS__ETC__q214 = - _theResult___sfd__h584843; + CASE_guard76048_0b0_theResult___snd83960_BITS__ETC__q214 = + _theResult___sfd__h584665; endcase end - always@(guard__h585538 or sfdin__h593758 or _theResult___sfd__h594494) + always@(guard__h585360 or sfdin__h593580 or _theResult___sfd__h594316) begin - case (guard__h585538) + case (guard__h585360) 2'b0: - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h593758[56:5]; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h593580[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h594494; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h594316; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h593758 or + sfdin__h593580 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 or - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q215) + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - sfdin__h593758[56:5]; + sfdin__h593580[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962; @@ -34849,24 +34596,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q215; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = 52'd0; endcase end - always@(guard__h585538 or - sfdin__h593758 or out_sfd__h594497 or _theResult___sfd__h594494) + always@(guard__h585360 or + sfdin__h593580 or out_sfd__h594319 or _theResult___sfd__h594316) begin - case (guard__h585538) + case (guard__h585360) 2'b0, 2'b01: - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h593758[56:5]; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h593580[56:5]; 2'b10: - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h594497; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h594319; 2'b11: - CASE_guard85538_0b0_sfdin93758_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h594494; + CASE_guard85360_0b0_sfdin93580_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h594316; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34901,28 +34648,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963; endcase end - always@(guard__h594607 or - _theResult___snd__h602543 or _theResult___sfd__h603278) + always@(guard__h594429 or + _theResult___snd__h602365 or _theResult___sfd__h603100) begin - case (guard__h594607) + case (guard__h594429) 2'b0: - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q217 = - _theResult___snd__h602543[56:5]; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q217 = + _theResult___snd__h602365[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q217 = - _theResult___sfd__h603278; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q217 = + _theResult___sfd__h603100; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h602543 or + _theResult___snd__h602365 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 or - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q217) + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - _theResult___snd__h602543[56:5]; + _theResult___snd__h602365[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981; @@ -34931,25 +34678,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q217; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = 52'd0; endcase end - always@(guard__h594607 or - _theResult___snd__h602543 or - out_sfd__h603281 or _theResult___sfd__h603278) + always@(guard__h594429 or + _theResult___snd__h602365 or + out_sfd__h603103 or _theResult___sfd__h603100) begin - case (guard__h594607) + case (guard__h594429) 2'b0, 2'b01: - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q218 = - _theResult___snd__h602543[56:5]; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q218 = + _theResult___snd__h602365[56:5]; 2'b10: - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q218 = - out_sfd__h603281; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q218 = + out_sfd__h603103; 2'b11: - CASE_guard94607_0b0_theResult___snd02543_BITS__ETC__q218 = - _theResult___sfd__h603278; + CASE_guard94429_0b0_theResult___snd02365_BITS__ETC__q218 = + _theResult___sfd__h603100; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -35000,102 +34747,30 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131; endcase end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q219 = - coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q219 = 3'd7; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q219) - begin - case (coreFix_aluExe_0_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q220 = - coreFix_aluExe_0_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q220 = - { coreFix_aluExe_0_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q219, - coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q220 = - { 3'd5, 18'h2AAAA }; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[394:383]) - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q221 = - coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q221 = - 12'd2303; - endcase - end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q222 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q222 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q222) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219) begin case (coreFix_aluExe_1_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q223 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = coreFix_aluExe_1_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q223 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = { coreFix_aluExe_1_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q222, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q223 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = { 3'd5, 18'h2AAAA }; endcase end @@ -35138,9 +34813,81 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q224 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q224 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[399:397]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = + coreFix_aluExe_0_regToExeQ$first[399:397]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = 3'd7; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222) + begin + case (coreFix_aluExe_0_regToExeQ$first[416:414]) + 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = + coreFix_aluExe_0_regToExeQ$first[416:396]; + 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = + { coreFix_aluExe_0_regToExeQ$first[416:414], + 9'h0AA, + coreFix_aluExe_0_regToExeQ$first[404:400], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, + coreFix_aluExe_0_regToExeQ$first[396] }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = + { 3'd5, 18'h2AAAA }; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[394:383]) + 12'd3860, + 12'd3859, + 12'd3858, + 12'd3857, + 12'd2818, + 12'd2816, + 12'd836, + 12'd835, + 12'd834, + 12'd833, + 12'd832, + 12'd774, + 12'd773, + 12'd772, + 12'd771, + 12'd770, + 12'd769, + 12'd768, + 12'd384, + 12'd324, + 12'd323, + 12'd322, + 12'd321, + 12'd320, + 12'd262, + 12'd261, + 12'd260, + 12'd256, + 12'd2049, + 12'd2048, + 12'd3074, + 12'd3073, + 12'd3072, + 12'd3, + 12'd2, + 12'd1: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = + coreFix_aluExe_0_regToExeQ$first[394:383]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = 12'd2303; endcase end @@ -35261,10 +35008,10 @@ module mkCore(CLK, 4'd11; endcase end - always@(k__h671653 or + always@(k__h671475 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h671653) + case (k__h671475) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476 = coreFix_aluExe_0_rsAlu$canEnq; @@ -35303,10 +35050,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13488; endcase end - always@(k__h671653 or + always@(k__h671475 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h671653) + case (k__h671475) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__346_ETC___d13509 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -35448,14 +35195,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h686994 or + always@(idx__h686816 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13751 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2863_BITS_19_ETC___d13757 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686994) + case (idx__h686816) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2861_AN_ETC___d13776 = fetchStage$pipelines_0_canDeq && @@ -35588,18 +35335,29 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2872_BITS_19_ETC___d13742; endcase end - always@(k__h671653 or + always@(k__h671475 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h671653) + case (k__h671475) 1'd0: - CASE_k71653_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k71475_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k71653_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k71475_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544 or @@ -35619,17 +35377,6 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544); endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544 or @@ -35699,14 +35446,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13488; endcase end - always@(idx__h686994 or + always@(idx__h686816 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13979 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2863_BITS_194_TO_ETC___d13986 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686994) + case (idx__h686816) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__286_ETC___d13990 = (!fetchStage$pipelines_0_canDeq || @@ -35742,21 +35489,6 @@ module mkCore(CLK, coreFix_memExe_lsq$RDY_enqSt; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d14032 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476; - default: IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d14032 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544); - endcase - end always@(fetchStage$pipelines_0_first or IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476 or @@ -35774,6 +35506,21 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d14032 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3466_co_ETC___d13476; + default: IF_fetchStage_pipelines_0_first__2863_BITS_194_ETC___d14032 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d13544); + endcase + end always@(fetchStage$pipelines_1_first or fetchStage_pipelines_0_canDeq__2861_AND_regRen_ETC___d14051 or SEL_ARR_fetchStage_pipelines_0_canDeq__2861_AN_ETC___d13776 or @@ -35834,10 +35581,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14124 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14124 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -35845,10 +35592,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14133 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14124 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2863_BITS_191_ETC___d14124 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -35867,10 +35614,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14291 = + !coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14291 = + !coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_1_first or @@ -35878,10 +35625,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14291 = - !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14291 = - !coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_1_first__2872_BITS_191_ETC___d14293 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -39134,21 +38881,21 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12068[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h625021)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624843)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12068[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h625021)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624843)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 281, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12068[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h625021)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h624843)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -39185,21 +38932,21 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12710[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646758)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646580)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12710[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646758)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646580)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 281, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12710[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646758)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h646580)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -39995,15 +39742,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h608735 == 2'd0) + v__h608557 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h608735 == 2'd0) + v__h608557 == 2'd0) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 172, column 38\ncredit underflow"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h608735 == 2'd0) + v__h608557 == 2'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 46c2145..549c8fb 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -7,9 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const -// RDY_set_htif_addrs O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg +// RDY_start O 1 // cpu_imem_master_awvalid O 1 // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg @@ -22,7 +20,6 @@ // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg @@ -51,7 +48,6 @@ // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg // cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg @@ -68,12 +64,13 @@ // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg +// RST_N_dm_power_on_reset I 1 unused // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 unused -// set_htif_addrs_tohost_addr I 64 reg -// set_htif_addrs_fromhost_addr I 64 reg +// start_tohost_addr I 64 reg +// start_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -112,10 +109,9 @@ // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 +// nmi_req_set_not_clear I 1 unused // EN_set_verbosity I 1 -// EN_set_htif_addrs I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 +// EN_start I 1 // // Combinational paths from inputs to outputs: // (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready @@ -135,7 +131,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkCoreW(CLK, +module mkCoreW(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -143,16 +140,10 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, - set_htif_addrs_tohost_addr, - set_htif_addrs_fromhost_addr, - EN_set_htif_addrs, - RDY_set_htif_addrs, - - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start, cpu_imem_master_awvalid, @@ -180,8 +171,6 @@ module mkCoreW(CLK, cpu_imem_master_wvalid, - cpu_imem_master_wid, - cpu_imem_master_wdata, cpu_imem_master_wstrb, @@ -254,8 +243,6 @@ module mkCoreW(CLK, cpu_dmem_master_wvalid, - cpu_dmem_master_wid, - cpu_dmem_master_wdata, cpu_dmem_master_wstrb, @@ -332,7 +319,10 @@ module mkCoreW(CLK, core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear); + core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, + + nmi_req_set_not_clear); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -342,19 +332,11 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // action method set_htif_addrs - input [63 : 0] set_htif_addrs_tohost_addr; - input [63 : 0] set_htif_addrs_fromhost_addr; - input EN_set_htif_addrs; - output RDY_set_htif_addrs; - - // action method cpu_reset_server_request_put - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // action method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; @@ -397,9 +379,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; @@ -511,9 +490,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid output cpu_dmem_master_wvalid; - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - // value method cpu_dmem_master_m_wdata output [63 : 0] cpu_dmem_master_wdata; @@ -632,6 +608,9 @@ module mkCoreW(CLK, // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; + // action method nmi_req + input nmi_req_set_not_clear; + // signals for module outputs wire [63 : 0] cpu_dmem_master_araddr, cpu_dmem_master_awaddr, @@ -653,7 +632,6 @@ module mkCoreW(CLK, cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, - cpu_dmem_master_wid, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, @@ -661,8 +639,7 @@ module mkCoreW(CLK, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; + cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, @@ -675,10 +652,8 @@ module mkCoreW(CLK, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_htif_addrs, - RDY_set_verbosity, + wire RDY_set_verbosity, + RDY_start, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, cpu_dmem_master_awlock, @@ -696,37 +671,6 @@ module mkCoreW(CLK, cpu_imem_master_wlast, cpu_imem_master_wvalid; - // register rg_fromhost_addr - reg [63 : 0] rg_fromhost_addr; - wire [63 : 0] rg_fromhost_addr$D_IN; - wire rg_fromhost_addr$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // ports of submodule f_proc_start - wire f_proc_start$CLR, - f_proc_start$DEQ, - f_proc_start$EMPTY_N, - f_proc_start$ENQ, - f_proc_start$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, fabric_2x3$v_from_masters_0_awaddr, @@ -773,7 +717,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, @@ -782,7 +725,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_1_awid, fabric_2x3$v_from_masters_1_awqos, fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, @@ -793,7 +735,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, @@ -804,7 +745,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, @@ -814,8 +754,7 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; + fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, @@ -856,7 +795,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, @@ -942,7 +880,6 @@ module mkCoreW(CLK, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, - plic$axi4_slave_wid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -957,8 +894,6 @@ module mkCoreW(CLK, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, @@ -1027,7 +962,6 @@ module mkCoreW(CLK, proc$debug_module_mem_server_awregion, proc$debug_module_mem_server_bid, proc$debug_module_mem_server_rid, - proc$debug_module_mem_server_wid, proc$master0_arcache, proc$master0_arid, proc$master0_arqos, @@ -1038,7 +972,6 @@ module mkCoreW(CLK, proc$master0_awregion, proc$master0_bid, proc$master0_rid, - proc$master0_wid, proc$master1_arcache, proc$master1_arid, proc$master1_arqos, @@ -1049,7 +982,6 @@ module mkCoreW(CLK, proc$master1_awregion, proc$master1_bid, proc$master1_rid, - proc$master1_wid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1075,12 +1007,8 @@ module mkCoreW(CLK, proc$master1_awburst, proc$master1_bresp, proc$master1_rresp; - wire proc$EN_init_server_request_put, - proc$EN_init_server_response_get, - proc$EN_set_verbosity, + wire proc$EN_set_verbosity, proc$EN_start, - proc$RDY_init_server_request_put, - proc$RDY_init_server_response_get, proc$RDY_start, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, @@ -1136,10 +1064,7 @@ module mkCoreW(CLK, soc_map$m_plic_addr_lim; // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_cpu_hart0_reset_proc_start, - CAN_FIRE_RL_rl_rd_addr_channel, + wire CAN_FIRE_RL_rl_rd_addr_channel, CAN_FIRE_RL_rl_rd_addr_channel_1, CAN_FIRE_RL_rl_rd_addr_channel_2, CAN_FIRE_RL_rl_rd_addr_channel_3, @@ -1148,7 +1073,6 @@ module mkCoreW(CLK, CAN_FIRE_RL_rl_rd_data_channel_2, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_non_maskable_interrupt, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, @@ -1187,13 +1111,9 @@ module mkCoreW(CLK, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_set_htif_addrs, + CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_cpu_hart0_reset_proc_start, + CAN_FIRE_start, WILL_FIRE_RL_rl_rd_addr_channel, WILL_FIRE_RL_rl_rd_addr_channel_1, WILL_FIRE_RL_rl_rd_addr_channel_2, @@ -1203,7 +1123,6 @@ module mkCoreW(CLK, WILL_FIRE_RL_rl_rd_data_channel_2, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_non_maskable_interrupt, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, @@ -1242,19 +1161,14 @@ module mkCoreW(CLK, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_set_htif_addrs, - WILL_FIRE_set_verbosity; + WILL_FIRE_nmi_req, + WILL_FIRE_set_verbosity, + WILL_FIRE_start; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4705; - reg [31 : 0] v__h4271; - reg [31 : 0] v__h4588; - reg [31 : 0] v__h4265; - reg [31 : 0] v__h4582; - reg [31 : 0] v__h4699; + reg [31 : 0] v__h6490; + reg [31 : 0] v__h6484; // synopsys translate_on // action method set_verbosity @@ -1262,22 +1176,10 @@ module mkCoreW(CLK, assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // action method set_htif_addrs - assign RDY_set_htif_addrs = 1'd1 ; - assign CAN_FIRE_set_htif_addrs = 1'd1 ; - assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // action method cpu_reset_server_response_get - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; + // action method start + assign RDY_start = proc$RDY_start ; + assign CAN_FIRE_start = proc$RDY_start ; + assign WILL_FIRE_start = EN_start ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = proc$master0_awvalid ; @@ -1319,9 +1221,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = proc$master0_wvalid ; - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = proc$master0_wid ; - // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = proc$master0_wdata ; @@ -1426,9 +1325,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - // value method cpu_dmem_master_m_wdata assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; @@ -1557,32 +1453,9 @@ module mkCoreW(CLK, assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - // submodule f_proc_start - FIFO20 #(.guarded(32'd1)) f_proc_start(.RST(RST_N), - .CLK(CLK), - .ENQ(f_proc_start$ENQ), - .DEQ(f_proc_start$DEQ), - .CLR(f_proc_start$CLR), - .FULL_N(f_proc_start$FULL_N), - .EMPTY_N(f_proc_start$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); + // action method nmi_req + assign CAN_FIRE_nmi_req = 1'd1 ; + assign WILL_FIRE_nmi_req = 1'd1 ; // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), @@ -1613,7 +1486,6 @@ module mkCoreW(CLK, .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), @@ -1642,7 +1514,6 @@ module mkCoreW(CLK, .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), @@ -1681,7 +1552,7 @@ module mkCoreW(CLK, .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), + .RDY_reset(), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), @@ -1717,7 +1588,6 @@ module mkCoreW(CLK, .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), @@ -1746,7 +1616,6 @@ module mkCoreW(CLK, .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), @@ -1775,7 +1644,6 @@ module mkCoreW(CLK, .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), @@ -1821,7 +1689,6 @@ module mkCoreW(CLK, .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), @@ -1851,8 +1718,8 @@ module mkCoreW(CLK, .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), + .RDY_server_reset_request_put(), + .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), @@ -1896,7 +1763,6 @@ module mkCoreW(CLK, .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), - .debug_module_mem_server_wid(proc$debug_module_mem_server_wid), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), @@ -1929,12 +1795,8 @@ module mkCoreW(CLK, .start_fromhostAddr(proc$start_fromhostAddr), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), - .EN_init_server_request_put(proc$EN_init_server_request_put), - .EN_init_server_response_get(proc$EN_init_server_response_get), .EN_start(proc$EN_start), .EN_set_verbosity(proc$EN_set_verbosity), - .RDY_init_server_request_put(proc$RDY_init_server_request_put), - .RDY_init_server_response_get(proc$RDY_init_server_response_get), .RDY_start(proc$RDY_start), .master0_awvalid(proc$master0_awvalid), .master0_awid(proc$master0_awid), @@ -1948,7 +1810,6 @@ module mkCoreW(CLK, .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), .master0_wvalid(proc$master0_wvalid), - .master0_wid(proc$master0_wid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), @@ -1977,7 +1838,6 @@ module mkCoreW(CLK, .master1_awqos(proc$master1_awqos), .master1_awregion(proc$master1_awregion), .master1_wvalid(proc$master1_wvalid), - .master1_wid(proc$master1_wid), .master1_wdata(proc$master1_wdata), .master1_wstrb(proc$master1_wstrb), .master1_wlast(proc$master1_wlast), @@ -2038,12 +1898,6 @@ module mkCoreW(CLK, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // rule RL_rl_cpu_hart0_reset_proc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_proc_start = - proc$RDY_start && f_proc_start$EMPTY_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_proc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_proc_start ; - // rule RL_rl_wr_addr_channel assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; @@ -2128,51 +1982,6 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - proc$RDY_init_server_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3$RDY_reset && - f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - proc$RDY_init_server_response_get && - plic$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - f_proc_start$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // rule RL_rl_relay_non_maskable_interrupt - assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - - // register rg_fromhost_addr - assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; - assign rg_fromhost_addr$EN = EN_set_htif_addrs ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_htif_addrs ; - - // submodule f_proc_start - assign f_proc_start$ENQ = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign f_proc_start$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_proc_start ; - assign f_proc_start$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ; @@ -2200,7 +2009,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ; assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ; assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ; - assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ; assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ; @@ -2246,7 +2054,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; assign fabric_2x3$v_from_masters_1_wdata = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wstrb = 8'b10101010 /* unspecified value */ ; @@ -2289,7 +2096,7 @@ module mkCoreW(CLK, proc$debug_module_mem_server_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = proc$debug_module_mem_server_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign fabric_2x3$EN_reset = 1'b0 ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule plic @@ -2318,7 +2125,6 @@ module mkCoreW(CLK, assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; @@ -2359,11 +2165,9 @@ module mkCoreW(CLK, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$EN_server_reset_request_put = 1'b0 ; + assign plic$EN_server_reset_response_get = 1'b0 ; + assign plic$EN_set_addr_map = EN_start ; // submodule proc assign proc$debug_module_mem_server_araddr = @@ -2409,7 +2213,6 @@ module mkCoreW(CLK, assign proc$debug_module_mem_server_rready = fabric_2x3$v_to_slaves_2_rready ; assign proc$debug_module_mem_server_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign proc$debug_module_mem_server_wid = fabric_2x3$v_to_slaves_2_wid ; assign proc$debug_module_mem_server_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign proc$debug_module_mem_server_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign proc$debug_module_mem_server_wvalid = @@ -2442,14 +2245,10 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_fromhostAddr = start_fromhost_addr ; assign proc$start_startpc = 64'h0000000000001000 ; - assign proc$start_tohostAddr = rg_tohost_addr ; - assign proc$EN_init_server_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign proc$EN_init_server_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_proc_start ; + assign proc$start_tohostAddr = start_tohost_addr ; + assign proc$EN_start = EN_start ; assign proc$EN_set_verbosity = EN_set_verbosity ; // submodule soc_map @@ -2457,35 +2256,6 @@ module mkCoreW(CLK, assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; - end - else - begin - if (rg_fromhost_addr$EN) - rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - // handling of system tasks // synopsys translate_off @@ -2493,39 +2263,19 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_proc_start) + if (EN_start) begin - v__h4705 = $stime; + v__h6490 = $stime; #0; end - v__h4699 = v__h4705 / 32'd10; + v__h6484 = v__h6490 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_proc_start) - $display("%0d: Core.rl_cpu_hart0_reset_proc_start; started running proc", - v__h4699); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4271 = $stime; - #0; - end - v__h4265 = v__h4271 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start (requestor %0d)", - v__h4265, - 1'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4588 = $stime; - #0; - end - v__h4582 = v__h4588 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; starting proc", - v__h4582); + if (EN_start) + $display("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)", + v__h6484, + 64'h0000000000001000, + start_tohost_addr, + start_fromhost_addr); end // synopsys translate_on endmodule // mkCoreW diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v index 5deebfd..4b44c8e 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,38 +1175,59 @@ module mkFabric(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ, - fabric_v_f_rd_err_id_0$FULL_N; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ, - fabric_v_f_rd_err_id_1$FULL_N; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ, - fabric_v_f_rd_err_user_0$FULL_N; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ, - fabric_v_f_rd_err_user_1$FULL_N; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ, + fabric_v_f_rd_err_info_0$FULL_N; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ, + fabric_v_f_rd_err_info_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1241,7 +1235,7 @@ module mkFabric(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1249,7 +1243,7 @@ module mkFabric(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1274,56 +1268,63 @@ module mkFabric(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ, - fabric_v_f_wr_err_id_0$FULL_N; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ, - fabric_v_f_wr_err_id_1$FULL_N; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ, - fabric_v_f_wr_err_user_0$FULL_N; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ, + fabric_v_f_wr_err_info_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ, - fabric_v_f_wr_err_user_1$FULL_N; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ, + fabric_v_f_wr_err_info_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1374,7 +1375,7 @@ module mkFabric(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1419,7 +1420,7 @@ module mkFabric(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1464,7 +1465,7 @@ module mkFabric(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1509,7 +1510,7 @@ module mkFabric(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1554,7 +1555,7 @@ module mkFabric(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1614,6 +1615,8 @@ module mkFabric(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, CAN_FIRE_reset, @@ -1674,6 +1677,8 @@ module mkFabric(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, WILL_FIRE_reset, @@ -1705,119 +1710,182 @@ module mkFabric(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8274; - reg [31 : 0] v__h8777; - reg [31 : 0] v__h9280; - reg [31 : 0] v__h9876; - reg [31 : 0] v__h10363; - reg [31 : 0] v__h10850; - reg [31 : 0] v__h11306; - reg [31 : 0] v__h11679; - reg [31 : 0] v__h12144; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13338; - reg [31 : 0] v__h13691; - reg [31 : 0] v__h14044; - reg [31 : 0] v__h14407; - reg [31 : 0] v__h14734; - reg [31 : 0] v__h15084; - reg [31 : 0] v__h15377; - reg [31 : 0] v__h15670; - reg [31 : 0] v__h15976; - reg [31 : 0] v__h16243; - reg [31 : 0] v__h16510; - reg [31 : 0] v__h16817; - reg [31 : 0] v__h17084; - reg [31 : 0] v__h17431; - reg [31 : 0] v__h17754; - reg [31 : 0] v__h18077; - reg [31 : 0] v__h18404; - reg [31 : 0] v__h18690; - reg [31 : 0] v__h18976; - reg [31 : 0] v__h19301; - reg [31 : 0] v__h19575; - reg [31 : 0] v__h5374; - reg [31 : 0] v__h5368; - reg [31 : 0] v__h8268; - reg [31 : 0] v__h8771; - reg [31 : 0] v__h9274; - reg [31 : 0] v__h9870; - reg [31 : 0] v__h10357; - reg [31 : 0] v__h10844; - reg [31 : 0] v__h11300; - reg [31 : 0] v__h11673; - reg [31 : 0] v__h12138; - reg [31 : 0] v__h12515; - reg [31 : 0] v__h12892; - reg [31 : 0] v__h13332; - reg [31 : 0] v__h13685; - reg [31 : 0] v__h14038; - reg [31 : 0] v__h14401; - reg [31 : 0] v__h14728; - reg [31 : 0] v__h15078; - reg [31 : 0] v__h15371; - reg [31 : 0] v__h15664; - reg [31 : 0] v__h15970; - reg [31 : 0] v__h16237; - reg [31 : 0] v__h16504; - reg [31 : 0] v__h16811; - reg [31 : 0] v__h17078; - reg [31 : 0] v__h17425; - reg [31 : 0] v__h17748; - reg [31 : 0] v__h18071; - reg [31 : 0] v__h18398; - reg [31 : 0] v__h18684; - reg [31 : 0] v__h18970; - reg [31 : 0] v__h19295; - reg [31 : 0] v__h19569; + reg [31 : 0] v__h8683; + reg [31 : 0] v__h9083; + reg [31 : 0] v__h9483; + reg [31 : 0] v__h9953; + reg [31 : 0] v__h10347; + reg [31 : 0] v__h10741; + reg [31 : 0] v__h11189; + reg [31 : 0] v__h11593; + reg [31 : 0] v__h12057; + reg [31 : 0] v__h12500; + reg [31 : 0] v__h12875; + reg [31 : 0] v__h13167; + reg [31 : 0] v__h13459; + reg [31 : 0] v__h13762; + reg [31 : 0] v__h14028; + reg [31 : 0] v__h14294; + reg [31 : 0] v__h14558; + reg [31 : 0] v__h14784; + reg [31 : 0] v__h15238; + reg [31 : 0] v__h15619; + reg [31 : 0] v__h16000; + reg [31 : 0] v__h16442; + reg [31 : 0] v__h16799; + reg [31 : 0] v__h17156; + reg [31 : 0] v__h17507; + reg [31 : 0] v__h17808; + reg [31 : 0] v__h18216; + reg [31 : 0] v__h18467; + reg [31 : 0] v__h18842; + reg [31 : 0] v__h19083; + reg [31 : 0] v__h19458; + reg [31 : 0] v__h19699; + reg [31 : 0] v__h20061; + reg [31 : 0] v__h20312; + reg [31 : 0] v__h20642; + reg [31 : 0] v__h20883; + reg [31 : 0] v__h21213; + reg [31 : 0] v__h21454; + reg [31 : 0] v__h21967; + reg [31 : 0] v__h22368; + reg [31 : 0] v__h5698; + reg [31 : 0] v__h5692; + reg [31 : 0] v__h8677; + reg [31 : 0] v__h9077; + reg [31 : 0] v__h9477; + reg [31 : 0] v__h9947; + reg [31 : 0] v__h10341; + reg [31 : 0] v__h10735; + reg [31 : 0] v__h11183; + reg [31 : 0] v__h11587; + reg [31 : 0] v__h12051; + reg [31 : 0] v__h12494; + reg [31 : 0] v__h12869; + reg [31 : 0] v__h13161; + reg [31 : 0] v__h13453; + reg [31 : 0] v__h13756; + reg [31 : 0] v__h14022; + reg [31 : 0] v__h14288; + reg [31 : 0] v__h14552; + reg [31 : 0] v__h14778; + reg [31 : 0] v__h15232; + reg [31 : 0] v__h15613; + reg [31 : 0] v__h15994; + reg [31 : 0] v__h16436; + reg [31 : 0] v__h16793; + reg [31 : 0] v__h17150; + reg [31 : 0] v__h17501; + reg [31 : 0] v__h17802; + reg [31 : 0] v__h18210; + reg [31 : 0] v__h18461; + reg [31 : 0] v__h18836; + reg [31 : 0] v__h19077; + reg [31 : 0] v__h19452; + reg [31 : 0] v__h19693; + reg [31 : 0] v__h20055; + reg [31 : 0] v__h20306; + reg [31 : 0] v__h20636; + reg [31 : 0] v__h20877; + reg [31 : 0] v__h21207; + reg [31 : 0] v__h21448; + reg [31 : 0] v__h21961; + reg [31 : 0] v__h22362; // synopsys translate_on // remaining internal signals - wire [1 : 0] IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36; - wire NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11962, + x__h12405, + x__h18353, + x__h18979, + x__h19595, + x__h21899, + x__h22300; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396, + x1_avValue_rresp__h18331, + x1_avValue_rresp__h18957, + x1_avValue_rresp__h19573; + wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457, + _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, + fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550, + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622, + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640, + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -2008,10 +2076,6 @@ module mkFabric(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2140,10 +2204,6 @@ module mkFabric(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2272,10 +2332,6 @@ module mkFabric(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2353,58 +2409,36 @@ module mkFabric(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_id_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_id_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(fabric_v_f_rd_err_user_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(fabric_v_f_rd_err_user_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2418,7 +2452,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2432,7 +2466,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2473,58 +2507,58 @@ module mkFabric(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_id_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_id_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(fabric_v_f_wr_err_user_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(fabric_v_f_wr_err_user_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2538,7 +2572,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2552,7 +2586,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2630,7 +2664,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2690,7 +2724,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2750,7 +2784,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2810,7 +2844,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2870,7 +2904,7 @@ module mkFabric(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2927,13 +2961,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2941,13 +2974,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2955,13 +2987,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; @@ -2969,13 +3000,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && @@ -2984,13 +3014,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && @@ -2999,13 +3028,12 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && @@ -3014,33 +3042,133 @@ module mkFabric(CLK, // rule RL_fabric_rl_wr_xaction_no_such_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - fabric_v_f_wr_err_id_0$FULL_N && - fabric_v_f_wr_err_user_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169 ; + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wr_err_info_0$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; // rule RL_fabric_rl_wr_xaction_no_such_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - fabric_v_f_wr_err_id_1$FULL_N && - fabric_v_f_wr_err_user_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189 ; + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wr_err_info_1$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; + + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = + fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + !fabric_v_f_wr_mis_0$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_1 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_1$EMPTY_N && + fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && + !fabric_v_f_wr_mis_1$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_2 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_2$EMPTY_N && + fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && + !fabric_v_f_wr_mis_2$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_3 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = + fabric_v_f_wr_mis_0$EMPTY_N && + fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_0$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_4 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = + fabric_v_f_wr_mis_1$EMPTY_N && + fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_1$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_5 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = + fabric_v_f_wr_mis_2$EMPTY_N && + fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_2$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; + + // rule RL_fabric_rl_wr_resp_err_to_master + assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_err_info_0$EMPTY_N && + fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = + CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; + + // rule RL_fabric_rl_wr_resp_err_to_master_1 + assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_err_info_1$EMPTY_N && + fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = + CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && fabric_v_f_rd_mis_0$FULL_N && fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; @@ -3051,8 +3179,8 @@ module mkFabric(CLK, fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; @@ -3063,8 +3191,8 @@ module mkFabric(CLK, fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; @@ -3075,8 +3203,8 @@ module mkFabric(CLK, fabric_v_f_rd_mis_0$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && @@ -3088,8 +3216,8 @@ module mkFabric(CLK, fabric_v_f_rd_mis_1$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && @@ -3101,8 +3229,8 @@ module mkFabric(CLK, fabric_v_f_rd_mis_2$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && @@ -3112,9 +3240,8 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_id_0$FULL_N && - fabric_v_f_rd_err_user_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314 ; + fabric_v_f_rd_err_info_0$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; @@ -3122,125 +3249,46 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_id_1$FULL_N && - fabric_v_f_rd_err_user_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333 ; + fabric_v_f_rd_err_info_1$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3249,9 +3297,9 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3260,9 +3308,9 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3271,9 +3319,9 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3282,8 +3330,7 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3292,8 +3339,7 @@ module mkFabric(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3303,14 +3349,79 @@ module mkFabric(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = + { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = + { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? + 8'd0 : + x__h18353 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? + 8'd0 : + x__h18979 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? + 8'd0 : + x__h19595 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? + 8'd0 : + x__h11962 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ? + 8'd0 : + x__h12405 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3320,73 +3431,162 @@ module mkFabric(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] ; - assign fabric_v_f_rd_err_id_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ? + 8'd0 : + x__h21899 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] ; - assign fabric_v_f_rd_err_id_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ? + 8'd0 : + x__h22300 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; + + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = + { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; + assign fabric_v_f_rd_err_info_0$ENQ = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = + { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; + assign fabric_v_f_rd_err_info_1$ENQ = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3413,10 +3613,14 @@ module mkFabric(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3443,47 +3647,103 @@ module mkFabric(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_id_0$ENQ = + assign fabric_v_f_wr_err_info_0$ENQ = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_id_0$DEQ = + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_id_1$ENQ = + assign fabric_v_f_wr_err_info_1$ENQ = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_id_1$DEQ = + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3494,9 +3754,7 @@ module mkFabric(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3507,9 +3765,7 @@ module mkFabric(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3602,24 +3858,24 @@ module mkFabric(CLK, // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3661,18 +3917,15 @@ module mkFabric(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3736,24 +3989,24 @@ module mkFabric(CLK, // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3795,18 +4048,15 @@ module mkFabric(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3888,12 +4138,14 @@ module mkFabric(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3952,12 +4204,14 @@ module mkFabric(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -4016,12 +4270,14 @@ module mkFabric(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -4044,168 +4300,267 @@ module mkFabric(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102) ? + assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498 = + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? + x1_avValue_rresp__h18331 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537 = + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? + x1_avValue_rresp__h18957 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576 = + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? + x1_avValue_rresp__h19573 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) ? 2'd0 : 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264) ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203 = + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390) ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 = + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 = + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 = + soc_map$m_boot_rom_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 = soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 = - soc_map$m_mem0_controller_addr_base <= + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = + soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30 ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 = - soc_map$m_uart0_addr_base <= + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = + soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = soc_map$m_uart0_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h18331 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18957 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19573 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11962 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12405 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h18353 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18979 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19595 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21899 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h22300 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -4215,6 +4570,13 @@ module mkFabric(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -4223,6 +4585,27 @@ module mkFabric(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4233,6 +4616,13 @@ module mkFabric(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4245,3021 +4635,3449 @@ module mkFabric(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h8274 = $stime; + v__h8683 = $stime; #0; end - v__h8268 = v__h8274 / 32'd10; + v__h8677 = v__h8683 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8268, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8677, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9083 = $stime; + #0; + end + v__h9077 = v__h9083 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9077, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9483 = $stime; + #0; + end + v__h9477 = v__h9483 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9477, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9953 = $stime; + #0; + end + v__h9947 = v__h9953 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9947, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10347 = $stime; + #0; + end + v__h10341 = v__h10347 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10341, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10741 = $stime; + #0; + end + v__h10735 = v__h10741 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10735, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h11189 = $stime; + #0; + end + v__h11183 = v__h11189 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", + v__h11183, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h11593 = $stime; + #0; + end + v__h11587 = v__h11593 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", + v__h11587, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h12057 = $stime; + #0; + end + v__h12051 = v__h12057 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12051, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h8777 = $stime; - #0; - end - v__h8771 = v__h8777 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8771, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h9280 = $stime; - #0; - end - v__h9274 = v__h9280 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9274, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9876 = $stime; + v__h12500 = $stime; #0; end - v__h9870 = v__h9876 / 32'd10; + v__h12494 = v__h12500 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9870, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12494, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h10363 = $stime; - #0; - end - v__h10357 = v__h10363 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10357, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h10850 = $stime; - #0; - end - v__h10844 = v__h10850 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10844, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h11306 = $stime; - #0; - end - v__h11300 = v__h11306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", - v__h11300, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h11679 = $stime; - #0; - end - v__h11673 = v__h11679 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", - v__h11673, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12144 = $stime; - #0; - end - v__h12138 = v__h12144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12138, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12521 = $stime; - #0; - end - v__h12515 = v__h12521 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12515, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12898 = $stime; - #0; - end - v__h12892 = v__h12898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12892, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h13338 = $stime; - #0; - end - v__h13332 = v__h13338 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13332, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h13691 = $stime; - #0; - end - v__h13685 = v__h13691 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13685, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14044 = $stime; - #0; - end - v__h14038 = v__h14044 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h14038, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14407 = $stime; - #0; - end - v__h14401 = v__h14407 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", - v__h14401, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14734 = $stime; - #0; - end - v__h14728 = v__h14734 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", - v__h14728, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15084 = $stime; + v__h12875 = $stime; #0; end - v__h15078 = v__h15084 / 32'd10; + v__h12869 = v__h12875 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15078, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12869, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15377 = $stime; + v__h13167 = $stime; #0; end - v__h15371 = v__h15377 / 32'd10; + v__h13161 = v__h13167 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15371, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13161, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15670 = $stime; + v__h13459 = $stime; #0; end - v__h15664 = v__h15670 / 32'd10; + v__h13453 = v__h13459 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15664, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13453, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15976 = $stime; + v__h13762 = $stime; #0; end - v__h15970 = v__h15976 / 32'd10; + v__h13756 = v__h13762 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15970, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13756, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16243 = $stime; + v__h14028 = $stime; #0; end - v__h16237 = v__h16243 / 32'd10; + v__h14022 = v__h14028 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16237, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14022, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16510 = $stime; + v__h14294 = $stime; #0; end - v__h16504 = v__h16510 / 32'd10; + v__h14288 = v__h14294 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16504, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14288, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16817 = $stime; + v__h14558 = $stime; #0; end - v__h16811 = v__h16817 / 32'd10; + v__h14552 = v__h14558 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16811, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14552, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h17084 = $stime; + v__h14784 = $stime; #0; end - v__h17078 = v__h17084 / 32'd10; + v__h14778 = v__h14784 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h17078, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14778, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15238 = $stime; + #0; + end + v__h15232 = v__h15238 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15232, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15619 = $stime; + #0; + end + v__h15613 = v__h15619 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15613, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16000 = $stime; + #0; + end + v__h15994 = v__h16000 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15994, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16442 = $stime; + #0; + end + v__h16436 = v__h16442 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16436, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16799 = $stime; + #0; + end + v__h16793 = v__h16799 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16793, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h17156 = $stime; + #0; + end + v__h17150 = v__h17156 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h17150, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h17507 = $stime; + #0; + end + v__h17501 = v__h17507 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", + v__h17501, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h17808 = $stime; + #0; + end + v__h17802 = v__h17808 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", + v__h17802, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17431 = $stime; + v__h18216 = $stime; #0; end - v__h17425 = v__h17431 / 32'd10; + v__h18210 = v__h18216 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17425, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18210, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18467 = $stime; + #0; + end + v__h18461 = v__h18467 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18461, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17754 = $stime; + v__h18842 = $stime; #0; end - v__h17748 = v__h17754 / 32'd10; + v__h18836 = v__h18842 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17748, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18836, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19083 = $stime; + #0; + end + v__h19077 = v__h19083 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19077, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18077 = $stime; + v__h19458 = $stime; #0; end - v__h18071 = v__h18077 / 32'd10; + v__h19452 = v__h19458 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18071, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19452, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19699 = $stime; + #0; + end + v__h19693 = v__h19699 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19693, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18404 = $stime; + v__h20061 = $stime; #0; end - v__h18398 = v__h18404 / 32'd10; + v__h20055 = v__h20061 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18398, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20055, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20312 = $stime; + #0; + end + v__h20306 = v__h20312 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20306, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18690 = $stime; + v__h20642 = $stime; #0; end - v__h18684 = v__h18690 / 32'd10; + v__h20636 = v__h20642 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18684, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20636, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20883 = $stime; + #0; + end + v__h20877 = v__h20883 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20877, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18976 = $stime; + v__h21213 = $stime; #0; end - v__h18970 = v__h18976 / 32'd10; + v__h21207 = v__h21213 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18970, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h21207, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21454 = $stime; + #0; + end + v__h21448 = v__h21454 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21448, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h19301 = $stime; + v__h21967 = $stime; #0; end - v__h19295 = v__h19301 / 32'd10; + v__h21961 = v__h21967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19295, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21961, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h19575 = $stime; + v__h22368 = $stime; #0; end - v__h19569 = v__h19575 / 32'd10; + v__h22362 = v__h22368 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19569, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h22362, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5374 = $stime; + v__h5698 = $stime; #0; end - v__h5368 = v__h5374 / 32'd10; + v__h5692 = v__h5698 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5368); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); end // synopsys translate_on endmodule // mkFabric diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v index 9f15fd0..a6d7266 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric_2x3(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric_2x3(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric_2x3(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric_2x3(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,34 +1175,57 @@ module mkFabric_2x3(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1237,7 +1233,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1245,7 +1241,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1270,52 +1266,61 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1366,7 +1371,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1411,7 +1416,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1456,7 +1461,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1501,7 +1506,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1546,7 +1551,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1602,6 +1607,8 @@ module mkFabric_2x3(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_reset, CAN_FIRE_set_verbosity, CAN_FIRE_v_from_masters_0_m_arvalid, @@ -1658,6 +1665,8 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_reset, WILL_FIRE_set_verbosity, WILL_FIRE_v_from_masters_0_m_arvalid, @@ -1687,91 +1696,152 @@ module mkFabric_2x3(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8241; - reg [31 : 0] v__h8719; - reg [31 : 0] v__h9197; - reg [31 : 0] v__h9768; - reg [31 : 0] v__h10230; - reg [31 : 0] v__h10692; - reg [31 : 0] v__h11917; - reg [31 : 0] v__h12269; - reg [31 : 0] v__h12621; - reg [31 : 0] v__h13036; - reg [31 : 0] v__h13364; - reg [31 : 0] v__h13692; - reg [31 : 0] v__h14688; - reg [31 : 0] v__h14981; - reg [31 : 0] v__h15274; - reg [31 : 0] v__h15580; - reg [31 : 0] v__h15847; - reg [31 : 0] v__h16114; - reg [31 : 0] v__h16421; - reg [31 : 0] v__h16688; - reg [31 : 0] v__h17035; - reg [31 : 0] v__h17358; - reg [31 : 0] v__h17681; - reg [31 : 0] v__h18008; - reg [31 : 0] v__h18294; - reg [31 : 0] v__h18580; - reg [31 : 0] v__h18905; - reg [31 : 0] v__h19179; - reg [31 : 0] v__h5374; - reg [31 : 0] v__h5368; - reg [31 : 0] v__h8235; - reg [31 : 0] v__h8713; - reg [31 : 0] v__h9191; - reg [31 : 0] v__h9762; - reg [31 : 0] v__h10224; - reg [31 : 0] v__h10686; - reg [31 : 0] v__h11911; - reg [31 : 0] v__h12263; - reg [31 : 0] v__h12615; - reg [31 : 0] v__h13030; - reg [31 : 0] v__h13358; - reg [31 : 0] v__h13686; - reg [31 : 0] v__h14682; - reg [31 : 0] v__h14975; - reg [31 : 0] v__h15268; - reg [31 : 0] v__h15574; - reg [31 : 0] v__h15841; - reg [31 : 0] v__h16108; - reg [31 : 0] v__h16415; - reg [31 : 0] v__h16682; - reg [31 : 0] v__h17029; - reg [31 : 0] v__h17352; - reg [31 : 0] v__h17675; - reg [31 : 0] v__h18002; - reg [31 : 0] v__h18288; - reg [31 : 0] v__h18574; - reg [31 : 0] v__h18899; - reg [31 : 0] v__h19173; + reg [31 : 0] v__h8650; + reg [31 : 0] v__h9025; + reg [31 : 0] v__h9400; + reg [31 : 0] v__h9845; + reg [31 : 0] v__h10214; + reg [31 : 0] v__h10583; + reg [31 : 0] v__h11855; + reg [31 : 0] v__h12298; + reg [31 : 0] v__h12673; + reg [31 : 0] v__h12965; + reg [31 : 0] v__h13257; + reg [31 : 0] v__h13560; + reg [31 : 0] v__h13826; + reg [31 : 0] v__h14092; + reg [31 : 0] v__h14356; + reg [31 : 0] v__h14582; + reg [31 : 0] v__h15011; + reg [31 : 0] v__h15367; + reg [31 : 0] v__h15723; + reg [31 : 0] v__h16140; + reg [31 : 0] v__h16472; + reg [31 : 0] v__h16804; + reg [31 : 0] v__h17820; + reg [31 : 0] v__h18071; + reg [31 : 0] v__h18446; + reg [31 : 0] v__h18687; + reg [31 : 0] v__h19062; + reg [31 : 0] v__h19303; + reg [31 : 0] v__h19665; + reg [31 : 0] v__h19916; + reg [31 : 0] v__h20246; + reg [31 : 0] v__h20487; + reg [31 : 0] v__h20817; + reg [31 : 0] v__h21058; + reg [31 : 0] v__h21571; + reg [31 : 0] v__h21972; + reg [31 : 0] v__h5698; + reg [31 : 0] v__h5692; + reg [31 : 0] v__h8644; + reg [31 : 0] v__h9019; + reg [31 : 0] v__h9394; + reg [31 : 0] v__h9839; + reg [31 : 0] v__h10208; + reg [31 : 0] v__h10577; + reg [31 : 0] v__h11849; + reg [31 : 0] v__h12292; + reg [31 : 0] v__h12667; + reg [31 : 0] v__h12959; + reg [31 : 0] v__h13251; + reg [31 : 0] v__h13554; + reg [31 : 0] v__h13820; + reg [31 : 0] v__h14086; + reg [31 : 0] v__h14350; + reg [31 : 0] v__h14576; + reg [31 : 0] v__h15005; + reg [31 : 0] v__h15361; + reg [31 : 0] v__h15717; + reg [31 : 0] v__h16134; + reg [31 : 0] v__h16466; + reg [31 : 0] v__h16798; + reg [31 : 0] v__h17814; + reg [31 : 0] v__h18065; + reg [31 : 0] v__h18440; + reg [31 : 0] v__h18681; + reg [31 : 0] v__h19056; + reg [31 : 0] v__h19297; + reg [31 : 0] v__h19659; + reg [31 : 0] v__h19910; + reg [31 : 0] v__h20240; + reg [31 : 0] v__h20481; + reg [31 : 0] v__h20811; + reg [31 : 0] v__h21052; + reg [31 : 0] v__h21565; + reg [31 : 0] v__h21966; // synopsys translate_on // remaining internal signals - wire NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11760, + x__h12203, + x__h17957, + x__h18583, + x__h19199, + x__h21503, + x__h21904; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + x1_avValue_rresp__h17935, + x1_avValue_rresp__h18561, + x1_avValue_rresp__h19177; + wire _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538, + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -1962,10 +2032,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2094,10 +2160,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2226,10 +2288,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2307,58 +2365,36 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2372,7 +2408,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2386,7 +2422,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2427,58 +2463,58 @@ module mkFabric_2x3(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2492,7 +2528,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2506,7 +2542,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2584,7 +2620,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2644,7 +2680,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2704,7 +2740,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2764,7 +2800,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2824,7 +2860,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2881,58 +2917,54 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2940,15 +2972,14 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2956,100 +2987,37 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; @@ -3060,7 +3028,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; @@ -3071,7 +3039,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; @@ -3082,7 +3050,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && + fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; @@ -3093,7 +3061,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && + fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; @@ -3104,7 +3072,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && + fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; @@ -3113,8 +3081,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && + fabric_v_f_wr_err_info_0$EMPTY_N && fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; @@ -3123,40 +3090,123 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && + fabric_v_f_wr_err_info_1$EMPTY_N && fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_v_f_rd_sjs_0$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_1 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_2 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_3 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_4 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_5 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3165,9 +3215,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3176,9 +3226,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3187,9 +3237,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3198,8 +3248,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3208,8 +3257,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3219,14 +3267,75 @@ module mkFabric_2x3(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + 8'd0 : + x__h17957 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + 8'd0 : + x__h18583 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + 8'd0 : + x__h19199 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? + 8'd0 : + x__h11760 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ? + 8'd0 : + x__h12203 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3236,67 +3345,156 @@ module mkFabric_2x3(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ? + 8'd0 : + x__h21503 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ? + 8'd0 : + x__h21904 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3319,10 +3517,14 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3345,41 +3547,89 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_0$DEQ = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_1$DEQ = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3390,9 +3640,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3403,9 +3651,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3489,24 +3735,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3547,17 +3793,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3620,24 +3863,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3678,17 +3921,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3770,12 +4010,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3834,12 +4076,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -3898,12 +4142,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -3926,56 +4172,155 @@ module mkFabric_2x3(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 = - fabric_cfg_verbosity > 4'd1 ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 = + assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + x1_avValue_rresp__h17935 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + x1_avValue_rresp__h18561 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + x1_avValue_rresp__h19177 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < + soc_map$m_plic_addr_lim ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 = + soc_map$m_mem0_controller_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h17935 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18561 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19177 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11760 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12203 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h17957 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18583 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19199 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21503 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h21904 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -3985,6 +4330,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -3993,6 +4345,27 @@ module mkFabric_2x3(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4003,6 +4376,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4015,2581 +4395,3009 @@ module mkFabric_2x3(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8241 = $stime; + v__h8650 = $stime; #0; end - v__h8235 = v__h8241 / 32'd10; + v__h8644 = v__h8650 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8235, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8644, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8719 = $stime; + v__h9025 = $stime; #0; end - v__h8713 = v__h8719 / 32'd10; + v__h9019 = v__h9025 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8713, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9019, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h9197 = $stime; + v__h9400 = $stime; #0; end - v__h9191 = v__h9197 / 32'd10; + v__h9394 = v__h9400 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9191, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9394, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9845 = $stime; + #0; + end + v__h9839 = v__h9845 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9839, + $signed(32'd1), + $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10214 = $stime; + #0; + end + v__h10208 = v__h10214 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10208, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10583 = $stime; + #0; + end + v__h10577 = v__h10583 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10577, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h11855 = $stime; + #0; + end + v__h11849 = v__h11855 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h11849, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9768 = $stime; + v__h12298 = $stime; #0; end - v__h9762 = v__h9768 / 32'd10; + v__h12292 = v__h12298 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9762, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12292, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10230 = $stime; - #0; - end - v__h10224 = v__h10230 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10224, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10692 = $stime; - #0; - end - v__h10686 = v__h10692 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10686, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h11917 = $stime; - #0; - end - v__h11911 = v__h11917 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h11911, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12269 = $stime; - #0; - end - v__h12263 = v__h12269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12263, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12621 = $stime; - #0; - end - v__h12615 = v__h12621 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12615, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13036 = $stime; - #0; - end - v__h13030 = v__h13036 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13030, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13364 = $stime; - #0; - end - v__h13358 = v__h13364 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13358, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13692 = $stime; - #0; - end - v__h13686 = v__h13692 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13686, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h14688 = $stime; + v__h12673 = $stime; #0; end - v__h14682 = v__h14688 / 32'd10; + v__h12667 = v__h12673 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h14682, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12667, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h14981 = $stime; + v__h12965 = $stime; #0; end - v__h14975 = v__h14981 / 32'd10; + v__h12959 = v__h12965 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h14975, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12959, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15274 = $stime; + v__h13257 = $stime; #0; end - v__h15268 = v__h15274 / 32'd10; + v__h13251 = v__h13257 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15268, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13251, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15580 = $stime; + v__h13560 = $stime; #0; end - v__h15574 = v__h15580 / 32'd10; + v__h13554 = v__h13560 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15574, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13554, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15847 = $stime; + v__h13826 = $stime; #0; end - v__h15841 = v__h15847 / 32'd10; + v__h13820 = v__h13826 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15841, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13820, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16114 = $stime; + v__h14092 = $stime; #0; end - v__h16108 = v__h16114 / 32'd10; + v__h14086 = v__h14092 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16108, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14086, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16421 = $stime; + v__h14356 = $stime; #0; end - v__h16415 = v__h16421 / 32'd10; + v__h14350 = v__h14356 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16415, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14350, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16688 = $stime; + v__h14582 = $stime; #0; end - v__h16682 = v__h16688 / 32'd10; + v__h14576 = v__h14582 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16682, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14576, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15011 = $stime; + #0; + end + v__h15005 = v__h15011 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15005, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15367 = $stime; + #0; + end + v__h15361 = v__h15367 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15361, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15723 = $stime; + #0; + end + v__h15717 = v__h15723 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15717, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16140 = $stime; + #0; + end + v__h16134 = v__h16140 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16134, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16472 = $stime; + #0; + end + v__h16466 = v__h16472 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16466, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16804 = $stime; + #0; + end + v__h16798 = v__h16804 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16798, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17035 = $stime; + v__h17820 = $stime; #0; end - v__h17029 = v__h17035 / 32'd10; + v__h17814 = v__h17820 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17029, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h17814, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18071 = $stime; + #0; + end + v__h18065 = v__h18071 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18065, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17358 = $stime; + v__h18446 = $stime; #0; end - v__h17352 = v__h17358 / 32'd10; + v__h18440 = v__h18446 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17352, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18440, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h18687 = $stime; + #0; + end + v__h18681 = v__h18687 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18681, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h17681 = $stime; + v__h19062 = $stime; #0; end - v__h17675 = v__h17681 / 32'd10; + v__h19056 = v__h19062 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17675, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19056, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19303 = $stime; + #0; + end + v__h19297 = v__h19303 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19297, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18008 = $stime; + v__h19665 = $stime; #0; end - v__h18002 = v__h18008 / 32'd10; + v__h19659 = v__h19665 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18002, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19659, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19916 = $stime; + #0; + end + v__h19910 = v__h19916 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19910, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18294 = $stime; + v__h20246 = $stime; #0; end - v__h18288 = v__h18294 / 32'd10; + v__h20240 = v__h20246 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18288, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20240, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20487 = $stime; + #0; + end + v__h20481 = v__h20487 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20481, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18580 = $stime; + v__h20817 = $stime; #0; end - v__h18574 = v__h18580 / 32'd10; + v__h20811 = v__h20817 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18574, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20811, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21058 = $stime; + #0; + end + v__h21052 = v__h21058 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21052, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h18905 = $stime; + v__h21571 = $stime; #0; end - v__h18899 = v__h18905 / 32'd10; + v__h21565 = v__h21571 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h18899, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21565, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19179 = $stime; + v__h21972 = $stime; #0; end - v__h19173 = v__h19179 / 32'd10; + v__h21966 = v__h21972 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19173, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21966, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5374 = $stime; + v__h5698 = $stime; #0; end - v__h5368 = v__h5374 / 32'd10; + v__h5692 = v__h5698 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5368); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); end // synopsys translate_on endmodule // mkFabric_2x3 diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v index be05e55..4786808 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric_AXI4(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric_AXI4(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric_AXI4(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric_AXI4(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric_AXI4(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric_AXI4(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric_AXI4(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric_AXI4(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric_AXI4(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric_AXI4(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,38 +1175,59 @@ module mkFabric_AXI4(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ, - fabric_v_f_rd_err_id_0$FULL_N; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ, - fabric_v_f_rd_err_id_1$FULL_N; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ, - fabric_v_f_rd_err_user_0$FULL_N; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ, - fabric_v_f_rd_err_user_1$FULL_N; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ, + fabric_v_f_rd_err_info_0$FULL_N; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ, + fabric_v_f_rd_err_info_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1241,7 +1235,7 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1249,7 +1243,7 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1274,56 +1268,63 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ, - fabric_v_f_wr_err_id_0$FULL_N; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ, - fabric_v_f_wr_err_id_1$FULL_N; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ, - fabric_v_f_wr_err_user_0$FULL_N; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ, + fabric_v_f_wr_err_info_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ, - fabric_v_f_wr_err_user_1$FULL_N; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ, + fabric_v_f_wr_err_info_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1374,7 +1375,7 @@ module mkFabric_AXI4(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1419,7 +1420,7 @@ module mkFabric_AXI4(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1464,7 +1465,7 @@ module mkFabric_AXI4(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1509,7 +1510,7 @@ module mkFabric_AXI4(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1554,7 +1555,7 @@ module mkFabric_AXI4(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1614,6 +1615,8 @@ module mkFabric_AXI4(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, CAN_FIRE_reset, @@ -1674,6 +1677,8 @@ module mkFabric_AXI4(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, WILL_FIRE_reset, @@ -1705,119 +1710,182 @@ module mkFabric_AXI4(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8274; - reg [31 : 0] v__h8777; - reg [31 : 0] v__h9280; - reg [31 : 0] v__h9876; - reg [31 : 0] v__h10363; - reg [31 : 0] v__h10850; - reg [31 : 0] v__h11306; - reg [31 : 0] v__h11679; - reg [31 : 0] v__h12144; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13338; - reg [31 : 0] v__h13691; - reg [31 : 0] v__h14044; - reg [31 : 0] v__h14407; - reg [31 : 0] v__h14734; - reg [31 : 0] v__h15084; - reg [31 : 0] v__h15377; - reg [31 : 0] v__h15670; - reg [31 : 0] v__h15976; - reg [31 : 0] v__h16243; - reg [31 : 0] v__h16510; - reg [31 : 0] v__h16817; - reg [31 : 0] v__h17084; - reg [31 : 0] v__h17431; - reg [31 : 0] v__h17754; - reg [31 : 0] v__h18077; - reg [31 : 0] v__h18404; - reg [31 : 0] v__h18690; - reg [31 : 0] v__h18976; - reg [31 : 0] v__h19301; - reg [31 : 0] v__h19575; - reg [31 : 0] v__h5374; - reg [31 : 0] v__h5368; - reg [31 : 0] v__h8268; - reg [31 : 0] v__h8771; - reg [31 : 0] v__h9274; - reg [31 : 0] v__h9870; - reg [31 : 0] v__h10357; - reg [31 : 0] v__h10844; - reg [31 : 0] v__h11300; - reg [31 : 0] v__h11673; - reg [31 : 0] v__h12138; - reg [31 : 0] v__h12515; - reg [31 : 0] v__h12892; - reg [31 : 0] v__h13332; - reg [31 : 0] v__h13685; - reg [31 : 0] v__h14038; - reg [31 : 0] v__h14401; - reg [31 : 0] v__h14728; - reg [31 : 0] v__h15078; - reg [31 : 0] v__h15371; - reg [31 : 0] v__h15664; - reg [31 : 0] v__h15970; - reg [31 : 0] v__h16237; - reg [31 : 0] v__h16504; - reg [31 : 0] v__h16811; - reg [31 : 0] v__h17078; - reg [31 : 0] v__h17425; - reg [31 : 0] v__h17748; - reg [31 : 0] v__h18071; - reg [31 : 0] v__h18398; - reg [31 : 0] v__h18684; - reg [31 : 0] v__h18970; - reg [31 : 0] v__h19295; - reg [31 : 0] v__h19569; + reg [31 : 0] v__h8683; + reg [31 : 0] v__h9083; + reg [31 : 0] v__h9483; + reg [31 : 0] v__h9953; + reg [31 : 0] v__h10347; + reg [31 : 0] v__h10741; + reg [31 : 0] v__h11189; + reg [31 : 0] v__h11593; + reg [31 : 0] v__h12057; + reg [31 : 0] v__h12500; + reg [31 : 0] v__h12875; + reg [31 : 0] v__h13167; + reg [31 : 0] v__h13459; + reg [31 : 0] v__h13762; + reg [31 : 0] v__h14028; + reg [31 : 0] v__h14294; + reg [31 : 0] v__h14558; + reg [31 : 0] v__h14784; + reg [31 : 0] v__h15238; + reg [31 : 0] v__h15619; + reg [31 : 0] v__h16000; + reg [31 : 0] v__h16442; + reg [31 : 0] v__h16799; + reg [31 : 0] v__h17156; + reg [31 : 0] v__h17507; + reg [31 : 0] v__h17808; + reg [31 : 0] v__h18216; + reg [31 : 0] v__h18467; + reg [31 : 0] v__h18842; + reg [31 : 0] v__h19083; + reg [31 : 0] v__h19458; + reg [31 : 0] v__h19699; + reg [31 : 0] v__h20061; + reg [31 : 0] v__h20312; + reg [31 : 0] v__h20642; + reg [31 : 0] v__h20883; + reg [31 : 0] v__h21213; + reg [31 : 0] v__h21454; + reg [31 : 0] v__h21967; + reg [31 : 0] v__h22368; + reg [31 : 0] v__h5698; + reg [31 : 0] v__h5692; + reg [31 : 0] v__h8677; + reg [31 : 0] v__h9077; + reg [31 : 0] v__h9477; + reg [31 : 0] v__h9947; + reg [31 : 0] v__h10341; + reg [31 : 0] v__h10735; + reg [31 : 0] v__h11183; + reg [31 : 0] v__h11587; + reg [31 : 0] v__h12051; + reg [31 : 0] v__h12494; + reg [31 : 0] v__h12869; + reg [31 : 0] v__h13161; + reg [31 : 0] v__h13453; + reg [31 : 0] v__h13756; + reg [31 : 0] v__h14022; + reg [31 : 0] v__h14288; + reg [31 : 0] v__h14552; + reg [31 : 0] v__h14778; + reg [31 : 0] v__h15232; + reg [31 : 0] v__h15613; + reg [31 : 0] v__h15994; + reg [31 : 0] v__h16436; + reg [31 : 0] v__h16793; + reg [31 : 0] v__h17150; + reg [31 : 0] v__h17501; + reg [31 : 0] v__h17802; + reg [31 : 0] v__h18210; + reg [31 : 0] v__h18461; + reg [31 : 0] v__h18836; + reg [31 : 0] v__h19077; + reg [31 : 0] v__h19452; + reg [31 : 0] v__h19693; + reg [31 : 0] v__h20055; + reg [31 : 0] v__h20306; + reg [31 : 0] v__h20636; + reg [31 : 0] v__h20877; + reg [31 : 0] v__h21207; + reg [31 : 0] v__h21448; + reg [31 : 0] v__h21961; + reg [31 : 0] v__h22362; // synopsys translate_on // remaining internal signals - wire [1 : 0] IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270, - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36; - wire NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314, - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23, - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263, - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11962, + x__h12405, + x__h18353, + x__h18979, + x__h19595, + x__h21899, + x__h22300; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340, + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396, + x1_avValue_rresp__h18331, + x1_avValue_rresp__h18957, + x1_avValue_rresp__h19573; + wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439, + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457, + _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, + fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550, + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622, + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640, + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386, + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389, + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -2008,10 +2076,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2140,10 +2204,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2272,10 +2332,6 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2353,58 +2409,36 @@ module mkFabric_AXI4(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_id_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_id_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(fabric_v_f_rd_err_user_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(fabric_v_f_rd_err_user_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2418,7 +2452,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2432,7 +2466,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2473,58 +2507,58 @@ module mkFabric_AXI4(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_id_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_id_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(fabric_v_f_wr_err_user_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(fabric_v_f_wr_err_user_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2538,7 +2572,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2552,7 +2586,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2630,7 +2664,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2690,7 +2724,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2750,7 +2784,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2810,7 +2844,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2870,7 +2904,7 @@ module mkFabric_AXI4(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2927,13 +2961,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2941,13 +2974,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2955,13 +2987,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; @@ -2969,13 +3000,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && @@ -2984,13 +3014,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && @@ -2999,13 +3028,12 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && @@ -3014,33 +3042,133 @@ module mkFabric_AXI4(CLK, // rule RL_fabric_rl_wr_xaction_no_such_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - fabric_v_f_wr_err_id_0$FULL_N && - fabric_v_f_wr_err_user_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169 ; + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wr_err_info_0$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; // rule RL_fabric_rl_wr_xaction_no_such_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - fabric_v_f_wr_err_id_1$FULL_N && - fabric_v_f_wr_err_user_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189 ; + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wr_err_info_1$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; + + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = + fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + !fabric_v_f_wr_mis_0$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_1 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_1$EMPTY_N && + fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && + !fabric_v_f_wr_mis_1$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_2 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_2$EMPTY_N && + fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && + !fabric_v_f_wr_mis_2$D_OUT && + fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_3 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = + fabric_v_f_wr_mis_0$EMPTY_N && + fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_0$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_4 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = + fabric_v_f_wr_mis_1$EMPTY_N && + fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_1$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; + + // rule RL_fabric_rl_wr_resp_slave_to_master_5 + assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = + fabric_v_f_wr_mis_2$EMPTY_N && + fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_mis_2$D_OUT && + fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = + CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; + + // rule RL_fabric_rl_wr_resp_err_to_master + assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = + fabric_v_f_wr_sjs_0$EMPTY_N && + fabric_xactors_from_masters_0_f_wr_resp$FULL_N && + fabric_v_f_wr_err_info_0$EMPTY_N && + fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = + CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; + + // rule RL_fabric_rl_wr_resp_err_to_master_1 + assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = + fabric_v_f_wr_sjs_1$EMPTY_N && + fabric_xactors_from_masters_1_f_wr_resp$FULL_N && + fabric_v_f_wr_err_info_1$EMPTY_N && + fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; + assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = + CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && fabric_v_f_rd_mis_0$FULL_N && fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; @@ -3051,8 +3179,8 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; @@ -3063,8 +3191,8 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; @@ -3075,8 +3203,8 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_mis_0$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && @@ -3088,8 +3216,8 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_mis_1$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && @@ -3101,8 +3229,8 @@ module mkFabric_AXI4(CLK, fabric_v_f_rd_mis_2$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 && - IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 == + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && + IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && @@ -3112,9 +3240,8 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_id_0$FULL_N && - fabric_v_f_rd_err_user_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314 ; + fabric_v_f_rd_err_info_0$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; @@ -3122,125 +3249,46 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_id_1$FULL_N && - fabric_v_f_rd_err_user_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333 ; + fabric_v_f_rd_err_info_1$FULL_N && + NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3249,9 +3297,9 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3260,9 +3308,9 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3271,9 +3319,9 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3282,8 +3330,7 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3292,8 +3339,7 @@ module mkFabric_AXI4(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3303,14 +3349,79 @@ module mkFabric_AXI4(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = + { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = + { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? + 8'd0 : + x__h18353 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? + 8'd0 : + x__h18979 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? + 8'd0 : + x__h19595 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? + 8'd0 : + x__h11962 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ? + 8'd0 : + x__h12405 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3320,73 +3431,162 @@ module mkFabric_AXI4(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] ; - assign fabric_v_f_rd_err_id_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ? + 8'd0 : + x__h21899 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] ; - assign fabric_v_f_rd_err_id_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ? + 8'd0 : + x__h22300 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; + + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = + { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; + assign fabric_v_f_rd_err_info_0$ENQ = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = + { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; + assign fabric_v_f_rd_err_info_1$ENQ = CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3413,10 +3613,14 @@ module mkFabric_AXI4(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3443,47 +3647,103 @@ module mkFabric_AXI4(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_id_0$ENQ = + assign fabric_v_f_wr_err_info_0$ENQ = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_id_0$DEQ = + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_id_1$ENQ = + assign fabric_v_f_wr_err_info_1$ENQ = CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_id_1$DEQ = + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3494,9 +3754,7 @@ module mkFabric_AXI4(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3507,9 +3765,7 @@ module mkFabric_AXI4(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3602,24 +3858,24 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3661,18 +3917,15 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3736,24 +3989,24 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3795,18 +4048,15 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3888,12 +4138,14 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3952,12 +4204,14 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -4016,12 +4270,14 @@ module mkFabric_AXI4(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -4044,168 +4300,267 @@ module mkFabric_AXI4(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d114 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102) ? + assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498 = + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? + x1_avValue_rresp__h18331 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537 = + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? + x1_avValue_rresp__h18957 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576 = + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? + x1_avValue_rresp__h19573 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d215 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d270 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) ? 2'd0 : 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__5_ULE__ETC___d36 = - (soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20) ? + assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 = + (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) ? 2'd1 : - ((soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25) ? + ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) ? 2'd0 : 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d169 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d189 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d314 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209) ; - assign NOT_soc_map_m_mem0_controller_addr_base__5_ULE_ETC___d333 = - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258) && - (!soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261) && - (!soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264) ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203 = + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334) ; + assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 = + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) && + (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) && + (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390) ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 = + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 = + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 = + soc_map$m_boot_rom_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 = soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 = - soc_map$m_mem0_controller_addr_base <= + assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = + soc_map$m_boot_rom_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d111 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d101 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d102 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d104 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d105 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d108 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d212 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d202 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d203 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d205 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d206 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d209 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d267 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d257 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d258 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d260 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d261 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d264 ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d33 = - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d20 || - soc_map_m_boot_rom_addr_base__2_ULE_fabric_xac_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d25 || - soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d30 ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d107 = - soc_map$m_uart0_addr_base <= + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = + soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d208 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d263 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__7_ULE_fabric_xactor_ETC___d28 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || + soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || + soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = soc_map$m_uart0_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = + soc_map$m_uart0_addr_base <= + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h18331 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18957 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19573 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11962 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12405 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h18353 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18979 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19595 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21899 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h22300 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -4215,6 +4570,13 @@ module mkFabric_AXI4(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -4223,6 +4585,27 @@ module mkFabric_AXI4(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4233,6 +4616,13 @@ module mkFabric_AXI4(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4245,3021 +4635,3449 @@ module mkFabric_AXI4(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h8274 = $stime; + v__h8683 = $stime; #0; end - v__h8268 = v__h8274 / 32'd10; + v__h8677 = v__h8683 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8268, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8677, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9083 = $stime; + #0; + end + v__h9077 = v__h9083 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9077, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9483 = $stime; + #0; + end + v__h9477 = v__h9483 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9477, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9953 = $stime; + #0; + end + v__h9947 = v__h9953 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9947, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10347 = $stime; + #0; + end + v__h10341 = v__h10347 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10341, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10741 = $stime; + #0; + end + v__h10735 = v__h10741 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10735, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h11189 = $stime; + #0; + end + v__h11183 = v__h11189 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", + v__h11183, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h11593 = $stime; + #0; + end + v__h11587 = v__h11593 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", + v__h11587, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h12057 = $stime; + #0; + end + v__h12051 = v__h12057 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12051, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h8777 = $stime; - #0; - end - v__h8771 = v__h8777 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8771, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h9280 = $stime; - #0; - end - v__h9274 = v__h9280 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9274, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9876 = $stime; + v__h12500 = $stime; #0; end - v__h9870 = v__h9876 / 32'd10; + v__h12494 = v__h12500 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9870, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12494, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h10363 = $stime; - #0; - end - v__h10357 = v__h10363 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10357, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h10850 = $stime; - #0; - end - v__h10844 = v__h10850 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10844, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h11306 = $stime; - #0; - end - v__h11300 = v__h11306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", - v__h11300, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h11679 = $stime; - #0; - end - v__h11673 = v__h11679 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", - v__h11673, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12144 = $stime; - #0; - end - v__h12138 = v__h12144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12138, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12521 = $stime; - #0; - end - v__h12515 = v__h12521 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12515, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h12898 = $stime; - #0; - end - v__h12892 = v__h12898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12892, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h13338 = $stime; - #0; - end - v__h13332 = v__h13338 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13332, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h13691 = $stime; - #0; - end - v__h13685 = v__h13691 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13685, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14044 = $stime; - #0; - end - v__h14038 = v__h14044 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h14038, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14407 = $stime; - #0; - end - v__h14401 = v__h14407 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", - v__h14401, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - begin - v__h14734 = $stime; - #0; - end - v__h14728 = v__h14734 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", - v__h14728, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15084 = $stime; + v__h12875 = $stime; #0; end - v__h15078 = v__h15084 / 32'd10; + v__h12869 = v__h12875 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15078, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12869, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15377 = $stime; + v__h13167 = $stime; #0; end - v__h15371 = v__h15377 / 32'd10; + v__h13161 = v__h13167 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15371, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13161, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15670 = $stime; + v__h13459 = $stime; #0; end - v__h15664 = v__h15670 / 32'd10; + v__h13453 = v__h13459 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15664, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13453, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h15976 = $stime; + v__h13762 = $stime; #0; end - v__h15970 = v__h15976 / 32'd10; + v__h13756 = v__h13762 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15970, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13756, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16243 = $stime; + v__h14028 = $stime; #0; end - v__h16237 = v__h16243 / 32'd10; + v__h14022 = v__h14028 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16237, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14022, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16510 = $stime; + v__h14294 = $stime; #0; end - v__h16504 = v__h16510 / 32'd10; + v__h14288 = v__h14294 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16504, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14288, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h16817 = $stime; + v__h14558 = $stime; #0; end - v__h16811 = v__h16817 / 32'd10; + v__h14552 = v__h14558 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16811, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14552, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h17084 = $stime; + v__h14784 = $stime; #0; end - v__h17078 = v__h17084 / 32'd10; + v__h14778 = v__h14784 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h17078, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14778, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15238 = $stime; + #0; + end + v__h15232 = v__h15238 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15232, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15619 = $stime; + #0; + end + v__h15613 = v__h15619 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15613, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16000 = $stime; + #0; + end + v__h15994 = v__h16000 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15994, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16442 = $stime; + #0; + end + v__h16436 = v__h16442 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16436, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16799 = $stime; + #0; + end + v__h16793 = v__h16799 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16793, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h17156 = $stime; + #0; + end + v__h17150 = v__h17156 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h17150, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h17507 = $stime; + #0; + end + v__h17501 = v__h17507 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", + v__h17501, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h17808 = $stime; + #0; + end + v__h17802 = v__h17808 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", + v__h17802, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17431 = $stime; + v__h18216 = $stime; #0; end - v__h17425 = v__h17431 / 32'd10; + v__h18210 = v__h18216 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17425, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18210, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18467 = $stime; + #0; + end + v__h18461 = v__h18467 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18461, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17754 = $stime; + v__h18842 = $stime; #0; end - v__h17748 = v__h17754 / 32'd10; + v__h18836 = v__h18842 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17748, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18836, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19083 = $stime; + #0; + end + v__h19077 = v__h19083 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19077, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18077 = $stime; + v__h19458 = $stime; #0; end - v__h18071 = v__h18077 / 32'd10; + v__h19452 = v__h19458 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18071, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19452, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19699 = $stime; + #0; + end + v__h19693 = v__h19699 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19693, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18404 = $stime; + v__h20061 = $stime; #0; end - v__h18398 = v__h18404 / 32'd10; + v__h20055 = v__h20061 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18398, + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20055, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20312 = $stime; + #0; + end + v__h20306 = v__h20312 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20306, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18690 = $stime; + v__h20642 = $stime; #0; end - v__h18684 = v__h18690 / 32'd10; + v__h20636 = v__h20642 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18684, + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20636, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20883 = $stime; + #0; + end + v__h20877 = v__h20883 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20877, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18976 = $stime; + v__h21213 = $stime; #0; end - v__h18970 = v__h18976 / 32'd10; + v__h21207 = v__h21213 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18970, + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h21207, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43 && + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21454 = $stime; + #0; + end + v__h21448 = v__h21454 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21448, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h19301 = $stime; + v__h21967 = $stime; #0; end - v__h19295 = v__h19301 / 32'd10; + v__h21961 = v__h21967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19295, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21961, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) begin - v__h19575 = $stime; + v__h22368 = $stime; #0; end - v__h19569 = v__h19575 / 32'd10; + v__h22362 = v__h22368 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19569, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h22362, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__1_ULE_1_2___d43) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5374 = $stime; + v__h5698 = $stime; #0; end - v__h5368 = v__h5374 / 32'd10; + v__h5692 = v__h5698 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5368); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); end // synopsys translate_on endmodule // mkFabric_AXI4 diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v index a3f2d12..01ed3ba 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v @@ -177,7 +177,6 @@ module mkMemLoader(CLK_portalClk, // inlined wires wire [640 : 0] memReqQ_enqReq_lat_0$wget; - wire memReqQ_enqReq_lat_0$whas; // register busy reg busy; @@ -680,6 +679,7 @@ module mkMemLoader(CLK_portalClk, wire MUX_busy$write_1__SEL_1, MUX_busy$write_1__SEL_2, MUX_expectWrData$write_1__SEL_1, + MUX_pendStCnt$write_1__SEL_2, MUX_writing$write_1__SEL_2; // remaining internal signals @@ -693,15 +693,15 @@ module mkMemLoader(CLK_portalClk, x_addr__h44134, x_wget__h7957; wire [47 : 0] IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d871; - wire [31 : 0] IF_hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_X_ETC___d157, + wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, + IF_hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_X_ETC___d157, + IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, + IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, - IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864, - x__h10336, - x__h1966, - x__h7547; + IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864; wire [7 : 0] IF_reqSel_69_EQ_0_76_THEN_hostWrDataQ_q_wDataO_ETC___d480, IF_reqSel_69_EQ_1_97_THEN_hostWrDataQ_q_wDataO_ETC___d499, IF_reqSel_69_EQ_2_16_THEN_hostWrDataQ_q_wDataO_ETC___d518, @@ -1328,10 +1328,13 @@ module mkMemLoader(CLK_portalClk, mmio_req_wrBE_BIT_0_31_OR_mmio_req_wrBE_BIT_1__ETC___d849 ; assign MUX_expectWrData$write_1__SEL_1 = WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ; + assign MUX_pendStCnt$write_1__SEL_2 = + WILL_FIRE_RL_doStReq && + reqSel_69_EQ_7_70_OR_hostWrDataQ_q_wDataOut_wg_ETC___d800 ; assign MUX_writing$write_1__SEL_2 = WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ; assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostStartQ_q_rRdPtr_rsCounter[x__h7547[0]]) ? + (~hostStartQ_q_rRdPtr_rsCounter[IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187[0]]) ? hostStartQ_q_rRdPtr_rsCounter | x__h7382 : hostStartQ_q_rRdPtr_rsCounter & y__h7569 ; assign MUX_hostStartQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1339,7 +1342,7 @@ module mkMemLoader(CLK_portalClk, hostStartQ_q_rWrPtr_rsCounter | x__h6527 : hostStartQ_q_rWrPtr_rsCounter & y__h6714 ; assign MUX_hostWrAddrQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrAddrQ_q_rRdPtr_rsCounter[x__h1966[0]]) ? + (~hostWrAddrQ_q_rRdPtr_rsCounter[IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41[0]]) ? hostWrAddrQ_q_rRdPtr_rsCounter | x__h1801 : hostWrAddrQ_q_rRdPtr_rsCounter & y__h1988 ; assign MUX_hostWrAddrQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1355,7 +1358,7 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rWrPtr_rsCounter | x__h3738 : hostWrDataQ_q_rWrPtr_rsCounter & y__h3925 ; assign MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDoneQ_q_rRdPtr_rsCounter[x__h10336[0]]) ? + (~hostWrDoneQ_q_rRdPtr_rsCounter[IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260[0]]) ? hostWrDoneQ_q_rRdPtr_rsCounter | x__h10171 : hostWrDoneQ_q_rRdPtr_rsCounter & y__h10358 ; assign MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1392,9 +1395,6 @@ module mkMemLoader(CLK_portalClk, IF_reqSel_69_EQ_1_97_THEN_hostWrDataQ_q_wDataO_ETC___d499, IF_reqSel_69_EQ_0_76_THEN_hostWrDataQ_q_wDataO_ETC___d480, IF_reqSel_69_EQ_7_70_THEN_hostWrDataQ_q_wDataO_ETC___d726 } ; - assign memReqQ_enqReq_lat_0$whas = - WILL_FIRE_RL_doStReq && - reqSel_69_EQ_7_70_OR_hostWrDataQ_q_wDataOut_wg_ETC___d800 ; // register busy assign busy$D_IN = !MUX_busy$write_1__SEL_1 ; @@ -1569,7 +1569,7 @@ module mkMemLoader(CLK_portalClk, // register memReqQ_data_0 assign memReqQ_data_0$D_IN = { x_addr__h44134, - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[575:0] : memReqQ_enqReq_rl[575:0] } ; assign memReqQ_data_0$EN = @@ -1604,13 +1604,13 @@ module mkMemLoader(CLK_portalClk, // register pendStCnt always@(MUX_expectWrData$write_1__SEL_1 or - memReqQ_enqReq_lat_0$whas or + MUX_pendStCnt$write_1__SEL_2 or MUX_pendStCnt$write_1__VAL_2 or WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3) begin case (1'b1) // synopsys parallel_case MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0; - memReqQ_enqReq_lat_0$whas: + MUX_pendStCnt$write_1__SEL_2: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2; WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3; default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ; @@ -1772,7 +1772,7 @@ module mkMemLoader(CLK_portalClk, // submodule memReqQ_enqReq_dummy2_0 assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ; + assign memReqQ_enqReq_dummy2_0$EN = MUX_pendStCnt$write_1__SEL_2 ; // submodule memReqQ_enqReq_dummy2_1 assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; @@ -1815,10 +1815,18 @@ module mkMemLoader(CLK_portalClk, assign respStQ_enqReq_dummy2_2$EN = 1'd1 ; // remaining internal signals + assign IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187 = + hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186 ? + 32'd1 : + 32'd0 ; assign IF_hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_X_ETC___d157 = hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_XOR__ETC___d156 ? 32'd1 : 32'd0 ; + assign IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 = + hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 ? + 32'd1 : + 32'd0 ; assign IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 = hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ? 32'd1 : @@ -1831,12 +1839,16 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? 32'd1 : 32'd0 ; + assign IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 = + hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? + 32'd1 : + 32'd0 ; assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 = hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 ? 32'd1 : 32'd0 ; assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[640] : memReqQ_enqReq_rl[640] ; assign IF_mmio_req_wrBE_BIT_7_38_THEN_mmio_req_wrData_ETC___d864 = @@ -2067,7 +2079,7 @@ module mkMemLoader(CLK_portalClk, !memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ; assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 = (!memReqQ_enqReq_dummy2_2$Q_OUT || - (memReqQ_enqReq_lat_0$whas ? + (MUX_pendStCnt$write_1__SEL_2 ? !memReqQ_enqReq_lat_0$wget[640] : !memReqQ_enqReq_rl[640])) && (memReqQ_deqReq_dummy2_2$Q_OUT && @@ -2167,17 +2179,13 @@ module mkMemLoader(CLK_portalClk, (!respStQ_deqReq_dummy2_2$Q_OUT || !CAN_FIRE_RL_doStResp && !respStQ_deqReq_rl) && respStQ_full ; - assign x__h10171 = 2'd1 << x__h10336 ; - assign x__h10336 = - hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ? - 32'd1 : - 32'd0 ; + assign x__h10171 = + 2'd1 << + IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ; assign x__h11131 = x_sReadBin__h10580 + 2'd1 ; - assign x__h1801 = 2'd1 << x__h1966 ; - assign x__h1966 = - hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 ? - 32'd1 : - 32'd0 ; + assign x__h1801 = + 2'd1 << + IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 ; assign x__h2762 = x_sReadBin__h2210 + 2'd1 ; assign x__h3738 = 2'd1 << @@ -2189,11 +2197,9 @@ module mkMemLoader(CLK_portalClk, assign x__h6527 = 2'd1 << IF_hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_X_ETC___d157 ; - assign x__h7382 = 2'd1 << x__h7547 ; - assign x__h7547 = - hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186 ? - 32'd1 : - 32'd0 ; + assign x__h7382 = + 2'd1 << + IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187 ; assign x__h8341 = x_sReadBin__h7791 + 2'd1 ; assign x__h9316 = 2'd1 << @@ -2202,7 +2208,7 @@ module mkMemLoader(CLK_portalClk, 2'd1 << IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 ; assign x_addr__h44134 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[639:576] : memReqQ_enqReq_rl[639:576] ; assign x_dReadBin__h10583 = diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v index e5a766e..e38964e 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v @@ -23,6 +23,7 @@ // to_raw_mem_request_get O 353 // RDY_to_raw_mem_request_get O 1 // RDY_to_raw_mem_response_put O 1 +// status O 8 reg // RDY_set_watch_tohost O 1 const // CLK I 1 clock // RST_N I 1 reset @@ -40,7 +41,6 @@ // slave_awqos I 4 reg // slave_awregion I 4 reg // slave_wvalid I 1 -// slave_wid I 4 reg // slave_wdata I 64 reg // slave_wstrb I 8 reg // slave_wlast I 1 reg @@ -113,7 +113,6 @@ module mkMem_Controller(CLK, slave_awready, slave_wvalid, - slave_wid, slave_wdata, slave_wstrb, slave_wlast, @@ -162,6 +161,8 @@ module mkMem_Controller(CLK, EN_to_raw_mem_response_put, RDY_to_raw_mem_response_put, + status, + set_watch_tohost_watch_tohost, set_watch_tohost_tohost_addr, EN_set_watch_tohost, @@ -201,7 +202,6 @@ module mkMem_Controller(CLK, // action method slave_m_wvalid input slave_wvalid; - input [3 : 0] slave_wid; input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; @@ -269,6 +269,9 @@ module mkMem_Controller(CLK, input EN_to_raw_mem_response_put; output RDY_to_raw_mem_response_put; + // value method status + output [7 : 0] status; + // action method set_watch_tohost input set_watch_tohost_watch_tohost; input [63 : 0] set_watch_tohost_tohost_addr; @@ -278,6 +281,7 @@ module mkMem_Controller(CLK, // signals for module outputs wire [352 : 0] to_raw_mem_request_get; wire [63 : 0] slave_rdata; + wire [7 : 0] status; wire [3 : 0] slave_bid, slave_rid; wire [1 : 0] slave_bresp, slave_rresp; wire RDY_server_reset_request_put, @@ -358,6 +362,11 @@ module mkMem_Controller(CLK, reg [1 : 0] rg_state$D_IN; wire rg_state$EN; + // register rg_status + reg [7 : 0] rg_status; + wire [7 : 0] rg_status$D_IN; + wire rg_status$EN; + // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; @@ -406,7 +415,7 @@ module mkMem_Controller(CLK, slave_xactor_f_wr_addr$FULL_N; // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; wire slave_xactor_f_wr_data$CLR, slave_xactor_f_wr_data$DEQ, slave_xactor_f_wr_data$EMPTY_N, @@ -487,67 +496,67 @@ module mkMem_Controller(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2462; - reg [31 : 0] v__h3405; - reg [31 : 0] v__h3898; - reg [31 : 0] v__h4367; - reg [31 : 0] v__h4630; - reg [31 : 0] v__h5349; - reg [31 : 0] v__h7546; - reg [31 : 0] v__h7747; - reg [31 : 0] v__h8264; - reg [31 : 0] v__h9048; - reg [31 : 0] v__h9641; - reg [31 : 0] v__h2777; - reg [31 : 0] v__h3117; - reg [31 : 0] v__h1706; - reg [31 : 0] v__h2028; - reg [31 : 0] v__h1700; - reg [31 : 0] v__h2022; - reg [31 : 0] v__h2456; - reg [31 : 0] v__h2771; - reg [31 : 0] v__h3111; - reg [31 : 0] v__h3399; - reg [31 : 0] v__h3892; - reg [31 : 0] v__h4361; - reg [31 : 0] v__h4624; - reg [31 : 0] v__h5343; - reg [31 : 0] v__h7540; - reg [31 : 0] v__h7741; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h9042; - reg [31 : 0] v__h9635; + reg [31 : 0] v__h2538; + reg [31 : 0] v__h3474; + reg [31 : 0] v__h3967; + reg [31 : 0] v__h4436; + reg [31 : 0] v__h4699; + reg [31 : 0] v__h5418; + reg [31 : 0] v__h7615; + reg [31 : 0] v__h7816; + reg [31 : 0] v__h8328; + reg [31 : 0] v__h9112; + reg [31 : 0] v__h9707; + reg [31 : 0] v__h2853; + reg [31 : 0] v__h3188; + reg [31 : 0] v__h1743; + reg [31 : 0] v__h2088; + reg [31 : 0] v__h1737; + reg [31 : 0] v__h2082; + reg [31 : 0] v__h2532; + reg [31 : 0] v__h2847; + reg [31 : 0] v__h3182; + reg [31 : 0] v__h3468; + reg [31 : 0] v__h3961; + reg [31 : 0] v__h4430; + reg [31 : 0] v__h4693; + reg [31 : 0] v__h5412; + reg [31 : 0] v__h7609; + reg [31 : 0] v__h7810; + reg [31 : 0] v__h8322; + reg [31 : 0] v__h9106; + reg [31 : 0] v__h9701; // synopsys translate_on // remaining internal signals - reg [63 : 0] rdata__h4992, word64_old__h5786; - wire [63 : 0] exit_value__h7784, + reg [63 : 0] rdata__h5061, word64_old__h5855; + wire [63 : 0] exit_value__h7853, f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5791, - req_raw_mem_addr__h3238, - updated_word64__h5792, - x__h6165, - y__h6166, - y__h6167; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h4991; + mask__h5860, + req_raw_mem_addr__h3307, + updated_word64__h5861, + x__h6234, + y__h6235, + y__h6236; + wire [7 : 0] SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214, + SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, + SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, + SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, + SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, + SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, + SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, + SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190; + wire [4 : 0] n__h5060; wire NOT_cfg_verbosity_read_ULE_1___d5, NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d281, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d286, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; + NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278, + f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127, + f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122, + rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125, + rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134, + rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283, + rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130, + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242; // action method server_reset_request_put assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -629,6 +638,9 @@ module mkMem_Controller(CLK, !f_raw_mem_rsps_rv$port1__read[256] ; assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; + // value method status + assign status = rg_status ; + // action method set_watch_tohost assign RDY_set_watch_tohost = 1'd1 ; assign CAN_FIRE_set_watch_tohost = 1'd1 ; @@ -686,7 +698,7 @@ module mkMem_Controller(CLK, .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), + FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(slave_xactor_f_wr_data$D_IN), .ENQ(slave_xactor_f_wr_data$ENQ), @@ -724,16 +736,16 @@ module mkMem_Controller(CLK, // rule RL_rl_writeback_dirty assign CAN_FIRE_RL_rl_writeback_dirty = !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && + rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && + !rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && !rg_cached_clean ; assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; // rule RL_rl_miss_clean_req assign CAN_FIRE_RL_rl_miss_clean_req = f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && + rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && + !rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && rg_cached_clean ; assign WILL_FIRE_RL_rl_miss_clean_req = CAN_FIRE_RL_rl_miss_clean_req && @@ -747,23 +759,23 @@ module mkMem_Controller(CLK, // rule RL_rl_process_rd_req assign CAN_FIRE_RL_rl_process_rd_req = f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && + rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && + rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && !f_reqs_rv[169] ; assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; // rule RL_rl_process_wr_req assign CAN_FIRE_RL_rl_process_wr_req = f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && + rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && + rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && f_reqs_rv[169] ; assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; // rule RL_rl_invalid_rd_address assign CAN_FIRE_RL_rl_invalid_rd_address = f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d286 && + rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 && !f_reqs_rv[169] ; assign WILL_FIRE_RL_rl_invalid_rd_address = CAN_FIRE_RL_rl_invalid_rd_address ; @@ -771,7 +783,7 @@ module mkMem_Controller(CLK, // rule RL_rl_invalid_wr_address assign CAN_FIRE_RL_rl_invalid_wr_address = f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d286 && + rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 && f_reqs_rv[169] ; assign WILL_FIRE_RL_rl_invalid_wr_address = CAN_FIRE_RL_rl_invalid_wr_address ; @@ -813,7 +825,7 @@ module mkMem_Controller(CLK, rg_cached_raw_mem_word } ; assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = { 34'h2FFFFFFFF, - req_raw_mem_addr__h3238, + req_raw_mem_addr__h3307, 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_f_reqs_rv$port1__write_1__VAL_1 = { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; @@ -824,19 +836,19 @@ module mkMem_Controller(CLK, slave_xactor_f_wr_data$D_OUT[72:9] } ; assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5792 : + updated_word64__h5861 : rg_cached_raw_mem_word[255:192], (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5792 : + updated_word64__h5861 : rg_cached_raw_mem_word[191:128], (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5792 : + updated_word64__h5861 : rg_cached_raw_mem_word[127:64], (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5792 : + updated_word64__h5861 : rg_cached_raw_mem_word[63:0] } ; assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h4992, 3'd1 } ; + { f_reqs_rv[168:165], rdata__h5061, 3'd1 } ; assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = { f_reqs_rv[168:101], 3'd5 } ; assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = @@ -950,7 +962,7 @@ module mkMem_Controller(CLK, // register rg_cached_raw_mem_addr assign rg_cached_raw_mem_addr$D_IN = WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3238 : + req_raw_mem_addr__h3307 : 64'd0 ; assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; @@ -980,6 +992,18 @@ module mkMem_Controller(CLK, WILL_FIRE_RL_rl_reset_reload_cache || WILL_FIRE_RL_rl_reload ; + // register rg_status + assign rg_status$D_IN = + (WILL_FIRE_RL_rl_external_reset || + WILL_FIRE_RL_rl_power_on_reset) ? + 8'd0 : + 8'd1 ; + assign rg_status$EN = + WILL_FIRE_RL_rl_process_wr_req && + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 || + WILL_FIRE_RL_rl_external_reset || + WILL_FIRE_RL_rl_power_on_reset ; + // register rg_tohost_addr assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; assign rg_tohost_addr$EN = EN_set_watch_tohost ; @@ -1046,7 +1070,7 @@ module mkMem_Controller(CLK, // submodule slave_xactor_f_wr_data assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; + { slave_wdata, slave_wstrb, slave_wlast } ; assign slave_xactor_f_wr_data$ENQ = slave_wvalid && slave_xactor_f_wr_data$FULL_N ; assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; @@ -1067,7 +1091,7 @@ module mkMem_Controller(CLK, // remaining internal signals assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d281 = + assign NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 = f_reqs_rv[92:90] != 3'b0 && (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && @@ -1076,20 +1100,20 @@ module mkMem_Controller(CLK, (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7784 = { 1'd0, f_reqs_rv[63:1] } ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 = {8{f_reqs_rv[64]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211 = {8{f_reqs_rv[65]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207 = {8{f_reqs_rv[66]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204 = {8{f_reqs_rv[67]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200 = {8{f_reqs_rv[68]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197 = {8{f_reqs_rv[69]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193 = {8{f_reqs_rv[70]}} ; + assign SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190 = {8{f_reqs_rv[71]}} ; + assign exit_value__h7853 = { 1'd0, f_reqs_rv[63:1] } ; assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = + assign f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 = f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = + assign f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 = f_reqs_rv[92:90] == 3'b0 || f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || @@ -1098,65 +1122,65 @@ module mkMem_Controller(CLK, f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5791 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h4991 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3238 = + assign mask__h5860 = + { SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190, + SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, + SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, + SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, + SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, + SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, + SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, + SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ; + assign n__h5060 = { 3'd0, f_reqs_rv[105:104] } ; + assign req_raw_mem_addr__h3307 = { 5'd0, f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = + assign rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 = rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3238 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d286 = + assign rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 = + rg_cached_raw_mem_addr == req_raw_mem_addr__h3307 ; + assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 = rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d281 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = + (NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 || + !rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 || + !f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127) ; + assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 = rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = + f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 && + rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 && + f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 ; + assign rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 = rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5792 = x__h6165 | y__h6166 ; - assign x__h6165 = word64_old__h5786 & y__h6167 ; - assign y__h6166 = f_reqs_rv[63:0] & mask__h5791 ; - assign y__h6167 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; + assign updated_word64__h5861 = x__h6234 | y__h6235 ; + assign x__h6234 = word64_old__h5855 & y__h6236 ; + assign y__h6235 = f_reqs_rv[63:0] & mask__h5860 ; + assign y__h6236 = + { ~SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190, + ~SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, + ~SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, + ~SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, + ~SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, + ~SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, + ~SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, + ~SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ; always@(f_reqs_rv or rg_cached_raw_mem_word) begin case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5786 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5786 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5786 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5786 = rg_cached_raw_mem_word[255:192]; + 2'd0: word64_old__h5855 = rg_cached_raw_mem_word[63:0]; + 2'd1: word64_old__h5855 = rg_cached_raw_mem_word[127:64]; + 2'd2: word64_old__h5855 = rg_cached_raw_mem_word[191:128]; + 2'd3: word64_old__h5855 = rg_cached_raw_mem_word[255:192]; endcase end - always@(n__h4991 or rg_cached_raw_mem_word) + always@(n__h5060 or rg_cached_raw_mem_word) begin - case (n__h4991) - 5'd0: rdata__h4992 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h4992 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h4992 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h4992 = rg_cached_raw_mem_word[255:192]; - default: rdata__h4992 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (n__h5060) + 5'd0: rdata__h5061 = rg_cached_raw_mem_word[63:0]; + 5'd1: rdata__h5061 = rg_cached_raw_mem_word[127:64]; + 5'd2: rdata__h5061 = rg_cached_raw_mem_word[191:128]; + 5'd3: rdata__h5061 = rg_cached_raw_mem_word[255:192]; + default: rdata__h5061 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end @@ -1174,6 +1198,7 @@ module mkMem_Controller(CLK, f_reqs_rv <= `BSV_ASSIGNMENT_DELAY 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; end @@ -1187,6 +1212,7 @@ module mkMem_Controller(CLK, f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; + if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; if (rg_watch_tohost$EN) @@ -1223,6 +1249,7 @@ module mkMem_Controller(CLK, rg_cached_raw_mem_word = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; rg_state = 2'h2; + rg_status = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; rg_watch_tohost = 1'h0; end @@ -1239,68 +1266,68 @@ module mkMem_Controller(CLK, if (WILL_FIRE_RL_rl_reset_reload_cache && NOT_cfg_verbosity_read_ULE_1___d5) begin - v__h2462 = $stime; + v__h2538 = $stime; #0; end - v__h2456 = v__h2462 / 32'd10; + v__h2532 = v__h2538 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_reload_cache && NOT_cfg_verbosity_read_ULE_1___d5) $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2456); + v__h2532); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_writeback_dirty_idle && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h3405 = $stime; + v__h3474 = $stime; #0; end - v__h3399 = v__h3405 / 32'd10; + v__h3468 = v__h3474 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_writeback_dirty_idle && NOT_cfg_verbosity_read_ULE_2_2___d33) $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3399, + v__h3468, rg_cached_raw_mem_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_writeback_dirty && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h3898 = $stime; + v__h3967 = $stime; #0; end - v__h3892 = v__h3898 / 32'd10; + v__h3961 = v__h3967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_writeback_dirty && NOT_cfg_verbosity_read_ULE_2_2___d33) $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3892, + v__h3961, rg_cached_raw_mem_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_miss_clean_req && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h4367 = $stime; + v__h4436 = $stime; #0; end - v__h4361 = v__h4367 / 32'd10; + v__h4430 = v__h4436 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_miss_clean_req && NOT_cfg_verbosity_read_ULE_2_2___d33) $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4361, - req_raw_mem_addr__h3238); + v__h4430, + req_raw_mem_addr__h3307); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h4630 = $stime; + v__h4699 = $stime; #0; end - v__h4624 = v__h4630 / 32'd10; + v__h4693 = v__h4699 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4624, + v__h4693, rg_cached_raw_mem_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) @@ -1314,13 +1341,13 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) begin - v__h5349 = $stime; + v__h5418 = $stime; #0; end - v__h5343 = v__h5349 / 32'd10; + v__h5412 = v__h5418 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5343); + $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5412); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) $write(" "); @@ -1425,7 +1452,7 @@ module mkMem_Controller(CLK, $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h4992); + $write("'h%h", rdata__h5061); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) $write(", ", "rresp: "); @@ -1450,13 +1477,13 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) begin - v__h7546 = $stime; + v__h7615 = $stime; #0; end - v__h7540 = v__h7546 / 32'd10; + v__h7609 = v__h7615 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7540); + $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) $write(" "); @@ -1573,50 +1600,46 @@ module mkMem_Controller(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242) begin - v__h7747 = $stime; + v__h7816 = $stime; #0; end - v__h7741 = v__h7747 / 32'd10; + v__h7810 = v__h7816 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242) $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7741, + v__h7810, f_reqs_rv[164:101], f_reqs_rv[63:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 && f_reqs_rv[63:1] == 63'd0) $display("PASS"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && + rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 && f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7784); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $finish({ 30'd0, f_reqs_rv[2:1] }); + $display("FAIL %0d", exit_value__h7853); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_rd_address) begin - v__h8264 = $stime; + v__h8328 = $stime; #0; end - v__h8258 = v__h8264 / 32'd10; + v__h8322 = v__h8328 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8258); + $write("%0d: ERROR: Mem_Controller:", v__h8322); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d281) + NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278) $display(" read-addr is misaligned"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) + f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122) $display(" read-addr is out of bounds"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_rd_address) @@ -1724,20 +1747,20 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_wr_address) begin - v__h9048 = $stime; + v__h9112 = $stime; #0; end - v__h9042 = v__h9048 / 32'd10; + v__h9106 = v__h9112 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9042); + $write("%0d: ERROR: Mem_Controller:", v__h9106); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d281) + NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278) $display(" write-addr is misaligned"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) + f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122) $display(" write-addr is out of bounds"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_invalid_wr_address) @@ -1836,28 +1859,28 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map) begin - v__h9641 = $stime; + v__h9707 = $stime; #0; end - v__h9635 = v__h9641 / 32'd10; + v__h9701 = v__h9707 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map) $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9635, + v__h9701, set_addr_map_addr_base, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_rd_req && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h2777 = $stime; + v__h2853 = $stime; #0; end - v__h2771 = v__h2777 / 32'd10; + v__h2847 = v__h2853 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_rd_req && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2771); + $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_rd_req && NOT_cfg_verbosity_read_ULE_2_2___d33) @@ -1958,14 +1981,14 @@ module mkMem_Controller(CLK, if (WILL_FIRE_RL_rl_merge_wr_req && NOT_cfg_verbosity_read_ULE_2_2___d33) begin - v__h3117 = $stime; + v__h3188 = $stime; #0; end - v__h3111 = v__h3117 / 32'd10; + v__h3182 = v__h3188 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_wr_req && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3111); + $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3182); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_wr_req && NOT_cfg_verbosity_read_ULE_2_2___d33) @@ -2069,15 +2092,7 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_wr_req && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_merge_wr_req && NOT_cfg_verbosity_read_ULE_2_2___d33) @@ -2119,24 +2134,24 @@ module mkMem_Controller(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) begin - v__h1706 = $stime; + v__h1743 = $stime; #0; end - v__h1700 = v__h1706 / 32'd10; + v__h1737 = v__h1743 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1700); + $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) begin - v__h2028 = $stime; + v__h2088 = $stime; #0; end - v__h2022 = v__h2028 / 32'd10; + v__h2082 = v__h2088 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2022); + v__h2082); end // synopsys translate_on endmodule // mkMem_Controller diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v index 34e9210..f701399 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v @@ -41,7 +41,6 @@ // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg // axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg @@ -133,7 +132,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awready, axi4_slave_wvalid, - axi4_slave_wid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, @@ -253,7 +251,6 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_m_wvalid input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; @@ -814,7 +811,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_wr_addr$FULL_N; // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; wire m_slave_xactor_f_wr_data$CLR, m_slave_xactor_f_wr_data$DEQ, m_slave_xactor_f_wr_data$EMPTY_N, @@ -1015,22 +1012,22 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75673; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76063; - reg [31 : 0] v__h76258; - reg [31 : 0] v__h76453; - reg [31 : 0] v__h76648; - reg [31 : 0] v__h76843; - reg [31 : 0] v__h77038; - reg [31 : 0] v__h77233; - reg [31 : 0] v__h77428; - reg [31 : 0] v__h77623; - reg [31 : 0] v__h77818; - reg [31 : 0] v__h78013; - reg [31 : 0] v__h78208; - reg [31 : 0] v__h78403; - reg [31 : 0] v__h78598; + reg [31 : 0] v__h75658; + reg [31 : 0] v__h75853; + reg [31 : 0] v__h76048; + reg [31 : 0] v__h76243; + reg [31 : 0] v__h76438; + reg [31 : 0] v__h76633; + reg [31 : 0] v__h76828; + reg [31 : 0] v__h77023; + reg [31 : 0] v__h77218; + reg [31 : 0] v__h77413; + reg [31 : 0] v__h77608; + reg [31 : 0] v__h77803; + reg [31 : 0] v__h77998; + reg [31 : 0] v__h78193; + reg [31 : 0] v__h78388; + reg [31 : 0] v__h78583; reg [31 : 0] v__h6144; reg [31 : 0] v__h13080; reg [31 : 0] v__h13265; @@ -1042,19 +1039,19 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h24056; reg [31 : 0] v__h26250; reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; + reg [31 : 0] v__h26737; + reg [31 : 0] v__h26961; + reg [31 : 0] v__h27856; + reg [31 : 0] v__h28039; + reg [31 : 0] v__h67021; + reg [31 : 0] v__h67309; + reg [31 : 0] v__h67838; + reg [31 : 0] v__h67924; + reg [31 : 0] v__h68123; + reg [31 : 0] v__h68342; + reg [31 : 0] v__h74677; + reg [31 : 0] v__h74787; + reg [31 : 0] v__h74900; reg [31 : 0] v__h6138; reg [31 : 0] v__h13074; reg [31 : 0] v__h13259; @@ -1066,42 +1063,42 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h25969; reg [31 : 0] v__h26244; reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75667; - reg [31 : 0] v__h75862; - reg [31 : 0] v__h76057; - reg [31 : 0] v__h76252; - reg [31 : 0] v__h76447; - reg [31 : 0] v__h76642; - reg [31 : 0] v__h76837; - reg [31 : 0] v__h77032; - reg [31 : 0] v__h77227; - reg [31 : 0] v__h77422; - reg [31 : 0] v__h77617; - reg [31 : 0] v__h77812; - reg [31 : 0] v__h78007; - reg [31 : 0] v__h78202; - reg [31 : 0] v__h78397; - reg [31 : 0] v__h78592; + reg [31 : 0] v__h26731; + reg [31 : 0] v__h26955; + reg [31 : 0] v__h27850; + reg [31 : 0] v__h28033; + reg [31 : 0] v__h67015; + reg [31 : 0] v__h67303; + reg [31 : 0] v__h67832; + reg [31 : 0] v__h67918; + reg [31 : 0] v__h68117; + reg [31 : 0] v__h68336; + reg [31 : 0] v__h74671; + reg [31 : 0] v__h74781; + reg [31 : 0] v__h74894; + reg [31 : 0] v__h75652; + reg [31 : 0] v__h75847; + reg [31 : 0] v__h76042; + reg [31 : 0] v__h76237; + reg [31 : 0] v__h76432; + reg [31 : 0] v__h76627; + reg [31 : 0] v__h76822; + reg [31 : 0] v__h77017; + reg [31 : 0] v__h77212; + reg [31 : 0] v__h77407; + reg [31 : 0] v__h77602; + reg [31 : 0] v__h77797; + reg [31 : 0] v__h77992; + reg [31 : 0] v__h78187; + reg [31 : 0] v__h78382; + reg [31 : 0] v__h78577; // synopsys translate_on // remaining internal signals reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; + reg [4 : 0] x__h24011, x__h67478; reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; + reg [1 : 0] v__h67098, y_avValue_snd__h26149; reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, @@ -1150,7 +1147,7 @@ module mkPLIC_16_2_7(CLK, CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, @@ -1248,7 +1245,7 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, + addr_offset__h26922, rdata___1__h26404, rdata__h26202, v__h13422, @@ -1269,9 +1266,9 @@ module mkPLIC_16_2_7(CLK, y_avValue_fst__h26194; wire [31 : 0] v_ie__h18147, v_ip__h13674, - wdata32__h26930, + wdata32__h26923, x__h23673, - x__h67110; + x__h67101; wire [9 : 0] source_id__h15665, source_id__h15772, source_id__h15845, @@ -1334,121 +1331,121 @@ module mkPLIC_16_2_7(CLK, source_id__h23229, source_id__h23337, source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, + source_id__h29466, + source_id__h30676, + source_id__h31886, + source_id__h33096, + source_id__h34306, + source_id__h35516, + source_id__h36726, + source_id__h37936, + source_id__h39146, + source_id__h40356, + source_id__h41566, + source_id__h42776, + source_id__h43986, + source_id__h45196, + source_id__h46406, + source_id__h47616, + source_id__h48826, + source_id__h50036, + source_id__h51246, + source_id__h52456, + source_id__h53666, + source_id__h54876, + source_id__h56086, + source_id__h57296, + source_id__h58506, + source_id__h59716, + source_id__h60926, + source_id__h62136, + source_id__h63346, + source_id__h64556, + source_id__h65766, + source_id__h67427, source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, + source_id_base__h28139; + wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, + b__h71300, + b__h73305, max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, + wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; + a__h71299, + a__h73304; wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, + v__h26927, + v__h27085, + v__h27098, + v__h27933, + v__h27952, + v__h28116, + v__h28135, + v__h67135, + v__h67423, + v__h67467, y_avValue_snd__h26095, y_avValue_snd__h26116, y_avValue_snd__h26128, @@ -1460,8 +1457,8 @@ module mkPLIC_16_2_7(CLK, y_avValue_snd__h26195; wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, NOT_m_cfg_verbosity_read_ULE_1_5___d16, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, @@ -1469,62 +1466,62 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320, - NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328, - NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336, - NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344, - NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352, - NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360, - NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256, - NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264, - NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272, - NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280, - NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288, - NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296, - NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304, - NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, + NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240, + NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318, + NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326, + NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334, + NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342, + NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350, + NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358, + NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247, + NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254, + NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262, + NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270, + NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278, + NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286, + NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294, + NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302, + NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310, _dfoo1, _dfoo10, _dfoo100, @@ -3098,83 +3095,83 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; @@ -3321,10 +3318,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h71299 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h73304 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3381,7 +3378,7 @@ module mkPLIC_16_2_7(CLK, .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(m_slave_xactor_f_wr_data$D_IN), @@ -3442,181 +3439,181 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67427 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; + addr_offset__h26922[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3686,174 +3683,174 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26923[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : + (source_id_base__h28139 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26923[0] : _dfoo1988 ; // register m_cfg_verbosity @@ -3879,8 +3876,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26922[16:12] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 @@ -3894,8 +3891,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26922[16:12] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3906,8 +3903,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3918,8 +3915,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3931,8 +3928,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3944,8 +3941,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3957,8 +3954,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3970,8 +3967,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3983,8 +3980,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3996,8 +3993,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4009,8 +4006,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67427 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4021,8 +4018,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4033,8 +4030,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4045,8 +4042,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4057,8 +4054,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4069,8 +4066,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4081,8 +4078,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4093,8 +4090,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4105,8 +4102,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 @@ -4312,192 +4309,192 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || + addr_offset__h26922[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : + wdata32__h26923[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4829,10 +4826,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_data assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; assign m_slave_xactor_f_wr_data$ENQ = axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; @@ -4840,7 +4834,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_resp assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; + { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26927 } ; assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_f_wr_resp$DEQ = axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; @@ -4863,54 +4857,54 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : + ((x__h67101 == 32'h00200000) ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : + x__h67101 != 32'h00200004 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + addr_offset__h26922[11:2] == 10'd0 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? m_vrg_source_prio_10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? m_vrg_source_prio_11 : @@ -4921,38 +4915,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? 5'd10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? m_vrg_source_prio_12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? m_vrg_source_prio_13 : @@ -4963,50 +4957,50 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? 5'd12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? m_vrg_source_prio_14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? 5'd15 : (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? 5'd14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : @@ -5015,39 +5009,39 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? m_vrg_source_prio_2 : IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? @@ -5065,38 +5059,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? m_vrg_source_prio_4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? m_vrg_source_prio_5 : @@ -5107,38 +5101,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? 5'd4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? m_vrg_source_prio_6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? m_vrg_source_prio_7 : @@ -5149,38 +5143,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? 5'd6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? m_vrg_source_prio_8 : IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? m_vrg_source_prio_9 : @@ -5237,10792 +5231,10792 @@ module mkPLIC_16_2_7(CLK, x__h23673 == 32'h00200004 && m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h30676 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h31886 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h33096 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h34306 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h35516 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h36726 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h37936 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h39146 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h40356 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h41566 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h42776 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h43986 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h45196 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h46406 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h47616 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h48826 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h50036 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h51246 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h52456 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h53666 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h54876 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h56086 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h57296 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h58506 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h59716 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h60926 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h62136 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h63346 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h64556 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h65766 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67101 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67101 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67101 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67101 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67101 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26922[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242 = + source_id__h29466 <= 10'd16 ; + assign NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240 = !m_vrg_source_busy_0 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_0 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320 = + assign NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328 = + assign NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336 = + assign NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344 = + assign NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352 = + assign NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360 = + assign NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249 = + assign NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256 = + assign NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264 = + assign NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272 = + assign NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280 = + assign NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288 = + assign NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296 = + assign NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304 = + assign NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_8_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312 = + assign NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_9_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo883 ; assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : + (source_id__h46406 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26923[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo963 ; assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo983 ; assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45196 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46406 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : + (source_id__h45196 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26923[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : + (source_id__h43986 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26923[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42776 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43986 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : + (source_id__h42776 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26923[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : + (source_id__h41566 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26923[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1233 ; assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1253 ; assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1273 ; assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40356 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41566 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : + (source_id__h40356 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26923[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : + (source_id__h39146 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26923[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1363 ; assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1373 ; assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1393 ; assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1413 ; assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37936 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39146 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : + (source_id__h37936 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26923[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : + (source_id__h36726 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26923[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1513 ; assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1533 ; assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1553 ; assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35516 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36726 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1563 ; assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : + (source_id__h35516 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26923[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : + (source_id__h34306 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26923[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1633 ; assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1653 ; assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1673 ; assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1693 ; assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33096 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34306 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : + (source_id__h33096 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26923[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : + (source_id__h31886 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26923[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1773 ; assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1793 ; assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1813 ; assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1833 ; assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30676 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31886 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : + (source_id__h30676 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26923[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62136 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63346 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : + (source_id__h62136 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26923[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : + (source_id__h29466 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26923[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29466 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1963 ; assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28139 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29466 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : + (source_id__h60926 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26923[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo137 ; assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo139 ; assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo141 ; assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo143 ; assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo145 ; assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo147 ; assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo149 ; assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo151 ; assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo153 ; assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo155 ; assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo157 ; assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo159 ; assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo161 ; assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo163 ; assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo165 ; assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo167 ; assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo169 ; assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo171 ; assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo173 ; assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo175 ; assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo177 ; assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo179 ; assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo181 ; assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo183 ; assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo185 ; assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo187 ; assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo189 ; assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo191 ; assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo193 ; assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo195 ; assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo197 ; assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo199 ; assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo201 ; assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59716 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60926 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo203 ; assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : + (source_id__h59716 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26923[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : + (source_id__h58506 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26923[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo273 ; assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo275 ; assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo277 ; assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo279 ; assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo281 ; assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo283 ; assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo285 ; assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo287 ; assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo289 ; assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo291 ; assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo293 ; assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo295 ; assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo297 ; assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo299 ; assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo301 ; assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo303 ; assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo305 ; assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo307 ; assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo309 ; assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo311 ; assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo313 ; assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo315 ; assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo317 ; assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo319 ; assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo321 ; assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo323 ; assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo325 ; assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo327 ; assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo329 ; assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo331 ; assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo333 ; assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo335 ; assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo337 ; assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57296 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58506 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo339 ; assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : + (source_id__h57296 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26923[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : + (source_id__h56086 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26923[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo409 ; assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo411 ; assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo413 ; assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo415 ; assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo417 ; assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo419 ; assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo421 ; assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo423 ; assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo425 ; assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo427 ; assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo429 ; assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo431 ; assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo433 ; assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo435 ; assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo437 ; assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo439 ; assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo441 ; assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo443 ; assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo445 ; assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo447 ; assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo449 ; assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo451 ; assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo453 ; assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo455 ; assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo457 ; assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo459 ; assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo461 ; assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo463 ; assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo465 ; assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo467 ; assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo469 ; assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo471 ; assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo473 ; assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54876 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56086 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo475 ; assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : + (source_id__h54876 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26923[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : + (source_id__h53666 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26923[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo545 ; assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo547 ; assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo549 ; assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo551 ; assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo553 ; assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo555 ; assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo557 ; assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo559 ; assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo561 ; assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo563 ; assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo565 ; assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo567 ; assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo569 ; assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo571 ; assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo573 ; assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo575 ; assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo577 ; assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo579 ; assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo581 ; assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo583 ; assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo585 ; assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo587 ; assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo589 ; assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo591 ; assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo593 ; assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo595 ; assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo597 ; assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo599 ; assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo601 ; assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo603 ; assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo605 ; assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo607 ; assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo609 ; assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52456 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53666 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo611 ; assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : + (source_id__h52456 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26923[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; + (source_id__h64556 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26923[30] : + wdata32__h26923[31] ; assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : + (source_id__h51246 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26923[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo681 ; assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo683 ; assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo685 ; assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo687 ; assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo689 ; assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo691 ; assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo693 ; assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo695 ; assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo697 ; assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo699 ; assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo701 ; assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo703 ; assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo705 ; assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo707 ; assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo709 ; assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo711 ; assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo713 ; assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo715 ; assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo717 ; assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo719 ; assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo721 ; assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo723 ; assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo725 ; assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo727 ; assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo729 ; assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo731 ; assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo733 ; assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo735 ; assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo737 ; assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo739 ; assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo741 ; assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo743 ; assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo745 ; assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50036 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51246 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo747 ; assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : + (source_id__h50036 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26923[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64556 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65766 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd9 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd8 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd7 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd6 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd5 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd4 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd3 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd2 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd1 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : + (source_id__h48826 == 10'd0 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26923[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo817 ; assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd16 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo819 ; assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd15 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo821 ; assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd14 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo823 ; assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd13 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo825 ; assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd12 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo827 ; assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd11 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo829 ; assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd10 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo831 ; assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd9 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo833 ; assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd8 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo835 ; assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd7 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo837 ; assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd6 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo839 ; assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd5 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo841 ; assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd4 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo843 ; assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : + (source_id__h63346 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26923[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd3 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo845 ; assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd2 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo847 ; assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd1 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo849 ; assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd0 && + addr_offset__h26922[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo851 ; assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd16 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo853 ; assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd15 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo855 ; assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd14 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo857 ; assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd13 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo859 ; assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd12 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo861 ; assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : + (source_id__h47616 == 10'd11 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26923[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47616 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48826 == 10'd10 && + addr_offset__h26922[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign a__h71299 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; + assign a__h73304 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; assign addr_offset__h13216 = m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = + assign addr_offset__h26922 = m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign b__h71300 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; + assign b__h73305 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = addr_offset__h13216 < 64'h0000000000003000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = @@ -16044,181 +16038,181 @@ module mkPLIC_16_2_7(CLK, addr_offset__h13216 < 64'h0000000000002000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = + addr_offset__h26922[16:12] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = + addr_offset__h26922[16:12] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = + addr_offset__h26922[16:12] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = + addr_offset__h26922 < 64'h0000000000001000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = + addr_offset__h26922[11:2] <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = + addr_offset__h26922[11:2] == 10'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = + addr_offset__h26922[11:2] == 10'd2 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = + addr_offset__h26922[11:2] == 10'd3 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = + addr_offset__h26922[11:2] == 10'd4 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = + addr_offset__h26922[11:2] == 10'd5 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = + addr_offset__h26922[11:2] == 10'd6 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = + addr_offset__h26922[11:2] == 10'd7 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = + addr_offset__h26922[11:2] == 10'd8 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = + addr_offset__h26922[11:2] == 10'd9 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = + addr_offset__h26922[11:2] == 10'd10 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = + addr_offset__h26922[11:2] == 10'd11 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = + addr_offset__h26922[11:2] == 10'd12 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = + addr_offset__h26922[11:2] == 10'd13 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = + addr_offset__h26922[11:2] == 10'd14 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = + addr_offset__h26922[11:2] == 10'd15 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = + addr_offset__h26922[11:2] == 10'd16 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26922[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = + addr_offset__h26922 < 64'h0000000000002000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = + source_id_base__h28139 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = + addr_offset__h26922 < 64'h0000000000003000 ; assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = + addr_offset__h26922[11:7] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = + addr_offset__h26922[11:7] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = + addr_offset__h26922[11:7] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && m_vvrg_ie_1_10 ; assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && m_vvrg_ie_1_11 ; assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && m_vvrg_ie_1_12 ; assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && m_vvrg_ie_1_13 ; assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = m_vrg_source_ip_13 && @@ -16233,45 +16227,45 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && m_vvrg_ie_1_14 ; assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && m_vvrg_ie_1_15 ; assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && m_vvrg_ie_1_16 ; assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = m_vrg_source_ip_16 && @@ -16285,90 +16279,90 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && m_vvrg_ie_1_2 ; assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && m_vvrg_ie_1_3 ; assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && m_vvrg_ie_1_4 ; assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && m_vvrg_ie_1_5 ; assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && m_vvrg_ie_1_6 ; assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && m_vvrg_ie_1_7 ; assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = m_vrg_source_ip_7 && @@ -16383,30 +16377,30 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && m_vvrg_ie_1_8 ; assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && m_vvrg_ie_1_9 ; assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = m_vrg_source_ip_9 && @@ -16493,40 +16487,40 @@ module mkPLIC_16_2_7(CLK, assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; + assign source_id__h29466 = { addr_offset__h26922[4:0], 5'd1 } ; + assign source_id__h30676 = { addr_offset__h26922[4:0], 5'd2 } ; + assign source_id__h31886 = { addr_offset__h26922[4:0], 5'd3 } ; + assign source_id__h33096 = { addr_offset__h26922[4:0], 5'd4 } ; + assign source_id__h34306 = { addr_offset__h26922[4:0], 5'd5 } ; + assign source_id__h35516 = { addr_offset__h26922[4:0], 5'd6 } ; + assign source_id__h36726 = { addr_offset__h26922[4:0], 5'd7 } ; + assign source_id__h37936 = { addr_offset__h26922[4:0], 5'd8 } ; + assign source_id__h39146 = { addr_offset__h26922[4:0], 5'd9 } ; + assign source_id__h40356 = { addr_offset__h26922[4:0], 5'd10 } ; + assign source_id__h41566 = { addr_offset__h26922[4:0], 5'd11 } ; + assign source_id__h42776 = { addr_offset__h26922[4:0], 5'd12 } ; + assign source_id__h43986 = { addr_offset__h26922[4:0], 5'd13 } ; + assign source_id__h45196 = { addr_offset__h26922[4:0], 5'd14 } ; + assign source_id__h46406 = { addr_offset__h26922[4:0], 5'd15 } ; + assign source_id__h47616 = { addr_offset__h26922[4:0], 5'd16 } ; + assign source_id__h48826 = { addr_offset__h26922[4:0], 5'd17 } ; + assign source_id__h50036 = { addr_offset__h26922[4:0], 5'd18 } ; + assign source_id__h51246 = { addr_offset__h26922[4:0], 5'd19 } ; + assign source_id__h52456 = { addr_offset__h26922[4:0], 5'd20 } ; + assign source_id__h53666 = { addr_offset__h26922[4:0], 5'd21 } ; + assign source_id__h54876 = { addr_offset__h26922[4:0], 5'd22 } ; + assign source_id__h56086 = { addr_offset__h26922[4:0], 5'd23 } ; + assign source_id__h57296 = { addr_offset__h26922[4:0], 5'd24 } ; + assign source_id__h58506 = { addr_offset__h26922[4:0], 5'd25 } ; + assign source_id__h59716 = { addr_offset__h26922[4:0], 5'd26 } ; + assign source_id__h60926 = { addr_offset__h26922[4:0], 5'd27 } ; + assign source_id__h62136 = { addr_offset__h26922[4:0], 5'd28 } ; + assign source_id__h63346 = { addr_offset__h26922[4:0], 5'd29 } ; + assign source_id__h64556 = { addr_offset__h26922[4:0], 5'd30 } ; + assign source_id__h65766 = { addr_offset__h26922[4:0], 5'd31 } ; + assign source_id__h67427 = { 5'd0, x__h67478 } ; assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; + assign source_id_base__h28139 = { addr_offset__h26922[4:0], 5'h0 } ; assign v__h13422 = { 61'd0, x__h13493 } ; assign v__h13671 = { 32'd0, v_ip__h13674 } ; assign v__h18144 = { 32'd0, v_ie__h18147 } ; @@ -16536,48 +16530,48 @@ module mkPLIC_16_2_7(CLK, v__h25474 : 64'd0 ; assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? + assign v__h26927 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? + v__h27085 ; + assign v__h27085 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + v__h27098 : + v__h27933 ; + assign v__h27098 = + (addr_offset__h26922[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? 2'b0 : 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? + assign v__h27933 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? + v__h27952 : + v__h28116 ; + assign v__h27952 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? 2'b0 : 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign v__h28116 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? + v__h28135 : + v__h67098 ; + assign v__h28135 = + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? 2'b0 : 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? + assign v__h67135 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? 2'b0 : 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : + assign v__h67423 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? + v__h67467 : 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? + assign v__h67467 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? 2'b0 : 2'b10 ; assign v_ie__h18147 = @@ -16710,8 +16704,8 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? + assign wdata32__h26923 = + (addr_offset__h26922[2:0] == 3'd4) ? m_slave_xactor_f_wr_data$D_OUT[72:41] : m_slave_xactor_f_wr_data$D_OUT[40:9] ; assign x__h23673 = @@ -16720,8 +16714,8 @@ module mkPLIC_16_2_7(CLK, (addr_offset__h13216[2:0] == 3'd4) ? rdata___1__h26404 : rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; + assign x__h67101 = + { addr_offset__h26922[31:16], 4'd0, addr_offset__h26922[11:0] } ; assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; assign y_avValue_fst__h26115 = m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? @@ -16853,86 +16847,13 @@ module mkPLIC_16_2_7(CLK, default: x__h24011 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h26929 or + always@(addr_offset__h26922 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; + case (addr_offset__h26922[16:12]) + 5'd0: x__h67478 = m_vrg_servicing_source_0; + 5'd1: x__h67478 = m_vrg_servicing_source_1; + default: x__h67478 = 5'b01010 /* unspecified value */ ; endcase end always@(source_id_base__h13630 or @@ -17081,79 +17002,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h20137 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -17227,6 +17075,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h20313 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h20313) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h20137 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -17811,79 +17732,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h20745 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -17957,6 +17805,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h20637 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h20637) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h20745 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -18103,6 +18024,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h20853 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h20853) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h15918 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -18249,79 +18243,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h20961 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -18395,79 +18316,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h20961 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -18541,6 +18389,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h15991 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h15991) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h16064 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -18833,6 +18754,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h21177 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h21177) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h16137 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -18906,76 +18900,76 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + always@(source_id__h16210 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h21177) + case (source_id__h16210) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = 1'b0 /* unspecified value */ ; endcase end @@ -19052,79 +19046,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h21393 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -19198,6 +19119,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h21285 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h21285) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h21393 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -19417,79 +19411,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h21501 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -19636,76 +19557,76 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + always@(source_id__h21501 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h16429) + case (source_id__h21501) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = 1'b0 /* unspecified value */ ; endcase end @@ -19782,6 +19703,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h16429 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h16429) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h16502 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -20074,79 +20068,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h21825 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -20293,6 +20214,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h16575 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h16575) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h21933 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -20366,79 +20360,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22041 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -20512,6 +20433,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h21933 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h21933) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h22041 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -20658,6 +20652,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h22149 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h22149) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h16794 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -20804,79 +20871,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22257 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -20950,79 +20944,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22257 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -21096,6 +21017,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h16867 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h16867) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h16940 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -21388,79 +21382,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22473 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -21534,6 +21455,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h17013 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h17013) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h17086 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -21680,79 +21674,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22689 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -21826,6 +21747,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h22581 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h22581) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h22689 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -22045,79 +22039,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h22797 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -22264,76 +22185,76 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + always@(source_id__h22797 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h17305) + case (source_id__h22797) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = 1'b0 /* unspecified value */ ; endcase end @@ -22410,6 +22331,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h17305 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h17305) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h17378 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -22702,79 +22696,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h23121 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -22921,6 +22842,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h17451 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h17451) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h23229 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -22994,79 +22988,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h23337 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -23140,6 +23061,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h23229 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h23229) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h23337 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or @@ -23359,79 +23353,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end always@(source_id__h23445 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or @@ -23578,76 +23499,76 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + always@(source_id__h23445 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h17743) + case (source_id__h23445) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = 1'b0 /* unspecified value */ ; endcase end @@ -24277,6 +24198,79 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(source_id__h17743 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h17743) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + 1'b0 /* unspecified value */ ; + endcase + end always@(source_id__h17889 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or @@ -24350,14 +24344,6 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin case (addr_offset__h13216[16:12]) @@ -24371,6 +24357,14 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end + always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) + begin + case (x__h23673) + 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; + 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; + default: y_avValue_snd__h26149 = 2'b10; + endcase + end always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin case (addr_offset__h13216[16:12]) @@ -24574,7 +24568,7 @@ module mkPLIC_16_2_7(CLK, default: y_avValue_fst__h26148 = 64'd0; endcase end - always@(source_id__h67436 or + always@(source_id__h67427 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24592,68 +24586,68 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h67436) + case (source_id__h67427) 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_0; 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_1; 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_2; 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_3; 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_4; 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_5; 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_6; 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_7; 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_8; 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_9; 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_10; 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_11; 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_12; 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_13; 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_14; 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_15; 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h67110 or v__h67144 or v__h67432) + always@(x__h67101 or v__h67135 or v__h67423) begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; + case (x__h67101) + 32'h00200000: v__h67098 = v__h67135; + 32'h00200004: v__h67098 = v__h67423; + default: v__h67098 = 2'b10; endcase end @@ -25240,9 +25234,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, + a__h71299, m_vrg_target_threshold_0, - b__h71313, + b__h71300, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25283,216 +25277,216 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, + a__h73304, m_vrg_target_threshold_1, - b__h73318, + b__h73305, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) begin - v__h75673 = $stime; + v__h75658 = $stime; #0; end - v__h75667 = v__h75673 / 32'd10; + v__h75652 = v__h75658 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75667, + v__h75652, $signed(32'd0), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) begin - v__h75868 = $stime; + v__h75853 = $stime; #0; end - v__h75862 = v__h75868 / 32'd10; + v__h75847 = v__h75853 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75862, + v__h75847, $signed(32'd1), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) begin - v__h76063 = $stime; + v__h76048 = $stime; #0; end - v__h76057 = v__h76063 / 32'd10; + v__h76042 = v__h76048 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76057, + v__h76042, $signed(32'd2), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) begin - v__h76258 = $stime; + v__h76243 = $stime; #0; end - v__h76252 = v__h76258 / 32'd10; + v__h76237 = v__h76243 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76252, + v__h76237, $signed(32'd3), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) begin - v__h76453 = $stime; + v__h76438 = $stime; #0; end - v__h76447 = v__h76453 / 32'd10; + v__h76432 = v__h76438 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76447, + v__h76432, $signed(32'd4), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) begin - v__h76648 = $stime; + v__h76633 = $stime; #0; end - v__h76642 = v__h76648 / 32'd10; + v__h76627 = v__h76633 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76642, + v__h76627, $signed(32'd5), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) begin - v__h76843 = $stime; + v__h76828 = $stime; #0; end - v__h76837 = v__h76843 / 32'd10; + v__h76822 = v__h76828 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76837, + v__h76822, $signed(32'd6), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) begin - v__h77038 = $stime; + v__h77023 = $stime; #0; end - v__h77032 = v__h77038 / 32'd10; + v__h77017 = v__h77023 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77032, + v__h77017, $signed(32'd7), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) begin - v__h77233 = $stime; + v__h77218 = $stime; #0; end - v__h77227 = v__h77233 / 32'd10; + v__h77212 = v__h77218 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77227, + v__h77212, $signed(32'd8), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) begin - v__h77428 = $stime; + v__h77413 = $stime; #0; end - v__h77422 = v__h77428 / 32'd10; + v__h77407 = v__h77413 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77422, + v__h77407, $signed(32'd9), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) begin - v__h77623 = $stime; + v__h77608 = $stime; #0; end - v__h77617 = v__h77623 / 32'd10; + v__h77602 = v__h77608 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77617, + v__h77602, $signed(32'd10), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) begin - v__h77818 = $stime; + v__h77803 = $stime; #0; end - v__h77812 = v__h77818 / 32'd10; + v__h77797 = v__h77803 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77812, + v__h77797, $signed(32'd11), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) begin - v__h78013 = $stime; + v__h77998 = $stime; #0; end - v__h78007 = v__h78013 / 32'd10; + v__h77992 = v__h77998 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78007, + v__h77992, $signed(32'd12), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) begin - v__h78208 = $stime; + v__h78193 = $stime; #0; end - v__h78202 = v__h78208 / 32'd10; + v__h78187 = v__h78193 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78202, + v__h78187, $signed(32'd13), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) begin - v__h78403 = $stime; + v__h78388 = $stime; #0; end - v__h78397 = v__h78403 / 32'd10; + v__h78382 = v__h78388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78397, + v__h78382, $signed(32'd14), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) begin - v__h78598 = $stime; + v__h78583 = $stime; #0; end - v__h78592 = v__h78598 / 32'd10; + v__h78577 = v__h78583 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78592, + v__h78577, $signed(32'd15), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) @@ -26127,14 +26121,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h26740 = $stime; + v__h26737 = $stime; #0; end - v__h26734 = v__h26740 / 32'd10; + v__h26731 = v__h26737 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); + $display("%0d: PLIC.rl_process_wr_req", v__h26731); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26238,15 +26232,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26287,485 +26273,467 @@ module mkPLIC_16_2_7(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) begin - v__h26968 = $stime; + v__h26961 = $stime; #0; end - v__h26962 = v__h26968 / 32'd10; + v__h26955 = v__h26961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); + v__h26955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) begin - v__h27865 = $stime; + v__h27856 = $stime; #0; end - v__h27859 = v__h27865 / 32'd10; + v__h27850 = v__h27856 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); + v__h27850, + addr_offset__h26922[11:2], + wdata32__h26923); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) begin - v__h28048 = $stime; + v__h28039 = $stime; #0; end - v__h28042 = v__h28048 / 32'd10; + v__h28033 = v__h28039 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); + v__h28033, + source_id_base__h28139); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) begin - v__h67030 = $stime; + v__h67021 = $stime; #0; end - v__h67024 = v__h67030 / 32'd10; + v__h67015 = v__h67021 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); + v__h67015, + addr_offset__h26922[11:7], + source_id_base__h28139, + wdata32__h26923); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) begin - v__h67318 = $stime; + v__h67309 = $stime; #0; end - v__h67312 = v__h67318 / 32'd10; + v__h67303 = v__h67309 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); + v__h67303, + addr_offset__h26922[16:12], + wdata32__h26923); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) begin - v__h67847 = $stime; + v__h67838 = $stime; #0; end - v__h67841 = v__h67847 / 32'd10; + v__h67832 = v__h67838 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); + v__h67832, + addr_offset__h26922[16:12], + source_id__h67427); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) begin - v__h67933 = $stime; + v__h67924 = $stime; #0; end - v__h67927 = v__h67933 / 32'd10; + v__h67918 = v__h67924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); + v__h67918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); + addr_offset__h26922[16:12], + source_id__h67427); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) begin - v__h68132 = $stime; + v__h68123 = $stime; #0; end - v__h68126 = v__h68132 / 32'd10; + v__h68117 = v__h68123 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); + v__h68117); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h68353 = $stime; + v__h68342 = $stime; #0; end - v__h68347 = v__h68353 / 32'd10; + v__h68336 = v__h68342 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68336); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26869,15 +26837,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26935,7 +26895,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); + $write("'h%h", v__h26927); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26951,38 +26911,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74690 = $stime; + v__h74677 = $stime; #0; end - v__h74684 = v__h74690 / 32'd10; + v__h74671 = v__h74677 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, + v__h74671, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74800 = $stime; + v__h74787 = $stime; #0; end - v__h74794 = v__h74800 / 32'd10; + v__h74781 = v__h74787 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, + v__h74781, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74913 = $stime; + v__h74900 = $stime; #0; end - v__h74907 = v__h74913 / 32'd10; + v__h74894 = v__h74900 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, + v__h74894, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index ad26eea..2966d6a 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -6,8 +6,6 @@ // // Ports: // Name I/O size props -// RDY_init_server_request_put O 1 reg -// RDY_init_server_response_get O 1 reg // RDY_start O 1 // master0_awvalid O 1 // master0_awid O 4 reg @@ -21,7 +19,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -50,7 +47,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -122,7 +118,6 @@ // debug_module_mem_server_awqos I 4 reg // debug_module_mem_server_awregion I 4 reg // debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_wid I 4 reg // debug_module_mem_server_wdata I 64 reg // debug_module_mem_server_wstrb I 8 reg // debug_module_mem_server_wlast I 1 reg @@ -139,8 +134,6 @@ // debug_module_mem_server_arqos I 4 reg // debug_module_mem_server_arregion I 4 reg // debug_module_mem_server_rready I 1 -// EN_init_server_request_put I 1 -// EN_init_server_response_get I 1 // EN_start I 1 // EN_set_verbosity I 1 // @@ -166,12 +159,6 @@ module mkProc(CLK, RST_N, - EN_init_server_request_put, - RDY_init_server_request_put, - - EN_init_server_response_get, - RDY_init_server_response_get, - start_startpc, start_tohostAddr, start_fromhostAddr, @@ -204,8 +191,6 @@ module mkProc(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -278,8 +263,6 @@ module mkProc(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -351,7 +334,6 @@ module mkProc(CLK, debug_module_mem_server_awready, debug_module_mem_server_wvalid, - debug_module_mem_server_wid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, @@ -394,14 +376,6 @@ module mkProc(CLK, input CLK; input RST_N; - // action method init_server_request_put - input EN_init_server_request_put; - output RDY_init_server_request_put; - - // action method init_server_response_get - input EN_init_server_response_get; - output RDY_init_server_response_get; - // action method start input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; @@ -450,9 +424,6 @@ module mkProc(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -564,9 +535,6 @@ module mkProc(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -669,7 +637,6 @@ module mkProc(CLK, // action method debug_module_mem_server_m_wvalid input debug_module_mem_server_wvalid; - input [3 : 0] debug_module_mem_server_wid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; @@ -751,7 +718,6 @@ module mkProc(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -759,8 +725,7 @@ module mkProc(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -775,9 +740,7 @@ module mkProc(CLK, master0_awburst, master1_arburst, master1_awburst; - wire RDY_init_server_request_put, - RDY_init_server_response_get, - RDY_set_verbosity, + wire RDY_set_verbosity, RDY_start, debug_module_mem_server_arready, debug_module_mem_server_awready, @@ -812,11 +775,9 @@ module mkProc(CLK, wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read; wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, @@ -920,8 +881,8 @@ module mkProc(CLK, wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN; // register llc_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire llc_axi4_adapter_master_xactor_rg_wr_data$EN; // register llc_axi4_adapter_master_xactor_rg_wr_resp @@ -968,6 +929,26 @@ module mkProc(CLK, reg llc_mem_server_propDstIdx_0_rl; wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN; + // register llc_mem_server_rg_cacheline_cache_addr + reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr; + wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN; + wire llc_mem_server_rg_cacheline_cache_addr$EN; + + // register llc_mem_server_rg_cacheline_cache_data + reg [511 : 0] llc_mem_server_rg_cacheline_cache_data; + wire [511 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN; + wire llc_mem_server_rg_cacheline_cache_data$EN; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay; + wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN; + + // register llc_mem_server_rg_cacheline_cache_state + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state; + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN; + wire llc_mem_server_rg_cacheline_cache_state$EN; + // register mmioPlatform_amoResp reg [63 : 0] mmioPlatform_amoResp; wire [63 : 0] mmioPlatform_amoResp$D_IN; @@ -1168,8 +1149,8 @@ module mkProc(CLK, wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_resp @@ -1257,8 +1238,6 @@ module mkProc(CLK, core_0$EN_iCacheToParent_fromP_enq, core_0$EN_iCacheToParent_rqToP_deq, core_0$EN_iCacheToParent_rsToP_deq, - core_0$EN_init_server_request_put, - core_0$EN_init_server_response_get, core_0$EN_mmioToPlatform_cRq_deq, core_0$EN_mmioToPlatform_cRs_deq, core_0$EN_mmioToPlatform_pRq_enq, @@ -1291,8 +1270,6 @@ module mkProc(CLK, core_0$RDY_iCacheToParent_rqToP_first, core_0$RDY_iCacheToParent_rsToP_deq, core_0$RDY_iCacheToParent_rsToP_first, - core_0$RDY_init_server_request_put, - core_0$RDY_init_server_response_get, core_0$RDY_mmioToPlatform_cRq_deq, core_0$RDY_mmioToPlatform_cRq_first, core_0$RDY_mmioToPlatform_cRs_deq, @@ -1327,20 +1304,6 @@ module mkProc(CLK, enqDst_1_0_dummy2_1$EN, enqDst_1_0_dummy2_1$Q_OUT; - // ports of submodule f_init_reqs - wire f_init_reqs$CLR, - f_init_reqs$DEQ, - f_init_reqs$EMPTY_N, - f_init_reqs$ENQ, - f_init_reqs$FULL_N; - - // ports of submodule f_init_rsps - wire f_init_rsps$CLR, - f_init_rsps$DEQ, - f_init_rsps$EMPTY_N, - f_init_rsps$ENQ, - f_init_rsps$FULL_N; - // ports of submodule llc reg [644 : 0] llc$dma_memReq_enq_x; wire [640 : 0] llc$to_mem_toM_first; @@ -1421,7 +1384,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N; // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_data - wire [76 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, + wire [72 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT; wire llc_mem_server_axi4_slave_xactor_f_wr_data$CLR, llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ, @@ -1449,13 +1412,10 @@ module mkProc(CLK, llc_mem_server_enqDst_0_dummy2_1$Q_OUT; // ports of submodule llc_mem_server_f_dword_in_line - wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN, - llc_mem_server_f_dword_in_line$D_OUT; + wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN; wire llc_mem_server_f_dword_in_line$CLR, llc_mem_server_f_dword_in_line$DEQ, - llc_mem_server_f_dword_in_line$EMPTY_N, - llc_mem_server_f_dword_in_line$ENQ, - llc_mem_server_f_dword_in_line$FULL_N; + llc_mem_server_f_dword_in_line$ENQ; // ports of submodule llc_mem_server_propDstData_0_dummy2_0 wire llc_mem_server_propDstData_0_dummy2_0$D_IN, @@ -1661,11 +1621,17 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, CAN_FIRE_RL_llc_mem_server_propDstData_0_canon, CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader, CAN_FIRE_RL_llc_mem_server_sendStRespToTlb, CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC, CAN_FIRE_RL_llc_mem_server_srcPropose, @@ -1719,8 +1685,6 @@ module mkProc(CLK, CAN_FIRE_RL_rl_dummy7, CAN_FIRE_RL_rl_dummy8, CAN_FIRE_RL_rl_dummy9, - CAN_FIRE_RL_rl_init_finish, - CAN_FIRE_RL_rl_init_start, CAN_FIRE_RL_rl_terminate, CAN_FIRE_RL_rl_tohost, CAN_FIRE_RL_sendPRq, @@ -1736,8 +1700,6 @@ module mkProc(CLK, CAN_FIRE_debug_module_mem_server_m_bready, CAN_FIRE_debug_module_mem_server_m_rready, CAN_FIRE_debug_module_mem_server_m_wvalid, - CAN_FIRE_init_server_request_put, - CAN_FIRE_init_server_response_get, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_master0_m_arready, CAN_FIRE_master0_m_awready, @@ -1769,11 +1731,17 @@ module mkProc(CLK, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, WILL_FIRE_RL_llc_mem_server_propDstData_0_canon, WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader, WILL_FIRE_RL_llc_mem_server_sendStRespToTlb, WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC, WILL_FIRE_RL_llc_mem_server_srcPropose, @@ -1827,8 +1795,6 @@ module mkProc(CLK, WILL_FIRE_RL_rl_dummy7, WILL_FIRE_RL_rl_dummy8, WILL_FIRE_RL_rl_dummy9, - WILL_FIRE_RL_rl_init_finish, - WILL_FIRE_RL_rl_init_start, WILL_FIRE_RL_rl_terminate, WILL_FIRE_RL_rl_tohost, WILL_FIRE_RL_sendPRq, @@ -1844,8 +1810,6 @@ module mkProc(CLK, WILL_FIRE_debug_module_mem_server_m_bready, WILL_FIRE_debug_module_mem_server_m_rready, WILL_FIRE_debug_module_mem_server_m_wvalid, - WILL_FIRE_init_server_request_put, - WILL_FIRE_init_server_response_get, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_master0_m_arready, WILL_FIRE_master0_m_awready, @@ -1867,9 +1831,11 @@ module mkProc(CLK, MUX_mmioPlatform_state$write_1__VAL_4; wire [644 : 0] MUX_llc$dma_memReq_enq_1__VAL_1, MUX_llc$dma_memReq_enq_1__VAL_2, - MUX_llc$dma_memReq_enq_1__VAL_3; + MUX_llc$dma_memReq_enq_1__VAL_3, + MUX_llc$dma_memReq_enq_1__VAL_4; wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + wire [511 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3, @@ -1893,6 +1859,7 @@ module mkProc(CLK, wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4; + wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2; wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1; wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1, MUX_mmioPlatform_state$write_1__VAL_2, @@ -1907,7 +1874,8 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, MUX_llc$dma_memReq_enq_1__SEL_1, - MUX_llc$dma_memReq_enq_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, MUX_mmioPlatform_amoResp$write_1__SEL_1, MUX_mmioPlatform_amoResp$write_1__SEL_2, MUX_mmioPlatform_curReq$write_1__SEL_1, @@ -1923,307 +1891,303 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h152871; - reg [31 : 0] v__h4104; - reg [31 : 0] v__h4277; - reg [31 : 0] v__h4541; - reg [31 : 0] v__h6580; - reg [31 : 0] v__h2380; - reg [31 : 0] v__h6881; - reg [31 : 0] v__h7374; - reg [31 : 0] v__h7537; - reg [31 : 0] v__h94867; - reg [31 : 0] v__h94912; - reg [31 : 0] v__h94822; - reg [31 : 0] v__h105904; - reg [31 : 0] v__h105859; - reg [31 : 0] v__h124529; - reg [31 : 0] v__h124696; - reg [31 : 0] v__h126799; - reg [31 : 0] v__h144145; - reg [31 : 0] v__h123910; - reg [31 : 0] v__h150840; - reg [31 : 0] v__h151348; - reg [31 : 0] v__h2374; - reg [31 : 0] v__h4098; - reg [31 : 0] v__h4271; - reg [31 : 0] v__h4535; - reg [31 : 0] v__h6574; - reg [31 : 0] v__h6875; - reg [31 : 0] v__h7368; - reg [31 : 0] v__h7531; - reg [31 : 0] v__h94816; - reg [31 : 0] v__h94861; - reg [31 : 0] v__h94906; - reg [31 : 0] v__h105853; - reg [31 : 0] v__h105898; - reg [31 : 0] v__h123904; - reg [31 : 0] v__h124523; - reg [31 : 0] v__h124690; - reg [31 : 0] v__h126793; - reg [31 : 0] v__h144139; - reg [31 : 0] v__h150834; - reg [31 : 0] v__h151342; - reg [31 : 0] v__h152865; + reg [31 : 0] v__h161964; + reg [31 : 0] v__h161528; + reg [31 : 0] v__h3916; + reg [31 : 0] v__h4089; + reg [31 : 0] v__h4353; + reg [31 : 0] v__h6390; + reg [31 : 0] v__h2192; + reg [31 : 0] v__h6690; + reg [31 : 0] v__h7183; + reg [31 : 0] v__h7346; + reg [31 : 0] v__h99954; + reg [31 : 0] v__h100752; + reg [31 : 0] v__h100901; + reg [31 : 0] v__h133485; + reg [31 : 0] v__h133652; + reg [31 : 0] v__h135755; + reg [31 : 0] v__h153099; + reg [31 : 0] v__h132866; + reg [31 : 0] v__h159793; + reg [31 : 0] v__h160301; + reg [31 : 0] v__h2186; + reg [31 : 0] v__h3910; + reg [31 : 0] v__h4083; + reg [31 : 0] v__h4347; + reg [31 : 0] v__h6384; + reg [31 : 0] v__h6684; + reg [31 : 0] v__h7177; + reg [31 : 0] v__h7340; + reg [31 : 0] v__h99948; + reg [31 : 0] v__h100746; + reg [31 : 0] v__h100895; + reg [31 : 0] v__h132860; + reg [31 : 0] v__h133479; + reg [31 : 0] v__h133646; + reg [31 : 0] v__h135749; + reg [31 : 0] v__h153093; + reg [31 : 0] v__h159787; + reg [31 : 0] v__h160295; + reg [31 : 0] v__h161522; + reg [31 : 0] v__h161958; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x7912_0_n__read_addr8090_1_n__read_addr81_ETC__q26, - CASE_x9027_0_n__read_addr9209_1_n__read_addr92_ETC__q15, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917, - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884, - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852, - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854, - data64__h137969, - ld_data__h121954, - rd_data_rdata__h120403, - w1__h45627, - w1__h45632, - w2__h45628, - w2__h45634, - x__h45623; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952; - reg [7 : 0] strb8__h137970; - reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [2 : 0] x__h59341; - reg [1 : 0] CASE_x7912_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7721_0_n__read_addr7899_1_n__read_addr79_ETC__q26, + CASE_x8836_0_n__read_addr9018_1_n__read_addr91_ETC__q15, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916, + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883, + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851, + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853, + data64__h146925, + dword__h91879, + ld_data__h131014, + old_dword__h87569, + w1__h45436, + w1__h45441, + w2__h45437, + w2__h45443, + x__h45432; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951; + reg [7 : 0] strb8__h146926; + reg [5 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441; + reg [2 : 0] x__h59150; + reg [1 : 0] CASE_x7721_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x7912_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x9027_0_propDstData_0_dummy2_1_read__065__ETC__q12, - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332, - x__h59348, - x__h80328; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424, - new_cline__h124832; - wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407; - wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645; - wire [64 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206, - data__h29351, - failed_testnum__h152914, - line_addr__h105833, - mem_req_rd_addr_araddr__h124130, - mem_req_wr_addr_awaddr__h138054, - mmioPlatform_fromHostQ_data_0__h40198, - mmioPlatform_mtime__h34665, - mmioPlatform_reqData__h46219, - n__read_addr__h59209, - n__read_addr__h59294, - n__read_addr__h78090, - n__read_addr__h78169, - n__read_snd_addr__h93111, - newData__h29432, - newData__h32362, - op_result__h46235, - op_result__h46765, - op_result__h46770, - op_result__h46775, - op_result__h46780, - op_result__h46786, - op_result__h46793, - op_result__h46799, - req_addr__h94973, - result__h45678, - result__h45802, - result__h45830, - result__h45858, - result__h45886, - result__h45914, - result__h45942, - result__h45970, - result__h45998, - result__h46043, - result__h46071, - result__h46099, - result__h46127, - result__h46168, - result__h46196, - result__h46322, - result__h46349, - result__h46376, - result__h46403, - result__h46430, - result__h46457, - result__h46484, - result__h46511, - result__h46555, - result__h46582, - result__h46609, - result__h46636, - result__h46676, - result__h46703, - result__h46820, - result__h46886, - result__h46952, - result__h47018, - result__h47084, - result__h47150, - result__h47216, - result__h47278, - result__h47323, - result__h47389, - result__h47455, - result__h47513, - result__h47558, - w1___1__h45737, - w2___1__h45738, - x1_avValue_data__h37870, - x1_avValue_data__h42556, - x__h29543, - x__h32453, - x__h34813, - x__h38388, - x__h38399, - x__h40481, - x__h40492, - x__h47735; - wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674; - wire [31 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960, + CASE_x7721_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x8836_0_propDstData_0_dummy2_1_read__064__ETC__q12, + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331, + x__h59157, + x__h80137; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423, + new_cline__h133788; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644; + wire [64 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205, + data__h29160, + failed_testnum__h161571, + line_addr__h100665, + line_addr__h100814, + mask__h87566, + mem_req_rd_addr_araddr__h133086, + mem_req_wr_addr_awaddr__h147010, + mmioPlatform_fromHostQ_data_0__h40007, + mmioPlatform_mtime__h34474, + mmioPlatform_reqData__h46028, + n__read_addr__h59018, + n__read_addr__h59103, + n__read_addr__h77899, + n__read_addr__h77978, + n__read_snd_addr__h122318, + newData__h29241, + newData__h32171, + new_dword__h87570, + op_result__h46044, + op_result__h46574, + op_result__h46579, + op_result__h46584, + op_result__h46589, + op_result__h46595, + op_result__h46602, + op_result__h46608, + result__h45487, + result__h45611, + result__h45639, + result__h45667, + result__h45695, + result__h45723, + result__h45751, + result__h45779, + result__h45807, + result__h45852, + result__h45880, + result__h45908, + result__h45936, + result__h45977, + result__h46005, + result__h46131, + result__h46158, + result__h46185, + result__h46212, + result__h46239, + result__h46266, + result__h46293, + result__h46320, + result__h46364, + result__h46391, + result__h46418, + result__h46445, + result__h46485, + result__h46512, + result__h46629, + result__h46695, + result__h46761, + result__h46827, + result__h46893, + result__h46959, + result__h47025, + result__h47087, + result__h47132, + result__h47198, + result__h47264, + result__h47322, + result__h47367, + w1___1__h45546, + w2___1__h45547, + x1_avValue_data__h37679, + x1_avValue_data__h42365, + x__h29352, + x__h32262, + x__h34622, + x__h38197, + x__h38208, + x__h40290, + x__h40301, + x__h47544, + x__h88732, + y__h88733, + y__h88734; + wire [47 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673; + wire [31 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668, + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h29144, - v__h29181, - w15627_BITS_31_TO_0__q7, - w25628_BITS_31_TO_0__q8, - x_data__h27934; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129; - wire [5 : 0] x__h124165, x__h138079; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128; - wire [3 : 0] b__h123837, b__h2274; - wire [2 : 0] n__read_id__h59213, n__read_id__h59298; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081, - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211, - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085, - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095; - wire IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515, - IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062, - IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436, - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280, - IF_llc_mem_server_enqDst_0_lat_0_whas__499_THE_ETC___d1504, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__484_ETC___d1487, - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165, - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232, - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977, - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151, - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158, - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984, - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064, - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338, - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942, - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283, - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304, - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609, - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205, - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226, - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351, - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353, - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061, - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335, - NOT_propDstIdx_1_1_dummy2_1_read__309_310_OR_I_ETC___d1442, - NOT_propDstIdx_1_dummy2_1_read__040_041_OR_IF__ETC___d1140, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1604, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643, - mmioPlatform_cycle_12_ULT_99___d313, - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944, - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27559, - mmioPlatform_reqBE_BIT_4___h27519, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h59214, - n__read_child__h59299, - n__read_child__h78093, - n__read_child__h78172, - n__read_snd_id__h93112, - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101, - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105, - x__h59027, - x__h72841, - x__h77912; - - // action method init_server_request_put - assign RDY_init_server_request_put = f_init_reqs$FULL_N ; - assign CAN_FIRE_init_server_request_put = f_init_reqs$FULL_N ; - assign WILL_FIRE_init_server_request_put = EN_init_server_request_put ; - - // action method init_server_response_get - assign RDY_init_server_response_get = f_init_rsps$EMPTY_N ; - assign CAN_FIRE_init_server_response_get = f_init_rsps$EMPTY_N ; - assign WILL_FIRE_init_server_response_get = EN_init_server_response_get ; + v__h28953, + v__h28990, + w15436_BITS_31_TO_0__q7, + w25437_BITS_31_TO_0__q8, + x_data__h27743; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128; + wire [5 : 0] x__h133121, x__h147035; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127; + wire [3 : 0] b__h132793, b__h2086; + wire [2 : 0] n__read_id__h59022, n__read_id__h59107; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080, + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210, + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084, + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094; + wire IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514, + IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061, + IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435, + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279, + IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635, + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164, + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460, + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231, + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976, + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150, + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157, + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983, + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063, + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337, + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941, + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282, + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303, + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608, + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204, + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225, + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350, + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352, + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060, + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334, + NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441, + NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495, + mmioPlatform_cycle_11_ULT_99___d312, + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943, + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295, + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576, + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321, + mmioPlatform_reqBE_BIT_0___h27368, + mmioPlatform_reqBE_BIT_4___h27328, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596, + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217, + n__read_child__h59023, + n__read_child__h59108, + n__read_child__h77902, + n__read_child__h77981, + n__read_snd_id__h122319, + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100, + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104, + x__h58836, + x__h72650, + x__h77721; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -2270,9 +2234,6 @@ module mkProc(CLK, // value method master0_m_wvalid assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master0_m_wid - assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master0_m_wdata assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2379,9 +2340,6 @@ module mkProc(CLK, // value method master1_m_wvalid assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master1_m_wid - assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master1_m_wdata assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2546,8 +2504,6 @@ module mkProc(CLK, .setMEIP_v(core_0$setMEIP_v), .setSEIP_v(core_0$setSEIP_v), .tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x), - .EN_init_server_request_put(core_0$EN_init_server_request_put), - .EN_init_server_response_get(core_0$EN_init_server_response_get), .EN_coreReq_start(core_0$EN_coreReq_start), .EN_coreReq_perfReq(core_0$EN_coreReq_perfReq), .EN_coreIndInv_perfResp(core_0$EN_coreIndInv_perfResp), @@ -2579,8 +2535,6 @@ module mkProc(CLK, .EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get), .EN_setMEIP(core_0$EN_setMEIP), .EN_setSEIP(core_0$EN_setSEIP), - .RDY_init_server_request_put(core_0$RDY_init_server_request_put), - .RDY_init_server_response_get(core_0$RDY_init_server_response_get), .RDY_coreReq_start(), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), @@ -2686,24 +2640,6 @@ module mkProc(CLK, .EN(enqDst_1_0_dummy2_1$EN), .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT)); - // submodule f_init_reqs - FIFO20 #(.guarded(32'd1)) f_init_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_init_reqs$ENQ), - .DEQ(f_init_reqs$DEQ), - .CLR(f_init_reqs$CLR), - .FULL_N(f_init_reqs$FULL_N), - .EMPTY_N(f_init_reqs$EMPTY_N)); - - // submodule f_init_rsps - FIFO20 #(.guarded(32'd1)) f_init_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_init_rsps$ENQ), - .DEQ(f_init_rsps$DEQ), - .CLR(f_init_rsps$CLR), - .FULL_N(f_init_rsps$FULL_N), - .EMPTY_N(f_init_rsps$EMPTY_N)); - // submodule llc mkLLCache llc(.CLK(CLK), .RST_N(RST_N), @@ -2827,7 +2763,7 @@ module mkProc(CLK, .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N)); // submodule llc_mem_server_axi4_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN), @@ -2872,9 +2808,9 @@ module mkProc(CLK, .ENQ(llc_mem_server_f_dword_in_line$ENQ), .DEQ(llc_mem_server_f_dword_in_line$DEQ), .CLR(llc_mem_server_f_dword_in_line$CLR), - .D_OUT(llc_mem_server_f_dword_in_line$D_OUT), - .FULL_N(llc_mem_server_f_dword_in_line$FULL_N), - .EMPTY_N(llc_mem_server_f_dword_in_line$EMPTY_N)); + .D_OUT(), + .FULL_N(), + .EMPTY_N()); // submodule llc_mem_server_propDstData_0_dummy2_0 RevertReg #(.width(32'd1), @@ -3149,16 +3085,16 @@ module mkProc(CLK, // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = - core_0$RDY_dCacheToParent_rqToP_first && core_0$RDY_dCacheToParent_rqToP_deq && + core_0$RDY_dCacheToParent_rqToP_first && (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || !propDstIdx_0_rl) ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = - core_0$RDY_iCacheToParent_rqToP_first && core_0$RDY_iCacheToParent_rqToP_deq && + core_0$RDY_iCacheToParent_rqToP_first && (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || !propDstIdx_1_rl) ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; @@ -3170,13 +3106,13 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008 ; + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = - core_0$RDY_dCacheToParent_rsToP_first && core_0$RDY_dCacheToParent_rsToP_deq && + core_0$RDY_dCacheToParent_rsToP_first && (!propDstIdx_1_0_dummy2_0$Q_OUT || !propDstIdx_1_0_dummy2_1$Q_OUT || !propDstIdx_1_0_rl) ; @@ -3184,8 +3120,8 @@ module mkProc(CLK, // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = - core_0$RDY_iCacheToParent_rsToP_first && core_0$RDY_iCacheToParent_rsToP_deq && + core_0$RDY_iCacheToParent_rsToP_first && (!propDstIdx_1_1_dummy2_0$Q_OUT || !propDstIdx_1_1_dummy2_1$Q_OUT || !propDstIdx_1_1_rl) ; @@ -3198,41 +3134,37 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244 ; + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3284,11 +3216,6 @@ module mkProc(CLK, assign CAN_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ; assign WILL_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ; - // rule RL_rl_init_finish - assign CAN_FIRE_RL_rl_init_finish = - core_0$RDY_init_server_response_get && f_init_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_init_finish = CAN_FIRE_RL_rl_init_finish ; - // rule RL_rl_terminate assign CAN_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ; assign WILL_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ; @@ -3318,13 +3245,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2274 == 4'd0 ; + b__h2086 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2274 != 4'd0 && + b__h2086 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3348,23 +3275,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_12_ULT_99___d313 ; + mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_12_ULT_99___d313 ; + !mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 && + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3381,7 +3308,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 && + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3390,7 +3317,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 && + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3406,8 +3333,8 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMTimeCmpDone assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone = - core_0$RDY_mmioToPlatform_cRs_deq && core_0$RDY_mmioToPlatform_pRs_enq && + core_0$RDY_mmioToPlatform_cRs_deq && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone = @@ -3436,7 +3363,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40481 == 64'd0 || + x__h40290 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3454,7 +3381,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3462,14 +3389,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3479,22 +3406,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939 && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938 && + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3570,10 +3497,105 @@ module mkProc(CLK, assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ; assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ; + // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_st_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + !llc$dma_respSt_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd1 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + !llc$dma_respLd_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd2 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + // rule RL_llc_mem_server_srcPropose assign CAN_FIRE_RL_llc_mem_server_srcPropose = - core_0$RDY_tlbToMem_memReq_first && core_0$RDY_tlbToMem_memReq_deq && + core_0$RDY_tlbToMem_memReq_first && (!llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT || !llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT || !llc_mem_server_propDstIdx_0_rl) ; @@ -3588,84 +3610,32 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__499_THE_ETC___d1504 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_wr - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b011 || - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] || - llc$RDY_dma_memReq_enq) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_rd - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b011 || - llc$RDY_dma_memReq_enq && - llc_mem_server_f_dword_in_line$FULL_N) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - // rule RL_llc_mem_server_sendTlbReqToLLC assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC = llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ; assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC = CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendLdRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && - llc_mem_server_f_dword_in_line$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && - !llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && - llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + core_0$RDY_tlbToMem_respLd_enq && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; - // rule RL_llc_mem_server_sendStRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && - llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && - !llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; - // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3713,28 +3683,23 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h123837 == 4'd0 ; + b__h132793 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h123837 != 4'd0 && + b__h132793 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_rl_init_start - assign CAN_FIRE_RL_rl_init_start = - core_0$RDY_init_server_request_put && f_init_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_init_start = CAN_FIRE_RL_rl_init_start ; - // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 ; + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3742,41 +3707,36 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 || + (!mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1604 ; - assign MUX_llc$dma_memReq_enq_1__SEL_2 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign MUX_mmioPlatform_amoResp$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3788,12 +3748,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || @@ -3823,20 +3783,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h27934 } ; + x_data__h27743 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3850,35 +3810,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29351 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29160 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -3887,91 +3847,44 @@ module mkProc(CLK, { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } : mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = - { req_addr__h94973, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, + { llc_mem_server_rg_cacheline_cache_addr, + 64'hFFFFFFFFFFFFFFFF, + llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h105833, + { line_addr__h100665, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = + { line_addr__h100814, + 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], 577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd1) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[127:64], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd0) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[63:0] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = + llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd4194304 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305) ? @@ -3982,7 +3895,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366))) ; + IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -3995,11 +3908,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4010,32 +3923,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 or + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 or + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4043,75 +3956,75 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ? + (mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45623 } ; + x__h45432 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47735, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47544, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40481 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40290 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40481 != 64'd0 ; + x__h40290 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38388 == 64'd0 ; + x__h38197 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h59027 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58836 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x9027_0_n__read_addr9209_1_n__read_addr92_ETC__q15, - SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129 } ; + CASE_x8836_0_n__read_addr9018_1_n__read_addr91_ETC__q15, + SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77912 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77721 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7912_0_n__read_addr8090_1_n__read_addr81_ETC__q26, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431 } ; + CASE_x7721_0_n__read_addr7899_1_n__read_addr79_ETC__q26, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h93111, n__read_snd_id__h93112 } ; + { 1'd1, n__read_snd_addr__h122318, n__read_snd_id__h122319 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4160,15 +4073,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2274 - 4'd1 ; + b__h2086 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2274 ; - assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_init_start ? - 4'd0 : - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h2086 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4217,15 +4126,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h123837 - 4'd1 ; + b__h132793 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h123837 ; - assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_init_start ? - 4'd0 : - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h132793 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4234,10 +4139,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008, + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4245,8 +4150,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244, - IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283 } ; + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243, + IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4255,7 +4160,7 @@ module mkProc(CLK, // register llc_axi4_adapter_ctr_wr_rsps_pending_crg assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register llc_axi4_adapter_master_xactor_crg_rd_addr_full @@ -4285,7 +4190,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h124130, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133086, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4296,13 +4201,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h138054, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147010, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h137969, strb8__h137970, 1'd1 } ; + { data64__h146925, strb8__h146926, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4314,7 +4219,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h124832 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h133788 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4345,10 +4250,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__499_THE_ETC___d1504, + IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4362,10 +4267,66 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__484_ETC___d1487 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; + // register llc_mem_server_rg_cacheline_cache_addr + assign llc_mem_server_rg_cacheline_cache_addr$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? + line_addr__h100665 : + line_addr__h100814 ; + assign llc_mem_server_rg_cacheline_cache_addr$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; + + // register llc_mem_server_rg_cacheline_cache_data + assign llc_mem_server_rg_cacheline_cache_data$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 : + llc$dma_respLd_first[516:5] ; + assign llc_mem_server_rg_cacheline_cache_data$EN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 10'd1023 : + MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ; + assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // register llc_mem_server_rg_cacheline_cache_state + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3; + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4; + default: llc_mem_server_rg_cacheline_cache_state$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign llc_mem_server_rg_cacheline_cache_state$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + // register mmioPlatform_amoResp assign mmioPlatform_amoResp$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ? @@ -4388,7 +4349,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4401,11 +4362,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 && + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4415,11 +4376,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4433,7 +4394,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_data_0$D_IN = mmioPlatform_fromHostQ_enqReq_rl[63:0] ; assign mmioPlatform_fromHostQ_data_0$EN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] ; @@ -4445,7 +4406,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_empty$D_IN = mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_fromHostQ_clearReq_rl || - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 ; + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 ; assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ; // register mmioPlatform_fromHostQ_enqReq_rl @@ -4454,8 +4415,8 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_full assign mmioPlatform_fromHostQ_full$D_IN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 ; + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 ; assign mmioPlatform_fromHostQ_full$EN = 1'd1 ; // register mmioPlatform_instSel @@ -4466,16 +4427,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32362 : + newData__h32171 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4484,7 +4445,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29432 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29241 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4494,9 +4455,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4598,9 +4559,9 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] : mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4610,7 +4571,7 @@ module mkProc(CLK, assign mmioPlatform_toHostQ_empty$D_IN = mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_toHostQ_clearReq_rl || - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 ; + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 ; assign mmioPlatform_toHostQ_empty$EN = 1'd1 ; // register mmioPlatform_toHostQ_enqReq_rl @@ -4619,8 +4580,8 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 ; + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 ; assign mmioPlatform_toHostQ_full$EN = 1'd1 ; // register mmioPlatform_waitLowerMSIPCRs @@ -4630,7 +4591,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4638,15 +4599,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4654,7 +4615,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full @@ -4705,8 +4666,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_master_xactor_rg_wr_data assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], + { mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64], 1'd1 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN = @@ -4728,28 +4688,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173, + { IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 } ; + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211, + { IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 } ; + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4762,36 +4722,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 ; + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 ; + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -4892,9 +4852,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h121954, llc$dma_respLd_first[3] } ; - assign core_0$EN_init_server_request_put = CAN_FIRE_RL_rl_init_start ; - assign core_0$EN_init_server_response_get = CAN_FIRE_RL_rl_init_finish ; + { ld_data__h131014, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4915,13 +4873,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 || + (!mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -4932,15 +4890,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 || + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -4979,7 +4937,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -4988,39 +4946,31 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ; - // submodule f_init_reqs - assign f_init_reqs$ENQ = EN_init_server_request_put ; - assign f_init_reqs$DEQ = - core_0$RDY_init_server_request_put && f_init_reqs$EMPTY_N ; - assign f_init_reqs$CLR = 1'b0 ; - - // submodule f_init_rsps - assign f_init_rsps$ENQ = - core_0$RDY_init_server_response_get && f_init_rsps$FULL_N ; - assign f_init_rsps$DEQ = EN_init_server_response_get ; - assign f_init_rsps$CLR = 1'b0 ; - // submodule llc always@(MUX_llc$dma_memReq_enq_1__SEL_1 or MUX_llc$dma_memReq_enq_1__VAL_1 or - MUX_llc$dma_memReq_enq_1__SEL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or MUX_llc$dma_memReq_enq_1__VAL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or + MUX_llc$dma_memReq_enq_1__VAL_3 or WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or - MUX_llc$dma_memReq_enq_1__VAL_3) + MUX_llc$dma_memReq_enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case MUX_llc$dma_memReq_enq_1__SEL_1: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1; - MUX_llc$dma_memReq_enq_1__SEL_2: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2; - WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3; + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4; default: llc$dma_memReq_enq_x = 645'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5028,17 +4978,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 } ; + { IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h124832, + { new_cline__h133788, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5047,26 +4997,18 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign llc$EN_dma_memReq_enq = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1604 || - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; assign llc$EN_dma_respLd_deq = WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; assign llc$EN_dma_respSt_deq = WILL_FIRE_RL_llc_mem_server_sendStRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign llc$EN_to_mem_toM_deq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_rg_rd_req_beat == 3'd7 || @@ -5117,14 +5059,14 @@ module mkProc(CLK, debug_module_mem_server_arvalid && llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, rd_data_rdata__h120403, 3'd1 } ; + { 4'd0, dword__h91879, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = debug_module_mem_server_rready && llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ; @@ -5146,26 +5088,25 @@ module mkProc(CLK, debug_module_mem_server_awvalid && llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_data assign llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN = - { debug_module_mem_server_wid, - debug_module_mem_server_wdata, + { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast } ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ = debug_module_mem_server_wvalid && llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp assign llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN = 6'd0 ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ = debug_module_mem_server_bready && llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ; @@ -5174,7 +5115,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5182,12 +5123,9 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_doEnq ; // submodule llc_mem_server_f_dword_in_line - assign llc_mem_server_f_dword_in_line$D_IN = - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32] ; - assign llc_mem_server_f_dword_in_line$ENQ = - MUX_llc$dma_memReq_enq_1__SEL_2 ; - assign llc_mem_server_f_dword_in_line$DEQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ; + assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ; assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ; // submodule llc_mem_server_propDstData_0_dummy2_0 @@ -5207,11 +5145,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5405,86 +5343,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27519 && - mmioPlatform_reqBE_BIT_0___h27559, + mmioPlatform_reqBE_BIT_4___h27328 && + mmioPlatform_reqBE_BIT_0___h27368, 2'd0 }), - .amoExec_current_data(x__h34813), - .amoExec_in_data(mmioPlatform_reqData__h46219), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27519 && - !mmioPlatform_reqBE_BIT_0___h27559), - .amoExec(x__h29543)); + .amoExec_current_data(x__h34622), + .amoExec_in_data(mmioPlatform_reqData__h46028), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && + !mmioPlatform_reqBE_BIT_0___h27368), + .amoExec(x__h29352)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27519 && - mmioPlatform_reqBE_BIT_0___h27559, + mmioPlatform_reqBE_BIT_4___h27328 && + mmioPlatform_reqBE_BIT_0___h27368, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34665), - .amoExec_in_data(mmioPlatform_reqData__h46219), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27519 && - !mmioPlatform_reqBE_BIT_0___h27559), - .amoExec(x__h32453)); + .amoExec_current_data(mmioPlatform_mtime__h34474), + .amoExec_in_data(mmioPlatform_reqData__h46028), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && + !mmioPlatform_reqBE_BIT_0___h27368), + .amoExec(x__h32262)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27519 && - mmioPlatform_reqBE_BIT_0___h27559, + mmioPlatform_reqBE_BIT_4___h27328 && + mmioPlatform_reqBE_BIT_0___h27368, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40198), - .amoExec_in_data(mmioPlatform_reqData__h46219), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27519 && - !mmioPlatform_reqBE_BIT_0___h27559), - .amoExec(x__h38399)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40007), + .amoExec_in_data(mmioPlatform_reqData__h46028), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && + !mmioPlatform_reqBE_BIT_0___h27368), + .amoExec(x__h38208)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27519 && - mmioPlatform_reqBE_BIT_0___h27559, + mmioPlatform_reqBE_BIT_4___h27328 && + mmioPlatform_reqBE_BIT_0___h27368, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h46219), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27519 && - !mmioPlatform_reqBE_BIT_0___h27559), - .amoExec(x__h40492)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = + .amoExec_in_data(mmioPlatform_reqData__h46028), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27328 && + !mmioPlatform_reqBE_BIT_0___h27368), + .amoExec(x__h40301)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37870 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + x1_avValue_data__h37679 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 = + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 = + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29432 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062 = - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 ? + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 = + newData__h29241 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061 = + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 : + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336 = - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 ? + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335 = + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 : + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 = - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 ? + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 ? + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; - assign IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366 = + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; + assign IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5492,89 +5430,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008 = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + assign IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007 = + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282 = + assign IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - x__h72841 } ; - assign IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283 = + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + x__h72650 } ; + assign IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282 } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__499_THE_ETC___d1504 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 ? + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556 = + { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd7) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[511:448], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd6) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[447:384], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd5) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[383:320], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd4) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[319:256] } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd3) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[255:192], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd2) ? + new_dword__h87570 : + llc_mem_server_rg_cacheline_cache_data[191:128] } ; + assign IF_llc_mem_server_enqDst_0_lat_0_whas__647_THE_ETC___d1652 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__484_ETC___d1487 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 = - ((mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + assign IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 = + ((mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q3 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q4 } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5587,23 +5552,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5616,23 +5581,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -5645,144 +5610,144 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 = + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 = + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40481 == 64'd0 : - x__h38388 == 64'd0, + x__h40290 == 64'd0 : + x__h38197 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42556 } ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = + x1_avValue_data__h42365 } ; + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = + assign IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 = mmioPlatform_waitLowerMSIPCRs ? - core_0$RDY_mmioToPlatform_cRs_first && - core_0$RDY_mmioToPlatform_cRs_deq : + core_0$RDY_mmioToPlatform_cRs_deq && + core_0$RDY_mmioToPlatform_cRs_first : (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_first) && + core_0$RDY_mmioToPlatform_cRs_deq) && (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939 = + core_0$RDY_mmioToPlatform_cRs_first) ; + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951) : mmioPlatform_fetchedInsts_0 ; - assign IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081 = + assign IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091 = + assign IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085 = + assign IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095 = + assign IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 = + assign IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 = + assign IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 = + assign IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 = + assign IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 = + assign NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 || - IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062) ; - assign NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 || + IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061) ; + assign NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__484_ETC___d1487 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__632_ETC___d1635 ; + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5793,7 +5758,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5804,7 +5769,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5816,7 +5781,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5828,7 +5793,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5838,7 +5803,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5848,44 +5813,44 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 = + assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 = !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_fromHostQ_clearReq_rl ; - assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 = + assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 = (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT || !mmioPlatform_fromHostQ_enqReq_rl[64]) && (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT && (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 = + assign NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || !core_0$mmioToPlatform_cRq_notEmpty || - core_0$RDY_mmioToPlatform_cRq_first && - core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = + core_0$RDY_mmioToPlatform_cRq_deq && + core_0$RDY_mmioToPlatform_cRq_first ; + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 = + assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_toHostQ_clearReq_rl ; - assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 = + assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 = (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT || (mmioPlatform_toHostQ_enqReq_lat_0$whas ? !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -5894,107 +5859,115 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351 = + assign NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353 = + assign NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 = + assign NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 = + assign NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign NOT_propDstIdx_1_1_dummy2_1_read__309_310_OR_I_ETC___d1442 = + assign NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441 = !propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_propDstIdx_1_dummy2_1_read__040_041_OR_IF__ETC___d1140 = + assign NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139 = !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129 = - { CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, - SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431 = - { CASE_x7912_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x7912_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424, - x__h80328 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373 = - { CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128 = - { CASE_x9027_0_propDstData_0_dummy2_1_read__065__ETC__q12, - x__h59341, - x__h59348 } ; - assign b__h123837 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128 = + { CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, + SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430 = + { CASE_x7721_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x7721_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423, + x__h80137 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372 = + { CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127 = + { CASE_x8836_0_propDstData_0_dummy2_1_read__064__ETC__q12, + x__h59150, + x__h59157 } ; + assign b__h132793 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2274 = + assign b__h2086 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29351 = + assign data__h29160 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29144, 32'd0 } ; - assign failed_testnum__h152914 = + { v__h28953, 32'd0 } ; + assign failed_testnum__h161571 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h105833 = + assign line_addr__h100665 = + { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], + 6'b0 } ; + assign line_addr__h100814 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1604 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign mem_req_rd_addr_araddr__h124130 = - { llc$to_mem_toM_first[68:11], x__h124165 } ; - assign mem_req_wr_addr_awaddr__h138054 = - { llc$to_mem_toM_first[639:582], x__h138079 } ; - assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 = + line_addr__h100814 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 = + line_addr__h100665 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h87566 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'hFF : + 8'h0 } ; + assign mem_req_rd_addr_araddr__h133086 = + { llc$to_mem_toM_first[68:11], x__h133121 } ; + assign mem_req_wr_addr_awaddr__h147010 = + { llc$to_mem_toM_first[639:582], x__h147035 } ; + assign mmioPlatform_cycle_11_ULT_99___d312 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40198 = + assign mmioPlatform_fromHostQ_data_0__h40007 = mmioPlatform_fromHostQ_data_0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = + assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] || (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT || @@ -6003,275 +5976,273 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34665 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32362 ; - assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = + assign mmioPlatform_mtime__h34474 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 = + mmioPlatform_mtimecmp_0 <= newData__h32171 ; + assign mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27559 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27519 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h46219 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = + assign mmioPlatform_reqBE_BIT_0___h27368 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27328 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h46028 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (!IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (!mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 = + assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 || + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 || (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h59209 = + assign n__read_addr__h59018 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59294 = + assign n__read_addr__h59103 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h78090 = + assign n__read_addr__h77899 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168 : + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167 : 64'd0 ; - assign n__read_addr__h78169 = + assign n__read_addr__h77978 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206 : + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205 : 64'd0 ; - assign n__read_child__h59214 = + assign n__read_child__h59023 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59299 = + assign n__read_child__h59108 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h78093 = + assign n__read_child__h77902 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 ; - assign n__read_child__h78172 = + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 ; + assign n__read_child__h77981 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 ; - assign n__read_id__h59213 = + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 ; + assign n__read_id__h59022 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59298 = + assign n__read_id__h59107 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h93111 = + assign n__read_snd_addr__h122318 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h93112 = + assign n__read_snd_id__h122319 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h29432 = + assign newData__h29241 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29543 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32362 = + x__h29352 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 ; + assign newData__h32171 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32453 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h124832 = + x__h32262 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 ; + assign new_cline__h133788 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h46235 = - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 + - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ; - assign op_result__h46765 = w1__h45632 ^ w2__h45634 ; - assign op_result__h46770 = w1__h45632 & w2__h45634 ; - assign op_result__h46775 = w1__h45632 | w2__h45634 ; - assign op_result__h46780 = - (w1__h45632 < w2__h45634) ? w1__h45632 : w2__h45634 ; - assign op_result__h46786 = - (w1__h45632 <= w2__h45634) ? w2__h45634 : w1__h45632 ; - assign op_result__h46793 = - ((IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 ^ + assign new_dword__h87570 = x__h88732 | y__h88733 ; + assign op_result__h46044 = + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 + + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ; + assign op_result__h46574 = w1__h45441 ^ w2__h45443 ; + assign op_result__h46579 = w1__h45441 & w2__h45443 ; + assign op_result__h46584 = w1__h45441 | w2__h45443 ; + assign op_result__h46589 = + (w1__h45441 < w2__h45443) ? w1__h45441 : w2__h45443 ; + assign op_result__h46595 = + (w1__h45441 <= w2__h45443) ? w2__h45443 : w1__h45441 ; + assign op_result__h46602 = + ((IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ^ + (IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000)) ? - w1__h45632 : - w2__h45634 ; - assign op_result__h46799 = - ((IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 ^ + w1__h45441 : + w2__h45443 ; + assign op_result__h46608 = + ((IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ^ + (IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000)) ? - w2__h45634 : - w1__h45632 ; - assign propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101 = + w2__h45443 : + w1__h45441 ; + assign propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105 = + assign propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign req_addr__h94973 = - { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], - 6'b0 } ; - assign result__h45678 = + assign result__h45487 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0] } ; - assign result__h45802 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45830 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45858 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45886 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45914 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45942 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45970 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45998 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h46043 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h46071 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h46099 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h46127 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h46168 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h46196 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46322 = + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0] } ; + assign result__h45611 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45639 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45667 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45695 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45723 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45751 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45779 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45807 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45852 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45880 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45908 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45936 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45977 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h46005 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h46131 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46349 = + assign result__h46158 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46376 = + assign result__h46185 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46403 = + assign result__h46212 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46430 = + assign result__h46239 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46457 = + assign result__h46266 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46484 = + assign result__h46293 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46511 = + assign result__h46320 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46555 = + assign result__h46364 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46582 = + assign result__h46391 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46609 = + assign result__h46418 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46636 = + assign result__h46445 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46676 = + assign result__h46485 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46703 = + assign result__h46512 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46820 = + assign result__h46629 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46886 = + assign result__h46695 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46952 = + assign result__h46761 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h47018 = + assign result__h46827 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h47084 = + assign result__h46893 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h47150 = + assign result__h46959 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h47216 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + assign result__h47025 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47278 = + assign result__h47087 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0] } ; - assign result__h47323 = + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0] } ; + assign result__h47132 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47389 = + assign result__h47198 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47455 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + assign result__h47264 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47513 = + assign result__h47322 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[31:0] } ; - assign result__h47558 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[31:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[31:0] } ; + assign result__h47367 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29144 = mmioPlatform_waitUpperMSIPCRs ? v__h29181 : 32'd0 ; - assign v__h29181 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15627_BITS_31_TO_0__q7 = w1__h45627[31:0] ; - assign w1___1__h45737 = { 32'd0, w1__h45627[31:0] } ; - assign w25628_BITS_31_TO_0__q8 = w2__h45628[31:0] ; - assign w2___1__h45738 = { 32'd0, w2__h45628[31:0] } ; - assign x1_avValue_data__h37870 = + assign v__h28953 = mmioPlatform_waitUpperMSIPCRs ? v__h28990 : 32'd0 ; + assign v__h28990 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15436_BITS_31_TO_0__q7 = w1__h45436[31:0] ; + assign w1___1__h45546 = { 32'd0, w1__h45436[31:0] } ; + assign w25437_BITS_31_TO_0__q8 = w2__h45437[31:0] ; + assign w2___1__h45547 = { 32'd0, w2__h45437[31:0] } ; + assign x1_avValue_data__h37679 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42556 = + assign x1_avValue_data__h42365 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h124165 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h138079 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34813 = mmioPlatform_mtimecmp_0 ; - assign x__h38388 = + assign x__h133121 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147035 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34622 = mmioPlatform_mtimecmp_0 ; + assign x__h38197 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38399 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679 ; - assign x__h40481 = + x__h38208 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678 ; + assign x__h40290 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40492 : + x__h40301 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6280,461 +6251,512 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47735 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h59027 = - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 ? + assign x__h47544 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58836 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 ; - assign x__h72841 = + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 ; + assign x__h72650 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 ; - assign x__h77912 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 ? + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 ; + assign x__h77721 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 ; - assign x_data__h27934 = { 31'd0, mmioPlatform_reqData[0] } ; - always@(llc_mem_server_f_dword_in_line$D_OUT or llc$dma_respLd_first) + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 ; + assign x__h88732 = old_dword__h87569 & y__h88734 ; + assign x_data__h27743 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h88733 = + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & + mask__h87566 ; + assign y__h88734 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'd0 : + 8'd255 } ; + always@(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) begin - case (llc_mem_server_f_dword_in_line$D_OUT) - 3'd0: rd_data_rdata__h120403 = llc$dma_respLd_first[68:5]; - 3'd1: rd_data_rdata__h120403 = llc$dma_respLd_first[132:69]; - 3'd2: rd_data_rdata__h120403 = llc$dma_respLd_first[196:133]; - 3'd3: rd_data_rdata__h120403 = llc$dma_respLd_first[260:197]; - 3'd4: rd_data_rdata__h120403 = llc$dma_respLd_first[324:261]; - 3'd5: rd_data_rdata__h120403 = llc$dma_respLd_first[388:325]; - 3'd6: rd_data_rdata__h120403 = llc$dma_respLd_first[452:389]; - 3'd7: rd_data_rdata__h120403 = llc$dma_respLd_first[516:453]; + case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) + 3'd0: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h91879 = llc_mem_server_rg_cacheline_cache_data[511:448]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat) + 3'd0: data64__h146925 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h146925 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h146925 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h146925 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h146925 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h146925 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h146925 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h146925 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h121954 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h121954 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h121954 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h121954 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h121954 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h121954 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h121954 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h121954 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131014 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131014 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131014 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131014 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131014 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131014 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131014 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131014 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h137969 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h137969 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h137969 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h137969 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h137969 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h137969 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h137969 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h137969 = llc$to_mem_toM_first[511:448]; + 3'd0: strb8__h146926 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h146926 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h146926 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h146926 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h146926 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h146926 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h146926 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h146926 = llc$to_mem_toM_first[575:568]; endcase end - always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) begin - case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h137970 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h137970 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h137970 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h137970 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h137970 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h137970 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h137970 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h137970 = llc$to_mem_toM_first[575:568]; + case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) + 3'd0: old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: + old_dword__h87569 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h45802 or - result__h45830 or - result__h45858 or - result__h45886 or - result__h45914 or - result__h45942 or result__h45970 or result__h45998) + result__h45611 or + result__h45639 or + result__h45667 or + result__h45695 or + result__h45723 or + result__h45751 or result__h45779 or result__h45807) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45802; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45611; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45830; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45639; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45858; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45667; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45886; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45695; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45914; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45723; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45942; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45751; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45970; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45779; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45998; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45807; endcase end always@(mmioPlatform_curReq or - result__h46043 or - result__h46071 or result__h46099 or result__h46127) + result__h45852 or + result__h45880 or result__h45908 or result__h45936) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46043; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45852; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46071; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45880; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46099; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45908; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46127; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45936; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h46168 or result__h46196) + always@(mmioPlatform_curReq or result__h45977 or result__h46005) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h46168; + result__h45977; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h46196; + result__h46005; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45628 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; + w2__h45437 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; 2'b01: - w2__h45628 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; + w2__h45437 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; 2'b10: - w2__h45628 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h45437 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h45628 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + w2__h45437 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or - w2___1__h45738 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or + w2___1__h45547 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45634 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; + w2__h45443 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; 2'b01: - w2__h45634 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; - 2'b10: w2__h45634 = w2___1__h45738; + w2__h45443 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; + 2'b10: w2__h45443 = w2___1__h45547; 2'b11: - w2__h45634 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + w2__h45443 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_curReq or - result__h46555 or - result__h46582 or result__h46609 or result__h46636) + result__h46364 or + result__h46391 or result__h46418 or result__h46445) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46555; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46364; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46582; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46391; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46609; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46418; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46636; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46445; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h46322 or - result__h46349 or - result__h46376 or - result__h46403 or - result__h46430 or - result__h46457 or result__h46484 or result__h46511) + result__h46131 or + result__h46158 or + result__h46185 or + result__h46212 or + result__h46239 or + result__h46266 or result__h46293 or result__h46320) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46322; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46131; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46349; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46158; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46376; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46185; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46403; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46212; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46430; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46239; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46457; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46266; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46484; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46293; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46511; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46320; endcase end - always@(mmioPlatform_curReq or result__h46676 or result__h46703) + always@(mmioPlatform_curReq or result__h46485 or result__h46512) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46676; + result__h46485; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46703; + result__h46512; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45627 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; + w1__h45436 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - w1__h45627 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; + w1__h45436 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; 2'b10: - w1__h45627 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h45436 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h45627 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + w1__h45436 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or - w1___1__h45737 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or + w1___1__h45546 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45632 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; + w1__h45441 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - w1__h45632 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; - 2'b10: w1__h45632 = w1___1__h45737; + w1__h45441 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; + 2'b10: w1__h45441 = w1___1__h45546; 2'b11: - w1__h45632 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + w1__h45441 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or - w15627_BITS_31_TO_0__q7 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or + w15436_BITS_31_TO_0__q7 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; 2'b10: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - { {32{w15627_BITS_31_TO_0__q7[31]}}, w15627_BITS_31_TO_0__q7 }; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + { {32{w15436_BITS_31_TO_0__q7[31]}}, w15436_BITS_31_TO_0__q7 }; 2'b11: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or - w25628_BITS_31_TO_0__q8 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or + w25437_BITS_31_TO_0__q8 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; 2'b01: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; 2'b10: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - { {32{w25628_BITS_31_TO_0__q8[31]}}, w25628_BITS_31_TO_0__q8 }; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + { {32{w25437_BITS_31_TO_0__q8[31]}}, w25437_BITS_31_TO_0__q8 }; 2'b11: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46799 or - w2__h45634 or - op_result__h46235 or - op_result__h46765 or - op_result__h46770 or - op_result__h46775 or - op_result__h46793 or op_result__h46780 or op_result__h46786) + op_result__h46608 or + w2__h45443 or + op_result__h46044 or + op_result__h46574 or + op_result__h46579 or + op_result__h46584 or + op_result__h46602 or op_result__h46589 or op_result__h46595) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - w2__h45634; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + w2__h45443; 4'd1: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46235; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46044; 4'd2: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46765; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46574; 4'd3: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46770; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46579; 4'd4: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46775; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46584; 4'd5: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46793; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46602; 4'd7: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46780; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46589; 4'd8: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46786; - default: IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46799; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46595; + default: IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46608; endcase end always@(mmioPlatform_curReq or - result__h47278 or - result__h47323 or result__h47389 or result__h47455) + result__h47087 or + result__h47132 or result__h47198 or result__h47264) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47278; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47087; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47323; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47132; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47389; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47198; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47455; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47264; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45678 or - result__h46820 or - result__h46886 or - result__h46952 or - result__h47018 or - result__h47084 or result__h47150 or result__h47216) + result__h45487 or + result__h46629 or + result__h46695 or + result__h46761 or + result__h46827 or + result__h46893 or result__h46959 or result__h47025) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h45678; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h45487; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46820; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46629; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46886; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46695; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46952; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46761; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47018; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46827; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47084; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46893; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47150; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46959; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47216; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h47025; endcase end - always@(mmioPlatform_curReq or result__h47513 or result__h47558) + always@(mmioPlatform_curReq or result__h47322 or result__h47367) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47513; + result__h47322; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47558; + result__h47367; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) begin case (mmioPlatform_reqSz) 2'b0: - x__h45623 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908; + x__h45432 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907; 2'b01: - x__h45623 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917; + x__h45432 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916; 2'b10: - x__h45623 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h45432 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45623 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + x__h45432 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6742,15 +6764,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 or + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6758,11 +6780,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520; + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 or + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6770,315 +6792,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586; + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 or + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984) + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977; + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984; + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 or + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158) + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151; + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158; + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157; endcase end - always@(x__h59027 or n__read_id__h59213 or n__read_id__h59298) + always@(x__h58836 or n__read_id__h59022 or n__read_id__h59107) begin - case (x__h59027) - 1'd0: x__h59341 = n__read_id__h59213; - 1'd1: x__h59341 = n__read_id__h59298; + case (x__h58836) + 1'd0: x__h59150 = n__read_id__h59022; + 1'd1: x__h59150 = n__read_id__h59107; endcase end - always@(x__h59027 or n__read_child__h59214 or n__read_child__h59299) + always@(x__h58836 or n__read_child__h59023 or n__read_child__h59108) begin - case (x__h59027) - 1'd0: x__h59348 = n__read_child__h59214; - 1'd1: x__h59348 = n__read_child__h59299; + case (x__h58836) + 1'd0: x__h59157 = n__read_child__h59023; + 1'd1: x__h59157 = n__read_child__h59108; endcase end - always@(x__h59027 or - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101 or - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105) + always@(x__h58836 or + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100 or + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104) begin - case (x__h59027) + case (x__h58836) 1'd0: - CASE_x9027_0_propDstData_0_dummy2_1_read__065__ETC__q12 = - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101; + CASE_x8836_0_propDstData_0_dummy2_1_read__064__ETC__q12 = + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100; 1'd1: - CASE_x9027_0_propDstData_0_dummy2_1_read__065__ETC__q12 = - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105; + CASE_x8836_0_propDstData_0_dummy2_1_read__064__ETC__q12 = + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104; endcase end - always@(x__h59027 or - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081 or - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085) + always@(x__h58836 or + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080 or + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084) begin - case (x__h59027) + case (x__h58836) 1'd0: - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081; + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080; 1'd1: - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085; + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084; endcase end - always@(x__h59027 or - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091 or - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095) + always@(x__h58836 or + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090 or + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094) begin - case (x__h59027) + case (x__h58836) 1'd0: - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091; + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090; 1'd1: - CASE_x9027_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095; + CASE_x8836_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094; endcase end - always@(x__h59027 or n__read_addr__h59209 or n__read_addr__h59294) + always@(x__h58836 or n__read_addr__h59018 or n__read_addr__h59103) begin - case (x__h59027) + case (x__h58836) 1'd0: - CASE_x9027_0_n__read_addr9209_1_n__read_addr92_ETC__q15 = - n__read_addr__h59209; + CASE_x8836_0_n__read_addr9018_1_n__read_addr91_ETC__q15 = + n__read_addr__h59018; 1'd1: - CASE_x9027_0_n__read_addr9209_1_n__read_addr92_ETC__q15 = - n__read_addr__h59294; + CASE_x8836_0_n__read_addr9018_1_n__read_addr91_ETC__q15 = + n__read_addr__h59103; endcase end - always@(x__h77912 or n__read_child__h78093 or n__read_child__h78172) + always@(x__h77721 or n__read_child__h77902 or n__read_child__h77981) begin - case (x__h77912) - 1'd0: x__h80328 = n__read_child__h78093; - 1'd1: x__h80328 = n__read_child__h78172; + case (x__h77721) + 1'd0: x__h80137 = n__read_child__h77902; + 1'd1: x__h80137 = n__read_child__h77981; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77912 or + always@(x__h77721 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7912_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7721_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77912 or + always@(x__h77721 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 or + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211) + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7721_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 : + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 : 2'd0; 1'd1: - CASE_x7912_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7721_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211 : + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210 : 2'd0; endcase end - always@(x__h77912 or - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351 or - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353) + always@(x__h77721 or + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350 or + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351; + CASE_x7721_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350; 1'd1: - CASE_x7912_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353; + CASE_x7721_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352; endcase end - always@(x__h77912 or n__read_addr__h78090 or n__read_addr__h78169) + always@(x__h77721 or n__read_addr__h77899 or n__read_addr__h77978) begin - case (x__h77912) + case (x__h77721) 1'd0: - CASE_x7912_0_n__read_addr8090_1_n__read_addr81_ETC__q26 = - n__read_addr__h78090; + CASE_x7721_0_n__read_addr7899_1_n__read_addr79_ETC__q26 = + n__read_addr__h77899; 1'd1: - CASE_x7912_0_n__read_addr8090_1_n__read_addr81_ETC__q26 = - n__read_addr__h78169; + CASE_x7721_0_n__read_addr7899_1_n__read_addr79_ETC__q26 = + n__read_addr__h77978; endcase end @@ -7114,6 +7136,10 @@ module mkProc(CLK, llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1; + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + 10'd0; + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3; mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0; mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7211,6 +7237,15 @@ module mkProc(CLK, if (llc_mem_server_propDstIdx_0_rl$EN) llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY llc_mem_server_propDstIdx_0_rl$D_IN; + if (llc_mem_server_rg_cacheline_cache_addr$EN) + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_addr$D_IN; + if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN) + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + if (llc_mem_server_rg_cacheline_cache_state$EN) + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_state$D_IN; if (mmioPlatform_cycle$EN) mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN; if (mmioPlatform_fromHostAddr$EN) @@ -7323,6 +7358,9 @@ module mkProc(CLK, if (llc_axi4_adapter_rg_cline$EN) llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_cline$D_IN; + if (llc_mem_server_rg_cacheline_cache_data$EN) + llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_data$D_IN; if (mmioPlatform_amoResp$EN) mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN; if (mmioPlatform_curReq$EN) @@ -7391,7 +7429,7 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; llc_axi4_adapter_rg_cline = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7402,6 +7440,11 @@ module mkProc(CLK, llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA; llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl = 1'h0; + llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_data = + 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA; + llc_mem_server_rg_cacheline_cache_state = 3'h2; mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA; mmioPlatform_cycle = 7'h2A; @@ -7446,7 +7489,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = @@ -7472,69 +7515,77 @@ module mkProc(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", + begin + v__h161964 = $stime; + #0; + end + v__h161958 = v__h161964 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h161958, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 && - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 && + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 && - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 && + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 && - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 && + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h59027 && - NOT_propDstIdx_1_dummy2_1_read__040_041_OR_IF__ETC___d1140) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58836 && + NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h59027 && - NOT_propDstIdx_1_dummy2_1_read__040_041_OR_IF__ETC___d1140) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58836 && + NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h59027 && - NOT_propDstIdx_1_dummy2_1_read__040_041_OR_IF__ETC___d1140) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58836 && + NOT_propDstIdx_1_dummy2_1_read__039_040_OR_IF__ETC___d1139) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 && - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 && + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 && - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 && + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 && - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 && + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77912 && - NOT_propDstIdx_1_1_dummy2_1_read__309_310_OR_I_ETC___d1442) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77721 && + NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77912 && - NOT_propDstIdx_1_1_dummy2_1_read__309_310_OR_I_ETC___d1442) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77721 && + NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77912 && - NOT_propDstIdx_1_1_dummy2_1_read__309_310_OR_I_ETC___d1442) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77721 && + NOT_propDstIdx_1_1_dummy2_1_read__308_309_OR_I_ETC___d1441) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (core_0$RDY_coreIndInv_terminate) @@ -7542,14 +7593,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h152871 = $stime; + v__h161528 = $stime; #0; end - v__h152865 = v__h152871 / 32'd10; + v__h161522 = v__h161528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h152865, + v__h161522, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7559,7 +7610,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h152914); + $display("FAIL %0d", failed_testnum__h161571); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7567,14 +7618,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4104 = $stime; + v__h3916 = $stime; #0; end - v__h4098 = v__h4104 / 32'd10; + v__h3910 = v__h3916 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4098); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h3910); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7634,16 +7685,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4277 = $stime; + v__h4089 = $stime; #0; end - v__h4271 = v__h4277 / 32'd10; + v__h4083 = v__h4089 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4271); + v__h4083); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -7747,15 +7798,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4541 = $stime; + v__h4353 = $stime; #0; end - v__h4535 = v__h4541 / 32'd10; + v__h4347 = v__h4353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4535); + v__h4347); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7924,14 +7975,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6580 = $stime; + v__h6390 = $stime; #0; end - v__h6574 = v__h6580 / 32'd10; + v__h6384 = v__h6390 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6574); + $display("%0d: ERROR: CreditCounter: overflow", v__h6384); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8039,15 +8090,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8084,15 +8127,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2380 = $stime; + v__h2192 = $stime; #0; end - v__h2374 = v__h2380 / 32'd10; + v__h2186 = v__h2192 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2374); + v__h2186); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8357,14 +8400,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6881 = $stime; + v__h6690 = $stime; #0; end - v__h6875 = v__h6881 / 32'd10; + v__h6684 = v__h6690 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6875); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6684); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8401,15 +8444,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7374 = $stime; + v__h7183 = $stime; #0; end - v__h7368 = v__h7374 / 32'd10; + v__h7177 = v__h7183 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7368); + v__h7177); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -8449,14 +8492,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7537 = $stime; + v__h7346 = $stime; #0; end - v__h7531 = v__h7537 / 32'd10; + v__h7340 = v__h7346 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7531); + v__h7340); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -8648,7 +8691,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_toHostQ_empty) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 798, column 30\nCannot write tohost when toHostQ not empty"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 797, column 30\nCannot write tohost when toHostQ not empty"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && @@ -8665,7 +8708,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 820, column 33\nCannot do AMO on toHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 819, column 33\nCannot do AMO on toHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -8676,37 +8719,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40481 != 64'd0) + x__h40290 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40481 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); + x__h40290 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 855, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40481 != 64'd0) + x__h40290 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38388 != 64'd0) + x__h38197 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38388 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); + x__h38197 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 847, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38388 != 64'd0) + x__h38197 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -8719,7 +8762,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 871, column 33\nCannot do AMO on fromHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 870, column 33\nCannot do AMO on fromHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -8727,1101 +8770,144 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__530_ETC___d1537 && + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + begin + v__h99954 = $stime; + #0; + end + v__h99948 = v__h99954 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display("%0d: %m.fa_writeback line at %0h", + v__h99948, + llc_mem_server_rg_cacheline_cache_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + begin + v__h100752 = $stime; + #0; + end + v__h100746 = v__h100752 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h100746, + llc_mem_server_rg_cacheline_cache_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + begin + v__h100901 = $stime; + #0; + end + v__h100895 = v__h100901 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h100895, + llc_mem_server_rg_cacheline_cache_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); + if (RST_N != `BSV_RESET_VALUE) + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__678_ETC___d1685 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - begin - v__h94867 = $stime; - #0; - end - v__h94861 = v__h94867 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awsize is not code for 1,2,4,8", - v__h94861); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - begin - v__h94912 = $stime; - #0; - end - v__h94906 = v__h94912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: wlast is 1", - v__h94906); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1643) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - begin - v__h94822 = $stime; - #0; - end - v__h94816 = v__h94822 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awlen is not 0 (burst length is not 1)", - v__h94816); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - begin - v__h105904 = $stime; - #0; - end - v__h105898 = v__h105904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arsize is not code for 1,2,4,8", - v__h105898); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - begin - v__h105859 = $stime; - #0; - end - v__h105853 = v__h105859 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arlen is not 0 (burst length is not 1)", - v__h105853); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv\", line 304, column 25\nNo TLB st"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv\", line 423, column 25\nNo TLB st"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) begin - v__h124529 = $stime; + v__h133485 = $stime; #0; end - v__h124523 = v__h124529 / 32'd10; + v__h133479 = v__h133485 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h124523, + v__h133479, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784 && + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784 && + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h124696 = $stime; + v__h133652 = $stime; #0; end - v__h124690 = v__h124696 / 32'd10; + v__h133646 = v__h133652 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h124690); + v__h133646); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9883,135 +8969,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784 && + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784 && + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h126799 = $stime; + v__h135755 = $stime; #0; end - v__h126793 = v__h126799 / 32'd10; + v__h135749 = v__h135755 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h126793); + v__h135749); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11209,177 +10295,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h144145 = $stime; + v__h153099 = $stime; #0; end - v__h144139 = v__h144145 / 32'd10; + v__h153093 = v__h153099 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h144139); + $display("%0d: ERROR: CreditCounter: overflow", v__h153093); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("'h%h", mem_req_wr_addr_awaddr__h138054); + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + $write("'h%h", mem_req_wr_addr_awaddr__h147010); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("AXI4_Wr_Data { ", "wid: "); + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("'h%h", 4'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + $write("'h%h", data64__h146925); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("'h%h", data64__h137969); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("'h%h", strb8__h137970); + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + $write("'h%h", strb8__h146926); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h123910 = $stime; + v__h132866 = $stime; #0; end - v__h123904 = v__h123910 / 32'd10; + v__h132860 = v__h132866 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h123904, + v__h132860, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11450,159 +10528,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) - $write("'h%h", mem_req_rd_addr_araddr__h124130); + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) + $write("'h%h", mem_req_rd_addr_araddr__h133086); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) begin - v__h150840 = $stime; + v__h159793 = $stime; #0; end - v__h150834 = v__h150840 / 32'd10; + v__h159787 = v__h159793 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h150834, + v__h159787, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__767_U_ETC___d1784) + NOT_llc_axi4_adapter_cfg_verbosity_read__752_U_ETC___d1769) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h151348 = $stime; + v__h160301 = $stime; #0; end - v__h151342 = v__h151348 / 32'd10; + v__h160295 = v__h160301 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h151342); + v__h160295); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index ad9b421..6447566 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -13,19 +13,21 @@ // get_to_console_get O 8 reg // RDY_get_to_console_get O 1 reg // RDY_put_from_console_put O 1 reg -// RDY_set_watch_tohost O 1 const +// status O 8 reg +// RDY_start O 1 +// RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 unused // to_raw_mem_response_put I 256 // put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 -// set_watch_tohost_tohost_addr I 64 reg +// start_tohost_addr I 64 +// start_fromhost_addr I 64 reg // EN_set_verbosity I 1 // EN_to_raw_mem_response_put I 1 // EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 +// EN_start I 1 // EN_to_raw_mem_request_get I 1 // EN_get_to_console_get I 1 // @@ -46,7 +48,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkSoC_Top(CLK, +module mkSoC_Top(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -70,10 +73,13 @@ module mkSoC_Top(CLK, EN_put_from_console_put, RDY_put_from_console_put, - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); + status, + + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -103,19 +109,22 @@ module mkSoC_Top(CLK, input EN_put_from_console_put; output RDY_put_from_console_put; - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; + // value method status + output [7 : 0] status; + + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; // signals for module outputs wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get; + wire [7 : 0] get_to_console_get, status; wire RDY_get_to_console_get, RDY_put_from_console_put, RDY_set_verbosity, - RDY_set_watch_tohost, + RDY_start, RDY_to_raw_mem_request_get, RDY_to_raw_mem_response_put; @@ -143,8 +152,7 @@ module mkSoC_Top(CLK, boot_rom$slave_awqos, boot_rom$slave_awregion, boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; + boot_rom$slave_rid; wire [2 : 0] boot_rom$slave_arprot, boot_rom$slave_arsize, boot_rom$slave_awprot, @@ -169,6 +177,87 @@ module mkSoC_Top(CLK, boot_rom$slave_wready, boot_rom$slave_wvalid; + // ports of submodule boot_rom_axi4_deburster + wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, + boot_rom_axi4_deburster$from_master_awaddr, + boot_rom_axi4_deburster$from_master_rdata, + boot_rom_axi4_deburster$from_master_wdata, + boot_rom_axi4_deburster$to_slave_araddr, + boot_rom_axi4_deburster$to_slave_awaddr, + boot_rom_axi4_deburster$to_slave_rdata, + boot_rom_axi4_deburster$to_slave_wdata; + wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, + boot_rom_axi4_deburster$from_master_awlen, + boot_rom_axi4_deburster$from_master_wstrb, + boot_rom_axi4_deburster$to_slave_arlen, + boot_rom_axi4_deburster$to_slave_awlen, + boot_rom_axi4_deburster$to_slave_wstrb; + wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, + boot_rom_axi4_deburster$from_master_arid, + boot_rom_axi4_deburster$from_master_arqos, + boot_rom_axi4_deburster$from_master_arregion, + boot_rom_axi4_deburster$from_master_awcache, + boot_rom_axi4_deburster$from_master_awid, + boot_rom_axi4_deburster$from_master_awqos, + boot_rom_axi4_deburster$from_master_awregion, + boot_rom_axi4_deburster$from_master_bid, + boot_rom_axi4_deburster$from_master_rid, + boot_rom_axi4_deburster$to_slave_arcache, + boot_rom_axi4_deburster$to_slave_arid, + boot_rom_axi4_deburster$to_slave_arqos, + boot_rom_axi4_deburster$to_slave_arregion, + boot_rom_axi4_deburster$to_slave_awcache, + boot_rom_axi4_deburster$to_slave_awid, + boot_rom_axi4_deburster$to_slave_awqos, + boot_rom_axi4_deburster$to_slave_awregion, + boot_rom_axi4_deburster$to_slave_bid, + boot_rom_axi4_deburster$to_slave_rid; + wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, + boot_rom_axi4_deburster$from_master_arsize, + boot_rom_axi4_deburster$from_master_awprot, + boot_rom_axi4_deburster$from_master_awsize, + boot_rom_axi4_deburster$to_slave_arprot, + boot_rom_axi4_deburster$to_slave_arsize, + boot_rom_axi4_deburster$to_slave_awprot, + boot_rom_axi4_deburster$to_slave_awsize; + wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, + boot_rom_axi4_deburster$from_master_awburst, + boot_rom_axi4_deburster$from_master_bresp, + boot_rom_axi4_deburster$from_master_rresp, + boot_rom_axi4_deburster$to_slave_arburst, + boot_rom_axi4_deburster$to_slave_awburst, + boot_rom_axi4_deburster$to_slave_bresp, + boot_rom_axi4_deburster$to_slave_rresp; + wire boot_rom_axi4_deburster$EN_reset, + boot_rom_axi4_deburster$from_master_arlock, + boot_rom_axi4_deburster$from_master_arready, + boot_rom_axi4_deburster$from_master_arvalid, + boot_rom_axi4_deburster$from_master_awlock, + boot_rom_axi4_deburster$from_master_awready, + boot_rom_axi4_deburster$from_master_awvalid, + boot_rom_axi4_deburster$from_master_bready, + boot_rom_axi4_deburster$from_master_bvalid, + boot_rom_axi4_deburster$from_master_rlast, + boot_rom_axi4_deburster$from_master_rready, + boot_rom_axi4_deburster$from_master_rvalid, + boot_rom_axi4_deburster$from_master_wlast, + boot_rom_axi4_deburster$from_master_wready, + boot_rom_axi4_deburster$from_master_wvalid, + boot_rom_axi4_deburster$to_slave_arlock, + boot_rom_axi4_deburster$to_slave_arready, + boot_rom_axi4_deburster$to_slave_arvalid, + boot_rom_axi4_deburster$to_slave_awlock, + boot_rom_axi4_deburster$to_slave_awready, + boot_rom_axi4_deburster$to_slave_awvalid, + boot_rom_axi4_deburster$to_slave_bready, + boot_rom_axi4_deburster$to_slave_bvalid, + boot_rom_axi4_deburster$to_slave_rlast, + boot_rom_axi4_deburster$to_slave_rready, + boot_rom_axi4_deburster$to_slave_rvalid, + boot_rom_axi4_deburster$to_slave_wlast, + boot_rom_axi4_deburster$to_slave_wready, + boot_rom_axi4_deburster$to_slave_wvalid; + // ports of submodule corew wire [63 : 0] corew$cpu_dmem_master_araddr, corew$cpu_dmem_master_awaddr, @@ -178,9 +267,9 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, - corew$set_htif_addrs_fromhost_addr, - corew$set_htif_addrs_tohost_addr, - corew$set_verbosity_logdelay; + corew$set_verbosity_logdelay, + corew$start_fromhost_addr, + corew$start_tohost_addr; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, corew$cpu_dmem_master_wstrb, @@ -197,7 +286,6 @@ module mkSoC_Top(CLK, corew$cpu_dmem_master_awregion, corew$cpu_dmem_master_bid, corew$cpu_dmem_master_rid, - corew$cpu_dmem_master_wid, corew$cpu_imem_master_arcache, corew$cpu_imem_master_arid, corew$cpu_imem_master_arqos, @@ -208,7 +296,6 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_awregion, corew$cpu_imem_master_bid, corew$cpu_imem_master_rid, - corew$cpu_imem_master_wid, corew$set_verbosity_verbosity; wire [2 : 0] corew$cpu_dmem_master_arprot, corew$cpu_dmem_master_arsize, @@ -226,12 +313,9 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_awburst, corew$cpu_imem_master_bresp, corew$cpu_imem_master_rresp; - wire corew$EN_cpu_reset_server_request_put, - corew$EN_cpu_reset_server_response_get, - corew$EN_set_htif_addrs, - corew$EN_set_verbosity, - corew$RDY_cpu_reset_server_request_put, - corew$RDY_cpu_reset_server_response_get, + wire corew$EN_set_verbosity, + corew$EN_start, + corew$RDY_start, corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, @@ -275,7 +359,8 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_rvalid, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, - corew$cpu_imem_master_wvalid; + corew$cpu_imem_master_wvalid, + corew$nmi_req_set_not_clear; // ports of submodule fabric wire [63 : 0] fabric$v_from_masters_0_araddr, @@ -324,7 +409,6 @@ module mkSoC_Top(CLK, fabric$v_from_masters_0_awregion, fabric$v_from_masters_0_bid, fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, fabric$v_from_masters_1_arcache, fabric$v_from_masters_1_arid, fabric$v_from_masters_1_arqos, @@ -335,7 +419,6 @@ module mkSoC_Top(CLK, fabric$v_from_masters_1_awregion, fabric$v_from_masters_1_bid, fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, fabric$v_to_slaves_0_arcache, fabric$v_to_slaves_0_arid, fabric$v_to_slaves_0_arqos, @@ -346,7 +429,6 @@ module mkSoC_Top(CLK, fabric$v_to_slaves_0_awregion, fabric$v_to_slaves_0_bid, fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, fabric$v_to_slaves_1_arcache, fabric$v_to_slaves_1_arid, fabric$v_to_slaves_1_arqos, @@ -357,7 +439,6 @@ module mkSoC_Top(CLK, fabric$v_to_slaves_1_awregion, fabric$v_to_slaves_1_bid, fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, fabric$v_to_slaves_2_arcache, fabric$v_to_slaves_2_arid, fabric$v_to_slaves_2_arqos, @@ -367,8 +448,7 @@ module mkSoC_Top(CLK, fabric$v_to_slaves_2_awqos, fabric$v_to_slaves_2_awregion, fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; + fabric$v_to_slaves_2_rid; wire [2 : 0] fabric$v_from_masters_0_arprot, fabric$v_from_masters_0_arsize, fabric$v_from_masters_0_awprot, @@ -495,7 +575,8 @@ module mkSoC_Top(CLK, mem0_controller$slave_wdata; wire [7 : 0] mem0_controller$slave_arlen, mem0_controller$slave_awlen, - mem0_controller$slave_wstrb; + mem0_controller$slave_wstrb, + mem0_controller$status; wire [3 : 0] mem0_controller$slave_arcache, mem0_controller$slave_arid, mem0_controller$slave_arqos, @@ -505,8 +586,7 @@ module mkSoC_Top(CLK, mem0_controller$slave_awqos, mem0_controller$slave_awregion, mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; + mem0_controller$slave_rid; wire [2 : 0] mem0_controller$slave_arprot, mem0_controller$slave_arsize, mem0_controller$slave_awprot, @@ -542,6 +622,87 @@ module mkSoC_Top(CLK, mem0_controller$slave_wready, mem0_controller$slave_wvalid; + // ports of submodule mem0_controller_axi4_deburster + wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, + mem0_controller_axi4_deburster$from_master_awaddr, + mem0_controller_axi4_deburster$from_master_rdata, + mem0_controller_axi4_deburster$from_master_wdata, + mem0_controller_axi4_deburster$to_slave_araddr, + mem0_controller_axi4_deburster$to_slave_awaddr, + mem0_controller_axi4_deburster$to_slave_rdata, + mem0_controller_axi4_deburster$to_slave_wdata; + wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, + mem0_controller_axi4_deburster$from_master_awlen, + mem0_controller_axi4_deburster$from_master_wstrb, + mem0_controller_axi4_deburster$to_slave_arlen, + mem0_controller_axi4_deburster$to_slave_awlen, + mem0_controller_axi4_deburster$to_slave_wstrb; + wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, + mem0_controller_axi4_deburster$from_master_arid, + mem0_controller_axi4_deburster$from_master_arqos, + mem0_controller_axi4_deburster$from_master_arregion, + mem0_controller_axi4_deburster$from_master_awcache, + mem0_controller_axi4_deburster$from_master_awid, + mem0_controller_axi4_deburster$from_master_awqos, + mem0_controller_axi4_deburster$from_master_awregion, + mem0_controller_axi4_deburster$from_master_bid, + mem0_controller_axi4_deburster$from_master_rid, + mem0_controller_axi4_deburster$to_slave_arcache, + mem0_controller_axi4_deburster$to_slave_arid, + mem0_controller_axi4_deburster$to_slave_arqos, + mem0_controller_axi4_deburster$to_slave_arregion, + mem0_controller_axi4_deburster$to_slave_awcache, + mem0_controller_axi4_deburster$to_slave_awid, + mem0_controller_axi4_deburster$to_slave_awqos, + mem0_controller_axi4_deburster$to_slave_awregion, + mem0_controller_axi4_deburster$to_slave_bid, + mem0_controller_axi4_deburster$to_slave_rid; + wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, + mem0_controller_axi4_deburster$from_master_arsize, + mem0_controller_axi4_deburster$from_master_awprot, + mem0_controller_axi4_deburster$from_master_awsize, + mem0_controller_axi4_deburster$to_slave_arprot, + mem0_controller_axi4_deburster$to_slave_arsize, + mem0_controller_axi4_deburster$to_slave_awprot, + mem0_controller_axi4_deburster$to_slave_awsize; + wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, + mem0_controller_axi4_deburster$from_master_awburst, + mem0_controller_axi4_deburster$from_master_bresp, + mem0_controller_axi4_deburster$from_master_rresp, + mem0_controller_axi4_deburster$to_slave_arburst, + mem0_controller_axi4_deburster$to_slave_awburst, + mem0_controller_axi4_deburster$to_slave_bresp, + mem0_controller_axi4_deburster$to_slave_rresp; + wire mem0_controller_axi4_deburster$EN_reset, + mem0_controller_axi4_deburster$from_master_arlock, + mem0_controller_axi4_deburster$from_master_arready, + mem0_controller_axi4_deburster$from_master_arvalid, + mem0_controller_axi4_deburster$from_master_awlock, + mem0_controller_axi4_deburster$from_master_awready, + mem0_controller_axi4_deburster$from_master_awvalid, + mem0_controller_axi4_deburster$from_master_bready, + mem0_controller_axi4_deburster$from_master_bvalid, + mem0_controller_axi4_deburster$from_master_rlast, + mem0_controller_axi4_deburster$from_master_rready, + mem0_controller_axi4_deburster$from_master_rvalid, + mem0_controller_axi4_deburster$from_master_wlast, + mem0_controller_axi4_deburster$from_master_wready, + mem0_controller_axi4_deburster$from_master_wvalid, + mem0_controller_axi4_deburster$to_slave_arlock, + mem0_controller_axi4_deburster$to_slave_arready, + mem0_controller_axi4_deburster$to_slave_arvalid, + mem0_controller_axi4_deburster$to_slave_awlock, + mem0_controller_axi4_deburster$to_slave_awready, + mem0_controller_axi4_deburster$to_slave_awvalid, + mem0_controller_axi4_deburster$to_slave_bready, + mem0_controller_axi4_deburster$to_slave_bvalid, + mem0_controller_axi4_deburster$to_slave_rlast, + mem0_controller_axi4_deburster$to_slave_rready, + mem0_controller_axi4_deburster$to_slave_rvalid, + mem0_controller_axi4_deburster$to_slave_wlast, + mem0_controller_axi4_deburster$to_slave_wready, + mem0_controller_axi4_deburster$to_slave_wvalid; + // ports of submodule soc_map wire [63 : 0] soc_map$m_boot_rom_addr_base, soc_map$m_boot_rom_addr_lim, @@ -574,8 +735,7 @@ module mkSoC_Top(CLK, uart0$slave_awqos, uart0$slave_awregion, uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; + uart0$slave_rid; wire [2 : 0] uart0$slave_arprot, uart0$slave_arsize, uart0$slave_awprot, @@ -616,32 +776,42 @@ module mkSoC_Top(CLK, CAN_FIRE_RL_rl_rd_addr_channel_2, CAN_FIRE_RL_rl_rd_addr_channel_3, CAN_FIRE_RL_rl_rd_addr_channel_4, + CAN_FIRE_RL_rl_rd_addr_channel_5, + CAN_FIRE_RL_rl_rd_addr_channel_6, CAN_FIRE_RL_rl_rd_data_channel, CAN_FIRE_RL_rl_rd_data_channel_1, CAN_FIRE_RL_rl_rd_data_channel_2, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_start_2, + CAN_FIRE_RL_rl_rd_data_channel_5, + CAN_FIRE_RL_rl_rd_data_channel_6, + CAN_FIRE_RL_rl_reset_complete_initial, + CAN_FIRE_RL_rl_reset_start_initial, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, CAN_FIRE_RL_rl_wr_addr_channel_3, CAN_FIRE_RL_rl_wr_addr_channel_4, + CAN_FIRE_RL_rl_wr_addr_channel_5, + CAN_FIRE_RL_rl_wr_addr_channel_6, CAN_FIRE_RL_rl_wr_data_channel, CAN_FIRE_RL_rl_wr_data_channel_1, CAN_FIRE_RL_rl_wr_data_channel_2, CAN_FIRE_RL_rl_wr_data_channel_3, CAN_FIRE_RL_rl_wr_data_channel_4, + CAN_FIRE_RL_rl_wr_data_channel_5, + CAN_FIRE_RL_rl_wr_data_channel_6, CAN_FIRE_RL_rl_wr_response_channel, CAN_FIRE_RL_rl_wr_response_channel_1, CAN_FIRE_RL_rl_wr_response_channel_2, CAN_FIRE_RL_rl_wr_response_channel_3, CAN_FIRE_RL_rl_wr_response_channel_4, + CAN_FIRE_RL_rl_wr_response_channel_5, + CAN_FIRE_RL_rl_wr_response_channel_6, CAN_FIRE_get_to_console_get, CAN_FIRE_put_from_console_put, CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, + CAN_FIRE_start, CAN_FIRE_to_raw_mem_request_get, CAN_FIRE_to_raw_mem_response_put, WILL_FIRE_RL_rl_connect_external_interrupt_requests, @@ -650,41 +820,53 @@ module mkSoC_Top(CLK, WILL_FIRE_RL_rl_rd_addr_channel_2, WILL_FIRE_RL_rl_rd_addr_channel_3, WILL_FIRE_RL_rl_rd_addr_channel_4, + WILL_FIRE_RL_rl_rd_addr_channel_5, + WILL_FIRE_RL_rl_rd_addr_channel_6, WILL_FIRE_RL_rl_rd_data_channel, WILL_FIRE_RL_rl_rd_data_channel_1, WILL_FIRE_RL_rl_rd_data_channel_2, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_start_2, + WILL_FIRE_RL_rl_rd_data_channel_5, + WILL_FIRE_RL_rl_rd_data_channel_6, + WILL_FIRE_RL_rl_reset_complete_initial, + WILL_FIRE_RL_rl_reset_start_initial, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, WILL_FIRE_RL_rl_wr_addr_channel_3, WILL_FIRE_RL_rl_wr_addr_channel_4, + WILL_FIRE_RL_rl_wr_addr_channel_5, + WILL_FIRE_RL_rl_wr_addr_channel_6, WILL_FIRE_RL_rl_wr_data_channel, WILL_FIRE_RL_rl_wr_data_channel_1, WILL_FIRE_RL_rl_wr_data_channel_2, WILL_FIRE_RL_rl_wr_data_channel_3, WILL_FIRE_RL_rl_wr_data_channel_4, + WILL_FIRE_RL_rl_wr_data_channel_5, + WILL_FIRE_RL_rl_wr_data_channel_6, WILL_FIRE_RL_rl_wr_response_channel, WILL_FIRE_RL_rl_wr_response_channel_1, WILL_FIRE_RL_rl_wr_response_channel_2, WILL_FIRE_RL_rl_wr_response_channel_3, WILL_FIRE_RL_rl_wr_response_channel_4, + WILL_FIRE_RL_rl_wr_response_channel_5, + WILL_FIRE_RL_rl_wr_response_channel_6, WILL_FIRE_get_to_console_get, WILL_FIRE_put_from_console_put, WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, + WILL_FIRE_start, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8689; - reg [31 : 0] v__h8949; - reg [31 : 0] v__h8683; - reg [31 : 0] v__h8943; + reg [31 : 0] v__h11619; + reg [31 : 0] v__h11080; + reg [31 : 0] v__h11328; + reg [31 : 0] v__h11074; + reg [31 : 0] v__h11322; + reg [31 : 0] v__h11613; // synopsys translate_on // action method set_verbosity @@ -718,10 +900,13 @@ module mkSoC_Top(CLK, assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; + // value method status + assign status = mem0_controller$status ; + + // action method start + assign RDY_start = corew$RDY_start ; + assign CAN_FIRE_start = corew$RDY_start ; + assign WILL_FIRE_start = EN_start ; // submodule boot_rom mkBoot_ROM boot_rom(.CLK(CLK), @@ -753,7 +938,6 @@ module mkSoC_Top(CLK, .slave_bready(boot_rom$slave_bready), .slave_rready(boot_rom$slave_rready), .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), .slave_wlast(boot_rom$slave_wlast), .slave_wstrb(boot_rom$slave_wstrb), .slave_wvalid(boot_rom$slave_wvalid), @@ -771,8 +955,93 @@ module mkSoC_Top(CLK, .slave_rresp(boot_rom$slave_rresp), .slave_rlast(boot_rom$slave_rlast)); + // submodule boot_rom_axi4_deburster + mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), + .RST_N(RST_N), + .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), + .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), + .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), + .from_master_arid(boot_rom_axi4_deburster$from_master_arid), + .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), + .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), + .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), + .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), + .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), + .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), + .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), + .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), + .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), + .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), + .from_master_awid(boot_rom_axi4_deburster$from_master_awid), + .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), + .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), + .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), + .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), + .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), + .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), + .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), + .from_master_bready(boot_rom_axi4_deburster$from_master_bready), + .from_master_rready(boot_rom_axi4_deburster$from_master_rready), + .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), + .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), + .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), + .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), + .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), + .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), + .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), + .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), + .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), + .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), + .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), + .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), + .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), + .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), + .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), + .EN_reset(boot_rom_axi4_deburster$EN_reset), + .RDY_reset(), + .from_master_awready(boot_rom_axi4_deburster$from_master_awready), + .from_master_wready(boot_rom_axi4_deburster$from_master_wready), + .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), + .from_master_bid(boot_rom_axi4_deburster$from_master_bid), + .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), + .from_master_arready(boot_rom_axi4_deburster$from_master_arready), + .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), + .from_master_rid(boot_rom_axi4_deburster$from_master_rid), + .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), + .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), + .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), + .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), + .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), + .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), + .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), + .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), + .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), + .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), + .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), + .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), + .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), + .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), + .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), + .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), + .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), + .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), + .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), + .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), + .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), + .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), + .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), + .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), + .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), + .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), + .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), + .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), + .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), + .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), + .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); + // submodule corew - mkCoreW corew(.CLK(CLK), + mkCoreW corew(.RST_N_dm_power_on_reset(RST_N_dm_power_on_reset), + .CLK(CLK), .RST_N(RST_N), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), @@ -812,18 +1081,15 @@ module mkSoC_Top(CLK, .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), - .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), - .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), + .nmi_req_set_not_clear(corew$nmi_req_set_not_clear), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), + .start_fromhost_addr(corew$start_fromhost_addr), + .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), - .EN_set_htif_addrs(corew$EN_set_htif_addrs), - .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), + .EN_start(corew$EN_start), .RDY_set_verbosity(), - .RDY_set_htif_addrs(), - .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), - .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), + .RDY_start(corew$RDY_start), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), .cpu_imem_master_awid(corew$cpu_imem_master_awid), .cpu_imem_master_awaddr(corew$cpu_imem_master_awaddr), @@ -836,7 +1102,6 @@ module mkSoC_Top(CLK, .cpu_imem_master_awqos(corew$cpu_imem_master_awqos), .cpu_imem_master_awregion(corew$cpu_imem_master_awregion), .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), - .cpu_imem_master_wid(corew$cpu_imem_master_wid), .cpu_imem_master_wdata(corew$cpu_imem_master_wdata), .cpu_imem_master_wstrb(corew$cpu_imem_master_wstrb), .cpu_imem_master_wlast(corew$cpu_imem_master_wlast), @@ -865,7 +1130,6 @@ module mkSoC_Top(CLK, .cpu_dmem_master_awqos(corew$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(corew$cpu_dmem_master_awregion), .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(corew$cpu_dmem_master_wid), .cpu_dmem_master_wdata(corew$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(corew$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(corew$cpu_dmem_master_wlast), @@ -912,7 +1176,6 @@ module mkSoC_Top(CLK, .v_from_masters_0_bready(fabric$v_from_masters_0_bready), .v_from_masters_0_rready(fabric$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), @@ -941,7 +1204,6 @@ module mkSoC_Top(CLK, .v_from_masters_1_bready(fabric$v_from_masters_1_bready), .v_from_masters_1_rready(fabric$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), @@ -1016,7 +1278,6 @@ module mkSoC_Top(CLK, .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), @@ -1045,7 +1306,6 @@ module mkSoC_Top(CLK, .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), @@ -1074,7 +1334,6 @@ module mkSoC_Top(CLK, .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), @@ -1124,7 +1383,6 @@ module mkSoC_Top(CLK, .slave_bready(mem0_controller$slave_bready), .slave_rready(mem0_controller$slave_rready), .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), .slave_wlast(mem0_controller$slave_wlast), .slave_wstrb(mem0_controller$slave_wstrb), .slave_wvalid(mem0_controller$slave_wvalid), @@ -1152,8 +1410,93 @@ module mkSoC_Top(CLK, .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), + .status(mem0_controller$status), .RDY_set_watch_tohost()); + // submodule mem0_controller_axi4_deburster + mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), + .RST_N(RST_N), + .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), + .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), + .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), + .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), + .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), + .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), + .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), + .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), + .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), + .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), + .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), + .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), + .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), + .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), + .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), + .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), + .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), + .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), + .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), + .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), + .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), + .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), + .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), + .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), + .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), + .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), + .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), + .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), + .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), + .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), + .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), + .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), + .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), + .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), + .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), + .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), + .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), + .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), + .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), + .EN_reset(mem0_controller_axi4_deburster$EN_reset), + .RDY_reset(), + .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), + .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), + .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), + .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), + .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), + .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), + .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), + .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), + .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), + .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), + .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), + .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), + .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), + .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), + .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), + .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), + .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), + .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), + .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), + .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), + .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), + .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), + .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), + .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), + .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), + .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), + .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), + .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), + .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), + .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), + .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), + .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), + .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), + .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), + .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), + .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), + .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), + .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), + .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); + // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), @@ -1216,7 +1559,6 @@ module mkSoC_Top(CLK, .slave_bready(uart0$slave_bready), .slave_rready(uart0$slave_rready), .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), .slave_wlast(uart0$slave_wlast), .slave_wstrb(uart0$slave_wstrb), .slave_wvalid(uart0$slave_wvalid), @@ -1344,66 +1686,176 @@ module mkSoC_Top(CLK, assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; + // rule RL_rl_wr_addr_channel_5 + assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; + + // rule RL_rl_wr_data_channel_5 + assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; + + // rule RL_rl_wr_response_channel_5 + assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; + + // rule RL_rl_rd_addr_channel_5 + assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; + assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; + + // rule RL_rl_rd_data_channel_5 + assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; + assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; + + // rule RL_rl_wr_addr_channel_6 + assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; + + // rule RL_rl_wr_data_channel_6 + assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; + + // rule RL_rl_wr_response_channel_6 + assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; + + // rule RL_rl_rd_addr_channel_6 + assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; + assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; + + // rule RL_rl_rd_data_channel_6 + assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; + assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; + // rule RL_rl_connect_external_interrupt_requests assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - // rule RL_rl_reset_start_2 - assign CAN_FIRE_RL_rl_reset_start_2 = + // rule RL_rl_reset_start_initial + assign CAN_FIRE_RL_rl_reset_start_initial = mem0_controller$RDY_server_reset_request_put && uart0$RDY_server_reset_request_put && - corew$RDY_cpu_reset_server_request_put && fabric$RDY_reset && rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start_2 = CAN_FIRE_RL_rl_reset_start_2 ; + assign WILL_FIRE_RL_rl_reset_start_initial = + CAN_FIRE_RL_rl_reset_start_initial ; - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = + // rule RL_rl_reset_complete_initial + assign CAN_FIRE_RL_rl_reset_complete_initial = mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && mem0_controller$RDY_set_addr_map && - corew$RDY_cpu_reset_server_response_get && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = CAN_FIRE_RL_rl_reset_complete ; + assign WILL_FIRE_RL_rl_reset_complete_initial = + CAN_FIRE_RL_rl_reset_complete_initial ; // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_2 ? 2'd1 : 2'd2 ; + assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_2 || WILL_FIRE_RL_rl_reset_complete ; + WILL_FIRE_RL_rl_reset_start_initial || + WILL_FIRE_RL_rl_reset_complete_initial ; // submodule boot_rom assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = fabric$v_to_slaves_0_araddr ; - assign boot_rom$slave_arburst = fabric$v_to_slaves_0_arburst ; - assign boot_rom$slave_arcache = fabric$v_to_slaves_0_arcache ; - assign boot_rom$slave_arid = fabric$v_to_slaves_0_arid ; - assign boot_rom$slave_arlen = fabric$v_to_slaves_0_arlen ; - assign boot_rom$slave_arlock = fabric$v_to_slaves_0_arlock ; - assign boot_rom$slave_arprot = fabric$v_to_slaves_0_arprot ; - assign boot_rom$slave_arqos = fabric$v_to_slaves_0_arqos ; - assign boot_rom$slave_arregion = fabric$v_to_slaves_0_arregion ; - assign boot_rom$slave_arsize = fabric$v_to_slaves_0_arsize ; - assign boot_rom$slave_arvalid = fabric$v_to_slaves_0_arvalid ; - assign boot_rom$slave_awaddr = fabric$v_to_slaves_0_awaddr ; - assign boot_rom$slave_awburst = fabric$v_to_slaves_0_awburst ; - assign boot_rom$slave_awcache = fabric$v_to_slaves_0_awcache ; - assign boot_rom$slave_awid = fabric$v_to_slaves_0_awid ; - assign boot_rom$slave_awlen = fabric$v_to_slaves_0_awlen ; - assign boot_rom$slave_awlock = fabric$v_to_slaves_0_awlock ; - assign boot_rom$slave_awprot = fabric$v_to_slaves_0_awprot ; - assign boot_rom$slave_awqos = fabric$v_to_slaves_0_awqos ; - assign boot_rom$slave_awregion = fabric$v_to_slaves_0_awregion ; - assign boot_rom$slave_awsize = fabric$v_to_slaves_0_awsize ; - assign boot_rom$slave_awvalid = fabric$v_to_slaves_0_awvalid ; - assign boot_rom$slave_bready = fabric$v_to_slaves_0_bready ; - assign boot_rom$slave_rready = fabric$v_to_slaves_0_rready ; - assign boot_rom$slave_wdata = fabric$v_to_slaves_0_wdata ; - assign boot_rom$slave_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom$slave_wlast = fabric$v_to_slaves_0_wlast ; - assign boot_rom$slave_wstrb = fabric$v_to_slaves_0_wstrb ; - assign boot_rom$slave_wvalid = fabric$v_to_slaves_0_wvalid ; - assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; + assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; + assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; + assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; + assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; + assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; + assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; + assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; + assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; + assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; + assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; + assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; + assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; + assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; + assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; + assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; + assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; + assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; + assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; + assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; + assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; + assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; + assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; + assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; + assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; + assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; + assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; + assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; + assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; + + // submodule boot_rom_axi4_deburster + assign boot_rom_axi4_deburster$from_master_araddr = + fabric$v_to_slaves_0_araddr ; + assign boot_rom_axi4_deburster$from_master_arburst = + fabric$v_to_slaves_0_arburst ; + assign boot_rom_axi4_deburster$from_master_arcache = + fabric$v_to_slaves_0_arcache ; + assign boot_rom_axi4_deburster$from_master_arid = + fabric$v_to_slaves_0_arid ; + assign boot_rom_axi4_deburster$from_master_arlen = + fabric$v_to_slaves_0_arlen ; + assign boot_rom_axi4_deburster$from_master_arlock = + fabric$v_to_slaves_0_arlock ; + assign boot_rom_axi4_deburster$from_master_arprot = + fabric$v_to_slaves_0_arprot ; + assign boot_rom_axi4_deburster$from_master_arqos = + fabric$v_to_slaves_0_arqos ; + assign boot_rom_axi4_deburster$from_master_arregion = + fabric$v_to_slaves_0_arregion ; + assign boot_rom_axi4_deburster$from_master_arsize = + fabric$v_to_slaves_0_arsize ; + assign boot_rom_axi4_deburster$from_master_arvalid = + fabric$v_to_slaves_0_arvalid ; + assign boot_rom_axi4_deburster$from_master_awaddr = + fabric$v_to_slaves_0_awaddr ; + assign boot_rom_axi4_deburster$from_master_awburst = + fabric$v_to_slaves_0_awburst ; + assign boot_rom_axi4_deburster$from_master_awcache = + fabric$v_to_slaves_0_awcache ; + assign boot_rom_axi4_deburster$from_master_awid = + fabric$v_to_slaves_0_awid ; + assign boot_rom_axi4_deburster$from_master_awlen = + fabric$v_to_slaves_0_awlen ; + assign boot_rom_axi4_deburster$from_master_awlock = + fabric$v_to_slaves_0_awlock ; + assign boot_rom_axi4_deburster$from_master_awprot = + fabric$v_to_slaves_0_awprot ; + assign boot_rom_axi4_deburster$from_master_awqos = + fabric$v_to_slaves_0_awqos ; + assign boot_rom_axi4_deburster$from_master_awregion = + fabric$v_to_slaves_0_awregion ; + assign boot_rom_axi4_deburster$from_master_awsize = + fabric$v_to_slaves_0_awsize ; + assign boot_rom_axi4_deburster$from_master_awvalid = + fabric$v_to_slaves_0_awvalid ; + assign boot_rom_axi4_deburster$from_master_bready = + fabric$v_to_slaves_0_bready ; + assign boot_rom_axi4_deburster$from_master_rready = + fabric$v_to_slaves_0_rready ; + assign boot_rom_axi4_deburster$from_master_wdata = + fabric$v_to_slaves_0_wdata ; + assign boot_rom_axi4_deburster$from_master_wlast = + fabric$v_to_slaves_0_wlast ; + assign boot_rom_axi4_deburster$from_master_wstrb = + fabric$v_to_slaves_0_wstrb ; + assign boot_rom_axi4_deburster$from_master_wvalid = + fabric$v_to_slaves_0_wvalid ; + assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; + assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; + assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; + assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; + assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; + assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; + assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; + assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; + assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; + assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; + assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; + assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; // submodule corew assign corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = @@ -1460,17 +1912,13 @@ module mkSoC_Top(CLK, assign corew$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; assign corew$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; assign corew$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign corew$set_htif_addrs_fromhost_addr = 64'h0000000080001040 ; - assign corew$set_htif_addrs_tohost_addr = set_watch_tohost_tohost_addr ; + assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = set_verbosity_logdelay ; assign corew$set_verbosity_verbosity = set_verbosity_verbosity ; + assign corew$start_fromhost_addr = start_fromhost_addr ; + assign corew$start_tohost_addr = start_tohost_addr ; assign corew$EN_set_verbosity = EN_set_verbosity ; - assign corew$EN_set_htif_addrs = - EN_set_watch_tohost && set_watch_tohost_watch_tohost ; - assign corew$EN_cpu_reset_server_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; - assign corew$EN_cpu_reset_server_response_get = - CAN_FIRE_RL_rl_reset_complete ; + assign corew$EN_start = EN_start ; // submodule fabric assign fabric$set_verbosity_verbosity = 4'h0 ; @@ -1499,7 +1947,6 @@ module mkSoC_Top(CLK, assign fabric$v_from_masters_0_bready = corew$cpu_imem_master_bready ; assign fabric$v_from_masters_0_rready = corew$cpu_imem_master_rready ; assign fabric$v_from_masters_0_wdata = corew$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = corew$cpu_imem_master_wid ; assign fabric$v_from_masters_0_wlast = corew$cpu_imem_master_wlast ; assign fabric$v_from_masters_0_wstrb = corew$cpu_imem_master_wstrb ; assign fabric$v_from_masters_0_wvalid = corew$cpu_imem_master_wvalid ; @@ -1528,32 +1975,51 @@ module mkSoC_Top(CLK, assign fabric$v_from_masters_1_bready = corew$cpu_dmem_master_bready ; assign fabric$v_from_masters_1_rready = corew$cpu_dmem_master_rready ; assign fabric$v_from_masters_1_wdata = corew$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = corew$cpu_dmem_master_wid ; assign fabric$v_from_masters_1_wlast = corew$cpu_dmem_master_wlast ; assign fabric$v_from_masters_1_wstrb = corew$cpu_dmem_master_wstrb ; assign fabric$v_from_masters_1_wvalid = corew$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = boot_rom$slave_arready ; - assign fabric$v_to_slaves_0_awready = boot_rom$slave_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom$slave_bid ; - assign fabric$v_to_slaves_0_bresp = boot_rom$slave_bresp ; - assign fabric$v_to_slaves_0_bvalid = boot_rom$slave_bvalid ; - assign fabric$v_to_slaves_0_rdata = boot_rom$slave_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom$slave_rid ; - assign fabric$v_to_slaves_0_rlast = boot_rom$slave_rlast ; - assign fabric$v_to_slaves_0_rresp = boot_rom$slave_rresp ; - assign fabric$v_to_slaves_0_rvalid = boot_rom$slave_rvalid ; - assign fabric$v_to_slaves_0_wready = boot_rom$slave_wready ; - assign fabric$v_to_slaves_1_arready = mem0_controller$slave_arready ; - assign fabric$v_to_slaves_1_awready = mem0_controller$slave_awready ; - assign fabric$v_to_slaves_1_bid = mem0_controller$slave_bid ; - assign fabric$v_to_slaves_1_bresp = mem0_controller$slave_bresp ; - assign fabric$v_to_slaves_1_bvalid = mem0_controller$slave_bvalid ; - assign fabric$v_to_slaves_1_rdata = mem0_controller$slave_rdata ; - assign fabric$v_to_slaves_1_rid = mem0_controller$slave_rid ; - assign fabric$v_to_slaves_1_rlast = mem0_controller$slave_rlast ; - assign fabric$v_to_slaves_1_rresp = mem0_controller$slave_rresp ; - assign fabric$v_to_slaves_1_rvalid = mem0_controller$slave_rvalid ; - assign fabric$v_to_slaves_1_wready = mem0_controller$slave_wready ; + assign fabric$v_to_slaves_0_arready = + boot_rom_axi4_deburster$from_master_arready ; + assign fabric$v_to_slaves_0_awready = + boot_rom_axi4_deburster$from_master_awready ; + assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; + assign fabric$v_to_slaves_0_bresp = + boot_rom_axi4_deburster$from_master_bresp ; + assign fabric$v_to_slaves_0_bvalid = + boot_rom_axi4_deburster$from_master_bvalid ; + assign fabric$v_to_slaves_0_rdata = + boot_rom_axi4_deburster$from_master_rdata ; + assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; + assign fabric$v_to_slaves_0_rlast = + boot_rom_axi4_deburster$from_master_rlast ; + assign fabric$v_to_slaves_0_rresp = + boot_rom_axi4_deburster$from_master_rresp ; + assign fabric$v_to_slaves_0_rvalid = + boot_rom_axi4_deburster$from_master_rvalid ; + assign fabric$v_to_slaves_0_wready = + boot_rom_axi4_deburster$from_master_wready ; + assign fabric$v_to_slaves_1_arready = + mem0_controller_axi4_deburster$from_master_arready ; + assign fabric$v_to_slaves_1_awready = + mem0_controller_axi4_deburster$from_master_awready ; + assign fabric$v_to_slaves_1_bid = + mem0_controller_axi4_deburster$from_master_bid ; + assign fabric$v_to_slaves_1_bresp = + mem0_controller_axi4_deburster$from_master_bresp ; + assign fabric$v_to_slaves_1_bvalid = + mem0_controller_axi4_deburster$from_master_bvalid ; + assign fabric$v_to_slaves_1_rdata = + mem0_controller_axi4_deburster$from_master_rdata ; + assign fabric$v_to_slaves_1_rid = + mem0_controller_axi4_deburster$from_master_rid ; + assign fabric$v_to_slaves_1_rlast = + mem0_controller_axi4_deburster$from_master_rlast ; + assign fabric$v_to_slaves_1_rresp = + mem0_controller_axi4_deburster$from_master_rresp ; + assign fabric$v_to_slaves_1_rvalid = + mem0_controller_axi4_deburster$from_master_rvalid ; + assign fabric$v_to_slaves_1_wready = + mem0_controller_axi4_deburster$from_master_wready ; assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; @@ -1565,7 +2031,7 @@ module mkSoC_Top(CLK, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_2 ; + assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_initial ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -1573,50 +2039,158 @@ module mkSoC_Top(CLK, soc_map$m_mem0_controller_addr_base ; assign mem0_controller$set_addr_map_addr_lim = soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; + assign mem0_controller$set_watch_tohost_tohost_addr = start_tohost_addr ; assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = fabric$v_to_slaves_1_araddr ; - assign mem0_controller$slave_arburst = fabric$v_to_slaves_1_arburst ; - assign mem0_controller$slave_arcache = fabric$v_to_slaves_1_arcache ; - assign mem0_controller$slave_arid = fabric$v_to_slaves_1_arid ; - assign mem0_controller$slave_arlen = fabric$v_to_slaves_1_arlen ; - assign mem0_controller$slave_arlock = fabric$v_to_slaves_1_arlock ; - assign mem0_controller$slave_arprot = fabric$v_to_slaves_1_arprot ; - assign mem0_controller$slave_arqos = fabric$v_to_slaves_1_arqos ; - assign mem0_controller$slave_arregion = fabric$v_to_slaves_1_arregion ; - assign mem0_controller$slave_arsize = fabric$v_to_slaves_1_arsize ; - assign mem0_controller$slave_arvalid = fabric$v_to_slaves_1_arvalid ; - assign mem0_controller$slave_awaddr = fabric$v_to_slaves_1_awaddr ; - assign mem0_controller$slave_awburst = fabric$v_to_slaves_1_awburst ; - assign mem0_controller$slave_awcache = fabric$v_to_slaves_1_awcache ; - assign mem0_controller$slave_awid = fabric$v_to_slaves_1_awid ; - assign mem0_controller$slave_awlen = fabric$v_to_slaves_1_awlen ; - assign mem0_controller$slave_awlock = fabric$v_to_slaves_1_awlock ; - assign mem0_controller$slave_awprot = fabric$v_to_slaves_1_awprot ; - assign mem0_controller$slave_awqos = fabric$v_to_slaves_1_awqos ; - assign mem0_controller$slave_awregion = fabric$v_to_slaves_1_awregion ; - assign mem0_controller$slave_awsize = fabric$v_to_slaves_1_awsize ; - assign mem0_controller$slave_awvalid = fabric$v_to_slaves_1_awvalid ; - assign mem0_controller$slave_bready = fabric$v_to_slaves_1_bready ; - assign mem0_controller$slave_rready = fabric$v_to_slaves_1_rready ; - assign mem0_controller$slave_wdata = fabric$v_to_slaves_1_wdata ; - assign mem0_controller$slave_wid = fabric$v_to_slaves_1_wid ; - assign mem0_controller$slave_wlast = fabric$v_to_slaves_1_wlast ; - assign mem0_controller$slave_wstrb = fabric$v_to_slaves_1_wstrb ; - assign mem0_controller$slave_wvalid = fabric$v_to_slaves_1_wvalid ; + start_tohost_addr != 64'd0 ; + assign mem0_controller$slave_araddr = + mem0_controller_axi4_deburster$to_slave_araddr ; + assign mem0_controller$slave_arburst = + mem0_controller_axi4_deburster$to_slave_arburst ; + assign mem0_controller$slave_arcache = + mem0_controller_axi4_deburster$to_slave_arcache ; + assign mem0_controller$slave_arid = + mem0_controller_axi4_deburster$to_slave_arid ; + assign mem0_controller$slave_arlen = + mem0_controller_axi4_deburster$to_slave_arlen ; + assign mem0_controller$slave_arlock = + mem0_controller_axi4_deburster$to_slave_arlock ; + assign mem0_controller$slave_arprot = + mem0_controller_axi4_deburster$to_slave_arprot ; + assign mem0_controller$slave_arqos = + mem0_controller_axi4_deburster$to_slave_arqos ; + assign mem0_controller$slave_arregion = + mem0_controller_axi4_deburster$to_slave_arregion ; + assign mem0_controller$slave_arsize = + mem0_controller_axi4_deburster$to_slave_arsize ; + assign mem0_controller$slave_arvalid = + mem0_controller_axi4_deburster$to_slave_arvalid ; + assign mem0_controller$slave_awaddr = + mem0_controller_axi4_deburster$to_slave_awaddr ; + assign mem0_controller$slave_awburst = + mem0_controller_axi4_deburster$to_slave_awburst ; + assign mem0_controller$slave_awcache = + mem0_controller_axi4_deburster$to_slave_awcache ; + assign mem0_controller$slave_awid = + mem0_controller_axi4_deburster$to_slave_awid ; + assign mem0_controller$slave_awlen = + mem0_controller_axi4_deburster$to_slave_awlen ; + assign mem0_controller$slave_awlock = + mem0_controller_axi4_deburster$to_slave_awlock ; + assign mem0_controller$slave_awprot = + mem0_controller_axi4_deburster$to_slave_awprot ; + assign mem0_controller$slave_awqos = + mem0_controller_axi4_deburster$to_slave_awqos ; + assign mem0_controller$slave_awregion = + mem0_controller_axi4_deburster$to_slave_awregion ; + assign mem0_controller$slave_awsize = + mem0_controller_axi4_deburster$to_slave_awsize ; + assign mem0_controller$slave_awvalid = + mem0_controller_axi4_deburster$to_slave_awvalid ; + assign mem0_controller$slave_bready = + mem0_controller_axi4_deburster$to_slave_bready ; + assign mem0_controller$slave_rready = + mem0_controller_axi4_deburster$to_slave_rready ; + assign mem0_controller$slave_wdata = + mem0_controller_axi4_deburster$to_slave_wdata ; + assign mem0_controller$slave_wlast = + mem0_controller_axi4_deburster$to_slave_wlast ; + assign mem0_controller$slave_wstrb = + mem0_controller_axi4_deburster$to_slave_wstrb ; + assign mem0_controller$slave_wvalid = + mem0_controller_axi4_deburster$to_slave_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; + CAN_FIRE_RL_rl_reset_start_initial ; assign mem0_controller$EN_server_reset_response_get = - CAN_FIRE_RL_rl_reset_complete ; - assign mem0_controller$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + CAN_FIRE_RL_rl_reset_complete_initial ; + assign mem0_controller$EN_set_addr_map = + CAN_FIRE_RL_rl_reset_complete_initial ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; + assign mem0_controller$EN_set_watch_tohost = EN_start ; + + // submodule mem0_controller_axi4_deburster + assign mem0_controller_axi4_deburster$from_master_araddr = + fabric$v_to_slaves_1_araddr ; + assign mem0_controller_axi4_deburster$from_master_arburst = + fabric$v_to_slaves_1_arburst ; + assign mem0_controller_axi4_deburster$from_master_arcache = + fabric$v_to_slaves_1_arcache ; + assign mem0_controller_axi4_deburster$from_master_arid = + fabric$v_to_slaves_1_arid ; + assign mem0_controller_axi4_deburster$from_master_arlen = + fabric$v_to_slaves_1_arlen ; + assign mem0_controller_axi4_deburster$from_master_arlock = + fabric$v_to_slaves_1_arlock ; + assign mem0_controller_axi4_deburster$from_master_arprot = + fabric$v_to_slaves_1_arprot ; + assign mem0_controller_axi4_deburster$from_master_arqos = + fabric$v_to_slaves_1_arqos ; + assign mem0_controller_axi4_deburster$from_master_arregion = + fabric$v_to_slaves_1_arregion ; + assign mem0_controller_axi4_deburster$from_master_arsize = + fabric$v_to_slaves_1_arsize ; + assign mem0_controller_axi4_deburster$from_master_arvalid = + fabric$v_to_slaves_1_arvalid ; + assign mem0_controller_axi4_deburster$from_master_awaddr = + fabric$v_to_slaves_1_awaddr ; + assign mem0_controller_axi4_deburster$from_master_awburst = + fabric$v_to_slaves_1_awburst ; + assign mem0_controller_axi4_deburster$from_master_awcache = + fabric$v_to_slaves_1_awcache ; + assign mem0_controller_axi4_deburster$from_master_awid = + fabric$v_to_slaves_1_awid ; + assign mem0_controller_axi4_deburster$from_master_awlen = + fabric$v_to_slaves_1_awlen ; + assign mem0_controller_axi4_deburster$from_master_awlock = + fabric$v_to_slaves_1_awlock ; + assign mem0_controller_axi4_deburster$from_master_awprot = + fabric$v_to_slaves_1_awprot ; + assign mem0_controller_axi4_deburster$from_master_awqos = + fabric$v_to_slaves_1_awqos ; + assign mem0_controller_axi4_deburster$from_master_awregion = + fabric$v_to_slaves_1_awregion ; + assign mem0_controller_axi4_deburster$from_master_awsize = + fabric$v_to_slaves_1_awsize ; + assign mem0_controller_axi4_deburster$from_master_awvalid = + fabric$v_to_slaves_1_awvalid ; + assign mem0_controller_axi4_deburster$from_master_bready = + fabric$v_to_slaves_1_bready ; + assign mem0_controller_axi4_deburster$from_master_rready = + fabric$v_to_slaves_1_rready ; + assign mem0_controller_axi4_deburster$from_master_wdata = + fabric$v_to_slaves_1_wdata ; + assign mem0_controller_axi4_deburster$from_master_wlast = + fabric$v_to_slaves_1_wlast ; + assign mem0_controller_axi4_deburster$from_master_wstrb = + fabric$v_to_slaves_1_wstrb ; + assign mem0_controller_axi4_deburster$from_master_wvalid = + fabric$v_to_slaves_1_wvalid ; + assign mem0_controller_axi4_deburster$to_slave_arready = + mem0_controller$slave_arready ; + assign mem0_controller_axi4_deburster$to_slave_awready = + mem0_controller$slave_awready ; + assign mem0_controller_axi4_deburster$to_slave_bid = + mem0_controller$slave_bid ; + assign mem0_controller_axi4_deburster$to_slave_bresp = + mem0_controller$slave_bresp ; + assign mem0_controller_axi4_deburster$to_slave_bvalid = + mem0_controller$slave_bvalid ; + assign mem0_controller_axi4_deburster$to_slave_rdata = + mem0_controller$slave_rdata ; + assign mem0_controller_axi4_deburster$to_slave_rid = + mem0_controller$slave_rid ; + assign mem0_controller_axi4_deburster$to_slave_rlast = + mem0_controller$slave_rlast ; + assign mem0_controller_axi4_deburster$to_slave_rresp = + mem0_controller$slave_rresp ; + assign mem0_controller_axi4_deburster$to_slave_rvalid = + mem0_controller$slave_rvalid ; + assign mem0_controller_axi4_deburster$to_slave_wready = + mem0_controller$slave_wready ; + assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; @@ -1652,13 +2226,14 @@ module mkSoC_Top(CLK, assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start_2 ; - assign uart0$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_complete ; - assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign uart0$EN_server_reset_request_put = + CAN_FIRE_RL_rl_reset_start_initial ; + assign uart0$EN_server_reset_response_get = + CAN_FIRE_RL_rl_reset_complete_initial ; + assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; @@ -1693,25 +2268,38 @@ module mkSoC_Top(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_2) + if (EN_start) begin - v__h8689 = $stime; + v__h11619 = $stime; #0; end - v__h8683 = v__h8689 / 32'd10; + v__h11613 = v__h11619 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_2) - $display("%0d: SoC_Top. Reset start ...", v__h8683); + if (EN_start) + $display("%0d: %m.method start (tohost %0h, fromhost %0h)", + v__h11613, + start_tohost_addr, + start_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete) + if (WILL_FIRE_RL_rl_reset_start_initial) begin - v__h8949 = $stime; + v__h11080 = $stime; #0; end - v__h8943 = v__h8949 / 32'd10; + v__h11074 = v__h11080 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete) - $display("%0d: SoC_Top. Reset complete ...", v__h8943); + if (WILL_FIRE_RL_rl_reset_start_initial) + $display("%0d: %m.rl_reset_start_initial ...", v__h11074); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_reset_complete_initial) + begin + v__h11328 = $stime; + #0; + end + v__h11322 = v__h11328 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_reset_complete_initial) + $display("%0d: %m.rl_reset_complete_initial", v__h11322); end // synopsys translate_on endmodule // mkSoC_Top diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v index eb40700..5e3febf 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v @@ -52,20 +52,21 @@ module mkTop_HW_Side(CLK, wire [352 : 0] soc_top$to_raw_mem_request_get; wire [255 : 0] soc_top$to_raw_mem_response_put; wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; + soc_top$start_fromhost_addr, + soc_top$start_tohost_addr; wire [7 : 0] soc_top$get_to_console_get, soc_top$put_from_console_put; wire [3 : 0] soc_top$set_verbosity_verbosity; wire soc_top$EN_get_to_console_get, soc_top$EN_put_from_console_put, soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, + soc_top$EN_start, soc_top$EN_to_raw_mem_request_get, soc_top$EN_to_raw_mem_response_put, soc_top$RDY_get_to_console_get, soc_top$RDY_put_from_console_put, + soc_top$RDY_start, soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; + soc_top$RDY_to_raw_mem_response_put; // rule scheduling signals wire CAN_FIRE_RL_memCnx_ClientServerRequest, @@ -81,11 +82,14 @@ module mkTop_HW_Side(CLK, // declarations used by system tasks // synopsys translate_off - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg TASK_testplusargs___d15; - reg [63 : 0] tohost_addr__h559; - reg [7 : 0] v__h737; + reg TASK_testplusargs___d14; + reg TASK_testplusargs___d13; + reg TASK_testplusargs___d17; + reg [63 : 0] y_avValue_fst__h638; + reg [63 : 0] y_avValue_snd__h639; + reg [7 : 0] v__h831; + reg [63 : 0] tohost_addr__h647; + reg [63 : 0] fromhost_addr__h648; // synopsys translate_on // submodule mem_model @@ -99,20 +103,21 @@ module mkTop_HW_Side(CLK, .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), + mkSoC_Top soc_top(.RST_N_dm_power_on_reset(RST_N), + .CLK(CLK), .RST_N(RST_N), .put_from_console_put(soc_top$put_from_console_put), .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), + .start_fromhost_addr(soc_top$start_fromhost_addr), + .start_tohost_addr(soc_top$start_tohost_addr), .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), .EN_set_verbosity(soc_top$EN_set_verbosity), .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), .EN_get_to_console_get(soc_top$EN_get_to_console_get), .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), + .EN_start(soc_top$EN_start), .RDY_set_verbosity(), .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), @@ -120,10 +125,11 @@ module mkTop_HW_Side(CLK, .get_to_console_get(soc_top$get_to_console_get), .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), .RDY_put_from_console_put(soc_top$RDY_put_from_console_put), - .RDY_set_watch_tohost()); + .status(), + .RDY_start(soc_top$RDY_start)); // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; + assign CAN_FIRE_RL_rl_step0 = soc_top$RDY_start && !rg_banner_printed ; assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; // rule RL_rl_relay_console_out @@ -165,14 +171,14 @@ module mkTop_HW_Side(CLK, CAN_FIRE_RL_memCnx_ClientServerResponse ; // submodule soc_top - assign soc_top$put_from_console_put = v__h737 ; + assign soc_top$put_from_console_put = v__h831 ; assign soc_top$set_verbosity_logdelay = 64'd0 ; assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? + TASK_testplusargs___d13 ? 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h559 ; - assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ; + (TASK_testplusargs___d14 ? 4'd1 : 4'd0) ; + assign soc_top$start_fromhost_addr = fromhost_addr__h648 ; + assign soc_top$start_tohost_addr = tohost_addr__h647 ; assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; assign soc_top$EN_to_raw_mem_request_get = @@ -183,8 +189,8 @@ module mkTop_HW_Side(CLK, assign soc_top$EN_put_from_console_put = WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0 && - v__h737 != 8'd0 ; - assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ; + v__h831 != 8'd0 ; + assign soc_top$EN_start = CAN_FIRE_RL_rl_step0 ; // handling of inlined registers @@ -236,32 +242,42 @@ module mkTop_HW_Side(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_step0) begin - TASK_testplusargs___d12 = $test$plusargs("v1"); + TASK_testplusargs___d14 = $test$plusargs("v1"); #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_step0) begin - TASK_testplusargs___d11 = $test$plusargs("v2"); + TASK_testplusargs___d13 = $test$plusargs("v2"); #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_step0) begin - TASK_testplusargs___d15 = $test$plusargs("tohost"); + TASK_testplusargs___d17 = $test$plusargs("tohost"); #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) + if (WILL_FIRE_RL_rl_step0 && TASK_testplusargs___d17) begin - tohost_addr__h559 = $imported_c_get_symbol_val("tohost"); + y_avValue_fst__h638 = $imported_c_get_symbol_val("tohost"); #0; end + tohost_addr__h647 = TASK_testplusargs___d17 ? y_avValue_fst__h638 : 64'd0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_step0 && TASK_testplusargs___d17) + begin + y_avValue_snd__h639 = $imported_c_get_symbol_val("fromhost"); + #0; + end + fromhost_addr__h648 = + TASK_testplusargs___d17 ? y_avValue_snd__h639 : 64'd0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_step0) - $display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - TASK_testplusargs___d15, - tohost_addr__h559); + $display("INFO: watch_tohost %d, tohost_addr = 0x%0h, fromhost_addr = 0x%0h", + TASK_testplusargs___d17, + tohost_addr__h647, + fromhost_addr__h648); if (RST_N != `BSV_RESET_VALUE) if (soc_top$RDY_get_to_console_get) $write("%c", soc_top$get_to_console_get); @@ -270,7 +286,7 @@ module mkTop_HW_Side(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0) begin - v__h737 = $imported_c_trygetchar(8'hAA); + v__h831 = $imported_c_trygetchar(8'hAA); #0; end end diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v index 3d6722a..51efebf 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v @@ -40,7 +40,6 @@ // slave_awqos I 4 reg // slave_awregion I 4 reg // slave_wvalid I 1 -// slave_wid I 4 reg // slave_wdata I 64 reg // slave_wstrb I 8 reg // slave_wlast I 1 reg @@ -110,7 +109,6 @@ module mkUART(CLK, slave_awready, slave_wvalid, - slave_wid, slave_wdata, slave_wstrb, slave_wlast, @@ -195,7 +193,6 @@ module mkUART(CLK, // action method slave_m_wvalid input slave_wvalid; - input [3 : 0] slave_wid; input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; @@ -413,7 +410,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr$FULL_N; // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; wire slave_xactor_f_wr_data$CLR, slave_xactor_f_wr_data$DEQ, slave_xactor_f_wr_data$EMPTY_N, @@ -468,24 +465,24 @@ module mkUART(CLK, reg [31 : 0] v__h2187; reg [31 : 0] v__h2025; reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; + reg [31 : 0] v__h3239; + reg [31 : 0] v__h3997; + reg [31 : 0] v__h3442; + reg [31 : 0] v__h4295; + reg [31 : 0] v__h4736; + reg [31 : 0] v__h4846; reg [31 : 0] v__h1811; reg [31 : 0] v__h1805; reg [31 : 0] v__h2019; reg [31 : 0] v__h2181; reg [31 : 0] v__h2513; reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; + reg [31 : 0] v__h3233; + reg [31 : 0] v__h3436; + reg [31 : 0] v__h3991; + reg [31 : 0] v__h4289; + reg [31 : 0] v__h4730; + reg [31 : 0] v__h4840; // synopsys translate_on // remaining internal signals @@ -494,26 +491,26 @@ module mkUART(CLK, slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, + new_lsr__h4503, x__h2797, y_avValue_snd__h2696, y_avValue_snd__h2709, y_avValue_snd__h2724, y_avValue_snd__h2738; wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, + v__h3144, + v__h3388, + v__h3566, y_avValue_fst__h2737, y_avValue_fst__h2751; wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, + NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230, + NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241, slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176, + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180, + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184, + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187, slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; // action method server_reset_request_put @@ -672,7 +669,7 @@ module mkUART(CLK, .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), + FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(slave_xactor_f_wr_data$D_IN), .ENQ(slave_xactor_f_wr_data$ENQ), @@ -742,7 +739,7 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[16:9] ; assign rg_dll$EN = WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180 || WILL_FIRE_RL_rl_reset ; // register rg_dlm @@ -752,7 +749,7 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[16:9] ; assign rg_dlm$EN = WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187 || WILL_FIRE_RL_rl_reset ; // register rg_fcr @@ -778,7 +775,7 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[16:9] ; assign rg_ier$EN = WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184 || WILL_FIRE_RL_rl_reset ; // register rg_lcr @@ -800,11 +797,11 @@ module mkUART(CLK, // register rg_lsr always@(WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or + new_lsr__h4503 or MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; + WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4503; MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; endcase @@ -862,7 +859,7 @@ module mkUART(CLK, assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; assign rg_thr$EN = WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 ; // submodule f_from_console assign f_from_console$D_IN = put_from_console_put ; @@ -884,7 +881,7 @@ module mkUART(CLK, assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; assign f_to_console$ENQ = WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; + slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 ; assign f_to_console$DEQ = EN_get_to_console_get ; assign f_to_console$CLR = 1'b0 ; @@ -938,7 +935,7 @@ module mkUART(CLK, // submodule slave_xactor_f_wr_data assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; + { slave_wdata, slave_wstrb, slave_wlast } ; assign slave_xactor_f_wr_data$ENQ = slave_wvalid && slave_xactor_f_wr_data$FULL_N ; assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; @@ -947,7 +944,7 @@ module mkUART(CLK, // submodule slave_xactor_f_wr_resp assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; + { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3144 } ; assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; assign slave_xactor_f_wr_resp$DEQ = slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; @@ -956,7 +953,7 @@ module mkUART(CLK, // remaining internal signals assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = + assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230 = (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != 3'h1 || !rg_lcr[7]) && @@ -973,7 +970,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != 3'h7 && slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = + assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241 = (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != 3'h1 || !rg_lcr[7]) && @@ -992,7 +989,7 @@ module mkUART(CLK, !slave_xactor_f_wr_data$D_OUT[0] ; assign fn_iir__h1356 = (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; + assign new_lsr__h4503 = { rg_lsr[7:1], 1'd1 } ; assign rdata__h2759 = { 56'd0, x__h2797 } ; assign rdr_rresp__h2792 = (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == @@ -1011,7 +1008,7 @@ module mkUART(CLK, !rg_lcr[7] ; assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = + assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 = slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == 3'd0 && slave_xactor_f_wr_data$D_OUT[1] && @@ -1020,7 +1017,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == 3'h0 && !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = + assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180 = slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == 3'd0 && slave_xactor_f_wr_data$D_OUT[1] && @@ -1029,7 +1026,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == 3'h0 && rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = + assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184 = slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == 3'd0 && slave_xactor_f_wr_data$D_OUT[1] && @@ -1038,7 +1035,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == 3'h1 && !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = + assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187 = slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == 3'd0 && slave_xactor_f_wr_data$D_OUT[1] && @@ -1058,18 +1055,18 @@ module mkUART(CLK, 3'h0 || rg_lcr[7] || f_to_console$FULL_N) ; - assign v__h3147 = + assign v__h3144 = (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != 3'd0 || !slave_xactor_f_wr_data$D_OUT[1]) ? 2'b10 : - v__h3395 ; - assign v__h3395 = + v__h3388 ; + assign v__h3388 = (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == 2'd0) ? - v__h3575 : + v__h3566 : 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; + assign v__h3566 = y_avValue_fst__h2737 ; assign x__h2797 = (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != 3'd0 || @@ -1836,17 +1833,17 @@ module mkUART(CLK, 3'd0 || !slave_xactor_f_wr_data$D_OUT[1])) begin - v__h3244 = $stime; + v__h3239 = $stime; #0; end - v__h3238 = v__h3244 / 32'd10; + v__h3233 = v__h3239 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != 3'd0 || !slave_xactor_f_wr_data$D_OUT[1])) $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); + v__h3233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != @@ -2002,19 +1999,7 @@ module mkUART(CLK, (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != 3'd0 || !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != @@ -2078,10 +2063,10 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[1] && 1'b0) begin - v__h4006 = $stime; + v__h3997 = $stime; #0; end - v__h4000 = v__h4006 / 32'd10; + v__h3991 = v__h3997 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2089,7 +2074,7 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[1] && 1'b0) $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); + v__h3991); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2271,21 +2256,7 @@ module mkUART(CLK, 3'd0 && slave_xactor_f_wr_data$D_OUT[1] && 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2330,7 +2301,7 @@ module mkUART(CLK, (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != 3'h1 || rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) + NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && @@ -2348,7 +2319,7 @@ module mkUART(CLK, (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != 3'h1 || rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) + NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && @@ -2379,10 +2350,10 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != 2'd0) begin - v__h3449 = $stime; + v__h3442 = $stime; #0; end - v__h3443 = v__h3449 / 32'd10; + v__h3436 = v__h3442 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2391,7 +2362,7 @@ module mkUART(CLK, slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != 2'd0) $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); + v__h3436); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2599,23 +2570,7 @@ module mkUART(CLK, slave_xactor_f_wr_data$D_OUT[1] && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == @@ -2694,14 +2649,14 @@ module mkUART(CLK, if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) begin - v__h4306 = $stime; + v__h4295 = $stime; #0; end - v__h4300 = v__h4306 / 32'd10; + v__h4289 = v__h4295 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); + $display("%0d: UART.rl_process_wr_req", v__h4289); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) @@ -2805,15 +2760,7 @@ module mkUART(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) @@ -2871,7 +2818,7 @@ module mkUART(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); + $write("'h%h", v__h3144); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1_24___d125) @@ -2886,29 +2833,29 @@ module mkUART(CLK, $write("\n"); if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) begin - v__h4749 = $stime; + v__h4736 = $stime; #0; end - v__h4743 = v__h4749 / 32'd10; + v__h4730 = v__h4736 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, + v__h4730, set_addr_map_addr_base); if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) begin - v__h4859 = $stime; + v__h4846 = $stime; #0; end - v__h4853 = v__h4859 / 32'd10; + v__h4840 = v__h4846 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, + v__h4840, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", f_from_console$D_OUT, - new_lsr__h4516); + new_lsr__h4503); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) begin diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk index 68e22d3..83ea82f 100644 --- a/builds/Resources/Include_bluesim.mk +++ b/builds/Resources/Include_bluesim.mk @@ -24,10 +24,12 @@ compile: build_dir SIM_EXE_FILE = exe_HW_sim BSC_C_FLAGS += \ - -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 \ -Xl -v \ -Xc -O1 -Xc++ -O1 \ +# Removed this for Bluespec_2019.05.beta2-debian9stretch-amd64 +# -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 \ + .PHONY: simulator simulator: @echo "INFO: linking bsc-compiled objects into Bluesim executable" diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 2a6beca..db8d0f3 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -136,9 +136,6 @@ interface CoreRenameDebug; endinterface interface Core; - // Initialize - interface Server #(Bit #(0), Bit #(0)) init_server; - // core request & indication interface CoreReq coreReq; interface CoreIndInv coreIndInv; @@ -206,13 +203,6 @@ module mkCore#(CoreId coreId)(Core); // ================================================================ Integer verbosity = 0; // More levels of verbosity control than 'Bool verbose' - // ---------------- - // Init requests and responses - - FIFOF #(Bit #(0)) f_init_reqs <- mkFIFOF; - FIFOF #(Bit #(0)) f_init_rsps <- mkFIFOF; - - Reg#(Bool) outOfReset <- mkReg(False); rule rl_outOfReset if (!outOfReset); $fwrite(stderr, "mkProc came out of reset\n"); @@ -1297,28 +1287,9 @@ module mkCore#(CoreId coreId)(Core); // ================================================================ `endif - // ================================================================ - // Init interface - - rule rl_init; - let tok <- pop (f_init_reqs); - - csrf.init; - started <= False; - -`ifdef INCLUDE_GDB_CONTROL - rg_core_run_state <= CORE_RUNNING; -`endif - - f_init_rsps.enq (tok); - endrule - // ================================================================ // INTERFACE - // Initialize - interface init_server = toGPServer (f_init_reqs, f_init_rsps); - interface CoreReq coreReq; method Action start( Bit#(64) startpc, @@ -1330,7 +1301,7 @@ module mkCore#(CoreId coreId)(Core); rg_core_run_state <= CORE_RUNNING; `endif mmio.setHtifAddrs(toHostAddr, fromHostAddr); - // start rename debug + commitStage.startRenameDebug; endmethod diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index d126758..084c72e 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -49,9 +49,6 @@ import SoC_Map :: *; // ================================================================ interface CsrFile; - // Initialize to platform-level reset spec - method Action init; - // Read method Data rd(CSR csr); // normal write by CSRXXX inst to any CSR @@ -672,28 +669,6 @@ module mkCsrFile #(Data hartid)(CsrFile); // ================================================================ // INTERFACE - method Action init; - // Note: we initialize only certain CSRs (platform-level spec) - // Current privilege - prv_reg <= prvM; - - // Machine-level CSRs - mstatus_csr <= 0; - mie_csr <= 0; - mip_csr <= 0; - minstret_csr <= 0; - mcycle_csr <= 0; - - // User-level CSRs - time_reg <= 0; - -`ifdef INCLUDE_GDB_CONTROL - // Debug Module CSRs - rg_dcsr <= zeroExtend (dcsr_reset_value); - rg_dpc <= truncate (soc_map_struct.pc_reset_value); -`endif - endmethod - method Data rd(CSR csr); return get_csr(csr)._read; endmethod diff --git a/src_Core/CPU/LLC_AXI4_Adapter.bsv b/src_Core/CPU/LLC_AXI4_Adapter.bsv index 947aa24..e3c4b39 100644 --- a/src_Core/CPU/LLC_AXI4_Adapter.bsv +++ b/src_Core/CPU/LLC_AXI4_Adapter.bsv @@ -107,8 +107,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) awregion: fabric_default_region, awuser: fabric_default_user}; - let mem_req_wr_data = AXI4_Wr_Data {wid: fabric_default_id, - wdata: st_val, + let mem_req_wr_data = AXI4_Wr_Data {wdata: st_val, wstrb: strb, wlast: True, wuser: fabric_default_user}; diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 816c4e3..b9126d2 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -1,5 +1,6 @@ // Copyright (c) 2018 Massachusetts Institute of Technology +// Portions (c) 2019-2020 Bluespec, Inc. // // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation @@ -21,8 +22,6 @@ // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. -// Portions (c) 2019 Bluespec, Inc. - // This file is adapted from: MIT-riscy/riscy-OOO/procs/lib/MMIOPlatform.bsv // Modifications to fit into Bluespec's RISC-V execution environments. diff --git a/src_Core/CPU/MMIO_AXI4_Adapter.bsv b/src_Core/CPU/MMIO_AXI4_Adapter.bsv index 2c1f4f3..8a0e984 100644 --- a/src_Core/CPU/MMIO_AXI4_Adapter.bsv +++ b/src_Core/CPU/MMIO_AXI4_Adapter.bsv @@ -108,8 +108,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); awregion: fabric_default_region, awuser: fabric_default_user}; - let mem_req_wr_data = AXI4_Wr_Data {wid: fabric_default_id, - wdata: st_val, + let mem_req_wr_data = AXI4_Wr_Data {wdata: st_val, wstrb: strb, wlast: True, wuser: fabric_default_user}; diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index d355f36..6cd20d4 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -1,5 +1,7 @@ package Proc; +// Note: this module corresponds to module 'mkCPU' in Piccolo/Flute. + // Copyright (c) 2018 Massachusetts Institute of Technology // Portions Copyright (c) 2019-2020 Bluespec, Inc. // @@ -103,12 +105,6 @@ module mkProc (Proc_IFC); // Verbosity: 0=quiet; 1=instruction trace; 2=more detail Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0); - // ---------------- - // Init requests and responses - - FIFOF #(Bit #(0)) f_init_reqs <- mkFIFOF; - FIFOF #(Bit #(0)) f_init_rsps <- mkFIFOF; - // ---------------- // MMIO @@ -201,25 +197,6 @@ module mkProc (Proc_IFC); end // ================================================================ - // Init - - rule rl_init_start; - let x <- pop (f_init_reqs); - - llc_axi4_adapter.reset; - mmio_axi4_adapter.reset; - for (Integer j = 0; j < valueof(CoreNum); j = j+1) - core [j].init_server.request.put (?); - endrule - - rule rl_init_finish; - for (Integer j = 0; j < valueof(CoreNum); j = j+1) - let tok <- core [j].init_server.response.get; - - f_init_rsps.enq (?); - endrule - - // ---------------- // Termination detection for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin @@ -229,7 +206,9 @@ module mkProc (Proc_IFC); endrule end + // ================================================================ // Print out values written 'tohost' + rule rl_tohost; let x <- mmioPlatform.to_host; $display ("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", cur_cycle, x, x); @@ -251,11 +230,9 @@ module mkProc (Proc_IFC); // ================================================================ // INTERFACE - // Reset - interface Server init_server = toGPServer (f_init_reqs, f_init_rsps); - // ---------------- // Start the cores running + // Use toHostAddr = 0 if not monitoring tohost method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); action for(Integer i = 0; i < valueof(CoreNum); i = i+1) @@ -264,8 +241,8 @@ module mkProc (Proc_IFC); mmioPlatform.start (tohostAddr, fromhostAddr); - $display ("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", - startpc, tohostAddr, fromhostAddr); + $display ("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + cur_cycle, startpc, tohostAddr, fromhostAddr); endmethod // ---------------- @@ -312,18 +289,19 @@ module mkProc (Proc_IFC); `ifdef INCLUDE_GDB_CONTROL // run/halt, gpr, mem and csr control goes to core interface Server hart0_run_halt_server = core [0].hart0_run_halt_server; + + interface Put hart0_put_other_req; + method Action put (Bit #(4) req); + cfg_verbosity <= req; + endmethod + endinterface + interface Server hart0_gpr_mem_server = core[0].hart0_gpr_mem_server; `ifdef ISA_F interface Server hart0_fpr_mem_server = core[0].hart0_fpr_mem_server; `endif interface Server hart0_csr_mem_server = core[0].hart0_csr_mem_server; - // We don't implement 'other' functionality - interface Put hart0_put_other_req; - method Action put (Bit #(4) req); - cfg_verbosity <= req; - endmethod - endinterface `endif `ifdef INCLUDE_TANDEM_VERIF diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 574c88e..a2d4576 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +// Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved package Proc_IFC; @@ -34,11 +34,10 @@ import Trace_Data2 :: *; // because the RISCY-OOO mkProc contains those elements. interface Proc_IFC; - // Init - interface Server #(Token, Token) init_server; // ---------------- // Start the cores running + // Use toHostAddr = 0 if not monitoring tohost method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); // ---------------- diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index c5acfc0..49cc339 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -91,7 +91,53 @@ import DM_CPU_Req_Rsp ::*; // The Core module (* synthesize *) -module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); +module mkCoreW #(Reset dm_power_on_reset) + (CoreW_IFC #(N_External_Interrupt_Sources)); + + // ================================================================ + // Notes on 'reset' + + // This module's default reset (Verilog RST_N) is a + // 'non-debug-module reset', or 'ndm-reset': it resets everything + // in mkCoreW other than the optional RISC-V Debug Module (DM). + + // DM is reset ONLY by 'dm_power_on_reset' (parameter of this module). + // This is expected to be performed exactly once, on power-up. + + // Note: DM has an internal functionality that the DM spec calls + // 'dm_reset'. This is not really an electrical reset, it is just + // a module initializer wholly within the DM to put it into a + // known state. To be able to do a dm_reset, the DM has to be + // working already, at least to the point that it can field DMI + // requests from the external debugger asking the DM to proform a + // dm_reset. + + // DM can ask the environment to perform an 'ndm-reset', which the + // environment does by asserting the default reset (RST_N). At the + // same time, the environment may also reset part or all of the + // rest of the SoC. + + // DM can also individually reset each hart in mkCPU. + // 'hart' = hardware thread = independent PC and fetch-and-execute pipeline. + // mkCPU (instantiated in this module) has one or more harts. + // This hart-reset logic is entirely within this module. + + // ================================================================ + // The CPU's (hart's) reset is the ``or'' of the default reset + // (power-on reset) and the Debug Module's 'hart_reset' control. + + let ndm_reset <- exposeCurrentReset; + +`ifdef INCLUDE_GDB_CONTROL + let clk <- exposeCurrentClock; + Bool initial_reset_val = False; + Integer hart_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for hart + let dm_hart0_reset_controller <- mkReset(hart_reset_duration, initial_reset_val, clk); + + let hart0_reset <- mkResetEither (ndm_reset, dm_hart0_reset_controller.new_rst); +`else + let hart0_reset = ndm_reset; +`endif // ================================================================ // STATE @@ -100,7 +146,8 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); SoC_Map_IFC soc_map <- mkSoC_Map; // RISCY-OOO processor - Proc_IFC proc <- mkProc; + // TODO (when we do multicore): need resets for each core. + Proc_IFC proc <- mkProc (reset_by hart0_reset); // A 2x3 fabric for connecting {CPU, Debug_Module} to {Fabric, PLIC} Fabric_2x3_IFC fabric_2x3 <- mkFabric_2x3; @@ -108,13 +155,9 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); // PLIC (Platform-Level Interrupt Controller) PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7; - // Reset requests from SoC and responses to SoC - FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF; - FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF; - `ifdef INCLUDE_GDB_CONTROL // Debug Module - Debug_Module_IFC debug_module <- mkDebug_Module; + Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dm_power_on_reset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -127,97 +170,37 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); TV_Encode_IFC tv_encode <- mkTV_Encode; `endif - // HTIF locations (for debugging only) - Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0); - Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0); - // ================================================================ - // RESET - // There are two sources of reset requests to the CPU: externally - // from the SoC and, optionally, the DM. The SoC requires a - // response, the DM does not. When both requestors are present - // (i.e., DM is present), we merge the reset requests into the CPU, - // and we remember which one was the requestor in - // f_reset_requestor, so that we know whether or not to respond to - // the SoC. - - // TODO (multicore): currently the incoming 'init' token is from - // Debug Module's hart0_get_reset_req, but when we call - // proc.init_server here, we are resetting all the cores, i.e., all - // the harts. Needs to be cleaned up. - - Bit #(1) reset_requestor_dm = 0; - Bit #(1) reset_requestor_soc = 1; -`ifdef INCLUDE_GDB_CONTROL - FIFOF #(Bit #(1)) f_reset_requestor <- mkFIFOF; -`endif - - // Reset-hart0 request from SoC - rule rl_cpu_hart0_reset_from_soc_start; - let req <- pop (f_reset_reqs); - - proc.init_server.request.put (?); // CPU - plic.server_reset.request.put (?); // PLIC - fabric_2x3.reset; // Local 2x3 Fabric -`ifdef INCLUDE_TANDEM_VERIF - tv_encode.reset; -`endif + // Hart-reset from DM `ifdef INCLUDE_GDB_CONTROL - // Remember the requestor, so we can respond to it - f_reset_requestor.enq (reset_requestor_soc); -`endif - $display ("%0d: Core.rl_cpu_hart0_reset_from_soc_start (requestor %0d)", cur_cycle, reset_requestor_soc); + Reg #(Bit #(8)) rg_hart0_reset_delay <- mkReg (0); + Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0); + Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0); + + rule rl_dm_hart0_reset (rg_hart0_reset_delay == 0); + let x <- debug_module.hart0_reset_client.request.get; + dm_hart0_reset_controller.assertReset; + rg_hart0_reset_delay <= fromInteger (hart_reset_duration + 200); // NOTE: heuristic + + $display ("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", + cur_cycle, hart_reset_duration); endrule -`ifdef INCLUDE_GDB_CONTROL - // Reset-hart0 from Debug Module - rule rl_cpu_hart0_reset_from_dm_start; - let req <- debug_module.hart0_get_reset_req.get; + rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0); + if (rg_hart0_reset_delay == 1) begin + let pc = soc_map_struct.pc_reset_value; + proc.start (pc, rg_tohost_addr, rg_fromhost_addr); - proc.init_server.request.put (?); // CPU - plic.server_reset.request.put (?); // PLIC - fabric_2x3.reset; // Local 2x3 fabric -`ifdef INCLUDE_TANDEM_VERIF - tv_encode.reset; -`endif - - // Remember the requestor, so we can respond to it - f_reset_requestor.enq (reset_requestor_dm); - $display ("%0d: Core.rl_cpu_hart0_reset_from_dm_start (requestor %0d)", cur_cycle, reset_requestor_dm); - endrule -`endif - - FIFOF #(Bit #(0)) f_proc_start <- mkFIFOF; - - rule rl_cpu_hart0_reset_complete; - let rsp1 <- proc.init_server.response.get; // CPU - let rsp3 <- plic.server_reset.response.get; // PLIC - - plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base), - zeroExtend (soc_map.m_plic_addr_lim)); - - Bit #(1) requestor = reset_requestor_soc; -`ifdef INCLUDE_GDB_CONTROL - requestor <- pop (f_reset_requestor); -`endif - if (requestor == reset_requestor_soc) - f_reset_rsps.enq (?); - - // Start running the cores - f_proc_start.enq (?); - - $display ("%0d: Core.rl_cpu_hart0_reset_complete; starting proc", cur_cycle); - endrule - - rule rl_cpu_hart0_reset_proc_start; - let x <- pop (f_proc_start); - proc.start (soc_map_struct.pc_reset_value, - rg_tohost_addr, - rg_fromhost_addr); - $display ("%0d: Core.rl_cpu_hart0_reset_proc_start; started running proc", cur_cycle); + Bool is_running = True; + debug_module.hart0_reset_client.response.put (is_running); + $display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); + end + rg_hart0_reset_delay <= rg_hart0_reset_delay - 1; endrule +`endif `ifdef INCLUDE_GDB_CONTROL // ================================================================ @@ -359,13 +342,6 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); // $display ("%0d: Core.rl_relay_external_interrupts: relaying: %d", cur_cycle, pack (x)); endrule - // TODO: fixup. Need to combine NMIs from multiple sources (cache, fabric, devices, ...) - rule rl_relay_non_maskable_interrupt; - proc.non_maskable_interrupt_req (False); - - // $display ("%0d: Core.rl_relay_non_maskable_interrupts: relaying: %d", cur_cycle, pack (x)); - endrule - // ================================================================ // INTERFACE @@ -377,16 +353,26 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); proc.set_verbosity (verbosity); endmethod - method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + // ---------------------------------------------------------------- + // Start + + method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base), + zeroExtend (soc_map.m_plic_addr_lim)); + + let pc = soc_map_struct.pc_reset_value; + proc.start (pc, tohost_addr, fromhost_addr); + +`ifdef INCLUDE_GDB_CONTROL + // Save for potential future use by rl_dm_hart0_reset rg_tohost_addr <= tohost_addr; rg_fromhost_addr <= fromhost_addr; +`endif + + $display ("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)", + cur_cycle, pc, tohost_addr, fromhost_addr); endmethod - // ---------------------------------------------------------------- - // Soft reset - - interface Server cpu_reset_server = toGPServer (f_reset_reqs, f_reset_rsps); - // ---------------------------------------------------------------- // AXI4 Fabric interfaces @@ -401,6 +387,14 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); interface core_external_interrupt_sources = plic.v_sources; + // ---------------------------------------------------------------- + // Non-maskable interrupt request + + method Action nmi_req (Bool set_not_clear); + // TODO: fixup; passing const False for now + proc.non_maskable_interrupt_req (False); + endmethod + `ifdef INCLUDE_GDB_CONTROL // ---------------------------------------------------------------- // Optional DM interfaces @@ -408,13 +402,13 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); // ---------------- // DMI (Debug Module Interface) facing remote debugger - interface DMI dm_dmi = debug_module.dmi; + interface DMI dmi = debug_module.dmi; // ---------------- // Facing Platform // Non-Debug-Module Reset (reset all except DM) - interface Get dm_ndm_reset_req_get = debug_module.get_ndm_reset_req; + interface Client ndm_reset_client = debug_module.ndm_reset_client; `endif `ifdef INCLUDE_TANDEM_VERIF diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index 129337f..21b8928 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved. package CoreW_IFC; @@ -6,9 +6,8 @@ package CoreW_IFC; // This package defines the interface of a CoreW module which // contains: // - mkProc (the RISC-V CPU; this a variant of MIT's RISCY-OOO mkProc) -// Note: MIT's RISCY-OOO internally contains a 'mkCore' -// and hence this interface and its module is called -// 'CoreW', to disambiguate. +// Note: MIT's RISCY-OOO internally has a 'mkCore' and hence this +// interface and its module is called 'CoreW', to disambiguate. // - mkFabric_2x3 // - mkNear_Mem_IO_AXI4 // - mkPLIC_16_2_7 @@ -48,16 +47,14 @@ import TV_Info :: *; interface CoreW_IFC #(numeric type t_n_interrupt_sources); // ---------------------------------------------------------------- - // Debugging: set core's verbosity, htif addrs + // Debugging: set core's verbosity method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); - // ---------------------------------------------------------------- - // Soft reset + // Start - interface Server #(Bit #(0), Bit #(0)) cpu_reset_server; + method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); // ---------------------------------------------------------------- // AXI4 Fabric interfaces @@ -73,6 +70,12 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources); interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources; + // ---------------------------------------------------------------- + // Non-maskable interrupt request + + (* always_ready, always_enabled *) + method Action nmi_req (Bool set_not_clear); + `ifdef INCLUDE_GDB_CONTROL // ---------------------------------------------------------------- // Optional Debug Module interfaces @@ -80,13 +83,13 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources); // ---------------- // DMI (Debug Module Interface) facing remote debugger - interface DMI dm_dmi; + interface DMI dmi; // ---------------- // Facing Platform // Non-Debug-Module Reset (reset all except DM) - interface Get #(Bit #(0)) dm_ndm_reset_req_get; + interface Client #(Bool, Bool) ndm_reset_client; `endif `ifdef INCLUDE_TANDEM_VERIF diff --git a/src_Core/Debug_Module/DM_Abstract_Commands.bsv b/src_Core/Debug_Module/DM_Abstract_Commands.bsv index 6664186..7a4c322 100644 --- a/src_Core/Debug_Module/DM_Abstract_Commands.bsv +++ b/src_Core/Debug_Module/DM_Abstract_Commands.bsv @@ -58,18 +58,18 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC); Reg #(Bool) rg_start_reg_access <- mkReg (False); // FIFOs for request/response to access GPRs - FIFOF #(DM_CPU_Req #(5, XLEN)) f_hart0_gpr_reqs <- mkFIFOF1; - FIFOF #(DM_CPU_Rsp #(XLEN)) f_hart0_gpr_rsps <- mkFIFOF1; + FIFOF #(DM_CPU_Req #(5, XLEN)) f_hart0_gpr_reqs <- mkFIFOF; + FIFOF #(DM_CPU_Rsp #(XLEN)) f_hart0_gpr_rsps <- mkFIFOF; // FIFOs for request/response to access FPRs `ifdef ISA_F - FIFOF #(DM_CPU_Req #(5, FLEN)) f_hart0_fpr_reqs <- mkFIFOF1; - FIFOF #(DM_CPU_Rsp #(FLEN)) f_hart0_fpr_rsps <- mkFIFOF1; + FIFOF #(DM_CPU_Req #(5, FLEN)) f_hart0_fpr_reqs <- mkFIFOF; + FIFOF #(DM_CPU_Rsp #(FLEN)) f_hart0_fpr_rsps <- mkFIFOF; `endif // FIFOs for request/response to access CSRs - FIFOF #(DM_CPU_Req #(12, XLEN)) f_hart0_csr_reqs <- mkFIFOF1; - FIFOF #(DM_CPU_Rsp #(XLEN)) f_hart0_csr_rsps <- mkFIFOF1; + FIFOF #(DM_CPU_Req #(12, XLEN)) f_hart0_csr_reqs <- mkFIFOF; + FIFOF #(DM_CPU_Rsp #(XLEN)) f_hart0_csr_rsps <- mkFIFOF; // ---------------------------------------------------------------- // rg_data0 @@ -89,15 +89,18 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC); Reg #(Bool) rg_abstractcs_busy <- mkRegU; Reg #(DM_abstractcs_cmderr) rg_abstractcs_cmderr <- mkRegU; - Bit #(5) abstractcs_progsize = 0; - Bit #(5) abstractcs_datacount = 0; + // Size of program buffer, in 32b words + Bit #(5) abstractcs_progbufsize = 0; + // Number of data registers implemented (rg_data0, rg_data1) + Bit #(4) abstractcs_datacount = ((xlen == 32) ? 1 : 2); + DM_Word virt_rg_abstractcs = {3'b0, - abstractcs_progsize, + abstractcs_progbufsize, 11'b0, pack (rg_abstractcs_busy), 1'b0, pack (rg_abstractcs_cmderr), - 3'b0, + 4'b0, abstractcs_datacount}; function Action fa_rg_abstractcs_write (DM_Word dm_word); diff --git a/src_Core/Debug_Module/DM_Run_Control.bsv b/src_Core/Debug_Module/DM_Run_Control.bsv index be671ac..8b727cb 100644 --- a/src_Core/Debug_Module/DM_Run_Control.bsv +++ b/src_Core/Debug_Module/DM_Run_Control.bsv @@ -9,9 +9,15 @@ package DM_Run_Control; // ================================================================ // BSV library imports -import FIFOF :: *; -import GetPut :: *; -import ClientServer :: *; +import FIFOF :: *; +import GetPut :: *; +import ClientServer :: *; + +// ---------------- +// Other library imports + +import Cur_Cycle :: *; +import GetPut_Aux :: *; // ================================================================ // Project imports @@ -33,13 +39,14 @@ interface DM_Run_Control_IFC; // ---------------- // Facing a hart: reset and run-control - interface Get #(Token) hart0_get_reset_req; + interface Client #(Bool, Bool) hart0_reset_client; interface Client #(Bool, Bool) hart0_client_run_halt; interface Get #(Bit #(4)) hart0_get_other_req; // ---------------- // Facing Platform: Non-Debug-Module Reset (reset all except DM) - interface Get #(Token) get_ndm_reset_req; + // Bool indicates 'running' hart state. + interface Client #(Bool, Bool) ndm_reset_client; endinterface // ================================================================ @@ -52,7 +59,8 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // ---------------------------------------------------------------- // NDM Reset - FIFOF #(Token) f_ndm_reset_reqs <- mkFIFOF; + FIFOF #(Bool) f_ndm_reset_reqs <- mkFIFOF; + FIFOF #(Bool) f_ndm_reset_rsps <- mkFIFOF; // ---------------------------------------------------------------- // Hart0 run control @@ -60,7 +68,8 @@ module mkDM_Run_Control (DM_Run_Control_IFC); Reg #(Bool) rg_hart0_running <- mkRegU; // Reset requests to hart - FIFOF #(Token) f_hart0_reset_reqs <- mkFIFOF; + FIFOF #(Bool) f_hart0_reset_reqs <- mkFIFOF; + FIFOF #(Bool) f_hart0_reset_rsps <- mkFIFOF; // Run/halt requests to hart and responses FIFOF #(Bool) f_hart0_run_halt_reqs <- mkFIFOF; @@ -81,7 +90,13 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // 'anyXX' = 'allXX' // 'allrunning' = NOT 'allhalted' - Reg#(Bool) rg_dmstatus_allresumeack <- mkRegU; + Bool dmstatus_impebreak = False; + + Reg #(Bool) rg_hart0_hasreset <- mkRegU; + Bool dmstatus_allhavereset = rg_hart0_hasreset; + Bool dmstatus_anyhavereset = rg_hart0_hasreset; + + Reg #(Bool) rg_dmstatus_allresumeack <- mkRegU; Bool dmstatus_allresumeack = rg_dmstatus_allresumeack; Bool dmstatus_anyresumeack = rg_dmstatus_allresumeack; @@ -89,8 +104,9 @@ module mkDM_Run_Control (DM_Run_Control_IFC); Bool dmstatus_allnonexistent = False; Bool dmstatus_anynonexistent = dmstatus_allnonexistent; - Bool dmstatus_allunavail = False; - Bool dmstatus_anyunavail = dmstatus_allunavail; + Reg #(Bool) rg_dmstatus_allunavail <- mkReg (False); + Bool dmstatus_allunavail = rg_dmstatus_allunavail; + Bool dmstatus_anyunavail = rg_dmstatus_allunavail; Bool dmstatus_allrunning = rg_hart0_running; Bool dmstatus_anyrunning = dmstatus_allrunning; @@ -98,7 +114,11 @@ module mkDM_Run_Control (DM_Run_Control_IFC); Bool dmstatus_allhalted = (! rg_hart0_running); Bool dmstatus_anyhalted = dmstatus_allhalted; - DM_Word virt_rg_dmstatus = {14'b0, + DM_Word virt_rg_dmstatus = {9'b0, + pack (dmstatus_impebreak), + 2'b0, + pack (dmstatus_allhavereset), + pack (dmstatus_anyhavereset), pack (dmstatus_allresumeack), pack (dmstatus_anyresumeack), pack (dmstatus_allnonexistent), @@ -151,19 +171,17 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // Debug Module reset if (! dmactive) begin // Reset the DM module itself - $display ("DM_Run_Control.write: dmcontrol 0x%08h (dmactive=0): resetting Debug Module", - dm_word); + $display ("%0d: %m.dmcontrol_write 0x%08h (dmactive=0): resetting Debug Module", + cur_cycle, dm_word); // Error-checking if (ndmreset) begin - $display ("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - dm_word); + $display (" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", dm_word); $display (" [1] (ndmreset) and [0] (dmactive) both asserted"); $display (" dmactive has priority; ignoring ndmreset"); end if (hartreset) begin - $display ("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - dm_word); + $display (" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", dm_word); $display (" [29] (hartreset) and [0] (dmactive) both asserted"); $display (" dmactive has priority; ignoring hartreset"); end @@ -172,63 +190,84 @@ module mkDM_Run_Control (DM_Run_Control_IFC); noAction; end - // Platform reset (non-Debug Module) - else if (ndmreset) begin - $display ("DM_Run_Control.write: dmcontrol 0x%08h: ndmreset=1: resetting platform", - dm_word); - f_ndm_reset_reqs.enq (?); - rg_hart0_running <= True; // Must be same as run/halt state of CPU after hart_reset! + // Ignore if NDM reset is in progress + else if (rg_dmstatus_allunavail) begin + $display ("%0d: %m.dmcontrol_write 0x%0h: ndm reset in progress; ignoring this write", + cur_cycle, dm_word); + end + + // Non-Debug-Module reset (platform reset) posedge: ignore + else if ((! rg_dmcontrol_ndmreset) && ndmreset) begin + if (verbosity != 0) + $display ("%0d: %m.dmcontrol_write 0x%08h: ndmreset: 0->1: ignoring", + cur_cycle, dm_word); + end + + // Non-Debug-Module reset (platform reset) negedge: do it + else if (rg_dmcontrol_ndmreset && (! ndmreset)) begin + Bool running = (! haltreq); + if (verbosity != 0) begin + $display ("%0d: %m.dmcontrol_write 0x%08h: ndmreset: 1->0: resetting platform", + cur_cycle, dm_word); + $display (" Requested 'running' state = ", fshow (running)); + end + + f_ndm_reset_reqs.enq (running); + rg_dmstatus_allunavail <= True; // Error-checking if (hartreset) begin - $display ("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - dm_word); - $display (" Both ndmreset (bit 1) and hartreset (bit 29) are asserted"); + $display (" WARNING: %m.dmcontrol_write 0x%08h:", dm_word); + $display (" Both ndmreset [1] and hartreset [29] are asserted"); $display (" ndmreset has priority; ignoring hartreset"); end + end - else begin + + // Hart reset + else if (hartreset) begin + Bool running = (! haltreq); + f_hart0_reset_reqs.enq (running); + rg_hart0_hasreset <= True; + // Deassert platform reset - if ((verbosity != 0) && rg_dmcontrol_ndmreset) - $display ("DM_Run_Control.write: dmcontrol 0x%08h: clearing ndmreset", dm_word); - - // Hart reset - if (hartreset) begin - if (verbosity != 0) - $display ("DM_Run_Control.write: dmcontrol 0x%08h: hartreset=1: resetting hart", - dm_word); - f_hart0_reset_reqs.enq (?); - rg_hart0_running <= True; // Must be same as run/halt state of CPU after hart_reset! + if (verbosity != 0) begin + $display ("%0d: %m.dmcontrol_write 0x%08h: hartreset=1: resetting hart", + cur_cycle, dm_word); + $display (" Requested 'running' state = ", fshow (running)); end - else begin - // Deassert hart reset - if ((verbosity != 0) && rg_dmcontrol_hartreset) - $display ("DM_Run_Control.write: dmcontrol 0x%08h: clearing hartreset", dm_word); + end - if (hasel) - $display ("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: 'hasel' is not supported", - dm_word); + // run/halt commands + else begin + // Deassert hart reset + if ((verbosity != 0) && rg_dmcontrol_hartreset) + $display ("%0d: %m.dmcontrol_write 0x%08h: clearing hartreset", + cur_cycle, dm_word); - if (hartsel != 0) - $display ("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: hartsel 0x%0h not supported", - dm_word, hartsel); + if (hasel) + $display ("%0d:ERROR: %m.dmcontrol_write 0x%08h: hasel is not supported", + cur_cycle, dm_word); - if (haltreq && resumereq) begin - $display ("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: haltreq=1 and resumereq=1", - dm_word); - $display (" This behavior is 'undefined' in the spec; ignoring"); - end - // Resume hart(s) if not running - else if (resumereq && (! rg_hart0_running)) begin - f_hart0_run_halt_reqs.enq (True); - rg_dmstatus_allresumeack <= False; - $display ("DM_Run_Control.write: hart0 resume request"); - end - // Halt hart(s) - else if (haltreq && rg_hart0_running) begin - f_hart0_run_halt_reqs.enq (False); - $display ("DM_Run_Control.write: hart0 halt request"); - end + if (hartsel != 0) + $display ("%0d:ERROR: %m.dmcontrol_write 0x%08h: hartsel 0x%0h not supported", + cur_cycle, dm_word, hartsel); + + if (haltreq && resumereq) begin + $display ("%0d:ERROR: %m.dmcontrol_write 0x%08h: haltreq=1 and resumereq=1", + cur_cycle, dm_word); + $display (" This behavior is 'undefined' in the spec; ignoring"); + end + // Resume hart(s) if not running + else if (resumereq && (! rg_hart0_running)) begin + f_hart0_run_halt_reqs.enq (True); + rg_dmstatus_allresumeack <= False; + $display ("%0d: %m.dmcontrol_write: hart0 resume request", cur_cycle); + end + // Halt hart(s) + else if (haltreq && rg_hart0_running) begin + f_hart0_run_halt_reqs.enq (False); + $display ("%0d: %m.dmcontrol_write: hart0 halt request", cur_cycle); end end endaction @@ -250,19 +289,37 @@ module mkDM_Run_Control (DM_Run_Control_IFC); Reg #(Bit #(4)) rg_verbosity <- mkRegU; // ---------------------------------------------------------------- + // System responses - rule rl_hart0_run_rsp; - let x = f_hart0_run_halt_rsps.first; - f_hart0_run_halt_rsps.deq; + // Response from system for hart0 reset + rule rl_hart0_reset_rsp; + Bool running <- pop (f_hart0_reset_rsps); + rg_hart0_hasreset <= False; + rg_hart0_running <= running; - rg_hart0_running <= x; - if (x) begin + if (verbosity != 0) + $display ("%0d: %m.rl_hart0_reset_rsp: hart running = ", cur_cycle, fshow (running)); + endrule + + // Response from system for NDM reset + rule rl_ndm_reset_rsp; + Bool running <- pop (f_ndm_reset_rsps); + rg_hart0_running <= running; + rg_dmstatus_allunavail <= False; + + // if (verbosity != 0) TODO: UNCOMMENT AFTER DEBUGGING + $display ("%0d: %m.rl_ndm_reset_rsp: hart running = ", cur_cycle, fshow (running)); + endrule + + // Response from system for run/halt request + rule rl_hart0_run_rsp (! f_ndm_reset_rsps.notEmpty); + let running <- pop (f_hart0_run_halt_rsps); + rg_hart0_running <= running; + if (running) rg_dmstatus_allresumeack <= True; - $display ("DM_Run_Control: hart0 running"); - end - else begin - $display ("DM_Run_Control: hart0 halted"); - end + + if (verbosity != 0) + $display ("%0d: %m.rl_hart0_run_rsp: 'running' = ", cur_cycle, fshow (running)); endrule // ---------------------------------------------------------------- @@ -274,9 +331,12 @@ module mkDM_Run_Control (DM_Run_Control_IFC); method Action reset; f_ndm_reset_reqs.clear; + f_ndm_reset_rsps.clear; - rg_hart0_running <= True; // Must be same as run/halt state of CPU after hart_reset! f_hart0_reset_reqs.clear; + f_hart0_reset_rsps.clear; + + rg_hart0_running <= True; // Safe approximation of whether the CPU is running or not f_hart0_run_halt_reqs.clear; f_hart0_run_halt_rsps.clear; @@ -285,12 +345,14 @@ module mkDM_Run_Control (DM_Run_Control_IFC); rg_dmcontrol_ndmreset <= False; rg_dmcontrol_dmactive <= True; // DM module is now active + rg_hart0_hasreset <= False; rg_dmstatus_allresumeack <= False; + rg_dmstatus_allunavail <= False; // NDM not in progress rg_verbosity <= 0; if (verbosity != 0) - $display ("DM_Run_Control: reset"); + $display ("%0d: %m.reset", cur_cycle); endmethod // ---------------- @@ -307,7 +369,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); endcase; if (verbosity != 0) - $display ("DM_Run_Control.av_read: [", fshow_dm_addr (dm_addr), "] => 0x%08h", dm_word); + $display ("%0d: %m.av_read: [", cur_cycle, fshow_dm_addr (dm_addr), "] => 0x%08h", dm_word); return dm_word; endactionvalue @@ -316,7 +378,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); method Action write (DM_Addr dm_addr, DM_Word dm_word); action if (verbosity != 0) - $display ("DM_Run_Control.write: [", fshow_dm_addr (dm_addr), "] <= 0x%08h", dm_word); + $display ("%0d: %m.write: [", cur_cycle, fshow_dm_addr (dm_addr), "] <= 0x%08h", dm_word); case (dm_addr) dm_addr_dmcontrol: fa_rg_dmcontrol_write (dm_word); @@ -331,13 +393,13 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // ---------------- // Facing Hart: Reset, Run-control, etc. - interface Get hart0_get_reset_req = toGet (f_hart0_reset_reqs); + interface Client hart0_reset_client = toGPClient (f_hart0_reset_reqs, f_hart0_reset_rsps); interface Client hart0_client_run_halt = toGPClient (f_hart0_run_halt_reqs, f_hart0_run_halt_rsps); interface Get hart0_get_other_req = toGet (f_hart0_other_reqs); // ---------------- // Facing Platform: Non-Debug-Module Reset (reset all except DM) - interface Get get_ndm_reset_req = toGet (f_ndm_reset_reqs); + interface Client ndm_reset_client = toGPClient (f_ndm_reset_reqs, f_ndm_reset_rsps); endmodule // ================================================================ diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index 7ed6da6..e60fd38 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -179,7 +179,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------------------------------------------------------- // Interface to memory fabric - AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor_2; + AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor; // ---------------------------------------------------------------- // System Bus state @@ -318,8 +318,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); awuser: fabric_default_user}; master_xactor.i_wr_addr.enq (wra); - let wrd = AXI4_Wr_Data {wid: fabric_default_id, - wdata: fabric_data, + let wrd = AXI4_Wr_Data {wdata: fabric_data, wstrb: fabric_strb, wlast: True, wuser: fabric_default_user}; diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 8a6b773..6348466 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -96,7 +96,7 @@ interface Debug_Module_IFC; // This section replicated for additional harts. // Reset and run-control - interface Get #(Token) hart0_get_reset_req; + interface Client #(Bool, Bool) hart0_reset_client; interface Client #(Bool, Bool) hart0_client_run_halt; interface Get #(Bit #(4)) hart0_get_other_req; @@ -115,7 +115,8 @@ interface Debug_Module_IFC; // Facing Platform // Non-Debug-Module Reset (reset all except DM) - interface Get #(Token) get_ndm_reset_req; + // Bool indicates 'running' hart state. + interface Client #(Bool, Bool) ndm_reset_client; // Read/Write RISC-V memory interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master; @@ -126,6 +127,9 @@ endinterface (* synthesize *) module mkDebug_Module (Debug_Module_IFC); + // Local verbosity: 0 = quiet; 1 = print DMI transactions + Integer verbosity = 0; + // The three parts DM_Run_Control_IFC dm_run_control <- mkDM_Run_Control; DM_Abstract_Commands_IFC dm_abstract_commands <- mkDM_Abstract_Commands; @@ -152,6 +156,9 @@ module mkDebug_Module (Debug_Module_IFC); interface DMI dmi; method Action read_addr (DM_Addr dm_addr); f_read_addr.enq(dm_addr); + + if (verbosity != 0) + $display ("%0d: %m.DMI read: dm_addr 0x%0h", cur_cycle, dm_addr); endmethod method ActionValue #(DM_Word) read_data; @@ -209,6 +216,10 @@ module mkDebug_Module (Debug_Module_IFC); dm_word = 0; end + if (verbosity != 0) + $display ("%0d: %m.DMI read response: dm_addr 0x%0h, dm_word 0x%0h", + cur_cycle, dm_addr, dm_word); + return dm_word; endmethod @@ -261,6 +272,10 @@ module mkDebug_Module (Debug_Module_IFC); // TODO: set error status? noAction; end + + if (verbosity != 0) + $display ("%0d: %m.DMI write: dm_addr 0x%0h, dm_word 0x%0h", + cur_cycle, dm_addr, dm_word); endmethod endinterface @@ -268,7 +283,7 @@ module mkDebug_Module (Debug_Module_IFC); // Facing CPU/hart0 // Reset and run-control - interface Get hart0_get_reset_req = dm_run_control.hart0_get_reset_req; + interface Client hart0_reset_client = dm_run_control.hart0_reset_client; interface Client hart0_client_run_halt = dm_run_control.hart0_client_run_halt; interface Get hart0_get_other_req = dm_run_control.hart0_get_other_req; @@ -287,7 +302,7 @@ module mkDebug_Module (Debug_Module_IFC); // Facing Platform // Non-Debug-Module Reset (reset all except DM) - interface Get get_ndm_reset_req = dm_run_control.get_ndm_reset_req; + interface Client ndm_reset_client = dm_run_control.ndm_reset_client; // Read/Write RISC-V memory interface AXI4_Master_IFC master = dm_system_bus.master; diff --git a/src_Core/Debug_Module/README.txt b/src_Core/Debug_Module/README.txt index d907344..201e19a 100644 --- a/src_Core/Debug_Module/README.txt +++ b/src_Core/Debug_Module/README.txt @@ -1,3 +1,206 @@ +'Debug_Module' implements a Debug Module for RISC-V processors in +accordance with the RISC-V standard "External Debug Support" spec: + + RISC-V External Debug Support + Version 0.13.2 + d5029366d59e8563c08b6b9435f82573b603e48e + Fri Mar 22 09:06:04 2019 -0700 + +Note: the spec is independent of any particular RISC-V CPU +implementation. It just specifies the standard registers in the Debug +Module that can be read and written by an external debugger (such as +GDB). It specifies the address map of these registers, and the +semantics, i.e., what happens when one reads or writes these +registers. The spec does not say anything about how this spec is +implemented. + +Please see comments in Debug_Module.bsv for more details on our +implementation of the Debug Module spec. This implementation is also +not specific to any particular CPU implementation. We use it in +multiple Bluespec RISC-V CPU implementations, and it could be used +with other CPU implementations as well. + +// ================================================================ +What follows is a concise cheat-sheet for the registers in the Debug Module. + +DM_Addr dm_addr_data0 = 'h04; +DM_Addr dm_addr_data1 = 'h05; +DM_Addr dm_addr_data2 = 'h06; +DM_Addr dm_addr_data3 = 'h07; +DM_Addr dm_addr_data4 = 'h08; +DM_Addr dm_addr_data5 = 'h09; +DM_Addr dm_addr_data6 = 'h0a; +DM_Addr dm_addr_data7 = 'h0b; +DM_Addr dm_addr_data8 = 'h0c; +DM_Addr dm_addr_data9 = 'h0d; +DM_Addr dm_addr_data10 = 'h0d; +DM_Addr dm_addr_data11 = 'h0f; + +// ---------------- +// Run Control + +DM_Addr dm_addr_dmcontrol = 'h10; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + | | | | 0 | | | | | 0 0 | | | |dmactive + | | | | | | | | | | | |ndmreset + | | | | | | | | | | |clrresethaltreq + | | | | | | | | | |setresethaltreq + | | | | | | | |-----------10-----------|hartselhi + | | | | | |------------10--------------|hartsello + | | | | |hasel + | | | | 0: Single hart selected (hartsel) + | | | | 1: Multiple harts selected (hartsel + hart array mask) + | | | |ackhavereset + | | |hartreset + | |resumereq + |haltreq + +DM_Addr dm_addr_dmstatus = 'h11; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + 0 0 0 0 0 0 0 0 | | 0 0 | | | | | | | | | | | | | | | | |--4--|version + | | | | | | | | | | | | | | | | | | | 0: no DM present + | | | | | | | | | | | | | | | | | | | 1: DM v011 + | | | | | | | | | | | | | | | | | | | 2: DM v013 + | | | | | | | | | | | | | | | | | | | 15: DM vUnknown + | | | | | | | | | | | | | | | | | |confstrptrvalid + | | | | | | | | | | | | | | | | |hasresethaltreq + | | | | | | | | | | | | | | | |authbusy + | | | | | | | | | | | | | | |authenticated + | | | | | | | | | | | | | |anyhalted + | | | | | | | | | | | | |allhalted + | | | | | | | | | | | |anyrunning + | | | | | | | | | | |allrunning + | | | | | | | | | |anyunavail + | | | | | | | | |allunavail + | | | | | | | |anynonexistent + | | | | | | |allnonexistent + | | | | | |anyresumeack + | | | | |allresumeack + | | | |anyhavereset + | | |allhavereset + | |impebreak + | 0 No implicit EBREAK at end of PB + | 1 Implicit EBREAK at end of PB + +DM_Addr dm_addr_hartinfo = 'h12; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + 0 0 0 0 0 0 0 0 | | 0 0 0 | | | |-----------12-----------|dataaddr + | | | |----4---|datasize + |----4---|nscratch |dataaccess + + +DM_Addr dm_addr_haltsum1 = 'h13; +DM_Addr dm_addr_hawindowsel = 'h14; +DM_Addr dm_addr_hawindow = 'h15; + +// ---------------- +// Abstract commands (read/write RISC-V registers and RISC-V CSRs) + +DM_Addr dm_addr_abstractcs = 'h16; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + 0 0 0 | | 0 0 0 0 0 0 0 0 0 0 0 | 0 | | 0 0 0 0 |--4--|datacount + 0 0 0 |-----5------|progbufsize |busy |-3-|cmderr + +DM_Addr dm_addr_command = 'h17; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + | 0 | | | | | | |-----------------16------------------|regno + | | | | | | | | 0x0000-0x0FFF CSRs (dpc => PC) + | | | | | | | | 0x1000-0x101F GPRs + | | | | | | | | 0x1020-0x103F Floating Point Regs + | | | | | | | | 0xC000-0xFFFF Reserved + | | | | | | |write + | | | | | | 0: specified reg -> arg0 of data + | | | | | | 1: specified reg <- arg0 of data + | | | | | |transfer + | | | | | 0 Don't do the 'write' op + | | | | | 1 Do the 'write' op + | | | | | Allows exec of PB without valid vals in 'size' and 'regno' + | | | | |postexec + | | | | 1 exec Program Buffer exactly once after the xfer + | | | |aarpostincrement + | |--3--|aarsize + | 2 Lowest 32b of reg + | 3 Lowest 64b of reg + | 4 Lowest 128b of reg + |---------8-----------|cmdtype + 0 ACCESS_REG + 1 QUICK_ACCESS + +DM_Addr dm_addr_abstractauto = 'h18; +DM_Addr dm_addr_confstrptr0 = 'h19; +DM_Addr dm_addr_confstrptr1 = 'h1a; +DM_Addr dm_addr_confstrptr2 = 'h1b; +DM_Addr dm_addr_confstrptr3 = 'h1c; +DM_Addr dm_addr_nextdm = 'h1d; + +DM_Addr dm_addr_progbuf0 = 'h20; +DM_Addr dm_addr_progbuf1 = 'h21; +DM_Addr dm_addr_progbuf2 = 'h22; +DM_Addr dm_addr_progbuf3 = 'h23; +DM_Addr dm_addr_progbuf4 = 'h24; +DM_Addr dm_addr_progbuf5 = 'h25; +DM_Addr dm_addr_progbuf6 = 'h26; +DM_Addr dm_addr_progbuf7 = 'h27; +DM_Addr dm_addr_progbuf8 = 'h28; +DM_Addr dm_addr_progbuf9 = 'h29; +DM_Addr dm_addr_progbuf10 = 'h2a; +DM_Addr dm_addr_progbuf11 = 'h2b; +DM_Addr dm_addr_progbuf12 = 'h2c; +DM_Addr dm_addr_progbuf13 = 'h2d; +DM_Addr dm_addr_progbuf14 = 'h2e; +DM_Addr dm_addr_progbuf15 = 'h2f; + +DM_Addr dm_addr_authdata = 'h30; +DM_Addr dm_addr_haltsum2 = 'h34; +DM_Addr dm_addr_haltsum3 = 'h35; + +DM_Addr dm_addr_sbaddress3 = 'h37; + +// ---------------- +// System Bus access (read/write RISC-V memory/devices) + +DM_Addr dm_addr_sbcs = 'h38; + 31.30.29.28| 27.26.25.24| 23.22.21.20| 19.18.17.16| 15.14.13.12| 11.10.9.8| 7.6.5.4| 3.2.1.0| + | | 0 0 0 0 0 0 | | | | | | | | | | | | | | | |sbaccess8 + | | | | | | | | | | | | | | | | |sbaccess16 + | | | | | | | | | | | | | | | |sbaccess32 + | | | | | | | | | | | | | | |sbaccess64 + | | | | | | | | | | | | | |sbaccess128 + | | | | | | | | | | | |-----7-------|sbasize + | | | | | | | | | |--3--|sberror + | | | | | | | | | 0: no bus err + | | | | | | | | | 1: timeout + | | | | | | | | | 2: bad addr + | | | | | | | | | 3: alignment err + | | | | | | | | | 4: unsupported size + | | | | | | | | | 7: other + | | | | | | | | |sbreadondata: read on sbdata0 triggers sb read + | | | | | | | |sbautoincrement + | | | | | |--3--|sbaccess + | | | | | 0:8b, 1:16b, 2:32b, 3:64b, 4:128b + | | | | |sbreadonaddr + | | | | 1 Every write to sbaddress0 triggers sb read at new addr + | | | |sbbusy + | | |sbbusyerror + |--3--|sbversion + 0: System Bus interface spec version < 2018-01-01 + 1: This System Bus interface spec version + +DM_Addr dm_addr_sbaddress0 = 'h39; +DM_Addr dm_addr_sbaddress1 = 'h3a; +DM_Addr dm_addr_sbaddress2 = 'h3b; +DM_Addr dm_addr_sbdata0 = 'h3c; +DM_Addr dm_addr_sbdata1 = 'h3d; +DM_Addr dm_addr_sbdata2 = 'h3e; +DM_Addr dm_addr_sbdata3 = 'h3f; +DM_Addr dm_addr_haltsum0 = 'h40; + +// ================================================================ +// ================================================================ +// OLDER VERSIONS OF THE DEBUG MODULE SPEC +// ================================================================ +// ================================================================ + 'Debug_Module' implements a Debug Module for RISC-V processors in accordance with the RISC-V standard "External Debug Support" spec: diff --git a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv index 75cff2f..0e8fa88 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv @@ -1,16 +1,19 @@ -// This file is a modified version of: RISCY_OOO/procs/lib/LLCDmaConnect.bsv - -// The original module had, as 2nd parameter, MemLoaderMemClient memLoader -// The memLoader assumed only write-transactions (to load memory), and -// discarded load responses. - -// Here, the module instead offers an AXI4_Slave interface to be -// connected to the AXI4_Master of the Debug Module. -// This axi4_slave accepts and responds to both read and write transactions. - // Copyright (c) 2017 Massachusetts Institute of Technology // Portions Copyright (c) 2019-2020 Bluespec, Inc. -// + +// This file is a modified version of: RISCY_OOO/procs/lib/LLCDmaConnect.bsv +// Bluespec: this file is has many modifications. + +// The original module had 3 params and had an Empty interface. +// The 2nd param was: MemLoaderMemClient memLoader +// which issued only write-transactions (to load memory). +// The module discarded write responses, and ignored read-requests. + +// Here, that module parameter is removed and, instead, the module has an +// AXI4_Slave interface, to be connected to the AXI4_Master of the +// Debug Module. This axi4_slave accepts, processes and responds +// to both read and write transactions. + // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -87,31 +90,33 @@ typedef union tagged { } LLCDmaReqId deriving(Bits, Eq, FShow); // ================================================================ -// Functions to insert/extract axi4 data into/from a cache line +// Help functions for read-modify-writes of 4-Byte values on a 64-Byte Cache Line -// For writing, position the AXI4 8-byte data and 8-bit byte-enable -// into a 64-byte line and 64-bit line-byte-enable -function Tuple3 #(Addr, - Line, - LineByteEn) fn_line_and_line_byteen_from_axi4 (Addr axi4_addr, - Bit #(8) axi4_byteen, - Bit #(64) axi4_data); - Vector #(8, Bit #(64)) line_dwords = replicate (0); - Vector #(8, Bit #(8)) line_dword_byteen = replicate (0); - Bit #(3) dword_index = axi4_addr [5:3]; - line_dwords [dword_index] = axi4_data; - line_dword_byteen [dword_index] = axi4_byteen; - Addr line_addr = { axi4_addr [63:6], 6'b0 }; - return tuple3 (line_addr, - unpack (pack (line_dwords)), - unpack (pack (line_dword_byteen))); +typedef enum {CACHELINE_CACHE_INVALID, + CACHELINE_CACHE_WRITING_BACK, + CACHELINE_CACHE_RELOADING, + CACHELINE_CACHE_CLEAN, + CACHELINE_CACHE_DIRTY + } Cacheline_Cache_State +deriving (Bits, Eq, FShow); + +function Addr fn_align_addr_to_line (Addr addr); + Addr line_addr = { addr [63:6], 6'b0 }; + return line_addr; endfunction -// For reading, extract 8-byte AXI4 data from a 64-byte line -function Bit #(64) fn_axi4_data_from_line (Line line, Bit #(3) dword_in_line); - Vector #(8, Bit #(64)) line_words = unpack (pack (line)); - Bit #(64) dw = line_words [dword_in_line]; - return dw; +function Bool fn_addr_is_in_line (Addr addr, Addr line_addr); + return (fn_align_addr_to_line (addr) == line_addr); +endfunction + +function Bit #(64) fn_expand_strb_to_mask (Bit #(8) strb); + function Bit #(8) fn_bit_to_byte (Integer j); + return ((strb [j] == 1'b1) ? 8'hFF : 8'h00); + endfunction + + Vector #(8, Bit #(8)) v = genWith (fn_bit_to_byte); + + return pack (v); endfunction // ================================================================ @@ -133,6 +138,228 @@ module mkLLCDmaConnect #( // Slave transactor for requests from Debug Module AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) axi4_slave_xactor <- mkAXI4_Slave_Xactor; + // ================================================================ + // These regs are a 1-location local cache for an LLC Cache Line, + // to avoid doing a full read-modify-write to the LLC on each transaction. + + Reg #(Cacheline_Cache_State) rg_cacheline_cache_state <- mkReg (CACHELINE_CACHE_CLEAN); + Reg #(Addr) rg_cacheline_cache_addr <- mkReg (1); // never matches an LLC line addr + Reg #(Line) rg_cacheline_cache_data <- mkRegU; + + // Writeback dirty cacheline_cache if no new store requests within n-cycles + Reg #(Bit #(10)) rg_cacheline_cache_dirty_delay <- mkReg (0); + + // ================================================================ + // Write transactions from the external client (e.g., Debug Module) + + // Respond to store-requests from the external client on store-hit + rule rl_handle_MemLoader_st_req ( ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN) + || (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY)) + && (fn_addr_is_in_line (axi4_slave_xactor.o_wr_addr.first.awaddr, + rg_cacheline_cache_addr))); + let wr_addr <- pop_o (axi4_slave_xactor.o_wr_addr); + let wr_data <- pop_o (axi4_slave_xactor.o_wr_data); + Addr addr = wr_addr.awaddr; + Bit #(64) data = wr_data.wdata; + Bit #(64) mask = fn_expand_strb_to_mask (wr_data.wstrb); + + // Read rg_cacheline_cache_data as 64-bit words + Vector #(8, Bit #(64)) line_dwords = unpack (pack (rg_cacheline_cache_data)); + // Modify relevant bytes of relevant dword + Bit #(3) dword_in_line = addr [5:3]; + Bit #(64) old_dword = line_dwords [dword_in_line]; + Bit #(64) new_dword = ((old_dword & (~ mask)) | (data & mask)); + line_dwords [dword_in_line] = new_dword; + // Save it + rg_cacheline_cache_data <= unpack (pack (line_dwords)); + rg_cacheline_cache_state <= CACHELINE_CACHE_DIRTY; + rg_cacheline_cache_dirty_delay <= '1; // start write-back delay countdown + + // Send response to external client + AXI4_Wr_Resp #(Wd_Id, Wd_User) + wr_resp = AXI4_Wr_Resp {bid: 0, // TODO: change uniformly to Fabric_id + bresp: axi4_resp_okay, + buser: ?}; + axi4_slave_xactor.i_wr_resp.enq (wr_resp); + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_handle_MemLoader_st_req: addr %0h data %0h strb %0h", + cur_cycle, wr_addr.awaddr, wr_data.wdata, wr_data.wstrb); + $display (" old_dword: %0h", old_dword); + $display (" new_dword: %0h", old_dword); + end + endrule + + // ================================================================ + // Read transactions from the external memory client (e.g., Debug Module) + + // Responds to load-requests from the external client on load-hit + rule rl_handle_MemLoader_ld_req ( ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN) + || (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY)) + && (fn_addr_is_in_line (axi4_slave_xactor.o_rd_addr.first.araddr, + rg_cacheline_cache_addr))); + let rd_addr <- pop_o (axi4_slave_xactor.o_rd_addr); + Addr addr = rd_addr.araddr; + + // Read rg_cacheline_cache as 64-bit words + Vector #(8, Bit #(64)) line_dwords = unpack (pack (rg_cacheline_cache_data)); + Bit #(3) dword_in_line = addr [5:3]; + Bit #(64) dword = line_dwords [dword_in_line]; + + // Send response to external client + AXI4_Rd_Data #(Wd_Id, Wd_Data, Wd_User) + rd_data = AXI4_Rd_Data {rid: 0, // TODO: fixup + rdata: dword, + rresp: axi4_resp_okay, + rlast: True, + ruser: ?}; + axi4_slave_xactor.i_rd_data.enq (rd_data); + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_handle_MemLoader_ld_req: addr %0h", cur_cycle, rd_addr.araddr); + $display (" dword: %0h", dword); + end + endrule + + // ---------------------------------------------------------------- + // Miss and writeback processing + + // Maintain dirty delay countdown + rule rl_cacheline_cache_writeback_dirty_delay ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY) + && (rg_cacheline_cache_dirty_delay != 0)); + rg_cacheline_cache_dirty_delay <= rg_cacheline_cache_dirty_delay - 1; + endrule + + function Action fa_writeback; + action + dmaRqT req = DmaRq {addr: rg_cacheline_cache_addr, + byteEn: replicate (True), // Write all bytes + data: rg_cacheline_cache_data, + id: tagged MemLoader (?) // TODO: use wr_addr.awid? + }; + llc.memReq.enq (req); + // $display ("%0d: %m.fa_writeback line at %0h", cur_cycle, rg_cacheline_cache_addr); + // $display (" data %0128h", rg_cacheline_cache_data); + endaction + endfunction + + // Initiate writeback if dirty for full delay + rule rl_cacheline_cache_writeback_dirty_aged ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY) + && (rg_cacheline_cache_dirty_delay == 0)); + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_writeback_dirty_aged.", cur_cycle); + $display (" Old line addr %0h", rg_cacheline_cache_addr); + end + + fa_writeback; + rg_cacheline_cache_state <= CACHELINE_CACHE_WRITING_BACK; + endrule + + // Initiate writeback if dirty and next request is store-miss + rule rl_cacheline_cache_writeback_st_miss ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY) + && (! fn_addr_is_in_line (axi4_slave_xactor.o_wr_addr.first.awaddr, + rg_cacheline_cache_addr))); + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_writeback_st_miss.", cur_cycle); + $display (" Old line addr %0h", rg_cacheline_cache_addr); + $display (" New addr %0h", axi4_slave_xactor.o_wr_addr.first.awaddr); + end + + fa_writeback; + rg_cacheline_cache_state <= CACHELINE_CACHE_WRITING_BACK; + endrule + + // Initiate writeback if dirty and next request is load-miss + rule rl_cacheline_cache_writeback_ld_miss ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY) + && (! fn_addr_is_in_line (axi4_slave_xactor.o_rd_addr.first.araddr, + rg_cacheline_cache_addr))); + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_writeback_ld_miss.", cur_cycle); + $display (" Old line addr %0h", rg_cacheline_cache_addr); + $display (" New addr %0h", axi4_slave_xactor.o_wr_addr.first.awaddr); + end + + fa_writeback; + rg_cacheline_cache_state <= CACHELINE_CACHE_WRITING_BACK; + endrule + + // Finish writeback + rule rl_cacheline_cache_writeback_finish (llc.respSt.first matches tagged MemLoader .id + &&& (rg_cacheline_cache_state == CACHELINE_CACHE_WRITING_BACK)); + let resp = llc.respSt.first; + llc.respSt.deq; + rg_cacheline_cache_state <= CACHELINE_CACHE_CLEAN; + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_writeback_finish. Line addr %0h", + cur_cycle, rg_cacheline_cache_addr); + $display (" Line data %0h", rg_cacheline_cache_data); + end + endrule + + function Action fa_initiate_reload (Addr addr); + action + let line_addr = fn_align_addr_to_line (addr); + dmaRqT req = DmaRq {addr: line_addr, + byteEn: replicate (False), // all False means 'read' + data: ?, + id: tagged MemLoader (?)}; // TODO: change uniformly to wr_addr.awid + llc.memReq.enq (req); + rg_cacheline_cache_addr <= line_addr; + + if (verbosity >= 2) begin + $display (" fa_initiate_reload: line_addr %0h", line_addr); + end + endaction + endfunction + + // Initiate reload when cacheline_cache is clean on store-miss + rule rl_cacheline_cache_reload_req_st ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN) + && (! fn_addr_is_in_line (axi4_slave_xactor.o_wr_addr.first.awaddr, + rg_cacheline_cache_addr))); + let addr = axi4_slave_xactor.o_wr_addr.first.awaddr; + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_reload_req_st for addr %0h", cur_cycle, addr); + end + + fa_initiate_reload (addr); + rg_cacheline_cache_state <= CACHELINE_CACHE_RELOADING; + endrule + + // Initiate reload when cacheline_cache is clean on load-miss + rule rl_cacheline_cache_reload_req_ld ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN) + && (! fn_addr_is_in_line (axi4_slave_xactor.o_rd_addr.first.araddr, + rg_cacheline_cache_addr))); + let addr = axi4_slave_xactor.o_rd_addr.first.araddr; + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_reload_req_ld for addr %0h", cur_cycle, addr); + end + + fa_initiate_reload (addr); + rg_cacheline_cache_state <= CACHELINE_CACHE_RELOADING; + endrule + + // Finish reload + rule rl_cacheline_cache_reload_finish (llc.respLd.first.id matches tagged MemLoader .id + &&& (rg_cacheline_cache_state == CACHELINE_CACHE_RELOADING)); + let resp = llc.respLd.first; + llc.respLd.deq; + rg_cacheline_cache_state <= CACHELINE_CACHE_CLEAN; + rg_cacheline_cache_data <= resp.data; + + if (verbosity >= 2) begin + $display ("%0d: %m.rl_cacheline_cache_reload_finish. Line addr %0h", cur_cycle, rg_cacheline_cache_addr); + $display (" Line data %0h", resp.data); + end + endrule + + // ================================================================ + // Transactions from the TLB + // Expecting only LOAD requests from TLB + // This section is unchanged from the original riscy-ooo module. + // helper functions for cross bar function XBarDstInfo#(Bit#(0), Tuple2#(CoreId, TlbMemReq)) getTlbDst(CoreId core, TlbMemReq r); return XBarDstInfo {idx: 0, data: tuple2(core, r)}; @@ -159,84 +386,13 @@ module mkLLCDmaConnect #( }; endfunction - rule sendMemLoaderReqToLLC_wr; // write requests - let wr_addr <- pop_o (axi4_slave_xactor.o_wr_addr); - let wr_data <- pop_o (axi4_slave_xactor.o_wr_data); + // Prioritize external mem client over Tlb + (* descending_urgency = "rl_cacheline_cache_writeback_dirty_aged, sendTlbReqToLLC" *) + (* descending_urgency = "rl_cacheline_cache_writeback_st_miss, sendTlbReqToLLC" *) + (* descending_urgency = "rl_cacheline_cache_writeback_ld_miss, sendTlbReqToLLC" *) + (* descending_urgency = "rl_cacheline_cache_reload_req_st, sendTlbReqToLLC" *) + (* descending_urgency = "rl_cacheline_cache_reload_req_ld, sendTlbReqToLLC" *) - if (wr_addr.awlen != 0) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awlen is not 0 (burst length is not 1)", cur_cycle); - $display (" ", fshow (wr_addr)); - $display (" ", fshow (wr_data)); - end - else if ( (wr_addr.awsize != axsize_1) - && (wr_addr.awsize != axsize_2) - && (wr_addr.awsize != axsize_4) - && (wr_addr.awsize != axsize_8)) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awsize is not code for 1,2,4,8", cur_cycle); - $display (" ", fshow (wr_addr)); - $display (" ", fshow (wr_data)); - end - else if (! wr_data.wlast) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: wlast is 1", cur_cycle); - $display (" ", fshow (wr_addr)); - $display (" ", fshow (wr_data)); - end - else begin - match {.line_addr, - .line_data, - .line_byteen } = fn_line_and_line_byteen_from_axi4 (wr_addr.awaddr, - wr_data.wstrb, - wr_data.wdata); - dmaRqT req = DmaRq {addr: line_addr, - byteEn: line_byteen, - data: line_data, - id: tagged MemLoader (?) // TODO: change uniformly to wr_addr.awid - }; - llc.memReq.enq(req); - if (verbosity != 0) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_wr", cur_cycle); - $display (" ", fshow (wr_addr)); - $display (" ", fshow (wr_data)); - $display (" ", fshow (req)); - end - end - endrule - - rule sendMemLoaderReqToLLC_rd; // read requests - let rd_addr <- pop_o (axi4_slave_xactor.o_rd_addr); - - if (rd_addr.arlen != 0) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arlen is not 0 (burst length is not 1)", cur_cycle); - $display (" ", fshow (rd_addr)); - end - else if ( (rd_addr.arsize != axsize_1) - && (rd_addr.arsize != axsize_2) - && (rd_addr.arsize != axsize_4) - && (rd_addr.arsize != axsize_8)) begin - $display ("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arsize is not code for 1,2,4,8", cur_cycle); - $display (" ", fshow (rd_addr)); - end - else begin - Addr line_addr = { rd_addr.araddr [63:6], 6'b0 }; - dmaRqT req = DmaRq {addr: line_addr, - byteEn: replicate (False), - data: ?, - id: MemLoader (?) // TODO: change uniformly to rd_addr.arid - }; - llc.memReq.enq(req); - Bit #(3) dword_in_line = rd_addr.araddr [5:3]; - f_dword_in_line.enq (dword_in_line); - - if (verbosity != 0) begin - $display("[LLCDmaConnect sendMemLoaderReqToLLC_rd]"); - $display (" ", fshow (rd_addr)); - $display (" ", fshow (req)); - end - end - endrule - - (* descending_urgency = "sendMemLoaderReqToLLC_wr, sendTlbReqToLLC" *) - (* descending_urgency = "sendMemLoaderReqToLLC_rd, sendTlbReqToLLC" *) rule sendTlbReqToLLC; let {c, r} <- toGet(tlbQ).get; let req = getTlbDmaReq(c, r); @@ -246,26 +402,6 @@ module mkLLCDmaConnect #( end endrule - // send Ld resp from LLC - rule sendLdRespToMemLoader(llc.respLd.first.id matches tagged MemLoader .id); - let resp = llc.respLd.first; - llc.respLd.deq; - let dword_in_line = f_dword_in_line.first; - f_dword_in_line.deq; - AXI4_Rd_Data #(Wd_Id, Wd_Data, Wd_User) - rd_data = AXI4_Rd_Data {rid: 0, // TODO: change uniformly to Fabric_Id - rdata: fn_axi4_data_from_line (resp.data, dword_in_line), - rresp: axi4_resp_okay, - rlast: True, - ruser: ?}; - axi4_slave_xactor.i_rd_data.enq (rd_data); - if (verbosity != 0) begin - $display ("[LLCDmaConnect sendLdRespToMemLoader]"); - $display (" ", fshow (resp)); - $display (" ", fshow (rd_data)); - end - endrule - rule sendLdRespToTlb(llc.respLd.first.id matches tagged Tlb .id); llc.respLd.deq; let resp = llc.respLd.first; @@ -279,23 +415,6 @@ module mkLLCDmaConnect #( end endrule - // send St resp from LLC - rule sendStRespToMemLoader(llc.respSt.first matches tagged MemLoader .id); - let resp = llc.respSt.first; - llc.respSt.deq; - AXI4_Wr_Resp #(Wd_Id, Wd_User) - wr_resp = AXI4_Wr_Resp {bid: 0, // TODO: change uniformly to Fabric_id - bresp: axi4_resp_okay, - buser: ?}; - axi4_slave_xactor.i_wr_resp.enq (wr_resp); - - if (verbosity != 0) begin - $display ("[LLCDmaConnect sendStRespToMemLoader]"); - $display (" ", fshow (resp)); - $display (" ", fshow (wr_resp)); - end - endrule - rule sendStRespToTlb(llc.respSt.first matches tagged Tlb .id); llc.respSt.deq; if(verbose) begin @@ -304,5 +423,8 @@ module mkLLCDmaConnect #( doAssert(False, "No TLB st"); endrule + // ================================================================ + // INTERFACE + return axi4_slave_xactor.axi_side; endmodule diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 5224c90..e96531a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -86,7 +86,6 @@ // RDY_renameDebug_renameErr_get O 1 const // RDY_setMEIP O 1 const // RDY_setSEIP O 1 const -// RDY_setDEIP O 1 const // RDY_hart0_run_halt_server_request_put O 1 reg // hart0_run_halt_server_response_get O 1 reg // RDY_hart0_run_halt_server_response_get O 1 reg @@ -119,7 +118,6 @@ // recvDoStats_x I 1 reg // setMEIP_v I 1 // setSEIP_v I 1 -// setDEIP_v I 1 // hart0_run_halt_server_request_put I 1 reg // hart0_gpr_mem_server_request_put I 70 reg // hart0_fpr_mem_server_request_put I 70 reg @@ -144,7 +142,6 @@ // EN_deadlock_checkStarted_get I 1 unused // EN_setMEIP I 1 // EN_setSEIP I 1 -// EN_setDEIP I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -362,10 +359,6 @@ module mkCore(CLK, EN_setSEIP, RDY_setSEIP, - setDEIP_v, - EN_setDEIP, - RDY_setDEIP, - hart0_run_halt_server_request_put, EN_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_request_put, @@ -633,11 +626,6 @@ module mkCore(CLK, input EN_setSEIP; output RDY_setSEIP; - // action method setDEIP - input setDEIP_v; - input EN_setDEIP; - output RDY_setDEIP; - // action method hart0_run_halt_server_request_put input hart0_run_halt_server_request_put; input EN_hart0_run_halt_server_request_put; @@ -757,7 +745,6 @@ module mkCore(CLK, RDY_recvDoStats, RDY_renameDebug_renameErr_get, RDY_sendDoStats, - RDY_setDEIP, RDY_setMEIP, RDY_setSEIP, RDY_tlbToMem_memReq_deq, @@ -1319,11 +1306,6 @@ module mkCore(CLK, reg csrInstOrInterruptInflight_rl; wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN; - // register csrf_debug_int_pend - reg csrf_debug_int_pend; - reg csrf_debug_int_pend$D_IN; - wire csrf_debug_int_pend$EN; - // register csrf_external_int_en_vec_0 reg csrf_external_int_en_vec_0; wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN; @@ -1502,7 +1484,7 @@ module mkCore(CLK, // register csrf_prv_reg reg [1 : 0] csrf_prv_reg; - wire [1 : 0] csrf_prv_reg$D_IN; + reg [1 : 0] csrf_prv_reg$D_IN; wire csrf_prv_reg$EN; // register csrf_rg_dcsr @@ -3965,7 +3947,6 @@ module mkCore(CLK, CAN_FIRE_recvDoStats, CAN_FIRE_renameDebug_renameErr_get, CAN_FIRE_sendDoStats, - CAN_FIRE_setDEIP, CAN_FIRE_setMEIP, CAN_FIRE_setSEIP, CAN_FIRE_tlbToMem_memReq_deq, @@ -4201,7 +4182,6 @@ module mkCore(CLK, WILL_FIRE_recvDoStats, WILL_FIRE_renameDebug_renameErr_get, WILL_FIRE_sendDoStats, - WILL_FIRE_setDEIP, WILL_FIRE_setMEIP, WILL_FIRE_setSEIP, WILL_FIRE_tlbToMem_memReq_deq, @@ -4279,6 +4259,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2; wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; + wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4340,6 +4322,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2, + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2, MUX_coreFix_memExe_lsq$getHit_1__SEL_1, @@ -4355,12 +4338,12 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, - MUX_csrf_debug_int_pend$write_1__SEL_1, - MUX_csrf_debug_int_pend$write_1__SEL_2, MUX_csrf_external_int_en_vec_0$write_1__SEL_1, MUX_csrf_external_int_en_vec_3$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_2, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fflags_reg$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_3, @@ -4398,8 +4381,9 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_3$write_1__SEL_1, MUX_csrf_prev_ie_vec_3$write_1__VAL_1, MUX_csrf_prv_reg$write_1__SEL_1, + MUX_csrf_prv_reg$write_1__SEL_2, + MUX_csrf_prv_reg$write_1__SEL_3, MUX_csrf_rg_dcsr$write_1__SEL_1, - MUX_csrf_rg_dcsr$write_1__SEL_3, MUX_csrf_rg_dpc$write_1__SEL_1, MUX_csrf_rg_dpc$write_1__SEL_3, MUX_csrf_rg_dscratch0$write_1__SEL_1, @@ -4443,7 +4427,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, MUX_started$write_1__SEL_1, - MUX_update_vm_info$write_1__SEL_2, MUX_v_f_to_TV_0$enq_1__SEL_1; // remaining internal signals @@ -4470,34 +4453,34 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287946, - curData__h190796, - data_out__h718266, - rVal1__h606894, - rVal1__h631060, - trap_val__h699161, - x__h195006; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, + addr__h287914, + curData__h190763, + data_out__h718171, + rVal1__h606861, + rVal1__h631001, + trap_val__h699101, + x__h194973; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217, - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218, - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219, - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220, - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205, - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206, - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207, - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208, - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209, - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210, - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221, - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222, - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223, - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224, - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225, - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226, - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215, - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216, + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217, + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218, + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219, + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220, + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205, + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206, + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207, + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208, + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209, + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210, + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221, + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222, + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223, + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224, + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225, + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226, + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215, + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641, @@ -4509,45 +4492,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86, - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87, - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88, - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89, - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119, - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120, - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49, - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50, - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117, - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118, - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47, - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48, - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121, - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122, - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51, - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52, - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123, - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124, - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53, - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54, - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82, - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83, - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84, - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85, - _theResult___fst_sfd__h343945, - _theResult___fst_sfd__h352668, - _theResult___fst_sfd__h361250, - _theResult___fst_sfd__h370434, - _theResult___fst_sfd__h379070, - _theResult___fst_sfd__h389644, - _theResult___fst_sfd__h398365, - _theResult___fst_sfd__h406947, - _theResult___fst_sfd__h416131, - _theResult___fst_sfd__h424767, - _theResult___fst_sfd__h435339, - _theResult___fst_sfd__h444060, - _theResult___fst_sfd__h452642, - _theResult___fst_sfd__h461826, - _theResult___fst_sfd__h470462; + reg [22 : 0] CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86, + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87, + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88, + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89, + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119, + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120, + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49, + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50, + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117, + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118, + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47, + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48, + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121, + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122, + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51, + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52, + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123, + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124, + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54, + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55, + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84, + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85, + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82, + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83, + _theResult___fst_sfd__h343912, + _theResult___fst_sfd__h352635, + _theResult___fst_sfd__h361217, + _theResult___fst_sfd__h370401, + _theResult___fst_sfd__h379037, + _theResult___fst_sfd__h389611, + _theResult___fst_sfd__h398332, + _theResult___fst_sfd__h406914, + _theResult___fst_sfd__h416098, + _theResult___fst_sfd__h424734, + _theResult___fst_sfd__h435306, + _theResult___fst_sfd__h444027, + _theResult___fst_sfd__h452609, + _theResult___fst_sfd__h461793, + _theResult___fst_sfd__h470429; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278, @@ -4556,8 +4539,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282, @@ -4571,28 +4554,28 @@ module mkCore(CLK, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296, CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1, - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912; + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211, - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212, - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213, - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214, - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183, - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184, - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185, - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186, - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187, - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188, - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160, - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161, - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189, - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190, - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191, - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192, - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143, - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211, + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212, + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213, + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214, + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183, + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184, + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185, + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186, + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187, + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188, + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160, + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161, + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191, + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192, + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189, + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190, + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143, + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570, @@ -4602,54 +4585,54 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800; - reg [7 : 0] CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75, - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76, - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80, - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81, - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104, - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105, - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34, - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35, - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102, - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103, - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32, - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33, - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110, - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111, - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40, - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41, - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115, - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116, - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45, - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46, - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69, - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70, - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67, - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68, + reg [7 : 0] CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75, + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76, + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80, + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81, + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104, + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105, + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34, + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35, + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102, + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103, + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32, + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33, + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110, + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111, + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40, + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41, + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115, + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116, + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45, + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46, + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69, + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70, + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67, + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343944, - _theResult___fst_exp__h352667, - _theResult___fst_exp__h361249, - _theResult___fst_exp__h370433, - _theResult___fst_exp__h379069, - _theResult___fst_exp__h389643, - _theResult___fst_exp__h398364, - _theResult___fst_exp__h406946, - _theResult___fst_exp__h416130, - _theResult___fst_exp__h424766, - _theResult___fst_exp__h435338, - _theResult___fst_exp__h444059, - _theResult___fst_exp__h452641, - _theResult___fst_exp__h461825, - _theResult___fst_exp__h470461; + _theResult___fst_exp__h343911, + _theResult___fst_exp__h352634, + _theResult___fst_exp__h361216, + _theResult___fst_exp__h370400, + _theResult___fst_exp__h379036, + _theResult___fst_exp__h389610, + _theResult___fst_exp__h398331, + _theResult___fst_exp__h406913, + _theResult___fst_exp__h416097, + _theResult___fst_exp__h424733, + _theResult___fst_exp__h435305, + _theResult___fst_exp__h444026, + _theResult___fst_exp__h452608, + _theResult___fst_exp__h461792, + _theResult___fst_exp__h470428; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271, - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180; - reg [3 : 0] CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234, + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176; + reg [3 : 0] CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273, @@ -4660,11 +4643,11 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2, CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052, - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181, - i__h698137, - i__h698297; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048, + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177, + i__h698077, + i__h698237; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277, @@ -4678,8 +4661,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714, - x__h283725, - x__h289495; + x__h283692, + x__h289463; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263, @@ -4711,51 +4694,51 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239, + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240, + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4794,31 +4777,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378, - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374, + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517, @@ -4827,29 +4810,29 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573; - wire [321 : 0] basicExec___d11914, basicExec___d12560; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569; + wire [321 : 0] basicExec___d11911, basicExec___d12557; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994; wire [68 : 0] execFpuSimple___d11053; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344, @@ -4871,156 +4854,156 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - _theResult___fst__h601247, - _theResult___snd__h601248, - a___1__h600966, - a___1__h601252, - a__h600825, + _theResult___fst__h601214, + _theResult___snd__h601215, + a___1__h600933, + a___1__h601219, + a__h600792, amoExec___d880, - b___1__h600967, - b___1__h601297, - b__h600826, - base__h700740, - base__h700943, - data___1__h472885, - data___1__h473693, - data__h473159, - fcsr_csr__read__h607196, - fflags_csr__read__h607171, - frm_csr__read__h607182, - mcause_csr__read__h608843, - mcounteren_csr__read__h608588, - medeleg_csr__read__h608188, - mideleg_csr__read__h608283, - mie_csr__read__h608414, - mip_csr__read__h609083, - mstatus_csr__read__h608040, - mtvec_csr__read__h608496, - n___1__h196409, - n__h192334, - n__read__h609187, - n__read__h609378, - n__read__h6636, - n__read__h710013, - next_pc__h709359, - q___1__h473758, - rVal1__h479638, - rVal2__h479639, - r___1__h473784, - res_data__h335746, - res_data__h335751, - res_data__h381448, - res_data__h381453, - res_data__h427143, - res_data__h427148, - resp_addr__h289850, + b___1__h600934, + b___1__h601264, + b__h600793, + base__h700680, + base__h700883, + data___1__h472852, + data___1__h473660, + data__h473126, + fcsr_csr__read__h607163, + fflags_csr__read__h607138, + frm_csr__read__h607149, + mcause_csr__read__h608803, + mcounteren_csr__read__h608548, + medeleg_csr__read__h608155, + mideleg_csr__read__h608250, + mie_csr__read__h608374, + mip_csr__read__h609036, + mstatus_csr__read__h608007, + mtvec_csr__read__h608456, + n___1__h196376, + n__h192301, + n__read__h609140, + n__read__h609331, + n__read__h6604, + n__read__h709918, + next_pc__h709264, + q___1__h473725, + rVal1__h479605, + rVal2__h479606, + r___1__h473751, + res_data__h335713, + res_data__h335718, + res_data__h381415, + res_data__h381420, + res_data__h427110, + res_data__h427115, + resp_addr__h289818, robdeqPort_0_deq_data_BITS_95_TO_32__q270, - satp_csr__read__h607897, - scause_csr__read__h607695, - scounteren_csr__read__h607557, - shiftData__h181173, - sie_csr__read__h607461, - sip_csr__read__h607834, - sstatus_csr__read__h607392, - stvec_csr__read__h607504, - upd__h4024, - upd__h5341, - upd__h6750, - upd__h710124, - v__h605779, - v__h630099, - vaddr__h181168, - x__h153484, - x__h157031, - x__h159845, - x__h161693, - x__h181082, - x__h181083, - x__h18203, - x__h20741, - x__h285170, - x__h287024, - x__h46110, - x__h479547, - x__h479548, - x__h479549, - x__h48646, - x__h614583, - x__h614584, - x__h636445, - x__h636446, - x__h692296, - x__h712792, - x_addr__h311953, - x_quotient__h473073, - x_reg_ifc__read__h607301, - x_remainder__h473074, - y__h712818, - y__h714209, - y_avValue__h180170, - y_avValue__h180776, - y_avValue__h476683, - y_avValue__h477291, - y_avValue__h477893, - y_avValue__h606684, - y_avValue__h612440, - y_avValue__h630852, - y_avValue__h634312, - y_avValue__h699008, - y_avValue__h700777, - y_avValue_snd_snd_snd_snd_snd__h712833, - y_avValue_snd_snd_snd_snd_snd__h714258, - y_avValue_snd_snd_snd_snd_snd__h714287; + satp_csr__read__h607864, + scause_csr__read__h607662, + scounteren_csr__read__h607524, + shiftData__h181140, + sie_csr__read__h607428, + sip_csr__read__h607801, + sstatus_csr__read__h607359, + stvec_csr__read__h607471, + upd__h3992, + upd__h5309, + upd__h6718, + upd__h710029, + v__h605746, + v__h630040, + vaddr__h181135, + x__h153450, + x__h156997, + x__h159811, + x__h161659, + x__h181049, + x__h181050, + x__h18170, + x__h20708, + x__h285138, + x__h286992, + x__h46077, + x__h479514, + x__h479515, + x__h479516, + x__h48613, + x__h614524, + x__h614525, + x__h636385, + x__h636386, + x__h692236, + x__h712697, + x_addr__h311921, + x_quotient__h473040, + x_reg_ifc__read__h607268, + x_remainder__h473041, + y__h712723, + y__h714114, + y_avValue__h180137, + y_avValue__h180743, + y_avValue__h476650, + y_avValue__h477258, + y_avValue__h477860, + y_avValue__h606651, + y_avValue__h612381, + y_avValue__h630793, + y_avValue__h634252, + y_avValue__h698948, + y_avValue__h700717, + y_avValue_snd_snd_snd_snd_snd__h712738, + y_avValue_snd_snd_snd_snd_snd__h714163, + y_avValue_snd_snd_snd_snd_snd__h714192; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879, - r1__read__h610355, - r1__read__h610759, - r1__read__h611289, - r1__read__h611294, - r1__read__h611313, - r1__read__h611566, - r1__read__h611732, - r1__read__h611850, - r1__read__h611855, - r1__read__h611874; - wire [61 : 0] r1__read__h610357, - r1__read__h610761, - r1__read__h611296, - r1__read__h611315, - r1__read__h611568, - r1__read__h611708, - r1__read__h611734, - r1__read__h611857, - r1__read__h611876; - wire [60 : 0] r1__read__h611570, - r1__read__h611710, - r1__read__h611736, - r1__read__h611878; - wire [59 : 0] r1__read__h610359, - r1__read__h610763, - r1__read__h611307, - r1__read__h611317, - r1__read__h611572, - r1__read__h611738, - r1__read__h611868, - r1__read__h611880; - wire [58 : 0] r1__read__h610361, - r1__read__h610765, - r1__read__h611319, - r1__read__h611574, - r1__read__h611740, - r1__read__h611882; + r1__read__h610308, + r1__read__h610712, + r1__read__h611242, + r1__read__h611247, + r1__read__h611266, + r1__read__h611519, + r1__read__h611685, + r1__read__h611796, + r1__read__h611801, + r1__read__h611820; + wire [61 : 0] r1__read__h610310, + r1__read__h610714, + r1__read__h611249, + r1__read__h611268, + r1__read__h611521, + r1__read__h611661, + r1__read__h611687, + r1__read__h611803, + r1__read__h611822; + wire [60 : 0] r1__read__h611523, + r1__read__h611663, + r1__read__h611689, + r1__read__h611824; + wire [59 : 0] r1__read__h610312, + r1__read__h610716, + r1__read__h611260, + r1__read__h611270, + r1__read__h611525, + r1__read__h611691, + r1__read__h611814, + r1__read__h611826; + wire [58 : 0] r1__read__h610314, + r1__read__h610718, + r1__read__h611272, + r1__read__h611527, + r1__read__h611693, + r1__read__h611828; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h610363, - r1__read__h610767, - r1__read__h611321, - r1__read__h611576, - r1__read__h611712, - r1__read__h611742, - r1__read__h611884, - y__h252683; + r1__read__h610316, + r1__read__h610720, + r1__read__h611274, + r1__read__h611529, + r1__read__h611665, + r1__read__h611695, + r1__read__h611830, + y__h252650; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5048,187 +5031,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338, - _theResult____h343962, - _theResult____h361601, - _theResult____h389661, - _theResult____h407298, - _theResult____h435356, - _theResult____h452993, - _theResult____h500746, - _theResult____h539599, - _theResult____h578903, - _theResult___snd__h352084, - _theResult___snd__h352095, - _theResult___snd__h352097, - _theResult___snd__h352107, - _theResult___snd__h352113, - _theResult___snd__h352136, - _theResult___snd__h360680, - _theResult___snd__h360682, - _theResult___snd__h360689, - _theResult___snd__h360695, - _theResult___snd__h360718, - _theResult___snd__h369850, - _theResult___snd__h369861, - _theResult___snd__h369863, - _theResult___snd__h369873, - _theResult___snd__h369879, - _theResult___snd__h369902, - _theResult___snd__h378470, - _theResult___snd__h378484, - _theResult___snd__h378490, - _theResult___snd__h378508, - _theResult___snd__h397781, - _theResult___snd__h397792, - _theResult___snd__h397794, - _theResult___snd__h397804, - _theResult___snd__h397810, - _theResult___snd__h397833, - _theResult___snd__h406377, - _theResult___snd__h406379, - _theResult___snd__h406386, - _theResult___snd__h406392, - _theResult___snd__h406415, - _theResult___snd__h415547, - _theResult___snd__h415558, - _theResult___snd__h415560, - _theResult___snd__h415570, - _theResult___snd__h415576, - _theResult___snd__h415599, - _theResult___snd__h424167, - _theResult___snd__h424181, - _theResult___snd__h424187, - _theResult___snd__h424205, - _theResult___snd__h443476, - _theResult___snd__h443487, - _theResult___snd__h443489, - _theResult___snd__h443499, - _theResult___snd__h443505, - _theResult___snd__h443528, - _theResult___snd__h452072, - _theResult___snd__h452074, - _theResult___snd__h452081, - _theResult___snd__h452087, - _theResult___snd__h452110, - _theResult___snd__h461242, - _theResult___snd__h461253, - _theResult___snd__h461255, - _theResult___snd__h461265, - _theResult___snd__h461271, - _theResult___snd__h461294, - _theResult___snd__h469862, - _theResult___snd__h469876, - _theResult___snd__h469882, - _theResult___snd__h469900, - _theResult___snd__h499356, - _theResult___snd__h499358, - _theResult___snd__h499365, - _theResult___snd__h499371, - _theResult___snd__h499394, - _theResult___snd__h508993, - _theResult___snd__h509004, - _theResult___snd__h509006, - _theResult___snd__h509016, - _theResult___snd__h509022, - _theResult___snd__h509045, - _theResult___snd__h517761, - _theResult___snd__h517775, - _theResult___snd__h517781, - _theResult___snd__h517799, - _theResult___snd__h538209, - _theResult___snd__h538211, - _theResult___snd__h538218, - _theResult___snd__h538224, - _theResult___snd__h538247, - _theResult___snd__h547846, - _theResult___snd__h547857, - _theResult___snd__h547859, - _theResult___snd__h547869, - _theResult___snd__h547875, - _theResult___snd__h547898, - _theResult___snd__h556614, - _theResult___snd__h556628, - _theResult___snd__h556634, - _theResult___snd__h556652, - _theResult___snd__h577513, - _theResult___snd__h577515, - _theResult___snd__h577522, - _theResult___snd__h577528, - _theResult___snd__h577551, - _theResult___snd__h587150, - _theResult___snd__h587161, - _theResult___snd__h587163, - _theResult___snd__h587173, - _theResult___snd__h587179, - _theResult___snd__h587202, - _theResult___snd__h595918, - _theResult___snd__h595932, - _theResult___snd__h595938, - _theResult___snd__h595956, - r1__read__h611578, - r1__read__h611714, - r1__read__h611744, - r1__read__h611886, - result__h362214, - result__h407911, - result__h453606, - result__h501359, - result__h540212, - result__h579516, - sfd__h336357, - sfd__h382059, - sfd__h427754, - sfd__h480379, - sfd__h519373, - sfd__h558677, - sfdin__h352067, - sfdin__h369833, - sfdin__h397764, - sfdin__h415530, - sfdin__h443459, - sfdin__h461225, - sfdin__h508976, - sfdin__h547829, - sfdin__h587133, - x__h362311, - x__h408008, - x__h453703, - x__h501454, - x__h540307, - x__h579611; - wire [55 : 0] r1__read__h610365, - r1__read__h610769, - r1__read__h611323, - r1__read__h611580, - r1__read__h611746, - r1__read__h611888; - wire [54 : 0] r1__read__h610367, - r1__read__h610771, - r1__read__h611325, - r1__read__h611582, - r1__read__h611748, - r1__read__h611890; - wire [53 : 0] r1__read__h611691, - r1__read__h611716, - r1__read__h611750, - r1__read__h611892, - sfd__h499423, - sfd__h509074, - sfd__h517834, - sfd__h538276, - sfd__h547927, - sfd__h556687, - sfd__h577580, - sfd__h587231, - sfd__h595991, - value__h344584, - value__h390281, - value__h435976; - wire [52 : 0] r1__read__h611584, - r1__read__h611693, - r1__read__h611718, - r1__read__h611752, - r1__read__h611894; + _theResult____h343929, + _theResult____h361568, + _theResult____h389628, + _theResult____h407265, + _theResult____h435323, + _theResult____h452960, + _theResult____h500713, + _theResult____h539566, + _theResult____h578870, + _theResult___snd__h352051, + _theResult___snd__h352062, + _theResult___snd__h352064, + _theResult___snd__h352074, + _theResult___snd__h352080, + _theResult___snd__h352103, + _theResult___snd__h360647, + _theResult___snd__h360649, + _theResult___snd__h360656, + _theResult___snd__h360662, + _theResult___snd__h360685, + _theResult___snd__h369817, + _theResult___snd__h369828, + _theResult___snd__h369830, + _theResult___snd__h369840, + _theResult___snd__h369846, + _theResult___snd__h369869, + _theResult___snd__h378437, + _theResult___snd__h378451, + _theResult___snd__h378457, + _theResult___snd__h378475, + _theResult___snd__h397748, + _theResult___snd__h397759, + _theResult___snd__h397761, + _theResult___snd__h397771, + _theResult___snd__h397777, + _theResult___snd__h397800, + _theResult___snd__h406344, + _theResult___snd__h406346, + _theResult___snd__h406353, + _theResult___snd__h406359, + _theResult___snd__h406382, + _theResult___snd__h415514, + _theResult___snd__h415525, + _theResult___snd__h415527, + _theResult___snd__h415537, + _theResult___snd__h415543, + _theResult___snd__h415566, + _theResult___snd__h424134, + _theResult___snd__h424148, + _theResult___snd__h424154, + _theResult___snd__h424172, + _theResult___snd__h443443, + _theResult___snd__h443454, + _theResult___snd__h443456, + _theResult___snd__h443466, + _theResult___snd__h443472, + _theResult___snd__h443495, + _theResult___snd__h452039, + _theResult___snd__h452041, + _theResult___snd__h452048, + _theResult___snd__h452054, + _theResult___snd__h452077, + _theResult___snd__h461209, + _theResult___snd__h461220, + _theResult___snd__h461222, + _theResult___snd__h461232, + _theResult___snd__h461238, + _theResult___snd__h461261, + _theResult___snd__h469829, + _theResult___snd__h469843, + _theResult___snd__h469849, + _theResult___snd__h469867, + _theResult___snd__h499323, + _theResult___snd__h499325, + _theResult___snd__h499332, + _theResult___snd__h499338, + _theResult___snd__h499361, + _theResult___snd__h508960, + _theResult___snd__h508971, + _theResult___snd__h508973, + _theResult___snd__h508983, + _theResult___snd__h508989, + _theResult___snd__h509012, + _theResult___snd__h517728, + _theResult___snd__h517742, + _theResult___snd__h517748, + _theResult___snd__h517766, + _theResult___snd__h538176, + _theResult___snd__h538178, + _theResult___snd__h538185, + _theResult___snd__h538191, + _theResult___snd__h538214, + _theResult___snd__h547813, + _theResult___snd__h547824, + _theResult___snd__h547826, + _theResult___snd__h547836, + _theResult___snd__h547842, + _theResult___snd__h547865, + _theResult___snd__h556581, + _theResult___snd__h556595, + _theResult___snd__h556601, + _theResult___snd__h556619, + _theResult___snd__h577480, + _theResult___snd__h577482, + _theResult___snd__h577489, + _theResult___snd__h577495, + _theResult___snd__h577518, + _theResult___snd__h587117, + _theResult___snd__h587128, + _theResult___snd__h587130, + _theResult___snd__h587140, + _theResult___snd__h587146, + _theResult___snd__h587169, + _theResult___snd__h595885, + _theResult___snd__h595899, + _theResult___snd__h595905, + _theResult___snd__h595923, + r1__read__h611531, + r1__read__h611667, + r1__read__h611697, + r1__read__h611832, + result__h362181, + result__h407878, + result__h453573, + result__h501326, + result__h540179, + result__h579483, + sfd__h336324, + sfd__h382026, + sfd__h427721, + sfd__h480346, + sfd__h519340, + sfd__h558644, + sfdin__h352034, + sfdin__h369800, + sfdin__h397731, + sfdin__h415497, + sfdin__h443426, + sfdin__h461192, + sfdin__h508943, + sfdin__h547796, + sfdin__h587100, + x__h362278, + x__h407975, + x__h453670, + x__h501421, + x__h540274, + x__h579578; + wire [55 : 0] r1__read__h610318, + r1__read__h610722, + r1__read__h611276, + r1__read__h611533, + r1__read__h611699, + r1__read__h611834; + wire [54 : 0] r1__read__h610320, + r1__read__h610724, + r1__read__h611278, + r1__read__h611535, + r1__read__h611701, + r1__read__h611836; + wire [53 : 0] r1__read__h611644, + r1__read__h611669, + r1__read__h611703, + r1__read__h611838, + sfd__h499390, + sfd__h509041, + sfd__h517801, + sfd__h538243, + sfd__h547894, + sfd__h556654, + sfd__h577547, + sfd__h587198, + sfd__h595958, + value__h344551, + value__h390248, + value__h435943; + wire [52 : 0] r1__read__h611537, + r1__read__h611646, + r1__read__h611671, + r1__read__h611705, + r1__read__h611840; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137, @@ -5250,110 +5233,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878, - _theResult___fst_sfd__h484333, - _theResult___fst_sfd__h500161, - _theResult___fst_sfd__h500164, - _theResult___fst_sfd__h509812, - _theResult___fst_sfd__h509815, - _theResult___fst_sfd__h518596, - _theResult___fst_sfd__h518599, - _theResult___fst_sfd__h518608, - _theResult___fst_sfd__h518614, - _theResult___fst_sfd__h523186, - _theResult___fst_sfd__h539014, - _theResult___fst_sfd__h539017, - _theResult___fst_sfd__h548665, - _theResult___fst_sfd__h548668, - _theResult___fst_sfd__h557449, - _theResult___fst_sfd__h557452, - _theResult___fst_sfd__h557461, - _theResult___fst_sfd__h557467, - _theResult___fst_sfd__h562490, - _theResult___fst_sfd__h578318, - _theResult___fst_sfd__h578321, - _theResult___fst_sfd__h587969, - _theResult___fst_sfd__h587972, - _theResult___fst_sfd__h596753, - _theResult___fst_sfd__h596756, - _theResult___fst_sfd__h596765, - _theResult___fst_sfd__h596771, - _theResult___sfd__h500061, - _theResult___sfd__h509712, - _theResult___sfd__h518496, - _theResult___sfd__h538914, - _theResult___sfd__h548565, - _theResult___sfd__h557349, - _theResult___sfd__h578218, - _theResult___sfd__h587869, - _theResult___sfd__h596653, - _theResult___snd_fst_sfd__h480333, - _theResult___snd_fst_sfd__h500167, - _theResult___snd_fst_sfd__h518602, - _theResult___snd_fst_sfd__h519327, - _theResult___snd_fst_sfd__h539020, - _theResult___snd_fst_sfd__h557455, - _theResult___snd_fst_sfd__h558631, - _theResult___snd_fst_sfd__h578324, - _theResult___snd_fst_sfd__h596759, - out___1_sfd__h480081, - out___1_sfd__h519075, - out___1_sfd__h558379, - out_sfd__h500064, - out_sfd__h509715, - out_sfd__h518499, - out_sfd__h538917, - out_sfd__h548568, - out_sfd__h557352, - out_sfd__h578221, - out_sfd__h587872, - out_sfd__h596656, - r1__read__h611896; - wire [50 : 0] r1__read__h610369, r1__read__h611586; - wire [49 : 0] r1__read__h611695, r1__read__h611898; - wire [48 : 0] r1__read__h610371, r1__read__h611588, r1__read__h611697; - wire [46 : 0] r1__read__h610373, r1__read__h611590; - wire [45 : 0] r1__read__h610375, r1__read__h611592; - wire [44 : 0] r1__read__h610377, r1__read__h611594; - wire [43 : 0] r1__read__h610379, r1__read__h611596; - wire [42 : 0] r1__read__h611598; - wire [41 : 0] r1__read__h611600; - wire [40 : 0] r1__read__h611602; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055, - IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184; + _theResult___fst_sfd__h484300, + _theResult___fst_sfd__h500128, + _theResult___fst_sfd__h500131, + _theResult___fst_sfd__h509779, + _theResult___fst_sfd__h509782, + _theResult___fst_sfd__h518563, + _theResult___fst_sfd__h518566, + _theResult___fst_sfd__h518575, + _theResult___fst_sfd__h518581, + _theResult___fst_sfd__h523153, + _theResult___fst_sfd__h538981, + _theResult___fst_sfd__h538984, + _theResult___fst_sfd__h548632, + _theResult___fst_sfd__h548635, + _theResult___fst_sfd__h557416, + _theResult___fst_sfd__h557419, + _theResult___fst_sfd__h557428, + _theResult___fst_sfd__h557434, + _theResult___fst_sfd__h562457, + _theResult___fst_sfd__h578285, + _theResult___fst_sfd__h578288, + _theResult___fst_sfd__h587936, + _theResult___fst_sfd__h587939, + _theResult___fst_sfd__h596720, + _theResult___fst_sfd__h596723, + _theResult___fst_sfd__h596732, + _theResult___fst_sfd__h596738, + _theResult___sfd__h500028, + _theResult___sfd__h509679, + _theResult___sfd__h518463, + _theResult___sfd__h538881, + _theResult___sfd__h548532, + _theResult___sfd__h557316, + _theResult___sfd__h578185, + _theResult___sfd__h587836, + _theResult___sfd__h596620, + _theResult___snd_fst_sfd__h480300, + _theResult___snd_fst_sfd__h500134, + _theResult___snd_fst_sfd__h518569, + _theResult___snd_fst_sfd__h519294, + _theResult___snd_fst_sfd__h538987, + _theResult___snd_fst_sfd__h557422, + _theResult___snd_fst_sfd__h558598, + _theResult___snd_fst_sfd__h578291, + _theResult___snd_fst_sfd__h596726, + out___1_sfd__h480048, + out___1_sfd__h519042, + out___1_sfd__h558346, + out_sfd__h500031, + out_sfd__h509682, + out_sfd__h518466, + out_sfd__h538884, + out_sfd__h548535, + out_sfd__h557319, + out_sfd__h578188, + out_sfd__h587839, + out_sfd__h596623; + wire [50 : 0] r1__read__h610322, r1__read__h611539; + wire [49 : 0] r1__read__h611648; + wire [48 : 0] r1__read__h610324, r1__read__h611541, r1__read__h611650; + wire [46 : 0] r1__read__h610326, r1__read__h611543; + wire [45 : 0] r1__read__h610328, r1__read__h611545; + wire [44 : 0] r1__read__h610330, r1__read__h611547; + wire [43 : 0] r1__read__h610332, r1__read__h611549; + wire [42 : 0] r1__read__h611551; + wire [41 : 0] r1__read__h611553; + wire [40 : 0] r1__read__h611555; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051, + IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12, - data73159_BITS_31_TO_0__q13, - imm__h651966, - r1__read__h610381, - r1__read__h611604, - x__h191559, - x__h335761, - x__h381463, - x__h427158, - x__h76055, - x_data__h65904, - x_data_imm__h671111, - x_data_imm__h686042; - wire [29 : 0] r1__read__h610383, r1__read__h611606; - wire [27 : 0] r1__read__h611608; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087, - sfd__h352165, - sfd__h360747, - sfd__h369931, - sfd__h378543, - sfd__h397862, - sfd__h406444, - sfd__h415628, - sfd__h424240, - sfd__h443557, - sfd__h452139, - sfd__h461323, - sfd__h469935, - value__h484962, - value__h523815, - value__h563119; + data73126_BITS_31_TO_0__q13, + imm__h651906, + r1__read__h610334, + r1__read__h611557, + x__h191526, + x__h335728, + x__h381430, + x__h427125, + x__h76022, + x_data__h65871, + x_data_imm__h671051, + x_data_imm__h685982; + wire [29 : 0] r1__read__h610336, r1__read__h611559; + wire [27 : 0] r1__read__h611561; + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083, + sfd__h352132, + sfd__h360714, + sfd__h369898, + sfd__h378510, + sfd__h397829, + sfd__h406411, + sfd__h415595, + sfd__h424207, + sfd__h443524, + sfd__h452106, + sfd__h461290, + sfd__h469902, + value__h484929, + value__h523782, + value__h563086; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -5378,80 +5360,80 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352671, - _theResult___fst_sfd__h361253, - _theResult___fst_sfd__h370437, - _theResult___fst_sfd__h379073, - _theResult___fst_sfd__h379082, - _theResult___fst_sfd__h379088, - _theResult___fst_sfd__h398368, - _theResult___fst_sfd__h406950, - _theResult___fst_sfd__h416134, - _theResult___fst_sfd__h424770, - _theResult___fst_sfd__h424779, - _theResult___fst_sfd__h424785, - _theResult___fst_sfd__h444063, - _theResult___fst_sfd__h452645, - _theResult___fst_sfd__h461829, - _theResult___fst_sfd__h470465, - _theResult___fst_sfd__h470474, - _theResult___fst_sfd__h470480, - _theResult___sfd__h352590, - _theResult___sfd__h361172, - _theResult___sfd__h370356, - _theResult___sfd__h378992, - _theResult___sfd__h379094, - _theResult___sfd__h398287, - _theResult___sfd__h406869, - _theResult___sfd__h416053, - _theResult___sfd__h424689, - _theResult___sfd__h424791, - _theResult___sfd__h443982, - _theResult___sfd__h452564, - _theResult___sfd__h461748, - _theResult___sfd__h470384, - _theResult___sfd__h470486, - _theResult___snd_fst_sfd__h336307, - _theResult___snd_fst_sfd__h361256, - _theResult___snd_fst_sfd__h379076, - _theResult___snd_fst_sfd__h382009, - _theResult___snd_fst_sfd__h406953, - _theResult___snd_fst_sfd__h424773, - _theResult___snd_fst_sfd__h427704, - _theResult___snd_fst_sfd__h452648, - _theResult___snd_fst_sfd__h470468, - f1_sfd__h480018, - f2_sfd__h519012, - f3_sfd__h558316, - out_f_sfd__h379371, - out_f_sfd__h425068, - out_f_sfd__h470763, - out_sfd__h352593, - out_sfd__h361175, - out_sfd__h370359, - out_sfd__h378995, - out_sfd__h398290, - out_sfd__h406872, - out_sfd__h416056, - out_sfd__h424692, - out_sfd__h443985, - out_sfd__h452567, - out_sfd__h461751, - out_sfd__h470387; - wire [19 : 0] r1__read__h611543; - wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771, - _theResult____h647786, - enabled_ints___1__h648311, - enabled_ints__h648358, - pend_ints__h647784, - y__h648323; - wire [13 : 0] r1__read_BITS_13_TO_0___h648334; - wire [12 : 0] fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598; + _theResult___fst_sfd__h352638, + _theResult___fst_sfd__h361220, + _theResult___fst_sfd__h370404, + _theResult___fst_sfd__h379040, + _theResult___fst_sfd__h379049, + _theResult___fst_sfd__h379055, + _theResult___fst_sfd__h398335, + _theResult___fst_sfd__h406917, + _theResult___fst_sfd__h416101, + _theResult___fst_sfd__h424737, + _theResult___fst_sfd__h424746, + _theResult___fst_sfd__h424752, + _theResult___fst_sfd__h444030, + _theResult___fst_sfd__h452612, + _theResult___fst_sfd__h461796, + _theResult___fst_sfd__h470432, + _theResult___fst_sfd__h470441, + _theResult___fst_sfd__h470447, + _theResult___sfd__h352557, + _theResult___sfd__h361139, + _theResult___sfd__h370323, + _theResult___sfd__h378959, + _theResult___sfd__h379061, + _theResult___sfd__h398254, + _theResult___sfd__h406836, + _theResult___sfd__h416020, + _theResult___sfd__h424656, + _theResult___sfd__h424758, + _theResult___sfd__h443949, + _theResult___sfd__h452531, + _theResult___sfd__h461715, + _theResult___sfd__h470351, + _theResult___sfd__h470453, + _theResult___snd_fst_sfd__h336274, + _theResult___snd_fst_sfd__h361223, + _theResult___snd_fst_sfd__h379043, + _theResult___snd_fst_sfd__h381976, + _theResult___snd_fst_sfd__h406920, + _theResult___snd_fst_sfd__h424740, + _theResult___snd_fst_sfd__h427671, + _theResult___snd_fst_sfd__h452615, + _theResult___snd_fst_sfd__h470435, + f1_sfd__h479985, + f2_sfd__h518979, + f3_sfd__h558283, + out_f_sfd__h379338, + out_f_sfd__h425035, + out_f_sfd__h470730, + out_sfd__h352560, + out_sfd__h361142, + out_sfd__h370326, + out_sfd__h378962, + out_sfd__h398257, + out_sfd__h406839, + out_sfd__h416023, + out_sfd__h424659, + out_sfd__h443952, + out_sfd__h452534, + out_sfd__h461718, + out_sfd__h470354; + wire [19 : 0] r1__read__h611496; + wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767, + _theResult____h647726, + enabled_ints___1__h648251, + enabled_ints__h648298, + pend_ints__h647724, + y__h648263; + wire [13 : 0] r1__read_BITS_13_TO_0___h648274; + wire [12 : 0] fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658, - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641, - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973, + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638, + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358, @@ -5464,7 +5446,7 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107, - _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744, + _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791, @@ -5477,24 +5459,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h678634, - result__h643363, - result__h643414, - spec_bits__h681761, - w__h643358, - x__h362344, - x__h408041, - x__h453736, - x__h501487, - x__h540340, - x__h579644, - x__h643362, - x__h643413, - y__h643392, - y__h681774, - y_avValue_fst__h675034, - y_avValue_fst__h675063, - y_avValue_fst__h675097; + renaming_spec_bits__h678574, + result__h643303, + result__h643354, + spec_bits__h681701, + w__h643298, + x__h362311, + x__h408008, + x__h453703, + x__h501454, + x__h540307, + x__h579611, + x__h643302, + x__h643353, + y__h643332, + y__h681714, + y_avValue_fst__h674974, + y_avValue_fst__h675003, + y_avValue_fst__h675037; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053, @@ -5516,102 +5498,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h500060, - _theResult___exp__h509711, - _theResult___exp__h518495, - _theResult___exp__h538913, - _theResult___exp__h548564, - _theResult___exp__h557348, - _theResult___exp__h578217, - _theResult___exp__h587868, - _theResult___exp__h596652, - _theResult___fst_exp__h484332, - _theResult___fst_exp__h499396, - _theResult___fst_exp__h499402, - _theResult___fst_exp__h499405, - _theResult___fst_exp__h500160, - _theResult___fst_exp__h500163, - _theResult___fst_exp__h508982, - _theResult___fst_exp__h509047, - _theResult___fst_exp__h509053, - _theResult___fst_exp__h509056, - _theResult___fst_exp__h509811, - _theResult___fst_exp__h509814, - _theResult___fst_exp__h517767, - _theResult___fst_exp__h517806, - _theResult___fst_exp__h517812, - _theResult___fst_exp__h517815, - _theResult___fst_exp__h518595, - _theResult___fst_exp__h518598, - _theResult___fst_exp__h518607, - _theResult___fst_exp__h518610, - _theResult___fst_exp__h523185, - _theResult___fst_exp__h538249, - _theResult___fst_exp__h538255, - _theResult___fst_exp__h538258, - _theResult___fst_exp__h539013, - _theResult___fst_exp__h539016, - _theResult___fst_exp__h547835, - _theResult___fst_exp__h547900, - _theResult___fst_exp__h547906, - _theResult___fst_exp__h547909, - _theResult___fst_exp__h548664, - _theResult___fst_exp__h548667, - _theResult___fst_exp__h556620, - _theResult___fst_exp__h556659, - _theResult___fst_exp__h556665, - _theResult___fst_exp__h556668, - _theResult___fst_exp__h557448, - _theResult___fst_exp__h557451, - _theResult___fst_exp__h557460, - _theResult___fst_exp__h557463, - _theResult___fst_exp__h562489, - _theResult___fst_exp__h577553, - _theResult___fst_exp__h577559, - _theResult___fst_exp__h577562, - _theResult___fst_exp__h578317, - _theResult___fst_exp__h578320, - _theResult___fst_exp__h587139, - _theResult___fst_exp__h587204, - _theResult___fst_exp__h587210, - _theResult___fst_exp__h587213, - _theResult___fst_exp__h587968, - _theResult___fst_exp__h587971, - _theResult___fst_exp__h595924, - _theResult___fst_exp__h595963, - _theResult___fst_exp__h595969, - _theResult___fst_exp__h595972, - _theResult___fst_exp__h596752, - _theResult___fst_exp__h596755, - _theResult___fst_exp__h596764, - _theResult___fst_exp__h596767, - _theResult___snd_fst_exp__h500166, - _theResult___snd_fst_exp__h518601, - _theResult___snd_fst_exp__h539019, - _theResult___snd_fst_exp__h557454, - _theResult___snd_fst_exp__h578323, - _theResult___snd_fst_exp__h596758, + _theResult___exp__h500027, + _theResult___exp__h509678, + _theResult___exp__h518462, + _theResult___exp__h538880, + _theResult___exp__h548531, + _theResult___exp__h557315, + _theResult___exp__h578184, + _theResult___exp__h587835, + _theResult___exp__h596619, + _theResult___fst_exp__h484299, + _theResult___fst_exp__h499363, + _theResult___fst_exp__h499369, + _theResult___fst_exp__h499372, + _theResult___fst_exp__h500127, + _theResult___fst_exp__h500130, + _theResult___fst_exp__h508949, + _theResult___fst_exp__h509014, + _theResult___fst_exp__h509020, + _theResult___fst_exp__h509023, + _theResult___fst_exp__h509778, + _theResult___fst_exp__h509781, + _theResult___fst_exp__h517734, + _theResult___fst_exp__h517773, + _theResult___fst_exp__h517779, + _theResult___fst_exp__h517782, + _theResult___fst_exp__h518562, + _theResult___fst_exp__h518565, + _theResult___fst_exp__h518574, + _theResult___fst_exp__h518577, + _theResult___fst_exp__h523152, + _theResult___fst_exp__h538216, + _theResult___fst_exp__h538222, + _theResult___fst_exp__h538225, + _theResult___fst_exp__h538980, + _theResult___fst_exp__h538983, + _theResult___fst_exp__h547802, + _theResult___fst_exp__h547867, + _theResult___fst_exp__h547873, + _theResult___fst_exp__h547876, + _theResult___fst_exp__h548631, + _theResult___fst_exp__h548634, + _theResult___fst_exp__h556587, + _theResult___fst_exp__h556626, + _theResult___fst_exp__h556632, + _theResult___fst_exp__h556635, + _theResult___fst_exp__h557415, + _theResult___fst_exp__h557418, + _theResult___fst_exp__h557427, + _theResult___fst_exp__h557430, + _theResult___fst_exp__h562456, + _theResult___fst_exp__h577520, + _theResult___fst_exp__h577526, + _theResult___fst_exp__h577529, + _theResult___fst_exp__h578284, + _theResult___fst_exp__h578287, + _theResult___fst_exp__h587106, + _theResult___fst_exp__h587171, + _theResult___fst_exp__h587177, + _theResult___fst_exp__h587180, + _theResult___fst_exp__h587935, + _theResult___fst_exp__h587938, + _theResult___fst_exp__h595891, + _theResult___fst_exp__h595930, + _theResult___fst_exp__h595936, + _theResult___fst_exp__h595939, + _theResult___fst_exp__h596719, + _theResult___fst_exp__h596722, + _theResult___fst_exp__h596731, + _theResult___fst_exp__h596734, + _theResult___snd_fst_exp__h500133, + _theResult___snd_fst_exp__h518568, + _theResult___snd_fst_exp__h538986, + _theResult___snd_fst_exp__h557421, + _theResult___snd_fst_exp__h578290, + _theResult___snd_fst_exp__h596725, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h518655, - din_inc___2_exp__h518690, - din_inc___2_exp__h518716, - din_inc___2_exp__h557508, - din_inc___2_exp__h557543, - din_inc___2_exp__h557569, - din_inc___2_exp__h596812, - din_inc___2_exp__h596847, - din_inc___2_exp__h596873, - out_exp__h500063, - out_exp__h509714, - out_exp__h518498, - out_exp__h538916, - out_exp__h548567, - out_exp__h557351, - out_exp__h578220, - out_exp__h587871, - out_exp__h596655; + din_inc___2_exp__h518622, + din_inc___2_exp__h518657, + din_inc___2_exp__h518683, + din_inc___2_exp__h557475, + din_inc___2_exp__h557510, + din_inc___2_exp__h557536, + din_inc___2_exp__h596779, + din_inc___2_exp__h596814, + din_inc___2_exp__h596840, + out_exp__h500030, + out_exp__h509681, + out_exp__h518465, + out_exp__h538883, + out_exp__h548534, + out_exp__h557318, + out_exp__h578187, + out_exp__h587838, + out_exp__h596622; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5642,125 +5624,125 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739, - _theResult___exp__h352589, - _theResult___exp__h361171, - _theResult___exp__h370355, - _theResult___exp__h378991, - _theResult___exp__h379093, - _theResult___exp__h398286, - _theResult___exp__h406868, - _theResult___exp__h416052, - _theResult___exp__h424688, - _theResult___exp__h424790, - _theResult___exp__h443981, - _theResult___exp__h452563, - _theResult___exp__h461747, - _theResult___exp__h470383, - _theResult___exp__h470485, - _theResult___fst_exp__h352073, - _theResult___fst_exp__h352138, - _theResult___fst_exp__h352144, - _theResult___fst_exp__h352147, - _theResult___fst_exp__h352670, - _theResult___fst_exp__h360720, - _theResult___fst_exp__h360726, - _theResult___fst_exp__h360729, - _theResult___fst_exp__h361252, - _theResult___fst_exp__h369839, - _theResult___fst_exp__h369904, - _theResult___fst_exp__h369910, - _theResult___fst_exp__h369913, - _theResult___fst_exp__h370436, - _theResult___fst_exp__h378476, - _theResult___fst_exp__h378515, - _theResult___fst_exp__h378521, - _theResult___fst_exp__h378524, - _theResult___fst_exp__h379072, - _theResult___fst_exp__h379081, - _theResult___fst_exp__h379084, - _theResult___fst_exp__h397770, - _theResult___fst_exp__h397835, - _theResult___fst_exp__h397841, - _theResult___fst_exp__h397844, - _theResult___fst_exp__h398367, - _theResult___fst_exp__h406417, - _theResult___fst_exp__h406423, - _theResult___fst_exp__h406426, - _theResult___fst_exp__h406949, - _theResult___fst_exp__h415536, - _theResult___fst_exp__h415601, - _theResult___fst_exp__h415607, - _theResult___fst_exp__h415610, - _theResult___fst_exp__h416133, - _theResult___fst_exp__h424173, - _theResult___fst_exp__h424212, - _theResult___fst_exp__h424218, - _theResult___fst_exp__h424221, - _theResult___fst_exp__h424769, - _theResult___fst_exp__h424778, - _theResult___fst_exp__h424781, - _theResult___fst_exp__h443465, - _theResult___fst_exp__h443530, - _theResult___fst_exp__h443536, - _theResult___fst_exp__h443539, - _theResult___fst_exp__h444062, - _theResult___fst_exp__h452112, - _theResult___fst_exp__h452118, - _theResult___fst_exp__h452121, - _theResult___fst_exp__h452644, - _theResult___fst_exp__h461231, - _theResult___fst_exp__h461296, - _theResult___fst_exp__h461302, - _theResult___fst_exp__h461305, - _theResult___fst_exp__h461828, - _theResult___fst_exp__h469868, - _theResult___fst_exp__h469907, - _theResult___fst_exp__h469913, - _theResult___fst_exp__h469916, - _theResult___fst_exp__h470464, - _theResult___fst_exp__h470473, - _theResult___fst_exp__h470476, - _theResult___snd_fst_exp__h361255, - _theResult___snd_fst_exp__h379075, - _theResult___snd_fst_exp__h406952, - _theResult___snd_fst_exp__h424772, - _theResult___snd_fst_exp__h452647, - _theResult___snd_fst_exp__h470467, - din_inc___2_exp__h379106, - din_inc___2_exp__h379130, - din_inc___2_exp__h379160, - din_inc___2_exp__h379184, - din_inc___2_exp__h424803, - din_inc___2_exp__h424827, - din_inc___2_exp__h424857, - din_inc___2_exp__h424881, - din_inc___2_exp__h470498, - din_inc___2_exp__h470522, - din_inc___2_exp__h470552, - din_inc___2_exp__h470576, - f1_exp80017_MINUS_127__q136, - f1_exp__h480017, - f2_exp19011_MINUS_127__q176, - f2_exp__h519011, - f3_exp58315_MINUS_127__q153, - f3_exp__h558315, - out_exp__h352592, - out_exp__h361174, - out_exp__h370358, - out_exp__h378994, - out_exp__h398289, - out_exp__h406871, - out_exp__h416055, - out_exp__h424691, - out_exp__h443984, - out_exp__h452566, - out_exp__h461750, - out_exp__h470386, - out_f_exp__h379370, - out_f_exp__h425067, - out_f_exp__h470762, - x__h610340; + _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735, + _theResult___exp__h352556, + _theResult___exp__h361138, + _theResult___exp__h370322, + _theResult___exp__h378958, + _theResult___exp__h379060, + _theResult___exp__h398253, + _theResult___exp__h406835, + _theResult___exp__h416019, + _theResult___exp__h424655, + _theResult___exp__h424757, + _theResult___exp__h443948, + _theResult___exp__h452530, + _theResult___exp__h461714, + _theResult___exp__h470350, + _theResult___exp__h470452, + _theResult___fst_exp__h352040, + _theResult___fst_exp__h352105, + _theResult___fst_exp__h352111, + _theResult___fst_exp__h352114, + _theResult___fst_exp__h352637, + _theResult___fst_exp__h360687, + _theResult___fst_exp__h360693, + _theResult___fst_exp__h360696, + _theResult___fst_exp__h361219, + _theResult___fst_exp__h369806, + _theResult___fst_exp__h369871, + _theResult___fst_exp__h369877, + _theResult___fst_exp__h369880, + _theResult___fst_exp__h370403, + _theResult___fst_exp__h378443, + _theResult___fst_exp__h378482, + _theResult___fst_exp__h378488, + _theResult___fst_exp__h378491, + _theResult___fst_exp__h379039, + _theResult___fst_exp__h379048, + _theResult___fst_exp__h379051, + _theResult___fst_exp__h397737, + _theResult___fst_exp__h397802, + _theResult___fst_exp__h397808, + _theResult___fst_exp__h397811, + _theResult___fst_exp__h398334, + _theResult___fst_exp__h406384, + _theResult___fst_exp__h406390, + _theResult___fst_exp__h406393, + _theResult___fst_exp__h406916, + _theResult___fst_exp__h415503, + _theResult___fst_exp__h415568, + _theResult___fst_exp__h415574, + _theResult___fst_exp__h415577, + _theResult___fst_exp__h416100, + _theResult___fst_exp__h424140, + _theResult___fst_exp__h424179, + _theResult___fst_exp__h424185, + _theResult___fst_exp__h424188, + _theResult___fst_exp__h424736, + _theResult___fst_exp__h424745, + _theResult___fst_exp__h424748, + _theResult___fst_exp__h443432, + _theResult___fst_exp__h443497, + _theResult___fst_exp__h443503, + _theResult___fst_exp__h443506, + _theResult___fst_exp__h444029, + _theResult___fst_exp__h452079, + _theResult___fst_exp__h452085, + _theResult___fst_exp__h452088, + _theResult___fst_exp__h452611, + _theResult___fst_exp__h461198, + _theResult___fst_exp__h461263, + _theResult___fst_exp__h461269, + _theResult___fst_exp__h461272, + _theResult___fst_exp__h461795, + _theResult___fst_exp__h469835, + _theResult___fst_exp__h469874, + _theResult___fst_exp__h469880, + _theResult___fst_exp__h469883, + _theResult___fst_exp__h470431, + _theResult___fst_exp__h470440, + _theResult___fst_exp__h470443, + _theResult___snd_fst_exp__h361222, + _theResult___snd_fst_exp__h379042, + _theResult___snd_fst_exp__h406919, + _theResult___snd_fst_exp__h424739, + _theResult___snd_fst_exp__h452614, + _theResult___snd_fst_exp__h470434, + din_inc___2_exp__h379073, + din_inc___2_exp__h379097, + din_inc___2_exp__h379127, + din_inc___2_exp__h379151, + din_inc___2_exp__h424770, + din_inc___2_exp__h424794, + din_inc___2_exp__h424824, + din_inc___2_exp__h424848, + din_inc___2_exp__h470465, + din_inc___2_exp__h470489, + din_inc___2_exp__h470519, + din_inc___2_exp__h470543, + f1_exp79984_MINUS_127__q136, + f1_exp__h479984, + f2_exp18978_MINUS_127__q176, + f2_exp__h518978, + f3_exp58282_MINUS_127__q153, + f3_exp__h558282, + out_exp__h352559, + out_exp__h361141, + out_exp__h370325, + out_exp__h378961, + out_exp__h398256, + out_exp__h406838, + out_exp__h416022, + out_exp__h424658, + out_exp__h443951, + out_exp__h452533, + out_exp__h461717, + out_exp__h470353, + out_f_exp__h379337, + out_f_exp__h425034, + out_f_exp__h470729, + x__h610293; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027, @@ -5780,11 +5762,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608, - x__h181305, - x__h700755; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225, - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604, + x__h181272, + x__h700695; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221, + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949, @@ -5800,116 +5782,116 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961, - checkForException___d12946, - checkForException___d13619, - fflags__h714186, - res_fflags__h335747, - res_fflags__h381449, - res_fflags__h427144, - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306, - rs1__h651965, - x__h153478, - x__h157025, - x__h159841, - x__h285158, - y_avValue_fst__h712379, - y_avValue_fst__h714101, - y_avValue_fst__h714129; + checkForException___d12942, + checkForException___d13615, + fflags__h714091, + res_fflags__h335714, + res_fflags__h381416, + res_fflags__h427111, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302, + rs1__h651905, + x__h153444, + x__h156991, + x__h159807, + x__h285126, + y_avValue_fst__h712284, + y_avValue_fst__h714006, + y_avValue_fst__h714034; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146, - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142, + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175, IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791, - IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219, - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095, + IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215, + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h698122, - vm_mode_reg__read__h611549; + cause_code__h698062, + vm_mode_reg__read__h611502; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h294400, - dcsr_cause__h697642, - next_deqP___1__h294679, - v__h293820, - v__h294051, - x__h300030, - x_decodeInfo_frm__h651649; + _theResult_____2__h294368, + dcsr_cause__h697582, + next_deqP___1__h294647, + v__h293788, + v__h294019, + x__h299998, + x_decodeInfo_frm__h651589; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206, - IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159, - IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135, - guard__h343972, - guard__h352681, - guard__h361611, - guard__h370447, - guard__h389671, - guard__h398378, - guard__h407308, - guard__h416144, - guard__h435366, - guard__h444073, - guard__h453003, - guard__h461839, - guard__h491444, - guard__h500756, - guard__h509825, - guard__h530297, - guard__h539609, - guard__h548678, - guard__h569601, - guard__h578913, - guard__h587982, - prv__h715821, - prv__h715865, - r1__read_BITS_13_TO_12___h651834, - sbIdx__h156904, - v__h601760, - v__h601770, - v__h602405, - x__h709419, - x__h714428, - y_avValue_snd_snd_snd_fst__h712827, - y_avValue_snd_snd_snd_fst__h714252, - y_avValue_snd_snd_snd_fst__h714281; + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201, + IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159, + IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135, + guard__h343939, + guard__h352648, + guard__h361578, + guard__h370414, + guard__h389638, + guard__h398345, + guard__h407275, + guard__h416111, + guard__h435333, + guard__h444040, + guard__h452970, + guard__h461806, + guard__h491411, + guard__h500723, + guard__h509792, + guard__h530264, + guard__h539576, + guard__h548645, + guard__h569568, + guard__h578880, + guard__h587949, + prv__h715726, + prv__h715770, + r1__read_BITS_13_TO_12___h651774, + sbIdx__h156870, + v__h601727, + v__h601737, + v__h602372, + x__h709324, + x__h714333, + y_avValue_snd_snd_snd_fst__h712732, + y_avValue_snd_snd_snd_fst__h714157, + y_avValue_snd_snd_snd_fst__h714186; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5928,9 +5910,9 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704, @@ -5956,12 +5938,12 @@ module mkCore(CLK, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11367, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11368, @@ -5985,11 +5967,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099, - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829, - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837, - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752, - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836, - IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197, + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825, + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833, + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748, + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832, + IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897, @@ -6019,8 +6001,8 @@ module mkCore(CLK, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11342, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376, IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214, @@ -6101,28 +6083,28 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554, - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365, - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754, - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005, + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361, + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750, + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198, + IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646, - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642, + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804, @@ -6136,13 +6118,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570, - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566, + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217, NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358, NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230, @@ -6193,37 +6175,37 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585, NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644, - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018, - NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407, - NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124, - NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640, + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014, + NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403, + NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120, + NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6239,21 +6221,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103, - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817, - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935, - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177, - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688, - NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932, - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928, - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099, + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813, + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930, + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172, + NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684, + NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927, + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924, + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644, @@ -6287,11 +6269,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653, - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849, - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750, - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573, + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845, + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746, + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180, @@ -6319,7 +6301,8 @@ module mkCore(CLK, _dfoo2, _dfoo20, _dfoo24, - _dfoo30, + _dfoo26, + _dfoo32, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6345,22 +6328,22 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h302396, - _theResult_____2__h308390, - _theResult_____2__h316244, - _theResult_____2__h326588, - _theResult_____2__h329813, - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533, - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534, - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168, - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207, - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181, - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213, - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189, - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217, - coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230, - coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623, - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374, + _theResult_____2__h302364, + _theResult_____2__h308358, + _theResult_____2__h316212, + _theResult_____2__h326556, + _theResult_____2__h329781, + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529, + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530, + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165, + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204, + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178, + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210, + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186, + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214, + coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227, + coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620, + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370, coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334, coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373, coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347, @@ -6368,7 +6351,7 @@ module mkCore(CLK, coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355, coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383, coreFix_aluExe_1_dispToRegQ_first__1311_BIT_13_ETC___d11396, - coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978, + coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268, @@ -6389,7 +6372,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944, coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570, coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608, coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583, @@ -6451,109 +6434,110 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712, - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593, - csrf_prv_reg_read__2730_ULE_1___d14571, - csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978, - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815, - f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408, - fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095, - fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215, - fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935, - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439, - fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756, - fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894, - fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906, - guard__h362209, - guard__h407906, - guard__h453601, - guard__h501354, - guard__h540207, - guard__h579511, - idx__h678765, - k__h664143, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708, + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589, + csrf_prv_reg_read__2727_ULE_1___d14567, + csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974, + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811, + f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403, + fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091, + fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211, + fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931, + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435, + fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752, + fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890, + fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902, + guard__h362176, + guard__h407873, + guard__h453568, + guard__h501321, + guard__h540174, + guard__h579478, + idx__h678705, + k__h664083, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153, mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h75940, - next_deqP___1__h302675, - next_deqP___1__h308956, - next_deqP___1__h316810, - next_deqP___1__h326867, - next_deqP___1__h330092, - r1__read_BIT_20___h652494, - r__h610387, - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862, - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841, - rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252, - rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693, - rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243, + msip__h75907, + next_deqP___1__h302643, + next_deqP___1__h308924, + next_deqP___1__h316778, + next_deqP___1__h326835, + next_deqP___1__h330060, + r1__read_BIT_20___h652434, + r__h610340, + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858, + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837, + rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247, + rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689, + rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h297165, - v__h297683, - v__h307679, - v__h307910, - v__h311555, - v__h311786, - v__h326156, - v__h326387, - v__h329381, - v__h329612, - x__h601261; + v__h297133, + v__h297651, + v__h307647, + v__h307878, + v__h311523, + v__h311754, + v__h326124, + v__h326355, + v__h329349, + v__h329580, + value_BIT_52___h399003, + x__h601228; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6594,7 +6578,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6614,7 +6598,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6846,11 +6830,6 @@ module mkCore(CLK, assign CAN_FIRE_setSEIP = 1'd1 ; assign WILL_FIRE_setSEIP = EN_setSEIP ; - // action method setDEIP - assign RDY_setDEIP = 1'd1 ; - assign CAN_FIRE_setDEIP = 1'd1 ; - assign WILL_FIRE_setDEIP = EN_setDEIP ; - // action method hart0_run_halt_server_request_put assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; @@ -9799,7 +9778,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252 && + rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9870,10 +9849,6 @@ module mkCore(CLK, f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ; assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ; - // rule RL_rl_debug_resume - assign CAN_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - // rule RL_rl_debug_run_redundant assign CAN_FIRE_RL_rl_debug_run_redundant = f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && @@ -9900,7 +9875,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408 && + f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10207,7 +10182,7 @@ module mkCore(CLK, (!fetchStage$pipelines_0_canDeq || epochManager$checkEpoch_0_check || fetchStage$RDY_pipelines_0_deq) && - NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715 && + NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 && !epochManager$checkEpoch_0_check ; assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath = CAN_FIRE_RL_renameStage_doRenaming_wrongPath ; @@ -10251,8 +10226,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510 && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534 && + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 && + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 && !commitStage_rg_run_state && commitStage_commitTrap[133] ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = @@ -10302,8 +10277,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693 && - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 && + rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 && + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 && (rob$deqPort_0_deq_data[186:182] == 5'd0 || rob$deqPort_0_deq_data[186:182] == 5'd21 || rob$deqPort_0_deq_data[186:182] == 5'd17 || @@ -10345,8 +10320,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935 && - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 && + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 && + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 && rob$deqPort_0_deq_data[186:182] != 5'd0 && rob$deqPort_0_deq_data[186:182] != 5'd21 && rob$deqPort_0_deq_data[186:182] != 5'd17 && @@ -10429,7 +10404,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = !coreFix_aluExe_0_exeToFinQ$first[17] && coreFix_aluExe_0_exeToFinQ$RDY_deq && - coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623 ; + coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10438,7 +10413,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = !coreFix_aluExe_1_exeToFinQ$first[17] && coreFix_aluExe_1_exeToFinQ$RDY_deq && - coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978 ; + coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ; @@ -10484,7 +10459,7 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ$RDY_deq && coreFix_aluExe_0_regToExeQ$RDY_enq && coreFix_aluExe_0_dispToRegQ$RDY_first && - coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230 ; + coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10989,6 +10964,19 @@ module mkCore(CLK, assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; + // rule RL_rl_debug_resume + assign CAN_FIRE_RL_rl_debug_resume = + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && + f_run_halt_reqs$EMPTY_N && + f_run_halt_rsps$FULL_N && + rg_core_run_state == 2'd1 && + f_run_halt_reqs$D_OUT && + !f_gpr_reqs$EMPTY_N && + !f_fpr_reqs$EMPTY_N && + !f_csr_reqs$EMPTY_N ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = coreFix_memExe_dispToRegQ$RDY_deq && @@ -11262,7 +11250,7 @@ module mkCore(CLK, epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 && rob$isEmpty && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = @@ -11274,8 +11262,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297 && + rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -11317,11 +11305,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365) && - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829 && - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015 ; + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) && + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 && + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -11360,7 +11348,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 ; + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11482,6 +11470,8 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && @@ -11547,20 +11537,12 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_handle && (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd3) ; - assign MUX_csrf_debug_int_pend$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == - 6'd29 ; - assign MUX_csrf_debug_int_pend$write_1__SEL_2 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11568,23 +11550,31 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd16 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd324 || f_csr_reqs$D_OUT[75:64] == 12'd836) ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd29 ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11593,22 +11583,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11620,33 +11610,33 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11660,7 +11650,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11668,7 +11658,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11682,17 +11672,17 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11704,24 +11694,26 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd384 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + assign MUX_csrf_prv_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ; + assign MUX_csrf_prv_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd36 ; - assign MUX_csrf_rg_dcsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd37 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11735,7 +11727,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11746,7 +11738,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11756,7 +11748,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd0 && mmio_pRqQ_data_0[37:36] != 2'd1 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd320 ; @@ -11766,7 +11758,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11777,13 +11769,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ; + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = @@ -11796,7 +11788,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -11838,15 +11830,8 @@ module mkCore(CLK, assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_started$write_1__SEL_1 = - commitStage_rg_run_state && f_run_halt_reqs$EMPTY_N && - f_run_halt_rsps$FULL_N && - rg_core_run_state == 2'd1 && - f_run_halt_reqs$D_OUT && - !f_gpr_reqs$EMPTY_N && - !f_fpr_reqs$EMPTY_N && - !f_csr_reqs$EMPTY_N ; - assign MUX_update_vm_info$write_1__SEL_2 = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -11857,19 +11842,19 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h692296, - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306 } ; + x__h692236, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 } ; assign MUX_commitStage_rg_serialnum$write_1__VAL_1 = commitStage_rg_serialnum + 64'd1 ; assign MUX_commitStage_rg_serialnum$write_1__VAL_2 = - commitStage_rg_serialnum + y__h714209 ; + commitStage_rg_serialnum + y__h714114 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h664143 == 1'd0 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021) ? + (k__h664083 == 1'd0 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11879,21 +11864,21 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11988,7 +11973,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -12002,10 +11987,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283725 } ; + x__h283692 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h285170, + x__h285138, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12013,7 +11998,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287946, + addr__h287914, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12026,12 +12011,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153478, x__h153484, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153444, x__h153450, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157025, x__h157031, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h156991, x__h156997, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h159841, - x__h159845, + { x__h159807, + x__h159811, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12042,7 +12027,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161693, + x__h161659, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12055,13 +12040,19 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289850, + resp_addr__h289818, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = + { prv__h715770, + prv__h715770 != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_lsq$getIssueLd[76:72], @@ -12135,7 +12126,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h195006 } ; + x__h194973 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12170,8 +12161,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190796 : - { {32{x__h191559[31]}}, x__h191559 } } ; + curData__h190763 : + { {32{x__h191526[31]}}, x__h191526 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12204,9 +12195,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h714186 ; + csrf_fflags_reg | fflags__h714091 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q270[7:5] ; @@ -12214,10 +12205,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 or + always@(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 or robdeqPort_0_deq_data_BITS_95_TO_32__q270) begin - case (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678) + case (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q270[14:13]; @@ -12232,57 +12223,61 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h710013 + 64'd1 ; + n__read__h709918 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h710013 + { 62'd0, x__h714428 } ; + n__read__h709918 + { 62'd0, x__h714333 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h699161 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h699101 ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd8 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ? + (rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd36) ? + MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : + ((rob$deqPort_0_deq_data[186:182] == 5'd19) ? + x__h709324 : + csrf_mpp_reg) ; + assign MUX_csrf_prv_reg$write_1__VAL_2 = + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ? 2'd1 : 2'd3 ; - assign MUX_csrf_prv_reg$write_1__VAL_2 = - (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h709419 : - csrf_mpp_reg ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h697642, + dcsr_cause__h697582, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12292,25 +12287,31 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h718266 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h718171 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ? - y_avValue__h699008 : - y_avValue__h700777 ; + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ? + y_avValue__h698948 : + y_avValue__h700717 ; always@(rob$deqPort_0_deq_data or - next_pc__h709359 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h709264 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h709359; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h709264; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12345,23 +12346,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473693 : - data__h473159 ; + data___1__h473660 : + data__h473126 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335751 : - res_data__h335746 ; + res_data__h335718 : + res_data__h335713 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h381453 : - res_data__h381448 ; + res_data__h381420 : + res_data__h381415 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h427148 : - res_data__h427143 ; + res_data__h427115 : + res_data__h427110 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472885 : + data___1__h472852 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -12376,7 +12377,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12387,16 +12388,16 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087 } ; + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 2'd1, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004, - IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000, + IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215, fetchStage$pipelines_0_first[63:0], 2'd0, fetchStage$pipelines_0_first[323:260], @@ -12407,7 +12408,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12425,21 +12426,21 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335747 ; + res_fflags__h335714 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h381449 ; + res_fflags__h381416 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h427144 ; + res_fflags__h427111 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serialnum, rob$deqPort_0_deq_data[282:181], CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302, rob$deqPort_0_deq_data[161:98], CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275, rob$deqPort_0_deq_data[95:26] } ; @@ -12461,7 +12462,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[199:195] == 5'd13 || WILL_FIRE_RL_renameStage_doRenaming_Trap && - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233 ; + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 ; assign mmio_dataReqQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ? MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 : @@ -12503,13 +12504,13 @@ module mkCore(CLK, coreFix_aluExe_1_exeToFinQ$first[16] ; assign coreFix_aluExe_0_bypassWire_0$wget = { coreFix_aluExe_0_regToExeQ$first[348:342], - basicExec___d12560[321:258] } ; + basicExec___d12557[321:258] } ; assign coreFix_aluExe_0_bypassWire_0$whas = WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[349] ; assign coreFix_aluExe_0_bypassWire_1$wget = { coreFix_aluExe_1_regToExeQ$first[348:342], - basicExec___d11914[321:258] } ; + basicExec___d11911[321:258] } ; assign coreFix_aluExe_0_bypassWire_1$whas = WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[349] ; @@ -12732,7 +12733,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serialnum @@ -12761,8 +12762,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h602405 : - v__h601760 ; + v__h602372 : + v__h601727 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12869,7 +12870,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h294400 ; + _theResult_____2__h294368 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12891,7 +12892,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293820 ; + v__h293788 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12937,7 +12938,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h302396 ; + _theResult_____2__h302364 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12955,7 +12956,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h297165 ; + v__h297133 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13055,7 +13056,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h308390 ; + _theResult_____2__h308358 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13073,7 +13074,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307679 ; + v__h307647 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13094,7 +13095,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311953, + { x_addr__h311921, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13124,7 +13125,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h316244 ; + _theResult_____2__h316212 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13142,7 +13143,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h311555 ; + v__h311523 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13219,7 +13220,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329813 ; + _theResult_____2__h329781 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13237,7 +13238,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h329381 ; + v__h329349 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13280,7 +13281,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h326588 ; + _theResult_____2__h326556 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13298,7 +13299,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h326156 ; + v__h326124 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13453,28 +13454,6 @@ module mkCore(CLK, csrInstOrInterruptInflight_rl) ; assign csrInstOrInterruptInflight_rl$EN = 1'd1 ; - // register csrf_debug_int_pend - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or - MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or - f_csr_reqs$D_OUT or EN_setDEIP or setDEIP_v) - case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: - csrf_debug_int_pend$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[14]; - MUX_csrf_debug_int_pend$write_1__SEL_2: - csrf_debug_int_pend$D_IN = f_csr_reqs$D_OUT[14]; - EN_setDEIP: csrf_debug_int_pend$D_IN = setDEIP_v; - default: csrf_debug_int_pend$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign csrf_debug_int_pend$EN = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == - 6'd29 || - EN_setDEIP ; - // register csrf_external_int_en_vec_0 assign csrf_external_int_en_vec_0$D_IN = MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ? @@ -13507,7 +13486,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13544,15 +13523,15 @@ module mkCore(CLK, EN_setSEIP ; // register csrf_external_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_external_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[11]; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11]; EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v; default: csrf_external_int_pend_vec_3$D_IN = @@ -13563,7 +13542,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29 || EN_setMEIP ; @@ -13585,12 +13564,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 || + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13603,9 +13582,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13627,7 +13606,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 || + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13660,10 +13639,10 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -13682,24 +13661,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h698122 or + cause_code__h698062 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h698122; + csrf_mcause_code_reg$D_IN = cause_code__h698062; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13708,11 +13687,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13735,11 +13714,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13752,7 +13731,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13765,7 +13744,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13778,11 +13757,11 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcycle_ehr_data_rl - assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5341 ; + assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5309 ; assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ; // register csrf_medeleg_13_11_reg @@ -13795,7 +13774,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_medeleg_15_reg @@ -13808,7 +13787,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -13821,7 +13800,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_mepc_csr @@ -13844,11 +13823,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd26 ; // register csrf_mideleg_11_reg @@ -13861,7 +13840,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -13874,7 +13853,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -13887,7 +13866,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -13900,13 +13879,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? - upd__h4024 : + upd__h3992 : IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; @@ -13925,12 +13904,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -13942,7 +13921,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_mscratch_csr @@ -13955,7 +13934,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd25 ; // register csrf_mtval_csr @@ -13978,11 +13957,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -13995,7 +13974,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14008,7 +13987,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd23 ; // register csrf_mxr_reg @@ -14032,7 +14011,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14061,10 +14040,10 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14084,49 +14063,59 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_prv_reg - assign csrf_prv_reg$D_IN = - MUX_csrf_prv_reg$write_1__SEL_1 ? - MUX_csrf_prv_reg$write_1__VAL_1 : - MUX_csrf_prv_reg$write_1__VAL_2 ; + always@(MUX_csrf_prv_reg$write_1__SEL_1 or + MUX_csrf_prv_reg$write_1__VAL_1 or + MUX_csrf_prv_reg$write_1__SEL_2 or + MUX_csrf_prv_reg$write_1__VAL_2 or + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prv_reg$write_1__SEL_1: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; + MUX_csrf_prv_reg$write_1__SEL_2: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2; + MUX_csrf_prv_reg$write_1__SEL_3: + csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; + default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_commitStage_rg_run_state$write_1__SEL_1 or MUX_csrf_rg_dcsr$write_1__VAL_2 or - MUX_csrf_rg_dcsr$write_1__SEL_3 or f_csr_reqs$D_OUT) + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_rg_dcsr$write_1__SEL_1: csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32]; MUX_commitStage_rg_run_state$write_1__SEL_1: csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2; - MUX_csrf_rg_dcsr$write_1__SEL_3: + MUX_csrf_prv_reg$write_1__SEL_3: csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_rg_dcsr$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd36 ; // register csrf_rg_dpc @@ -14145,12 +14134,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd37 ; // register csrf_rg_dscratch0 @@ -14163,7 +14152,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd38 ; // register csrf_rg_dscratch1 @@ -14176,20 +14165,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd39 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h698122 or + cause_code__h698062 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h698122; + csrf_scause_code_reg$D_IN = cause_code__h698062; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14198,11 +14187,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14225,11 +14214,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14242,7 +14231,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14255,7 +14244,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14268,7 +14257,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_sepc_csr @@ -14291,11 +14280,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14330,7 +14319,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14356,19 +14345,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; // register csrf_software_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or f_csr_reqs$D_OUT) + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3]; MUX_csrf_software_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_software_int_pend_vec_3$write_1__VAL_2; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3]; default: csrf_software_int_pend_vec_3$D_IN = 1'b0 /* unspecified value */ ; @@ -14381,7 +14370,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29 ; // register csrf_spp_reg @@ -14398,10 +14387,10 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14416,7 +14405,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd12 ; // register csrf_stats_module_doStats @@ -14443,11 +14432,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14460,7 +14449,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14473,7 +14462,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd10 ; // register csrf_sum_reg @@ -14523,7 +14512,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14564,7 +14553,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_tvm_reg @@ -14577,7 +14566,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_tw_reg @@ -14590,7 +14579,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14603,21 +14592,21 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_flushCaches ; // register flush_reservation @@ -14632,11 +14621,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd16 || rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14645,7 +14634,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46110, + { x__h46077, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14657,7 +14646,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48646 } ; + x__h48613 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -14750,7 +14739,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18203, + { x__h18170, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14762,7 +14751,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20741 } ; + x__h20708 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -14846,7 +14835,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65904 } ; + x_data__h65871 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -14936,7 +14925,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -14966,7 +14955,8 @@ module mkCore(CLK, EN_coreReq_start ; // register update_vm_info - assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_2 ; + assign update_vm_info$D_IN = + !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || @@ -14984,7 +14974,7 @@ module mkCore(CLK, coreFix_aluExe_0_rsAlu$dispatchData[8:4], coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -15024,13 +15014,13 @@ module mkCore(CLK, { coreFix_aluExe_0_regToExeQ$first[421:417], coreFix_aluExe_0_regToExeQ$first[349:305], coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11, - basicExec___d12560[321:258], + basicExec___d12557[321:258], coreFix_aluExe_0_regToExeQ$first[395], - basicExec___d12560[257:194], - basicExec___d12560[129:0], + basicExec___d12557[257:194], + basicExec___d12557[129:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15073,14 +15063,14 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h636445, - x__h636446, + x__h636385, + x__h636386, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, coreFix_aluExe_0_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15188,7 +15178,7 @@ module mkCore(CLK, end assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15276,7 +15266,7 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$dispatchData[8:4], coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15315,13 +15305,13 @@ module mkCore(CLK, { coreFix_aluExe_1_regToExeQ$first[421:417], coreFix_aluExe_1_regToExeQ$first[349:305], coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11, - basicExec___d11914[321:258], + basicExec___d11911[321:258], coreFix_aluExe_1_regToExeQ$first[395], - basicExec___d11914[257:194], - basicExec___d11914[129:0], + basicExec___d11911[257:194], + basicExec___d11911[129:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15364,14 +15354,14 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h614583, - x__h614584, + x__h614524, + x__h614525, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, coreFix_aluExe_1_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15407,12 +15397,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h664143 == 1'd1 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021) ? + (k__h664083 == 1'd1 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -15422,13 +15412,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15501,7 +15491,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15580,7 +15570,7 @@ module mkCore(CLK, { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15634,7 +15624,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15722,7 +15712,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15772,7 +15762,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15821,7 +15811,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15865,7 +15855,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15907,19 +15897,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h601247 : - a__h600825 ; + _theResult___fst__h601214 : + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h600826 == 64'd0, - a__h600825, + { b__h600793 == 64'd0, + a__h600792, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h601261, - a__h600825[63], + x__h601228, + a__h600792[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h601248 : - b__h600826 ; + _theResult___snd__h601215 : + b__h600793 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -15940,7 +15930,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15980,20 +15970,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h600825 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h600826 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h600792 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h600825 ; + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h600826 ; + b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h600825 ; + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h600826 ; + b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16022,12 +16012,12 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h479547, - x__h479548, - x__h479549, + x__h479514, + x__h479515, + x__h479516, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16065,18 +16055,18 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033) ? - { IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029) ? + { IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, + { IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16149,7 +16139,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16175,9 +16165,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167) ; + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -16230,8 +16220,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h285158, - x__h285170, + { x__h285126, + x__h285138, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -16242,13 +16232,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h287024, + x__h286992, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283725 ; + x__h283692 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16885,16 +16875,16 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h181168[2:0], - vaddr__h181168, + coreFix_memExe_lsq$getOrigBE << vaddr__h181135[2:0], + vaddr__h181135, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h181168[2:0] != 3'd0 : + vaddr__h181135[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h181168[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181168[0]), + vaddr__h181135[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181135[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16921,14 +16911,15 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h715865, - prv__h715865 != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; - assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign coreFix_memExe_dTlb$EN_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_procReq = CAN_FIRE_RL_coreFix_memExe_doExeMem ; assign coreFix_memExe_dTlb$EN_deqProcResp = @@ -16957,7 +16948,7 @@ module mkCore(CLK, coreFix_memExe_rsMem$dispatchData[71:66], coreFix_memExe_rsMem$dispatchData[20:9] } ; assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17030,44 +17021,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? specTagManager$currentSpecBits : - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? specTagManager$currentSpecBits : - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17103,7 +17094,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$setAtCommit_1_put = rob$deqPort_1_deq_data[24:19] ; assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17147,7 +17138,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181173 ; + shiftData__h181140 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17247,11 +17238,11 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181082, - x__h181083, + x__h181049, + x__h181050, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17499,9 +17490,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055, + IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17509,10 +17500,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184, + IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17585,7 +17576,7 @@ module mkCore(CLK, end assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17740,7 +17731,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -17754,7 +17745,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -17772,7 +17763,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -17783,7 +17774,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17802,8 +17793,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -17811,9 +17802,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -17950,18 +17941,16 @@ module mkCore(CLK, l2Tlb$toChildren_rsToC_first[80:0] ; assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ; assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; - always@(MUX_csrf_prv_reg$write_1__SEL_1 or + always@(MUX_csrf_prv_reg$write_1__SEL_2 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or @@ -17975,7 +17964,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_6) begin case (1'b1) // synopsys parallel_case - MUX_csrf_prv_reg$write_1__SEL_1: + MUX_csrf_prv_reg$write_1__SEL_2: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; @@ -18024,8 +18013,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18033,12 +18022,15 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; - assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; + assign fetchStage$EN_iTlbIfc_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ; assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ; assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ; @@ -18072,14 +18064,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18104,9 +18096,17 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 : MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ; assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ; - assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ; - assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ; - assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_2 ; + assign l2Tlb$updateVMInfo_vmD = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign l2Tlb$updateVMInfo_vmI = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; + assign l2Tlb$EN_updateVMInfo = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign l2Tlb$EN_toChildren_rqFromC_put = WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ; assign l2Tlb$EN_toChildren_rsToC_deq = @@ -18385,11 +18385,11 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -18415,8 +18415,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -18639,7 +18639,7 @@ module mkCore(CLK, { fetchStage$pipelines_1_first[387:324], fetchStage$pipelines_1_first[127:96], fetchStage$pipelines_1_first[199:195], - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -18651,11 +18651,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215 || - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 || + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221, 7'd32, - renaming_spec_bits__h678634 } ; + renaming_spec_bits__h678574 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18798,7 +18798,7 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[102:91] ; assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ; assign rob$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18844,8 +18844,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -18970,8 +18970,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19085,8 +19085,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19123,7 +19123,7 @@ module mkCore(CLK, // submodule specTagManager assign specTagManager$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign specTagManager$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -19148,9 +19148,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202) ; + (fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19173,7 +19173,7 @@ module mkCore(CLK, // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { x__h712792, + { x__h712697, rob$deqPort_1_deq_data[282:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296, 6'd10, @@ -19200,15 +19200,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190796), + .amoExec_current_data(curData__h190763), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h192334)); + .amoExec(n__h192301)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h75940 }), - .amoExec_in_data({ 32'd0, x__h76055 }), + msip__h75907 }), + .amoExec_in_data({ 32'd0, x__h76022 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -19222,7 +19222,7 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), - .basicExec(basicExec___d11914)); + .basicExec(basicExec___d11911)); module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, { coreFix_aluExe_0_regToExeQ$first[395], @@ -19234,13 +19234,13 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12560)); + .basicExec(basicExec___d12557)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, { { fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 }, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 }, fetchStage$pipelines_0_first[160], - x_data_imm__h671111 } }), + x_data_imm__h671051 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19249,12 +19249,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h651649, - r1__read_BITS_13_TO_12___h651834 != + .checkForException_csrState({ x_decodeInfo_frm__h651589, + r1__read_BITS_13_TO_12___h651774 != 2'd0, - { prv__h715821, + { prv__h715726, csrf_tvm_reg, - { r1__read_BIT_20___h652494, + { r1__read_BIT_20___h652434, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19265,12 +19265,12 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d12946)); + .checkForException(checkForException___d12942)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - { fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + { fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160], - x_data_imm__h686042 } }), + x_data_imm__h685982 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19279,12 +19279,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h651649, - r1__read_BITS_13_TO_12___h651834 != + .checkForException_csrState({ x_decodeInfo_frm__h651589, + r1__read_BITS_13_TO_12___h651774 != 2'd0, - { prv__h715821, + { prv__h715726, csrf_tvm_reg, - { r1__read_BIT_20___h652494, + { r1__read_BIT_20___h652434, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19295,1200 +19295,1200 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13619)); + .checkForException(checkForException___d13615)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h479638), - .execFpuSimple_rVal2(rVal2__h479639), + .execFpuSimple_rVal1(rVal1__h479605), + .execFpuSimple_rVal2(rVal2__h479606), .execFpuSimple(execFpuSimple___d11053)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h352136 : - _theResult____h343962 ; + _theResult___snd__h352103 : + _theResult____h343929 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397833 : - _theResult____h389661 ; + _theResult___snd__h397800 : + _theResult____h389628 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h443528 : - _theResult____h435356 ; + _theResult___snd__h443495 : + _theResult____h435323 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 ? - _theResult___snd__h509045 : - _theResult____h500746 ; + _theResult___snd__h509012 : + _theResult____h500713 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609 ? - _theResult___snd__h587202 : - _theResult____h578903 ; + _theResult___snd__h587169 : + _theResult____h578870 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 ? - _theResult___snd__h547898 : - _theResult____h539599 ; + _theResult___snd__h547865 : + _theResult____h539566 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h461294 : - _theResult____h452993 ; + _theResult___snd__h461261 : + _theResult____h452960 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369902 : - _theResult____h361601 ; + _theResult___snd__h369869 : + _theResult____h361568 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h415599 : - _theResult____h407298 ; + _theResult___snd__h415566 : + _theResult____h407265 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 ? - _theResult___snd__h499394 : + _theResult___snd__h499361 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944 ? - _theResult___snd__h499394 : - _theResult___snd__h517799 ; + _theResult___snd__h499361 : + _theResult___snd__h517766 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312 ? - _theResult___snd__h577551 : + _theResult___snd__h577518 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659 ? - _theResult___snd__h577551 : - _theResult___snd__h595956 ; + _theResult___snd__h577518 : + _theResult___snd__h595923 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 ? - _theResult___snd__h538247 : + _theResult___snd__h538214 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429 ? - _theResult___snd__h538247 : - _theResult___snd__h556652 ; + _theResult___snd__h538214 : + _theResult___snd__h556619 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h452110 : + _theResult___snd__h452077 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h452110 : - _theResult___snd__h469900 ; + _theResult___snd__h452077 : + _theResult___snd__h469867 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360718 : + _theResult___snd__h360685 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360718 : - _theResult___snd__h378508 ; + _theResult___snd__h360685 : + _theResult___snd__h378475 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h406415 : + _theResult___snd__h406382 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h406415 : - _theResult___snd__h424205 ; + _theResult___snd__h406382 : + _theResult___snd__h424172 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h352073 == 8'd255) ? + ((_theResult___fst_exp__h352040 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360729 == 8'd255) ? + ((_theResult___fst_exp__h360696 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h352073 == 8'd255) ? + ((_theResult___fst_exp__h352040 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360729 == 8'd255) ? + ((_theResult___fst_exp__h360696 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397770 == 8'd255) ? + ((_theResult___fst_exp__h397737 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h406426 == 8'd255) ? + ((_theResult___fst_exp__h406393 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397770 == 8'd255) ? + ((_theResult___fst_exp__h397737 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h406426 == 8'd255) ? + ((_theResult___fst_exp__h406393 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h443465 == 8'd255) ? + ((_theResult___fst_exp__h443432 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h452121 == 8'd255) ? + ((_theResult___fst_exp__h452088 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h443465 == 8'd255) ? + ((_theResult___fst_exp__h443432 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h452121 == 8'd255) ? + ((_theResult___fst_exp__h452088 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343962[56] ? + (_theResult____h343929[56] ? 6'd0 : - (_theResult____h343962[55] ? + (_theResult____h343929[55] ? 6'd1 : - (_theResult____h343962[54] ? + (_theResult____h343929[54] ? 6'd2 : - (_theResult____h343962[53] ? + (_theResult____h343929[53] ? 6'd3 : - (_theResult____h343962[52] ? + (_theResult____h343929[52] ? 6'd4 : - (_theResult____h343962[51] ? + (_theResult____h343929[51] ? 6'd5 : - (_theResult____h343962[50] ? + (_theResult____h343929[50] ? 6'd6 : - (_theResult____h343962[49] ? + (_theResult____h343929[49] ? 6'd7 : - (_theResult____h343962[48] ? + (_theResult____h343929[48] ? 6'd8 : - (_theResult____h343962[47] ? + (_theResult____h343929[47] ? 6'd9 : - (_theResult____h343962[46] ? + (_theResult____h343929[46] ? 6'd10 : - (_theResult____h343962[45] ? + (_theResult____h343929[45] ? 6'd11 : - (_theResult____h343962[44] ? + (_theResult____h343929[44] ? 6'd12 : - (_theResult____h343962[43] ? + (_theResult____h343929[43] ? 6'd13 : - (_theResult____h343962[42] ? + (_theResult____h343929[42] ? 6'd14 : - (_theResult____h343962[41] ? + (_theResult____h343929[41] ? 6'd15 : - (_theResult____h343962[40] ? + (_theResult____h343929[40] ? 6'd16 : - (_theResult____h343962[39] ? + (_theResult____h343929[39] ? 6'd17 : - (_theResult____h343962[38] ? + (_theResult____h343929[38] ? 6'd18 : - (_theResult____h343962[37] ? + (_theResult____h343929[37] ? 6'd19 : - (_theResult____h343962[36] ? + (_theResult____h343929[36] ? 6'd20 : - (_theResult____h343962[35] ? + (_theResult____h343929[35] ? 6'd21 : - (_theResult____h343962[34] ? + (_theResult____h343929[34] ? 6'd22 : - (_theResult____h343962[33] ? + (_theResult____h343929[33] ? 6'd23 : - (_theResult____h343962[32] ? + (_theResult____h343929[32] ? 6'd24 : - (_theResult____h343962[31] ? + (_theResult____h343929[31] ? 6'd25 : - (_theResult____h343962[30] ? + (_theResult____h343929[30] ? 6'd26 : - (_theResult____h343962[29] ? + (_theResult____h343929[29] ? 6'd27 : - (_theResult____h343962[28] ? + (_theResult____h343929[28] ? 6'd28 : - (_theResult____h343962[27] ? + (_theResult____h343929[27] ? 6'd29 : - (_theResult____h343962[26] ? + (_theResult____h343929[26] ? 6'd30 : - (_theResult____h343962[25] ? + (_theResult____h343929[25] ? 6'd31 : - (_theResult____h343962[24] ? + (_theResult____h343929[24] ? 6'd32 : - (_theResult____h343962[23] ? + (_theResult____h343929[23] ? 6'd33 : - (_theResult____h343962[22] ? + (_theResult____h343929[22] ? 6'd34 : - (_theResult____h343962[21] ? + (_theResult____h343929[21] ? 6'd35 : - (_theResult____h343962[20] ? + (_theResult____h343929[20] ? 6'd36 : - (_theResult____h343962[19] ? + (_theResult____h343929[19] ? 6'd37 : - (_theResult____h343962[18] ? + (_theResult____h343929[18] ? 6'd38 : - (_theResult____h343962[17] ? + (_theResult____h343929[17] ? 6'd39 : - (_theResult____h343962[16] ? + (_theResult____h343929[16] ? 6'd40 : - (_theResult____h343962[15] ? + (_theResult____h343929[15] ? 6'd41 : - (_theResult____h343962[14] ? + (_theResult____h343929[14] ? 6'd42 : - (_theResult____h343962[13] ? + (_theResult____h343929[13] ? 6'd43 : - (_theResult____h343962[12] ? + (_theResult____h343929[12] ? 6'd44 : - (_theResult____h343962[11] ? + (_theResult____h343929[11] ? 6'd45 : - (_theResult____h343962[10] ? + (_theResult____h343929[10] ? 6'd46 : - (_theResult____h343962[9] ? + (_theResult____h343929[9] ? 6'd47 : - (_theResult____h343962[8] ? + (_theResult____h343929[8] ? 6'd48 : - (_theResult____h343962[7] ? + (_theResult____h343929[7] ? 6'd49 : - (_theResult____h343962[6] ? + (_theResult____h343929[6] ? 6'd50 : - (_theResult____h343962[5] ? + (_theResult____h343929[5] ? 6'd51 : - (_theResult____h343962[4] ? + (_theResult____h343929[4] ? 6'd52 : - (_theResult____h343962[3] ? + (_theResult____h343929[3] ? 6'd53 : - (_theResult____h343962[2] ? + (_theResult____h343929[2] ? 6'd54 : - (_theResult____h343962[1] ? + (_theResult____h343929[1] ? 6'd55 : - (_theResult____h343962[0] ? + (_theResult____h343929[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h389661[56] ? + (_theResult____h389628[56] ? 6'd0 : - (_theResult____h389661[55] ? + (_theResult____h389628[55] ? 6'd1 : - (_theResult____h389661[54] ? + (_theResult____h389628[54] ? 6'd2 : - (_theResult____h389661[53] ? + (_theResult____h389628[53] ? 6'd3 : - (_theResult____h389661[52] ? + (_theResult____h389628[52] ? 6'd4 : - (_theResult____h389661[51] ? + (_theResult____h389628[51] ? 6'd5 : - (_theResult____h389661[50] ? + (_theResult____h389628[50] ? 6'd6 : - (_theResult____h389661[49] ? + (_theResult____h389628[49] ? 6'd7 : - (_theResult____h389661[48] ? + (_theResult____h389628[48] ? 6'd8 : - (_theResult____h389661[47] ? + (_theResult____h389628[47] ? 6'd9 : - (_theResult____h389661[46] ? + (_theResult____h389628[46] ? 6'd10 : - (_theResult____h389661[45] ? + (_theResult____h389628[45] ? 6'd11 : - (_theResult____h389661[44] ? + (_theResult____h389628[44] ? 6'd12 : - (_theResult____h389661[43] ? + (_theResult____h389628[43] ? 6'd13 : - (_theResult____h389661[42] ? + (_theResult____h389628[42] ? 6'd14 : - (_theResult____h389661[41] ? + (_theResult____h389628[41] ? 6'd15 : - (_theResult____h389661[40] ? + (_theResult____h389628[40] ? 6'd16 : - (_theResult____h389661[39] ? + (_theResult____h389628[39] ? 6'd17 : - (_theResult____h389661[38] ? + (_theResult____h389628[38] ? 6'd18 : - (_theResult____h389661[37] ? + (_theResult____h389628[37] ? 6'd19 : - (_theResult____h389661[36] ? + (_theResult____h389628[36] ? 6'd20 : - (_theResult____h389661[35] ? + (_theResult____h389628[35] ? 6'd21 : - (_theResult____h389661[34] ? + (_theResult____h389628[34] ? 6'd22 : - (_theResult____h389661[33] ? + (_theResult____h389628[33] ? 6'd23 : - (_theResult____h389661[32] ? + (_theResult____h389628[32] ? 6'd24 : - (_theResult____h389661[31] ? + (_theResult____h389628[31] ? 6'd25 : - (_theResult____h389661[30] ? + (_theResult____h389628[30] ? 6'd26 : - (_theResult____h389661[29] ? + (_theResult____h389628[29] ? 6'd27 : - (_theResult____h389661[28] ? + (_theResult____h389628[28] ? 6'd28 : - (_theResult____h389661[27] ? + (_theResult____h389628[27] ? 6'd29 : - (_theResult____h389661[26] ? + (_theResult____h389628[26] ? 6'd30 : - (_theResult____h389661[25] ? + (_theResult____h389628[25] ? 6'd31 : - (_theResult____h389661[24] ? + (_theResult____h389628[24] ? 6'd32 : - (_theResult____h389661[23] ? + (_theResult____h389628[23] ? 6'd33 : - (_theResult____h389661[22] ? + (_theResult____h389628[22] ? 6'd34 : - (_theResult____h389661[21] ? + (_theResult____h389628[21] ? 6'd35 : - (_theResult____h389661[20] ? + (_theResult____h389628[20] ? 6'd36 : - (_theResult____h389661[19] ? + (_theResult____h389628[19] ? 6'd37 : - (_theResult____h389661[18] ? + (_theResult____h389628[18] ? 6'd38 : - (_theResult____h389661[17] ? + (_theResult____h389628[17] ? 6'd39 : - (_theResult____h389661[16] ? + (_theResult____h389628[16] ? 6'd40 : - (_theResult____h389661[15] ? + (_theResult____h389628[15] ? 6'd41 : - (_theResult____h389661[14] ? + (_theResult____h389628[14] ? 6'd42 : - (_theResult____h389661[13] ? + (_theResult____h389628[13] ? 6'd43 : - (_theResult____h389661[12] ? + (_theResult____h389628[12] ? 6'd44 : - (_theResult____h389661[11] ? + (_theResult____h389628[11] ? 6'd45 : - (_theResult____h389661[10] ? + (_theResult____h389628[10] ? 6'd46 : - (_theResult____h389661[9] ? + (_theResult____h389628[9] ? 6'd47 : - (_theResult____h389661[8] ? + (_theResult____h389628[8] ? 6'd48 : - (_theResult____h389661[7] ? + (_theResult____h389628[7] ? 6'd49 : - (_theResult____h389661[6] ? + (_theResult____h389628[6] ? 6'd50 : - (_theResult____h389661[5] ? + (_theResult____h389628[5] ? 6'd51 : - (_theResult____h389661[4] ? + (_theResult____h389628[4] ? 6'd52 : - (_theResult____h389661[3] ? + (_theResult____h389628[3] ? 6'd53 : - (_theResult____h389661[2] ? + (_theResult____h389628[2] ? 6'd54 : - (_theResult____h389661[1] ? + (_theResult____h389628[1] ? 6'd55 : - (_theResult____h389661[0] ? + (_theResult____h389628[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h435356[56] ? + (_theResult____h435323[56] ? 6'd0 : - (_theResult____h435356[55] ? + (_theResult____h435323[55] ? 6'd1 : - (_theResult____h435356[54] ? + (_theResult____h435323[54] ? 6'd2 : - (_theResult____h435356[53] ? + (_theResult____h435323[53] ? 6'd3 : - (_theResult____h435356[52] ? + (_theResult____h435323[52] ? 6'd4 : - (_theResult____h435356[51] ? + (_theResult____h435323[51] ? 6'd5 : - (_theResult____h435356[50] ? + (_theResult____h435323[50] ? 6'd6 : - (_theResult____h435356[49] ? + (_theResult____h435323[49] ? 6'd7 : - (_theResult____h435356[48] ? + (_theResult____h435323[48] ? 6'd8 : - (_theResult____h435356[47] ? + (_theResult____h435323[47] ? 6'd9 : - (_theResult____h435356[46] ? + (_theResult____h435323[46] ? 6'd10 : - (_theResult____h435356[45] ? + (_theResult____h435323[45] ? 6'd11 : - (_theResult____h435356[44] ? + (_theResult____h435323[44] ? 6'd12 : - (_theResult____h435356[43] ? + (_theResult____h435323[43] ? 6'd13 : - (_theResult____h435356[42] ? + (_theResult____h435323[42] ? 6'd14 : - (_theResult____h435356[41] ? + (_theResult____h435323[41] ? 6'd15 : - (_theResult____h435356[40] ? + (_theResult____h435323[40] ? 6'd16 : - (_theResult____h435356[39] ? + (_theResult____h435323[39] ? 6'd17 : - (_theResult____h435356[38] ? + (_theResult____h435323[38] ? 6'd18 : - (_theResult____h435356[37] ? + (_theResult____h435323[37] ? 6'd19 : - (_theResult____h435356[36] ? + (_theResult____h435323[36] ? 6'd20 : - (_theResult____h435356[35] ? + (_theResult____h435323[35] ? 6'd21 : - (_theResult____h435356[34] ? + (_theResult____h435323[34] ? 6'd22 : - (_theResult____h435356[33] ? + (_theResult____h435323[33] ? 6'd23 : - (_theResult____h435356[32] ? + (_theResult____h435323[32] ? 6'd24 : - (_theResult____h435356[31] ? + (_theResult____h435323[31] ? 6'd25 : - (_theResult____h435356[30] ? + (_theResult____h435323[30] ? 6'd26 : - (_theResult____h435356[29] ? + (_theResult____h435323[29] ? 6'd27 : - (_theResult____h435356[28] ? + (_theResult____h435323[28] ? 6'd28 : - (_theResult____h435356[27] ? + (_theResult____h435323[27] ? 6'd29 : - (_theResult____h435356[26] ? + (_theResult____h435323[26] ? 6'd30 : - (_theResult____h435356[25] ? + (_theResult____h435323[25] ? 6'd31 : - (_theResult____h435356[24] ? + (_theResult____h435323[24] ? 6'd32 : - (_theResult____h435356[23] ? + (_theResult____h435323[23] ? 6'd33 : - (_theResult____h435356[22] ? + (_theResult____h435323[22] ? 6'd34 : - (_theResult____h435356[21] ? + (_theResult____h435323[21] ? 6'd35 : - (_theResult____h435356[20] ? + (_theResult____h435323[20] ? 6'd36 : - (_theResult____h435356[19] ? + (_theResult____h435323[19] ? 6'd37 : - (_theResult____h435356[18] ? + (_theResult____h435323[18] ? 6'd38 : - (_theResult____h435356[17] ? + (_theResult____h435323[17] ? 6'd39 : - (_theResult____h435356[16] ? + (_theResult____h435323[16] ? 6'd40 : - (_theResult____h435356[15] ? + (_theResult____h435323[15] ? 6'd41 : - (_theResult____h435356[14] ? + (_theResult____h435323[14] ? 6'd42 : - (_theResult____h435356[13] ? + (_theResult____h435323[13] ? 6'd43 : - (_theResult____h435356[12] ? + (_theResult____h435323[12] ? 6'd44 : - (_theResult____h435356[11] ? + (_theResult____h435323[11] ? 6'd45 : - (_theResult____h435356[10] ? + (_theResult____h435323[10] ? 6'd46 : - (_theResult____h435356[9] ? + (_theResult____h435323[9] ? 6'd47 : - (_theResult____h435356[8] ? + (_theResult____h435323[8] ? 6'd48 : - (_theResult____h435356[7] ? + (_theResult____h435323[7] ? 6'd49 : - (_theResult____h435356[6] ? + (_theResult____h435323[6] ? 6'd50 : - (_theResult____h435356[5] ? + (_theResult____h435323[5] ? 6'd51 : - (_theResult____h435356[4] ? + (_theResult____h435323[4] ? 6'd52 : - (_theResult____h435356[3] ? + (_theResult____h435323[3] ? 6'd53 : - (_theResult____h435356[2] ? + (_theResult____h435323[2] ? 6'd54 : - (_theResult____h435356[1] ? + (_theResult____h435323[1] ? 6'd55 : - (_theResult____h435356[0] ? + (_theResult____h435323[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 = - (_theResult____h539599[56] ? + (_theResult____h539566[56] ? 6'd0 : - (_theResult____h539599[55] ? + (_theResult____h539566[55] ? 6'd1 : - (_theResult____h539599[54] ? + (_theResult____h539566[54] ? 6'd2 : - (_theResult____h539599[53] ? + (_theResult____h539566[53] ? 6'd3 : - (_theResult____h539599[52] ? + (_theResult____h539566[52] ? 6'd4 : - (_theResult____h539599[51] ? + (_theResult____h539566[51] ? 6'd5 : - (_theResult____h539599[50] ? + (_theResult____h539566[50] ? 6'd6 : - (_theResult____h539599[49] ? + (_theResult____h539566[49] ? 6'd7 : - (_theResult____h539599[48] ? + (_theResult____h539566[48] ? 6'd8 : - (_theResult____h539599[47] ? + (_theResult____h539566[47] ? 6'd9 : - (_theResult____h539599[46] ? + (_theResult____h539566[46] ? 6'd10 : - (_theResult____h539599[45] ? + (_theResult____h539566[45] ? 6'd11 : - (_theResult____h539599[44] ? + (_theResult____h539566[44] ? 6'd12 : - (_theResult____h539599[43] ? + (_theResult____h539566[43] ? 6'd13 : - (_theResult____h539599[42] ? + (_theResult____h539566[42] ? 6'd14 : - (_theResult____h539599[41] ? + (_theResult____h539566[41] ? 6'd15 : - (_theResult____h539599[40] ? + (_theResult____h539566[40] ? 6'd16 : - (_theResult____h539599[39] ? + (_theResult____h539566[39] ? 6'd17 : - (_theResult____h539599[38] ? + (_theResult____h539566[38] ? 6'd18 : - (_theResult____h539599[37] ? + (_theResult____h539566[37] ? 6'd19 : - (_theResult____h539599[36] ? + (_theResult____h539566[36] ? 6'd20 : - (_theResult____h539599[35] ? + (_theResult____h539566[35] ? 6'd21 : - (_theResult____h539599[34] ? + (_theResult____h539566[34] ? 6'd22 : - (_theResult____h539599[33] ? + (_theResult____h539566[33] ? 6'd23 : - (_theResult____h539599[32] ? + (_theResult____h539566[32] ? 6'd24 : - (_theResult____h539599[31] ? + (_theResult____h539566[31] ? 6'd25 : - (_theResult____h539599[30] ? + (_theResult____h539566[30] ? 6'd26 : - (_theResult____h539599[29] ? + (_theResult____h539566[29] ? 6'd27 : - (_theResult____h539599[28] ? + (_theResult____h539566[28] ? 6'd28 : - (_theResult____h539599[27] ? + (_theResult____h539566[27] ? 6'd29 : - (_theResult____h539599[26] ? + (_theResult____h539566[26] ? 6'd30 : - (_theResult____h539599[25] ? + (_theResult____h539566[25] ? 6'd31 : - (_theResult____h539599[24] ? + (_theResult____h539566[24] ? 6'd32 : - (_theResult____h539599[23] ? + (_theResult____h539566[23] ? 6'd33 : - (_theResult____h539599[22] ? + (_theResult____h539566[22] ? 6'd34 : - (_theResult____h539599[21] ? + (_theResult____h539566[21] ? 6'd35 : - (_theResult____h539599[20] ? + (_theResult____h539566[20] ? 6'd36 : - (_theResult____h539599[19] ? + (_theResult____h539566[19] ? 6'd37 : - (_theResult____h539599[18] ? + (_theResult____h539566[18] ? 6'd38 : - (_theResult____h539599[17] ? + (_theResult____h539566[17] ? 6'd39 : - (_theResult____h539599[16] ? + (_theResult____h539566[16] ? 6'd40 : - (_theResult____h539599[15] ? + (_theResult____h539566[15] ? 6'd41 : - (_theResult____h539599[14] ? + (_theResult____h539566[14] ? 6'd42 : - (_theResult____h539599[13] ? + (_theResult____h539566[13] ? 6'd43 : - (_theResult____h539599[12] ? + (_theResult____h539566[12] ? 6'd44 : - (_theResult____h539599[11] ? + (_theResult____h539566[11] ? 6'd45 : - (_theResult____h539599[10] ? + (_theResult____h539566[10] ? 6'd46 : - (_theResult____h539599[9] ? + (_theResult____h539566[9] ? 6'd47 : - (_theResult____h539599[8] ? + (_theResult____h539566[8] ? 6'd48 : - (_theResult____h539599[7] ? + (_theResult____h539566[7] ? 6'd49 : - (_theResult____h539599[6] ? + (_theResult____h539566[6] ? 6'd50 : - (_theResult____h539599[5] ? + (_theResult____h539566[5] ? 6'd51 : - (_theResult____h539599[4] ? + (_theResult____h539566[4] ? 6'd52 : - (_theResult____h539599[3] ? + (_theResult____h539566[3] ? 6'd53 : - (_theResult____h539599[2] ? + (_theResult____h539566[2] ? 6'd54 : - (_theResult____h539599[1] ? + (_theResult____h539566[1] ? 6'd55 : - (_theResult____h539599[0] ? + (_theResult____h539566[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 = - (_theResult____h500746[56] ? + (_theResult____h500713[56] ? 6'd0 : - (_theResult____h500746[55] ? + (_theResult____h500713[55] ? 6'd1 : - (_theResult____h500746[54] ? + (_theResult____h500713[54] ? 6'd2 : - (_theResult____h500746[53] ? + (_theResult____h500713[53] ? 6'd3 : - (_theResult____h500746[52] ? + (_theResult____h500713[52] ? 6'd4 : - (_theResult____h500746[51] ? + (_theResult____h500713[51] ? 6'd5 : - (_theResult____h500746[50] ? + (_theResult____h500713[50] ? 6'd6 : - (_theResult____h500746[49] ? + (_theResult____h500713[49] ? 6'd7 : - (_theResult____h500746[48] ? + (_theResult____h500713[48] ? 6'd8 : - (_theResult____h500746[47] ? + (_theResult____h500713[47] ? 6'd9 : - (_theResult____h500746[46] ? + (_theResult____h500713[46] ? 6'd10 : - (_theResult____h500746[45] ? + (_theResult____h500713[45] ? 6'd11 : - (_theResult____h500746[44] ? + (_theResult____h500713[44] ? 6'd12 : - (_theResult____h500746[43] ? + (_theResult____h500713[43] ? 6'd13 : - (_theResult____h500746[42] ? + (_theResult____h500713[42] ? 6'd14 : - (_theResult____h500746[41] ? + (_theResult____h500713[41] ? 6'd15 : - (_theResult____h500746[40] ? + (_theResult____h500713[40] ? 6'd16 : - (_theResult____h500746[39] ? + (_theResult____h500713[39] ? 6'd17 : - (_theResult____h500746[38] ? + (_theResult____h500713[38] ? 6'd18 : - (_theResult____h500746[37] ? + (_theResult____h500713[37] ? 6'd19 : - (_theResult____h500746[36] ? + (_theResult____h500713[36] ? 6'd20 : - (_theResult____h500746[35] ? + (_theResult____h500713[35] ? 6'd21 : - (_theResult____h500746[34] ? + (_theResult____h500713[34] ? 6'd22 : - (_theResult____h500746[33] ? + (_theResult____h500713[33] ? 6'd23 : - (_theResult____h500746[32] ? + (_theResult____h500713[32] ? 6'd24 : - (_theResult____h500746[31] ? + (_theResult____h500713[31] ? 6'd25 : - (_theResult____h500746[30] ? + (_theResult____h500713[30] ? 6'd26 : - (_theResult____h500746[29] ? + (_theResult____h500713[29] ? 6'd27 : - (_theResult____h500746[28] ? + (_theResult____h500713[28] ? 6'd28 : - (_theResult____h500746[27] ? + (_theResult____h500713[27] ? 6'd29 : - (_theResult____h500746[26] ? + (_theResult____h500713[26] ? 6'd30 : - (_theResult____h500746[25] ? + (_theResult____h500713[25] ? 6'd31 : - (_theResult____h500746[24] ? + (_theResult____h500713[24] ? 6'd32 : - (_theResult____h500746[23] ? + (_theResult____h500713[23] ? 6'd33 : - (_theResult____h500746[22] ? + (_theResult____h500713[22] ? 6'd34 : - (_theResult____h500746[21] ? + (_theResult____h500713[21] ? 6'd35 : - (_theResult____h500746[20] ? + (_theResult____h500713[20] ? 6'd36 : - (_theResult____h500746[19] ? + (_theResult____h500713[19] ? 6'd37 : - (_theResult____h500746[18] ? + (_theResult____h500713[18] ? 6'd38 : - (_theResult____h500746[17] ? + (_theResult____h500713[17] ? 6'd39 : - (_theResult____h500746[16] ? + (_theResult____h500713[16] ? 6'd40 : - (_theResult____h500746[15] ? + (_theResult____h500713[15] ? 6'd41 : - (_theResult____h500746[14] ? + (_theResult____h500713[14] ? 6'd42 : - (_theResult____h500746[13] ? + (_theResult____h500713[13] ? 6'd43 : - (_theResult____h500746[12] ? + (_theResult____h500713[12] ? 6'd44 : - (_theResult____h500746[11] ? + (_theResult____h500713[11] ? 6'd45 : - (_theResult____h500746[10] ? + (_theResult____h500713[10] ? 6'd46 : - (_theResult____h500746[9] ? + (_theResult____h500713[9] ? 6'd47 : - (_theResult____h500746[8] ? + (_theResult____h500713[8] ? 6'd48 : - (_theResult____h500746[7] ? + (_theResult____h500713[7] ? 6'd49 : - (_theResult____h500746[6] ? + (_theResult____h500713[6] ? 6'd50 : - (_theResult____h500746[5] ? + (_theResult____h500713[5] ? 6'd51 : - (_theResult____h500746[4] ? + (_theResult____h500713[4] ? 6'd52 : - (_theResult____h500746[3] ? + (_theResult____h500713[3] ? 6'd53 : - (_theResult____h500746[2] ? + (_theResult____h500713[2] ? 6'd54 : - (_theResult____h500746[1] ? + (_theResult____h500713[1] ? 6'd55 : - (_theResult____h500746[0] ? + (_theResult____h500713[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 = - (_theResult____h578903[56] ? + (_theResult____h578870[56] ? 6'd0 : - (_theResult____h578903[55] ? + (_theResult____h578870[55] ? 6'd1 : - (_theResult____h578903[54] ? + (_theResult____h578870[54] ? 6'd2 : - (_theResult____h578903[53] ? + (_theResult____h578870[53] ? 6'd3 : - (_theResult____h578903[52] ? + (_theResult____h578870[52] ? 6'd4 : - (_theResult____h578903[51] ? + (_theResult____h578870[51] ? 6'd5 : - (_theResult____h578903[50] ? + (_theResult____h578870[50] ? 6'd6 : - (_theResult____h578903[49] ? + (_theResult____h578870[49] ? 6'd7 : - (_theResult____h578903[48] ? + (_theResult____h578870[48] ? 6'd8 : - (_theResult____h578903[47] ? + (_theResult____h578870[47] ? 6'd9 : - (_theResult____h578903[46] ? + (_theResult____h578870[46] ? 6'd10 : - (_theResult____h578903[45] ? + (_theResult____h578870[45] ? 6'd11 : - (_theResult____h578903[44] ? + (_theResult____h578870[44] ? 6'd12 : - (_theResult____h578903[43] ? + (_theResult____h578870[43] ? 6'd13 : - (_theResult____h578903[42] ? + (_theResult____h578870[42] ? 6'd14 : - (_theResult____h578903[41] ? + (_theResult____h578870[41] ? 6'd15 : - (_theResult____h578903[40] ? + (_theResult____h578870[40] ? 6'd16 : - (_theResult____h578903[39] ? + (_theResult____h578870[39] ? 6'd17 : - (_theResult____h578903[38] ? + (_theResult____h578870[38] ? 6'd18 : - (_theResult____h578903[37] ? + (_theResult____h578870[37] ? 6'd19 : - (_theResult____h578903[36] ? + (_theResult____h578870[36] ? 6'd20 : - (_theResult____h578903[35] ? + (_theResult____h578870[35] ? 6'd21 : - (_theResult____h578903[34] ? + (_theResult____h578870[34] ? 6'd22 : - (_theResult____h578903[33] ? + (_theResult____h578870[33] ? 6'd23 : - (_theResult____h578903[32] ? + (_theResult____h578870[32] ? 6'd24 : - (_theResult____h578903[31] ? + (_theResult____h578870[31] ? 6'd25 : - (_theResult____h578903[30] ? + (_theResult____h578870[30] ? 6'd26 : - (_theResult____h578903[29] ? + (_theResult____h578870[29] ? 6'd27 : - (_theResult____h578903[28] ? + (_theResult____h578870[28] ? 6'd28 : - (_theResult____h578903[27] ? + (_theResult____h578870[27] ? 6'd29 : - (_theResult____h578903[26] ? + (_theResult____h578870[26] ? 6'd30 : - (_theResult____h578903[25] ? + (_theResult____h578870[25] ? 6'd31 : - (_theResult____h578903[24] ? + (_theResult____h578870[24] ? 6'd32 : - (_theResult____h578903[23] ? + (_theResult____h578870[23] ? 6'd33 : - (_theResult____h578903[22] ? + (_theResult____h578870[22] ? 6'd34 : - (_theResult____h578903[21] ? + (_theResult____h578870[21] ? 6'd35 : - (_theResult____h578903[20] ? + (_theResult____h578870[20] ? 6'd36 : - (_theResult____h578903[19] ? + (_theResult____h578870[19] ? 6'd37 : - (_theResult____h578903[18] ? + (_theResult____h578870[18] ? 6'd38 : - (_theResult____h578903[17] ? + (_theResult____h578870[17] ? 6'd39 : - (_theResult____h578903[16] ? + (_theResult____h578870[16] ? 6'd40 : - (_theResult____h578903[15] ? + (_theResult____h578870[15] ? 6'd41 : - (_theResult____h578903[14] ? + (_theResult____h578870[14] ? 6'd42 : - (_theResult____h578903[13] ? + (_theResult____h578870[13] ? 6'd43 : - (_theResult____h578903[12] ? + (_theResult____h578870[12] ? 6'd44 : - (_theResult____h578903[11] ? + (_theResult____h578870[11] ? 6'd45 : - (_theResult____h578903[10] ? + (_theResult____h578870[10] ? 6'd46 : - (_theResult____h578903[9] ? + (_theResult____h578870[9] ? 6'd47 : - (_theResult____h578903[8] ? + (_theResult____h578870[8] ? 6'd48 : - (_theResult____h578903[7] ? + (_theResult____h578870[7] ? 6'd49 : - (_theResult____h578903[6] ? + (_theResult____h578870[6] ? 6'd50 : - (_theResult____h578903[5] ? + (_theResult____h578870[5] ? 6'd51 : - (_theResult____h578903[4] ? + (_theResult____h578870[4] ? 6'd52 : - (_theResult____h578903[3] ? + (_theResult____h578870[3] ? 6'd53 : - (_theResult____h578903[2] ? + (_theResult____h578870[2] ? 6'd54 : - (_theResult____h578903[1] ? + (_theResult____h578870[1] ? 6'd55 : - (_theResult____h578903[0] ? + (_theResult____h578870[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h361601[56] ? + (_theResult____h361568[56] ? 6'd0 : - (_theResult____h361601[55] ? + (_theResult____h361568[55] ? 6'd1 : - (_theResult____h361601[54] ? + (_theResult____h361568[54] ? 6'd2 : - (_theResult____h361601[53] ? + (_theResult____h361568[53] ? 6'd3 : - (_theResult____h361601[52] ? + (_theResult____h361568[52] ? 6'd4 : - (_theResult____h361601[51] ? + (_theResult____h361568[51] ? 6'd5 : - (_theResult____h361601[50] ? + (_theResult____h361568[50] ? 6'd6 : - (_theResult____h361601[49] ? + (_theResult____h361568[49] ? 6'd7 : - (_theResult____h361601[48] ? + (_theResult____h361568[48] ? 6'd8 : - (_theResult____h361601[47] ? + (_theResult____h361568[47] ? 6'd9 : - (_theResult____h361601[46] ? + (_theResult____h361568[46] ? 6'd10 : - (_theResult____h361601[45] ? + (_theResult____h361568[45] ? 6'd11 : - (_theResult____h361601[44] ? + (_theResult____h361568[44] ? 6'd12 : - (_theResult____h361601[43] ? + (_theResult____h361568[43] ? 6'd13 : - (_theResult____h361601[42] ? + (_theResult____h361568[42] ? 6'd14 : - (_theResult____h361601[41] ? + (_theResult____h361568[41] ? 6'd15 : - (_theResult____h361601[40] ? + (_theResult____h361568[40] ? 6'd16 : - (_theResult____h361601[39] ? + (_theResult____h361568[39] ? 6'd17 : - (_theResult____h361601[38] ? + (_theResult____h361568[38] ? 6'd18 : - (_theResult____h361601[37] ? + (_theResult____h361568[37] ? 6'd19 : - (_theResult____h361601[36] ? + (_theResult____h361568[36] ? 6'd20 : - (_theResult____h361601[35] ? + (_theResult____h361568[35] ? 6'd21 : - (_theResult____h361601[34] ? + (_theResult____h361568[34] ? 6'd22 : - (_theResult____h361601[33] ? + (_theResult____h361568[33] ? 6'd23 : - (_theResult____h361601[32] ? + (_theResult____h361568[32] ? 6'd24 : - (_theResult____h361601[31] ? + (_theResult____h361568[31] ? 6'd25 : - (_theResult____h361601[30] ? + (_theResult____h361568[30] ? 6'd26 : - (_theResult____h361601[29] ? + (_theResult____h361568[29] ? 6'd27 : - (_theResult____h361601[28] ? + (_theResult____h361568[28] ? 6'd28 : - (_theResult____h361601[27] ? + (_theResult____h361568[27] ? 6'd29 : - (_theResult____h361601[26] ? + (_theResult____h361568[26] ? 6'd30 : - (_theResult____h361601[25] ? + (_theResult____h361568[25] ? 6'd31 : - (_theResult____h361601[24] ? + (_theResult____h361568[24] ? 6'd32 : - (_theResult____h361601[23] ? + (_theResult____h361568[23] ? 6'd33 : - (_theResult____h361601[22] ? + (_theResult____h361568[22] ? 6'd34 : - (_theResult____h361601[21] ? + (_theResult____h361568[21] ? 6'd35 : - (_theResult____h361601[20] ? + (_theResult____h361568[20] ? 6'd36 : - (_theResult____h361601[19] ? + (_theResult____h361568[19] ? 6'd37 : - (_theResult____h361601[18] ? + (_theResult____h361568[18] ? 6'd38 : - (_theResult____h361601[17] ? + (_theResult____h361568[17] ? 6'd39 : - (_theResult____h361601[16] ? + (_theResult____h361568[16] ? 6'd40 : - (_theResult____h361601[15] ? + (_theResult____h361568[15] ? 6'd41 : - (_theResult____h361601[14] ? + (_theResult____h361568[14] ? 6'd42 : - (_theResult____h361601[13] ? + (_theResult____h361568[13] ? 6'd43 : - (_theResult____h361601[12] ? + (_theResult____h361568[12] ? 6'd44 : - (_theResult____h361601[11] ? + (_theResult____h361568[11] ? 6'd45 : - (_theResult____h361601[10] ? + (_theResult____h361568[10] ? 6'd46 : - (_theResult____h361601[9] ? + (_theResult____h361568[9] ? 6'd47 : - (_theResult____h361601[8] ? + (_theResult____h361568[8] ? 6'd48 : - (_theResult____h361601[7] ? + (_theResult____h361568[7] ? 6'd49 : - (_theResult____h361601[6] ? + (_theResult____h361568[6] ? 6'd50 : - (_theResult____h361601[5] ? + (_theResult____h361568[5] ? 6'd51 : - (_theResult____h361601[4] ? + (_theResult____h361568[4] ? 6'd52 : - (_theResult____h361601[3] ? + (_theResult____h361568[3] ? 6'd53 : - (_theResult____h361601[2] ? + (_theResult____h361568[2] ? 6'd54 : - (_theResult____h361601[1] ? + (_theResult____h361568[1] ? 6'd55 : - (_theResult____h361601[0] ? + (_theResult____h361568[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h407298[56] ? + (_theResult____h407265[56] ? 6'd0 : - (_theResult____h407298[55] ? + (_theResult____h407265[55] ? 6'd1 : - (_theResult____h407298[54] ? + (_theResult____h407265[54] ? 6'd2 : - (_theResult____h407298[53] ? + (_theResult____h407265[53] ? 6'd3 : - (_theResult____h407298[52] ? + (_theResult____h407265[52] ? 6'd4 : - (_theResult____h407298[51] ? + (_theResult____h407265[51] ? 6'd5 : - (_theResult____h407298[50] ? + (_theResult____h407265[50] ? 6'd6 : - (_theResult____h407298[49] ? + (_theResult____h407265[49] ? 6'd7 : - (_theResult____h407298[48] ? + (_theResult____h407265[48] ? 6'd8 : - (_theResult____h407298[47] ? + (_theResult____h407265[47] ? 6'd9 : - (_theResult____h407298[46] ? + (_theResult____h407265[46] ? 6'd10 : - (_theResult____h407298[45] ? + (_theResult____h407265[45] ? 6'd11 : - (_theResult____h407298[44] ? + (_theResult____h407265[44] ? 6'd12 : - (_theResult____h407298[43] ? + (_theResult____h407265[43] ? 6'd13 : - (_theResult____h407298[42] ? + (_theResult____h407265[42] ? 6'd14 : - (_theResult____h407298[41] ? + (_theResult____h407265[41] ? 6'd15 : - (_theResult____h407298[40] ? + (_theResult____h407265[40] ? 6'd16 : - (_theResult____h407298[39] ? + (_theResult____h407265[39] ? 6'd17 : - (_theResult____h407298[38] ? + (_theResult____h407265[38] ? 6'd18 : - (_theResult____h407298[37] ? + (_theResult____h407265[37] ? 6'd19 : - (_theResult____h407298[36] ? + (_theResult____h407265[36] ? 6'd20 : - (_theResult____h407298[35] ? + (_theResult____h407265[35] ? 6'd21 : - (_theResult____h407298[34] ? + (_theResult____h407265[34] ? 6'd22 : - (_theResult____h407298[33] ? + (_theResult____h407265[33] ? 6'd23 : - (_theResult____h407298[32] ? + (_theResult____h407265[32] ? 6'd24 : - (_theResult____h407298[31] ? + (_theResult____h407265[31] ? 6'd25 : - (_theResult____h407298[30] ? + (_theResult____h407265[30] ? 6'd26 : - (_theResult____h407298[29] ? + (_theResult____h407265[29] ? 6'd27 : - (_theResult____h407298[28] ? + (_theResult____h407265[28] ? 6'd28 : - (_theResult____h407298[27] ? + (_theResult____h407265[27] ? 6'd29 : - (_theResult____h407298[26] ? + (_theResult____h407265[26] ? 6'd30 : - (_theResult____h407298[25] ? + (_theResult____h407265[25] ? 6'd31 : - (_theResult____h407298[24] ? + (_theResult____h407265[24] ? 6'd32 : - (_theResult____h407298[23] ? + (_theResult____h407265[23] ? 6'd33 : - (_theResult____h407298[22] ? + (_theResult____h407265[22] ? 6'd34 : - (_theResult____h407298[21] ? + (_theResult____h407265[21] ? 6'd35 : - (_theResult____h407298[20] ? + (_theResult____h407265[20] ? 6'd36 : - (_theResult____h407298[19] ? + (_theResult____h407265[19] ? 6'd37 : - (_theResult____h407298[18] ? + (_theResult____h407265[18] ? 6'd38 : - (_theResult____h407298[17] ? + (_theResult____h407265[17] ? 6'd39 : - (_theResult____h407298[16] ? + (_theResult____h407265[16] ? 6'd40 : - (_theResult____h407298[15] ? + (_theResult____h407265[15] ? 6'd41 : - (_theResult____h407298[14] ? + (_theResult____h407265[14] ? 6'd42 : - (_theResult____h407298[13] ? + (_theResult____h407265[13] ? 6'd43 : - (_theResult____h407298[12] ? + (_theResult____h407265[12] ? 6'd44 : - (_theResult____h407298[11] ? + (_theResult____h407265[11] ? 6'd45 : - (_theResult____h407298[10] ? + (_theResult____h407265[10] ? 6'd46 : - (_theResult____h407298[9] ? + (_theResult____h407265[9] ? 6'd47 : - (_theResult____h407298[8] ? + (_theResult____h407265[8] ? 6'd48 : - (_theResult____h407298[7] ? + (_theResult____h407265[7] ? 6'd49 : - (_theResult____h407298[6] ? + (_theResult____h407265[6] ? 6'd50 : - (_theResult____h407298[5] ? + (_theResult____h407265[5] ? 6'd51 : - (_theResult____h407298[4] ? + (_theResult____h407265[4] ? 6'd52 : - (_theResult____h407298[3] ? + (_theResult____h407265[3] ? 6'd53 : - (_theResult____h407298[2] ? + (_theResult____h407265[2] ? 6'd54 : - (_theResult____h407298[1] ? + (_theResult____h407265[1] ? 6'd55 : - (_theResult____h407298[0] ? + (_theResult____h407265[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452993[56] ? + (_theResult____h452960[56] ? 6'd0 : - (_theResult____h452993[55] ? + (_theResult____h452960[55] ? 6'd1 : - (_theResult____h452993[54] ? + (_theResult____h452960[54] ? 6'd2 : - (_theResult____h452993[53] ? + (_theResult____h452960[53] ? 6'd3 : - (_theResult____h452993[52] ? + (_theResult____h452960[52] ? 6'd4 : - (_theResult____h452993[51] ? + (_theResult____h452960[51] ? 6'd5 : - (_theResult____h452993[50] ? + (_theResult____h452960[50] ? 6'd6 : - (_theResult____h452993[49] ? + (_theResult____h452960[49] ? 6'd7 : - (_theResult____h452993[48] ? + (_theResult____h452960[48] ? 6'd8 : - (_theResult____h452993[47] ? + (_theResult____h452960[47] ? 6'd9 : - (_theResult____h452993[46] ? + (_theResult____h452960[46] ? 6'd10 : - (_theResult____h452993[45] ? + (_theResult____h452960[45] ? 6'd11 : - (_theResult____h452993[44] ? + (_theResult____h452960[44] ? 6'd12 : - (_theResult____h452993[43] ? + (_theResult____h452960[43] ? 6'd13 : - (_theResult____h452993[42] ? + (_theResult____h452960[42] ? 6'd14 : - (_theResult____h452993[41] ? + (_theResult____h452960[41] ? 6'd15 : - (_theResult____h452993[40] ? + (_theResult____h452960[40] ? 6'd16 : - (_theResult____h452993[39] ? + (_theResult____h452960[39] ? 6'd17 : - (_theResult____h452993[38] ? + (_theResult____h452960[38] ? 6'd18 : - (_theResult____h452993[37] ? + (_theResult____h452960[37] ? 6'd19 : - (_theResult____h452993[36] ? + (_theResult____h452960[36] ? 6'd20 : - (_theResult____h452993[35] ? + (_theResult____h452960[35] ? 6'd21 : - (_theResult____h452993[34] ? + (_theResult____h452960[34] ? 6'd22 : - (_theResult____h452993[33] ? + (_theResult____h452960[33] ? 6'd23 : - (_theResult____h452993[32] ? + (_theResult____h452960[32] ? 6'd24 : - (_theResult____h452993[31] ? + (_theResult____h452960[31] ? 6'd25 : - (_theResult____h452993[30] ? + (_theResult____h452960[30] ? 6'd26 : - (_theResult____h452993[29] ? + (_theResult____h452960[29] ? 6'd27 : - (_theResult____h452993[28] ? + (_theResult____h452960[28] ? 6'd28 : - (_theResult____h452993[27] ? + (_theResult____h452960[27] ? 6'd29 : - (_theResult____h452993[26] ? + (_theResult____h452960[26] ? 6'd30 : - (_theResult____h452993[25] ? + (_theResult____h452960[25] ? 6'd31 : - (_theResult____h452993[24] ? + (_theResult____h452960[24] ? 6'd32 : - (_theResult____h452993[23] ? + (_theResult____h452960[23] ? 6'd33 : - (_theResult____h452993[22] ? + (_theResult____h452960[22] ? 6'd34 : - (_theResult____h452993[21] ? + (_theResult____h452960[21] ? 6'd35 : - (_theResult____h452993[20] ? + (_theResult____h452960[20] ? 6'd36 : - (_theResult____h452993[19] ? + (_theResult____h452960[19] ? 6'd37 : - (_theResult____h452993[18] ? + (_theResult____h452960[18] ? 6'd38 : - (_theResult____h452993[17] ? + (_theResult____h452960[17] ? 6'd39 : - (_theResult____h452993[16] ? + (_theResult____h452960[16] ? 6'd40 : - (_theResult____h452993[15] ? + (_theResult____h452960[15] ? 6'd41 : - (_theResult____h452993[14] ? + (_theResult____h452960[14] ? 6'd42 : - (_theResult____h452993[13] ? + (_theResult____h452960[13] ? 6'd43 : - (_theResult____h452993[12] ? + (_theResult____h452960[12] ? 6'd44 : - (_theResult____h452993[11] ? + (_theResult____h452960[11] ? 6'd45 : - (_theResult____h452993[10] ? + (_theResult____h452960[10] ? 6'd46 : - (_theResult____h452993[9] ? + (_theResult____h452960[9] ? 6'd47 : - (_theResult____h452993[8] ? + (_theResult____h452960[8] ? 6'd48 : - (_theResult____h452993[7] ? + (_theResult____h452960[7] ? 6'd49 : - (_theResult____h452993[6] ? + (_theResult____h452960[6] ? 6'd50 : - (_theResult____h452993[5] ? + (_theResult____h452960[5] ? 6'd51 : - (_theResult____h452993[4] ? + (_theResult____h452960[4] ? 6'd52 : - (_theResult____h452993[3] ? + (_theResult____h452960[3] ? 6'd53 : - (_theResult____h452993[2] ? + (_theResult____h452960[2] ? 6'd54 : - (_theResult____h452993[1] ? + (_theResult____h452960[1] ? 6'd55 : - (_theResult____h452993[0] ? + (_theResult____h452960[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10421 = - (_theResult___fst_exp__h547835 == 11'd2047) ? + (_theResult___fst_exp__h547802 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20496,10 +20496,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10688 = - (_theResult___fst_exp__h547835 == 11'd2047) ? + (_theResult___fst_exp__h547802 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20507,10 +20507,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8936 = - (_theResult___fst_exp__h508982 == 11'd2047) ? + (_theResult___fst_exp__h508949 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20518,10 +20518,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9651 = - (_theResult___fst_exp__h587139 == 11'd2047) ? + (_theResult___fst_exp__h587106 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20529,10 +20529,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9919 = - (_theResult___fst_exp__h587139 == 11'd2047) ? + (_theResult___fst_exp__h587106 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20540,538 +20540,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343972 == 2'b0 || + (guard__h343939 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h352073 : - _theResult___exp__h352589 ; + _theResult___fst_exp__h352040 : + _theResult___exp__h352556 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343972 == 2'b0) ? - _theResult___fst_exp__h352073 : + (guard__h343939 == 2'b0) ? + _theResult___fst_exp__h352040 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h352589 : - _theResult___fst_exp__h352073) ; + _theResult___exp__h352556 : + _theResult___fst_exp__h352040) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343972 == 2'b0 || + (guard__h343939 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h352067[56:34] : - _theResult___sfd__h352590 ; + sfdin__h352034[56:34] : + _theResult___sfd__h352557 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343972 == 2'b0) ? - sfdin__h352067[56:34] : + (guard__h343939 == 2'b0) ? + sfdin__h352034[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h352590 : - sfdin__h352067[56:34]) ; + _theResult___sfd__h352557 : + sfdin__h352034[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389671 == 2'b0 || + (guard__h389638 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397770 : - _theResult___exp__h398286 ; + _theResult___fst_exp__h397737 : + _theResult___exp__h398253 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389671 == 2'b0) ? - _theResult___fst_exp__h397770 : + (guard__h389638 == 2'b0) ? + _theResult___fst_exp__h397737 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h398286 : - _theResult___fst_exp__h397770) ; + _theResult___exp__h398253 : + _theResult___fst_exp__h397737) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389671 == 2'b0 || + (guard__h389638 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397764[56:34] : - _theResult___sfd__h398287 ; + sfdin__h397731[56:34] : + _theResult___sfd__h398254 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389671 == 2'b0) ? - sfdin__h397764[56:34] : + (guard__h389638 == 2'b0) ? + sfdin__h397731[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h398287 : - sfdin__h397764[56:34]) ; + _theResult___sfd__h398254 : + sfdin__h397731[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h435366 == 2'b0 || + (guard__h435333 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h443465 : - _theResult___exp__h443981 ; + _theResult___fst_exp__h443432 : + _theResult___exp__h443948 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h435366 == 2'b0) ? - _theResult___fst_exp__h443465 : + (guard__h435333 == 2'b0) ? + _theResult___fst_exp__h443432 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443981 : - _theResult___fst_exp__h443465) ; + _theResult___exp__h443948 : + _theResult___fst_exp__h443432) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h435366 == 2'b0 || + (guard__h435333 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h443459[56:34] : - _theResult___sfd__h443982 ; + sfdin__h443426[56:34] : + _theResult___sfd__h443949 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h435366 == 2'b0) ? - sfdin__h443459[56:34] : + (guard__h435333 == 2'b0) ? + sfdin__h443426[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443982 : - sfdin__h443459[56:34]) ; + _theResult___sfd__h443949 : + sfdin__h443426[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 = - (guard__h539609 == 2'b0 || + (guard__h539576 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547835 : - _theResult___exp__h548564 ; + _theResult___fst_exp__h547802 : + _theResult___exp__h548531 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 = - (guard__h539609 == 2'b0) ? - _theResult___fst_exp__h547835 : + (guard__h539576 == 2'b0) ? + _theResult___fst_exp__h547802 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h548564 : - _theResult___fst_exp__h547835) ; + _theResult___exp__h548531 : + _theResult___fst_exp__h547802) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 = - (guard__h539609 == 2'b0 || + (guard__h539576 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547829[56:5] : - _theResult___sfd__h548565 ; + sfdin__h547796[56:5] : + _theResult___sfd__h548532 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 = - (guard__h539609 == 2'b0) ? - sfdin__h547829[56:5] : + (guard__h539576 == 2'b0) ? + sfdin__h547796[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h548565 : - sfdin__h547829[56:5]) ; + _theResult___sfd__h548532 : + sfdin__h547796[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 = - (guard__h500756 == 2'b0 || + (guard__h500723 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508982 : - _theResult___exp__h509711 ; + _theResult___fst_exp__h508949 : + _theResult___exp__h509678 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 = - (guard__h500756 == 2'b0) ? - _theResult___fst_exp__h508982 : + (guard__h500723 == 2'b0) ? + _theResult___fst_exp__h508949 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h509711 : - _theResult___fst_exp__h508982) ; + _theResult___exp__h509678 : + _theResult___fst_exp__h508949) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 = - (guard__h500756 == 2'b0 || + (guard__h500723 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508976[56:5] : - _theResult___sfd__h509712 ; + sfdin__h508943[56:5] : + _theResult___sfd__h509679 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 = - (guard__h500756 == 2'b0) ? - sfdin__h508976[56:5] : + (guard__h500723 == 2'b0) ? + sfdin__h508943[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h509712 : - sfdin__h508976[56:5]) ; + _theResult___sfd__h509679 : + sfdin__h508943[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 = - (guard__h578913 == 2'b0 || + (guard__h578880 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h587139 : - _theResult___exp__h587868 ; + _theResult___fst_exp__h587106 : + _theResult___exp__h587835 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 = - (guard__h578913 == 2'b0) ? - _theResult___fst_exp__h587139 : + (guard__h578880 == 2'b0) ? + _theResult___fst_exp__h587106 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h587868 : - _theResult___fst_exp__h587139) ; + _theResult___exp__h587835 : + _theResult___fst_exp__h587106) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 = - (guard__h578913 == 2'b0 || + (guard__h578880 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h587133[56:5] : - _theResult___sfd__h587869 ; + sfdin__h587100[56:5] : + _theResult___sfd__h587836 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 = - (guard__h578913 == 2'b0) ? - sfdin__h587133[56:5] : + (guard__h578880 == 2'b0) ? + sfdin__h587100[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h587869 : - sfdin__h587133[56:5]) ; + _theResult___sfd__h587836 : + sfdin__h587100[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h361611 == 2'b0 || + (guard__h361578 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369839 : - _theResult___exp__h370355 ; + _theResult___fst_exp__h369806 : + _theResult___exp__h370322 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h361611 == 2'b0) ? - _theResult___fst_exp__h369839 : + (guard__h361578 == 2'b0) ? + _theResult___fst_exp__h369806 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h370355 : - _theResult___fst_exp__h369839) ; + _theResult___exp__h370322 : + _theResult___fst_exp__h369806) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h361611 == 2'b0 || + (guard__h361578 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369833[56:34] : - _theResult___sfd__h370356 ; + sfdin__h369800[56:34] : + _theResult___sfd__h370323 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h361611 == 2'b0) ? - sfdin__h369833[56:34] : + (guard__h361578 == 2'b0) ? + sfdin__h369800[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h370356 : - sfdin__h369833[56:34]) ; + _theResult___sfd__h370323 : + sfdin__h369800[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h407308 == 2'b0 || + (guard__h407275 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h415536 : - _theResult___exp__h416052 ; + _theResult___fst_exp__h415503 : + _theResult___exp__h416019 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h407308 == 2'b0) ? - _theResult___fst_exp__h415536 : + (guard__h407275 == 2'b0) ? + _theResult___fst_exp__h415503 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h416052 : - _theResult___fst_exp__h415536) ; + _theResult___exp__h416019 : + _theResult___fst_exp__h415503) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h407308 == 2'b0 || + (guard__h407275 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h415530[56:34] : - _theResult___sfd__h416053 ; + sfdin__h415497[56:34] : + _theResult___sfd__h416020 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h407308 == 2'b0) ? - sfdin__h415530[56:34] : + (guard__h407275 == 2'b0) ? + sfdin__h415497[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h416053 : - sfdin__h415530[56:34]) ; + _theResult___sfd__h416020 : + sfdin__h415497[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h453003 == 2'b0 || + (guard__h452970 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h461231 : - _theResult___exp__h461747 ; + _theResult___fst_exp__h461198 : + _theResult___exp__h461714 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h453003 == 2'b0) ? - _theResult___fst_exp__h461231 : + (guard__h452970 == 2'b0) ? + _theResult___fst_exp__h461198 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461747 : - _theResult___fst_exp__h461231) ; + _theResult___exp__h461714 : + _theResult___fst_exp__h461198) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h453003 == 2'b0 || + (guard__h452970 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h461225[56:34] : - _theResult___sfd__h461748 ; + sfdin__h461192[56:34] : + _theResult___sfd__h461715 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h453003 == 2'b0) ? - sfdin__h461225[56:34] : + (guard__h452970 == 2'b0) ? + sfdin__h461192[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461748 : - sfdin__h461225[56:34]) ; + _theResult___sfd__h461715 : + sfdin__h461192[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 = - (guard__h530297 == 2'b0 || + (guard__h530264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h538258 : - _theResult___exp__h538913 ; + _theResult___fst_exp__h538225 : + _theResult___exp__h538880 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 = - (guard__h530297 == 2'b0) ? - _theResult___fst_exp__h538258 : + (guard__h530264 == 2'b0) ? + _theResult___fst_exp__h538225 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h538913 : - _theResult___fst_exp__h538258) ; + _theResult___exp__h538880 : + _theResult___fst_exp__h538225) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 = - (guard__h548678 == 2'b0 || + (guard__h548645 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h556668 : - _theResult___exp__h557348 ; + _theResult___fst_exp__h556635 : + _theResult___exp__h557315 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 = - (guard__h548678 == 2'b0) ? - _theResult___fst_exp__h556668 : + (guard__h548645 == 2'b0) ? + _theResult___fst_exp__h556635 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h557348 : - _theResult___fst_exp__h556668) ; + _theResult___exp__h557315 : + _theResult___fst_exp__h556635) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 = - (guard__h530297 == 2'b0 || + (guard__h530264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h538209[56:5] : - _theResult___sfd__h538914 ; + _theResult___snd__h538176[56:5] : + _theResult___sfd__h538881 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 = - (guard__h530297 == 2'b0) ? - _theResult___snd__h538209[56:5] : + (guard__h530264 == 2'b0) ? + _theResult___snd__h538176[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h538914 : - _theResult___snd__h538209[56:5]) ; + _theResult___sfd__h538881 : + _theResult___snd__h538176[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 = - (guard__h548678 == 2'b0 || + (guard__h548645 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h556614[56:5] : - _theResult___sfd__h557349 ; + _theResult___snd__h556581[56:5] : + _theResult___sfd__h557316 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 = - (guard__h548678 == 2'b0) ? - _theResult___snd__h556614[56:5] : + (guard__h548645 == 2'b0) ? + _theResult___snd__h556581[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h557349 : - _theResult___snd__h556614[56:5]) ; + _theResult___sfd__h557316 : + _theResult___snd__h556581[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 = - (guard__h491444 == 2'b0 || + (guard__h491411 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h499405 : - _theResult___exp__h500060 ; + _theResult___fst_exp__h499372 : + _theResult___exp__h500027 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 = - (guard__h491444 == 2'b0) ? - _theResult___fst_exp__h499405 : + (guard__h491411 == 2'b0) ? + _theResult___fst_exp__h499372 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h500060 : - _theResult___fst_exp__h499405) ; + _theResult___exp__h500027 : + _theResult___fst_exp__h499372) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 = - (guard__h509825 == 2'b0 || + (guard__h509792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517815 : - _theResult___exp__h518495 ; + _theResult___fst_exp__h517782 : + _theResult___exp__h518462 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 = - (guard__h509825 == 2'b0) ? - _theResult___fst_exp__h517815 : + (guard__h509792 == 2'b0) ? + _theResult___fst_exp__h517782 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h518495 : - _theResult___fst_exp__h517815) ; + _theResult___exp__h518462 : + _theResult___fst_exp__h517782) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 = - (guard__h491444 == 2'b0 || + (guard__h491411 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h499356[56:5] : - _theResult___sfd__h500061 ; + _theResult___snd__h499323[56:5] : + _theResult___sfd__h500028 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 = - (guard__h491444 == 2'b0) ? - _theResult___snd__h499356[56:5] : + (guard__h491411 == 2'b0) ? + _theResult___snd__h499323[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h500061 : - _theResult___snd__h499356[56:5]) ; + _theResult___sfd__h500028 : + _theResult___snd__h499323[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 = - (guard__h509825 == 2'b0 || + (guard__h509792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517761[56:5] : - _theResult___sfd__h518496 ; + _theResult___snd__h517728[56:5] : + _theResult___sfd__h518463 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 = - (guard__h509825 == 2'b0) ? - _theResult___snd__h517761[56:5] : + (guard__h509792 == 2'b0) ? + _theResult___snd__h517728[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h518496 : - _theResult___snd__h517761[56:5]) ; + _theResult___sfd__h518463 : + _theResult___snd__h517728[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 = - (guard__h569601 == 2'b0 || + (guard__h569568 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h577562 : - _theResult___exp__h578217 ; + _theResult___fst_exp__h577529 : + _theResult___exp__h578184 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 = - (guard__h569601 == 2'b0) ? - _theResult___fst_exp__h577562 : + (guard__h569568 == 2'b0) ? + _theResult___fst_exp__h577529 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h578217 : - _theResult___fst_exp__h577562) ; + _theResult___exp__h578184 : + _theResult___fst_exp__h577529) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 = - (guard__h587982 == 2'b0 || + (guard__h587949 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595972 : - _theResult___exp__h596652 ; + _theResult___fst_exp__h595939 : + _theResult___exp__h596619 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 = - (guard__h587982 == 2'b0) ? - _theResult___fst_exp__h595972 : + (guard__h587949 == 2'b0) ? + _theResult___fst_exp__h595939 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h596652 : - _theResult___fst_exp__h595972) ; + _theResult___exp__h596619 : + _theResult___fst_exp__h595939) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 = - (guard__h569601 == 2'b0 || + (guard__h569568 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h577513[56:5] : - _theResult___sfd__h578218 ; + _theResult___snd__h577480[56:5] : + _theResult___sfd__h578185 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 = - (guard__h569601 == 2'b0) ? - _theResult___snd__h577513[56:5] : + (guard__h569568 == 2'b0) ? + _theResult___snd__h577480[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h578218 : - _theResult___snd__h577513[56:5]) ; + _theResult___sfd__h578185 : + _theResult___snd__h577480[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 = - (guard__h587982 == 2'b0 || + (guard__h587949 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595918[56:5] : - _theResult___sfd__h596653 ; + _theResult___snd__h595885[56:5] : + _theResult___sfd__h596620 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 = - (guard__h587982 == 2'b0) ? - _theResult___snd__h595918[56:5] : + (guard__h587949 == 2'b0) ? + _theResult___snd__h595885[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h596653 : - _theResult___snd__h595918[56:5]) ; + _theResult___sfd__h596620 : + _theResult___snd__h595885[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352681 == 2'b0 || + (guard__h352648 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360729 : - _theResult___exp__h361171 ; + _theResult___fst_exp__h360696 : + _theResult___exp__h361138 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352681 == 2'b0) ? - _theResult___fst_exp__h360729 : + (guard__h352648 == 2'b0) ? + _theResult___fst_exp__h360696 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h361171 : - _theResult___fst_exp__h360729) ; + _theResult___exp__h361138 : + _theResult___fst_exp__h360696) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h370447 == 2'b0 || + (guard__h370414 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h378524 : - _theResult___exp__h378991 ; + _theResult___fst_exp__h378491 : + _theResult___exp__h378958 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h370447 == 2'b0) ? - _theResult___fst_exp__h378524 : + (guard__h370414 == 2'b0) ? + _theResult___fst_exp__h378491 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378991 : - _theResult___fst_exp__h378524) ; + _theResult___exp__h378958 : + _theResult___fst_exp__h378491) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352681 == 2'b0 || + (guard__h352648 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360680[56:34] : - _theResult___sfd__h361172 ; + _theResult___snd__h360647[56:34] : + _theResult___sfd__h361139 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352681 == 2'b0) ? - _theResult___snd__h360680[56:34] : + (guard__h352648 == 2'b0) ? + _theResult___snd__h360647[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h361172 : - _theResult___snd__h360680[56:34]) ; + _theResult___sfd__h361139 : + _theResult___snd__h360647[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h370447 == 2'b0 || + (guard__h370414 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h378470[56:34] : - _theResult___sfd__h378992 ; + _theResult___snd__h378437[56:34] : + _theResult___sfd__h378959 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h370447 == 2'b0) ? - _theResult___snd__h378470[56:34] : + (guard__h370414 == 2'b0) ? + _theResult___snd__h378437[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378992 : - _theResult___snd__h378470[56:34]) ; + _theResult___sfd__h378959 : + _theResult___snd__h378437[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h398378 == 2'b0 || + (guard__h398345 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h406426 : - _theResult___exp__h406868 ; + _theResult___fst_exp__h406393 : + _theResult___exp__h406835 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h398378 == 2'b0) ? - _theResult___fst_exp__h406426 : + (guard__h398345 == 2'b0) ? + _theResult___fst_exp__h406393 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406868 : - _theResult___fst_exp__h406426) ; + _theResult___exp__h406835 : + _theResult___fst_exp__h406393) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h416144 == 2'b0 || + (guard__h416111 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h424221 : - _theResult___exp__h424688 ; + _theResult___fst_exp__h424188 : + _theResult___exp__h424655 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h416144 == 2'b0) ? - _theResult___fst_exp__h424221 : + (guard__h416111 == 2'b0) ? + _theResult___fst_exp__h424188 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424688 : - _theResult___fst_exp__h424221) ; + _theResult___exp__h424655 : + _theResult___fst_exp__h424188) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h398378 == 2'b0 || + (guard__h398345 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h406377[56:34] : - _theResult___sfd__h406869 ; + _theResult___snd__h406344[56:34] : + _theResult___sfd__h406836 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h398378 == 2'b0) ? - _theResult___snd__h406377[56:34] : + (guard__h398345 == 2'b0) ? + _theResult___snd__h406344[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406869 : - _theResult___snd__h406377[56:34]) ; + _theResult___sfd__h406836 : + _theResult___snd__h406344[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h416144 == 2'b0 || + (guard__h416111 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h424167[56:34] : - _theResult___sfd__h424689 ; + _theResult___snd__h424134[56:34] : + _theResult___sfd__h424656 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h416144 == 2'b0) ? - _theResult___snd__h424167[56:34] : + (guard__h416111 == 2'b0) ? + _theResult___snd__h424134[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424689 : - _theResult___snd__h424167[56:34]) ; + _theResult___sfd__h424656 : + _theResult___snd__h424134[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h444073 == 2'b0 || + (guard__h444040 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h452121 : - _theResult___exp__h452563 ; + _theResult___fst_exp__h452088 : + _theResult___exp__h452530 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h444073 == 2'b0) ? - _theResult___fst_exp__h452121 : + (guard__h444040 == 2'b0) ? + _theResult___fst_exp__h452088 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h452563 : - _theResult___fst_exp__h452121) ; + _theResult___exp__h452530 : + _theResult___fst_exp__h452088) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461839 == 2'b0 || + (guard__h461806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469916 : - _theResult___exp__h470383 ; + _theResult___fst_exp__h469883 : + _theResult___exp__h470350 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461839 == 2'b0) ? - _theResult___fst_exp__h469916 : + (guard__h461806 == 2'b0) ? + _theResult___fst_exp__h469883 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h470383 : - _theResult___fst_exp__h469916) ; + _theResult___exp__h470350 : + _theResult___fst_exp__h469883) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h444073 == 2'b0 || + (guard__h444040 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h452072[56:34] : - _theResult___sfd__h452564 ; + _theResult___snd__h452039[56:34] : + _theResult___sfd__h452531 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h444073 == 2'b0) ? - _theResult___snd__h452072[56:34] : + (guard__h444040 == 2'b0) ? + _theResult___snd__h452039[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h452564 : - _theResult___snd__h452072[56:34]) ; + _theResult___sfd__h452531 : + _theResult___snd__h452039[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461839 == 2'b0 || + (guard__h461806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469862[56:34] : - _theResult___sfd__h470384 ; + _theResult___snd__h469829[56:34] : + _theResult___sfd__h470351 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461839 == 2'b0) ? - _theResult___snd__h469862[56:34] : + (guard__h461806 == 2'b0) ? + _theResult___snd__h469829[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h470384 : - _theResult___snd__h469862[56:34]) ; + _theResult___sfd__h470351 : + _theResult___snd__h469829[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467 = - (_theResult___fst_exp__h556668 == 11'd2047) ? + (_theResult___fst_exp__h556635 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21079,10 +21079,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10673 = - (_theResult___fst_exp__h538258 == 11'd2047) ? + (_theResult___fst_exp__h538225 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21090,10 +21090,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10700 = - (_theResult___fst_exp__h556668 == 11'd2047) ? + (_theResult___fst_exp__h556635 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21101,10 +21101,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8982 = - (_theResult___fst_exp__h517815 == 11'd2047) ? + (_theResult___fst_exp__h517782 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21112,10 +21112,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697 = - (_theResult___fst_exp__h595972 == 11'd2047) ? + (_theResult___fst_exp__h595939 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21123,10 +21123,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904 = - (_theResult___fst_exp__h577562 == 11'd2047) ? + (_theResult___fst_exp__h577529 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21134,10 +21134,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931 = - (_theResult___fst_exp__h595972 == 11'd2047) ? + (_theResult___fst_exp__h595939 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21145,146 +21145,146 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771 = - (_theResult____h647786 == 16'd0 && + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767 = + (_theResult____h647726 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h648358 : - _theResult____h647786 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981 || + enabled_ints__h648298 : + _theResult____h647726 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 || fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d13619[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d13615[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 = - ((f2_exp__h519011 == 8'd0) ? - (f2_sfd__h519012[22] ? + ((f2_exp__h518978 == 8'd0) ? + (f2_sfd__h518979[22] ? 6'd2 : - (f2_sfd__h519012[21] ? + (f2_sfd__h518979[21] ? 6'd3 : - (f2_sfd__h519012[20] ? + (f2_sfd__h518979[20] ? 6'd4 : - (f2_sfd__h519012[19] ? + (f2_sfd__h518979[19] ? 6'd5 : - (f2_sfd__h519012[18] ? + (f2_sfd__h518979[18] ? 6'd6 : - (f2_sfd__h519012[17] ? + (f2_sfd__h518979[17] ? 6'd7 : - (f2_sfd__h519012[16] ? + (f2_sfd__h518979[16] ? 6'd8 : - (f2_sfd__h519012[15] ? + (f2_sfd__h518979[15] ? 6'd9 : - (f2_sfd__h519012[14] ? + (f2_sfd__h518979[14] ? 6'd10 : - (f2_sfd__h519012[13] ? + (f2_sfd__h518979[13] ? 6'd11 : - (f2_sfd__h519012[12] ? + (f2_sfd__h518979[12] ? 6'd12 : - (f2_sfd__h519012[11] ? + (f2_sfd__h518979[11] ? 6'd13 : - (f2_sfd__h519012[10] ? + (f2_sfd__h518979[10] ? 6'd14 : - (f2_sfd__h519012[9] ? + (f2_sfd__h518979[9] ? 6'd15 : - (f2_sfd__h519012[8] ? + (f2_sfd__h518979[8] ? 6'd16 : - (f2_sfd__h519012[7] ? + (f2_sfd__h518979[7] ? 6'd17 : - (f2_sfd__h519012[6] ? + (f2_sfd__h518979[6] ? 6'd18 : - (f2_sfd__h519012[5] ? + (f2_sfd__h518979[5] ? 6'd19 : - (f2_sfd__h519012[4] ? + (f2_sfd__h518979[4] ? 6'd20 : - (f2_sfd__h519012[3] ? + (f2_sfd__h518979[3] ? 6'd21 : - (f2_sfd__h519012[2] ? + (f2_sfd__h518979[2] ? 6'd22 : - (f2_sfd__h519012[1] ? + (f2_sfd__h518979[1] ? 6'd23 : - (f2_sfd__h519012[0] ? + (f2_sfd__h518979[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0 || - (f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 || + (f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h519011 == 8'd0) ? + ((f2_exp__h518978 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0) ? - _theResult___snd_fst_sfd__h519327 : - _theResult___fst_sfd__h557467 ; + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0) ? + _theResult___snd_fst_sfd__h519294 : + _theResult___fst_sfd__h557434 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649 = - { (f2_exp__h519011 == 8'd255) ? + { (f2_exp__h518978 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h557463, + _theResult___fst_exp__h557430, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21294,15 +21294,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0 || - (f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 || + (f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[4] : @@ -21310,7 +21310,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[4] : @@ -21318,7 +21318,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[4] : @@ -21326,7 +21326,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[3] : @@ -21334,7 +21334,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[3] : @@ -21342,7 +21342,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[3] : @@ -21350,211 +21350,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 = - ((f1_exp__h480017 == 8'd0) ? - (f1_sfd__h480018[22] ? + ((f1_exp__h479984 == 8'd0) ? + (f1_sfd__h479985[22] ? 6'd2 : - (f1_sfd__h480018[21] ? + (f1_sfd__h479985[21] ? 6'd3 : - (f1_sfd__h480018[20] ? + (f1_sfd__h479985[20] ? 6'd4 : - (f1_sfd__h480018[19] ? + (f1_sfd__h479985[19] ? 6'd5 : - (f1_sfd__h480018[18] ? + (f1_sfd__h479985[18] ? 6'd6 : - (f1_sfd__h480018[17] ? + (f1_sfd__h479985[17] ? 6'd7 : - (f1_sfd__h480018[16] ? + (f1_sfd__h479985[16] ? 6'd8 : - (f1_sfd__h480018[15] ? + (f1_sfd__h479985[15] ? 6'd9 : - (f1_sfd__h480018[14] ? + (f1_sfd__h479985[14] ? 6'd10 : - (f1_sfd__h480018[13] ? + (f1_sfd__h479985[13] ? 6'd11 : - (f1_sfd__h480018[12] ? + (f1_sfd__h479985[12] ? 6'd12 : - (f1_sfd__h480018[11] ? + (f1_sfd__h479985[11] ? 6'd13 : - (f1_sfd__h480018[10] ? + (f1_sfd__h479985[10] ? 6'd14 : - (f1_sfd__h480018[9] ? + (f1_sfd__h479985[9] ? 6'd15 : - (f1_sfd__h480018[8] ? + (f1_sfd__h479985[8] ? 6'd16 : - (f1_sfd__h480018[7] ? + (f1_sfd__h479985[7] ? 6'd17 : - (f1_sfd__h480018[6] ? + (f1_sfd__h479985[6] ? 6'd18 : - (f1_sfd__h480018[5] ? + (f1_sfd__h479985[5] ? 6'd19 : - (f1_sfd__h480018[4] ? + (f1_sfd__h479985[4] ? 6'd20 : - (f1_sfd__h480018[3] ? + (f1_sfd__h479985[3] ? 6'd21 : - (f1_sfd__h480018[2] ? + (f1_sfd__h479985[2] ? 6'd22 : - (f1_sfd__h480018[1] ? + (f1_sfd__h479985[1] ? 6'd23 : - (f1_sfd__h480018[0] ? + (f1_sfd__h479985[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986 = - (f1_exp__h480017 == 8'd255 && f1_sfd__h480018 != 23'd0 || - (f1_exp__h480017 == 8'd255 || f1_exp__h480017 == 8'd0) && - f1_sfd__h480018 == 23'd0) ? + (f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0 || + (f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) && + f1_sfd__h479985 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h480017 == 8'd0) ? + ((f1_exp__h479984 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8984) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 = - (f1_exp__h480017 == 8'd255 && f1_sfd__h480018 != 23'd0) ? - _theResult___snd_fst_sfd__h480333 : - _theResult___fst_sfd__h518614 ; + (f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0) ? + _theResult___snd_fst_sfd__h480300 : + _theResult___fst_sfd__h518581 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986, - (f1_exp__h480017 == 8'd255) ? + (f1_exp__h479984 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h518610, + _theResult___fst_exp__h518577, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 = - ((f3_exp__h558315 == 8'd0) ? - (f3_sfd__h558316[22] ? + ((f3_exp__h558282 == 8'd0) ? + (f3_sfd__h558283[22] ? 6'd2 : - (f3_sfd__h558316[21] ? + (f3_sfd__h558283[21] ? 6'd3 : - (f3_sfd__h558316[20] ? + (f3_sfd__h558283[20] ? 6'd4 : - (f3_sfd__h558316[19] ? + (f3_sfd__h558283[19] ? 6'd5 : - (f3_sfd__h558316[18] ? + (f3_sfd__h558283[18] ? 6'd6 : - (f3_sfd__h558316[17] ? + (f3_sfd__h558283[17] ? 6'd7 : - (f3_sfd__h558316[16] ? + (f3_sfd__h558283[16] ? 6'd8 : - (f3_sfd__h558316[15] ? + (f3_sfd__h558283[15] ? 6'd9 : - (f3_sfd__h558316[14] ? + (f3_sfd__h558283[14] ? 6'd10 : - (f3_sfd__h558316[13] ? + (f3_sfd__h558283[13] ? 6'd11 : - (f3_sfd__h558316[12] ? + (f3_sfd__h558283[12] ? 6'd12 : - (f3_sfd__h558316[11] ? + (f3_sfd__h558283[11] ? 6'd13 : - (f3_sfd__h558316[10] ? + (f3_sfd__h558283[10] ? 6'd14 : - (f3_sfd__h558316[9] ? + (f3_sfd__h558283[9] ? 6'd15 : - (f3_sfd__h558316[8] ? + (f3_sfd__h558283[8] ? 6'd16 : - (f3_sfd__h558316[7] ? + (f3_sfd__h558283[7] ? 6'd17 : - (f3_sfd__h558316[6] ? + (f3_sfd__h558283[6] ? 6'd18 : - (f3_sfd__h558316[5] ? + (f3_sfd__h558283[5] ? 6'd19 : - (f3_sfd__h558316[4] ? + (f3_sfd__h558283[4] ? 6'd20 : - (f3_sfd__h558316[3] ? + (f3_sfd__h558283[3] ? 6'd21 : - (f3_sfd__h558316[2] ? + (f3_sfd__h558283[2] ? 6'd22 : - (f3_sfd__h558316[1] ? + (f3_sfd__h558283[1] ? 6'd23 : - (f3_sfd__h558316[0] ? + (f3_sfd__h558283[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9701 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0 || - (f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 || + (f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h558315 == 8'd0) ? + ((f3_exp__h558282 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9699) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0) ? - _theResult___snd_fst_sfd__h558631 : - _theResult___fst_sfd__h596771 ; + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0) ? + _theResult___snd_fst_sfd__h558598 : + _theResult___fst_sfd__h596738 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 = - { (f3_exp__h558315 == 8'd255) ? + { (f3_exp__h558282 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h596767, + _theResult___fst_exp__h596734, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9934 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21564,9 +21564,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9933 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0 || - (f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 || + (f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21609,110 +21609,110 @@ module mkCore(CLK, (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ? 4'd1 : IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855) ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134 = + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd12 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd12) ? 4'd13 : 4'd15 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135 = + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd11 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd11) ? 4'd12 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd10 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd10) ? 4'd11 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd9 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd9) ? 4'd9 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd8 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd8) ? 4'd8 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd7 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd7) ? 4'd7 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd6 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd6) ? 4'd6 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd5 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd5) ? 4'd5 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd4 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd4) ? 4'd4 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd3 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd3) ? 4'd3 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd2 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd2) ? 4'd2 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd1 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd1) ? 4'd1 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd0 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd0) ? 4'd0 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145 ; + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 ; assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 = { (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 : @@ -21775,7 +21775,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 || - _theResult___fst_exp__h538258 == 11'd2047) ? + _theResult___fst_exp__h538225 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21783,12 +21783,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 || - _theResult___fst_exp__h499405 == 11'd2047) ? + _theResult___fst_exp__h499372 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21796,12 +21796,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 || - _theResult___fst_exp__h577562 == 11'd2047) ? + _theResult___fst_exp__h577529 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21809,139 +21809,139 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; - assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] ? + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ? 4'd0 : - (IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] ? + (IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ? 4'd1 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2]) ? 4'd2 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3]) ? 4'd3 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4]) ? 4'd4 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6]) ? 4'd5 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7]) ? 4'd6 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8]) ? 4'd7 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10]) ? 4'd8 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13]) ? 4'd9 : 4'd10))))))))) ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181 : + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 ? + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ? coreFix_aluExe_0_bypassWire_3$whas && coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213 : + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 ? + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ? coreFix_aluExe_0_bypassWire_3$whas && coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411 ; + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 ; assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ? @@ -21982,30 +21982,30 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_1_dispToRegQ$first[76:70] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11392 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765 ; + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 ; assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ? @@ -22199,102 +22199,102 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20 : CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 : + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836 : + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 ; - assign IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752 = + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ; + assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735 : + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) : - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750) ; - assign IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836 = - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660 ? - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 || + (regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) : + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746) ; + assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 = + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 ? + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 ; - assign IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219 = - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038 ? - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146 : + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ; + assign IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 ? + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd0 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd0) ? 4'd0 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd1 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd1) ? 4'd1 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd3 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd2) ? 4'd3 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd4 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd3) ? 4'd4 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd5 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd4) ? 4'd5 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd7 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd5) ? 4'd7 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd8 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd6) ? 4'd8 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd9 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd7) ? 4'd9 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd11 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd8) ? 4'd11 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd14 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197 = + assign IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -22333,48 +22333,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[2] : - _theResult___fst_exp__h518598 == 11'd2047 && - _theResult___fst_sfd__h518599 == 52'd0 ; + _theResult___fst_exp__h518565 == 11'd2047 && + _theResult___fst_sfd__h518566 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[2] : - _theResult___fst_exp__h557451 == 11'd2047 && - _theResult___fst_sfd__h557452 == 52'd0 ; + _theResult___fst_exp__h557418 == 11'd2047 && + _theResult___fst_sfd__h557419 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[2] : - _theResult___fst_exp__h596755 == 11'd2047 && - _theResult___fst_sfd__h596756 == 52'd0 ; + _theResult___fst_exp__h596722 == 11'd2047 && + _theResult___fst_sfd__h596723 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[1] : - _theResult___fst_exp__h517815 == 11'd0 && - guard__h509825 != 2'b0 ; + _theResult___fst_exp__h517782 == 11'd0 && + guard__h509792 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[1] : - _theResult___fst_exp__h556668 == 11'd0 && - guard__h548678 != 2'b0 ; + _theResult___fst_exp__h556635 == 11'd0 && + guard__h548645 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[1] : - _theResult___fst_exp__h595972 == 11'd0 && - guard__h587982 != 2'b0 ; + _theResult___fst_exp__h595939 == 11'd0 && + guard__h587949 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[0] : - _theResult___fst_exp__h517815 != 11'd2047 && - guard__h509825 != 2'b0 ; + _theResult___fst_exp__h517782 != 11'd2047 && + guard__h509792 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[0] : - _theResult___fst_exp__h556668 != 11'd2047 && - guard__h548678 != 2'b0 ; + _theResult___fst_exp__h556635 != 11'd2047 && + guard__h548645 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[0] : - _theResult___fst_exp__h595972 != 11'd2047 && - guard__h587982 != 2'b0 ; + _theResult___fst_exp__h595939 != 11'd2047 && + guard__h587949 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22420,35 +22420,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369839 == 8'd255) ? + ((_theResult___fst_exp__h369806 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h378524 == 8'd255) ? + ((_theResult___fst_exp__h378491 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369839 == 8'd255) ? + ((_theResult___fst_exp__h369806 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h378524 == 8'd255) ? + ((_theResult___fst_exp__h378491 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h379072 == 8'd255 && - _theResult___fst_sfd__h379073 == 23'd0 ; + _theResult___fst_exp__h379039 == 8'd255 && + _theResult___fst_sfd__h379040 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h378524 == 8'd0 && - guard__h370447 != 2'b0 ; + _theResult___fst_exp__h378491 == 8'd0 && + guard__h370414 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h378524 != 8'd255 && - guard__h370447 != 2'b0 ; + _theResult___fst_exp__h378491 != 8'd255 && + guard__h370414 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22458,35 +22458,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h415536 == 8'd255) ? + ((_theResult___fst_exp__h415503 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h424221 == 8'd255) ? + ((_theResult___fst_exp__h424188 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h415536 == 8'd255) ? + ((_theResult___fst_exp__h415503 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h424221 == 8'd255) ? + ((_theResult___fst_exp__h424188 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424769 == 8'd255 && - _theResult___fst_sfd__h424770 == 23'd0 ; + _theResult___fst_exp__h424736 == 8'd255 && + _theResult___fst_sfd__h424737 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h424221 == 8'd0 && - guard__h416144 != 2'b0 ; + _theResult___fst_exp__h424188 == 8'd0 && + guard__h416111 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h424221 != 8'd255 && - guard__h416144 != 2'b0 ; + _theResult___fst_exp__h424188 != 8'd255 && + guard__h416111 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22496,51 +22496,51 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h461231 == 8'd255) ? + ((_theResult___fst_exp__h461198 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469916 == 8'd255) ? + ((_theResult___fst_exp__h469883 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h461231 == 8'd255) ? + ((_theResult___fst_exp__h461198 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469916 == 8'd255) ? + ((_theResult___fst_exp__h469883 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h470464 == 8'd255 && - _theResult___fst_sfd__h470465 == 23'd0 ; + _theResult___fst_exp__h470431 == 8'd255 && + _theResult___fst_sfd__h470432 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469916 == 8'd0 && - guard__h461839 != 2'b0 ; + _theResult___fst_exp__h469883 == 8'd0 && + guard__h461806 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469916 != 8'd255 && - guard__h461839 != 2'b0 ; - assign IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 = - checkForException___d12946[4] ? - CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 : + _theResult___fst_exp__h469883 != 8'd255 && + guard__h461806 != 2'b0 ; + assign IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 = + checkForException___d12942[4] ? + CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || @@ -23183,10 +23183,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 } ; - assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 = + assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h643363 : - w__h643358 ; + result__h643303 : + w__h643298 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23208,39 +23208,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23293,7 +23293,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h195006 : + x__h194973 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -23305,7 +23305,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h294400 == v__h293820 ; + _theResult_____2__h294368 == v__h293788 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23314,7 +23314,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h302396 == v__h297165 ; + _theResult_____2__h302364 == v__h297133 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23343,7 +23343,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h300030 } ; + x__h299998 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -23441,35 +23441,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23497,7 +23497,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h308390 == v__h307679 ; + _theResult_____2__h308358 == v__h307647 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23506,7 +23506,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h316244 == v__h311555 ; + _theResult_____2__h316212 == v__h311523 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23658,7 +23658,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329813 == v__h329381 ; + _theResult_____2__h329781 == v__h329349 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -23707,7 +23707,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h326588 == v__h326156 ; + _theResult_____2__h326556 == v__h326124 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -23739,79 +23739,79 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h710124 : + upd__h710029 : csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365 = + assign IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 = + assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752 ; - assign IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 = + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 ; + assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660) ? - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 && - (IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 || + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656) ? + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 && + (IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875 = - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + assign IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055 = + assign IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 ? - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 : + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 ? + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 : { 1'h0, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 } } ; - assign IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 } } ; + assign IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969 = fetchStage$pipelines_0_first[173] ? - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 : + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 : 12'hCFF ; - assign IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005 = - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 && - (IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 || + assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 && + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 && + (IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 || rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999) ; - assign IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225 = + fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995) ; + assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179) ? - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 : + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175) ? + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 : { 1'h0, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 } ; - assign IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } ; + assign IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 ? - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 : + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 ? + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 : { 1'h0, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 } } ; + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -23836,58 +23836,58 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 = - rob$deqPort_0_canDeq ? y_avValue_fst__h712379 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 = + assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 = + rob$deqPort_0_canDeq ? y_avValue_fst__h712284 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h712827 : + y_avValue_snd_snd_snd_fst__h712732 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198 = + assign IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197 : + IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h508976[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h415530[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h443459[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h547829[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h352067[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h461225[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h369833[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h587133[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h397764[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h406377[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h517761[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h424167[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h538209[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h452072[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h556614[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h360680[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h469862[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h577513[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h378470[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h595918[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h499356[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h508943[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h415497[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h443426[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h547796[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h352034[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h461192[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h369800[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h587100[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h397731[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h406344[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h517728[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h424134[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h538176[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h452039[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h556581[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h360647[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h469829[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h577480[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h378437[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h595885[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h499323[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -23918,198 +23918,198 @@ module mkCore(CLK, (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[0] : _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[0]) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269 && + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 && (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d13619[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 = - (fflags__h714186 & csrf_fflags_reg) != fflags__h714186 || - !r__h610387 && - (IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198 || - fflags__h714186 != 5'd0) ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d13615[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 = + (fflags__h714091 & csrf_fflags_reg) != fflags__h714091 || + !r__h610340 && + (IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 || + fflags__h714091 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 = - !f2_sfd__h519012[21] && !f2_sfd__h519012[20] && - !f2_sfd__h519012[19] && - !f2_sfd__h519012[18] && - !f2_sfd__h519012[17] && - !f2_sfd__h519012[16] && - !f2_sfd__h519012[15] && - !f2_sfd__h519012[14] && - !f2_sfd__h519012[13] && - !f2_sfd__h519012[12] && - !f2_sfd__h519012[11] && - !f2_sfd__h519012[10] && - !f2_sfd__h519012[9] && - !f2_sfd__h519012[8] && - !f2_sfd__h519012[7] && - !f2_sfd__h519012[6] && - !f2_sfd__h519012[5] && - !f2_sfd__h519012[4] && - !f2_sfd__h519012[3] && - !f2_sfd__h519012[2] && - !f2_sfd__h519012[1] && - !f2_sfd__h519012[0] ; + !f2_sfd__h518979[21] && !f2_sfd__h518979[20] && + !f2_sfd__h518979[19] && + !f2_sfd__h518979[18] && + !f2_sfd__h518979[17] && + !f2_sfd__h518979[16] && + !f2_sfd__h518979[15] && + !f2_sfd__h518979[14] && + !f2_sfd__h518979[13] && + !f2_sfd__h518979[12] && + !f2_sfd__h518979[11] && + !f2_sfd__h518979[10] && + !f2_sfd__h518979[9] && + !f2_sfd__h518979[8] && + !f2_sfd__h518979[7] && + !f2_sfd__h518979[6] && + !f2_sfd__h518979[5] && + !f2_sfd__h518979[4] && + !f2_sfd__h518979[3] && + !f2_sfd__h518979[2] && + !f2_sfd__h518979[1] && + !f2_sfd__h518979[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 = - !f1_sfd__h480018[21] && !f1_sfd__h480018[20] && - !f1_sfd__h480018[19] && - !f1_sfd__h480018[18] && - !f1_sfd__h480018[17] && - !f1_sfd__h480018[16] && - !f1_sfd__h480018[15] && - !f1_sfd__h480018[14] && - !f1_sfd__h480018[13] && - !f1_sfd__h480018[12] && - !f1_sfd__h480018[11] && - !f1_sfd__h480018[10] && - !f1_sfd__h480018[9] && - !f1_sfd__h480018[8] && - !f1_sfd__h480018[7] && - !f1_sfd__h480018[6] && - !f1_sfd__h480018[5] && - !f1_sfd__h480018[4] && - !f1_sfd__h480018[3] && - !f1_sfd__h480018[2] && - !f1_sfd__h480018[1] && - !f1_sfd__h480018[0] ; + !f1_sfd__h479985[21] && !f1_sfd__h479985[20] && + !f1_sfd__h479985[19] && + !f1_sfd__h479985[18] && + !f1_sfd__h479985[17] && + !f1_sfd__h479985[16] && + !f1_sfd__h479985[15] && + !f1_sfd__h479985[14] && + !f1_sfd__h479985[13] && + !f1_sfd__h479985[12] && + !f1_sfd__h479985[11] && + !f1_sfd__h479985[10] && + !f1_sfd__h479985[9] && + !f1_sfd__h479985[8] && + !f1_sfd__h479985[7] && + !f1_sfd__h479985[6] && + !f1_sfd__h479985[5] && + !f1_sfd__h479985[4] && + !f1_sfd__h479985[3] && + !f1_sfd__h479985[2] && + !f1_sfd__h479985[1] && + !f1_sfd__h479985[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 = - !f3_sfd__h558316[21] && !f3_sfd__h558316[20] && - !f3_sfd__h558316[19] && - !f3_sfd__h558316[18] && - !f3_sfd__h558316[17] && - !f3_sfd__h558316[16] && - !f3_sfd__h558316[15] && - !f3_sfd__h558316[14] && - !f3_sfd__h558316[13] && - !f3_sfd__h558316[12] && - !f3_sfd__h558316[11] && - !f3_sfd__h558316[10] && - !f3_sfd__h558316[9] && - !f3_sfd__h558316[8] && - !f3_sfd__h558316[7] && - !f3_sfd__h558316[6] && - !f3_sfd__h558316[5] && - !f3_sfd__h558316[4] && - !f3_sfd__h558316[3] && - !f3_sfd__h558316[2] && - !f3_sfd__h558316[1] && - !f3_sfd__h558316[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 && + !f3_sfd__h558283[21] && !f3_sfd__h558283[20] && + !f3_sfd__h558283[19] && + !f3_sfd__h558283[18] && + !f3_sfd__h558283[17] && + !f3_sfd__h558283[16] && + !f3_sfd__h558283[15] && + !f3_sfd__h558283[14] && + !f3_sfd__h558283[13] && + !f3_sfd__h558283[12] && + !f3_sfd__h558283[11] && + !f3_sfd__h558283[10] && + !f3_sfd__h558283[9] && + !f3_sfd__h558283[8] && + !f3_sfd__h558283[7] && + !f3_sfd__h558283[6] && + !f3_sfd__h558283[5] && + !f3_sfd__h558283[4] && + !f3_sfd__h558283[3] && + !f3_sfd__h558283[2] && + !f3_sfd__h558283[1] && + !f3_sfd__h558283[0] ; + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 ; + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd0 || commitStage_commitTrap[3:0] == 4'd1 || @@ -24123,12 +24123,12 @@ module mkCore(CLK, (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510 = - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503 || + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 = + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 = + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd14) && (!commitStage_commitTrap[4] || @@ -24145,25 +24145,25 @@ module mkCore(CLK, (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 = + assign NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 = !commitStage_rg_run_state && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 = + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181) && + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189) ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 = + !coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186) ; + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213) && + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217) ; + !coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214) ; assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) && @@ -24642,7 +24642,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269 = + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24652,9 +24652,9 @@ module mkCore(CLK, (!fetchStage$pipelines_0_first[75] || !fetchStage$pipelines_0_first[74])) && (fetchStage$pipelines_0_first[199:195] != 5'd13 || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265 && - !csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 = + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 && + !csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ; + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24666,7 +24666,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 = + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -24678,195 +24678,195 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 = - !csrf_prv_reg_read__2730_ULE_1___d14571 || + assign NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 = + !csrf_prv_reg_read__2727_ULE_1___d14567 || (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + (regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 = + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449) && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) && + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877 && - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 && + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108 = + fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 && + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h651965 == 5'd0 && - imm__h651966 == 32'd0 || - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[11:10] != + rs1__h651905 == 5'd0 && + imm__h651906 == 32'd0 || + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374) ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046) ? - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 : + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042) ? + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 : { 1'h0, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 }, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407 = + assign NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 = !fetchStage$pipelines_0_first[68] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715 = + assign NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 = !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430 = + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428) ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424) ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 ; - assign NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 ; + assign NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13619[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 && + !checkForException___d13615[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -24949,7 +24949,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 = + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -24960,8 +24960,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680 ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 ; + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -24972,14 +24972,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756 ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103 = + fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 ; + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722 = + assign NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -24990,58 +24990,58 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15]) ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657 = + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815 ; - assign NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 ; + assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 = (!rob$deqPort_0_canDeq || rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932) ; - assign NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 = + NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927) ; + assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25055,15 +25055,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] != 5'd19 && rob$deqPort_0_deq_data[186:182] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688 = + assign NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932 = + assign NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -25077,18 +25077,18 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd20 || rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928 = + assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995 = + assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916 = @@ -25108,27 +25108,27 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h289495 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608 = + x__h289463 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 = - { {4{f2_exp19011_MINUS_127__q176[7]}}, - f2_exp19011_MINUS_127__q176 } ; + { {4{f2_exp18978_MINUS_127__q176[7]}}, + f2_exp18978_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 ^ 12'h800) <= @@ -25138,8 +25138,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 = - { {4{f1_exp80017_MINUS_127__q136[7]}}, - f1_exp80017_MINUS_127__q136 } ; + { {4{f1_exp79984_MINUS_127__q136[7]}}, + f1_exp79984_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 ^ 12'h800) <= @@ -25149,8 +25149,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 = - { {4{f3_exp58315_MINUS_127__q153[7]}}, - f3_exp58315_MINUS_127__q153 } ; + { {4{f3_exp58282_MINUS_127__q153[7]}}, + f3_exp58282_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 ^ 12'h800) <= @@ -25235,15 +25235,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h352073 == 8'd0 && - (sfdin__h352067[56:34] == 23'd0 || guard__h343972 != 2'b0), + _theResult___fst_exp__h352040 == 8'd0 && + (sfdin__h352034[56:34] == 23'd0 || guard__h343939 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352670 == 8'd255 && - _theResult___fst_sfd__h352671 == 23'd0, + _theResult___fst_exp__h352637 == 8'd255 && + _theResult___fst_sfd__h352638 == 23'd0, 1'd0, - _theResult___fst_exp__h352073 != 8'd255 && - guard__h343972 != 2'b0 } ; + _theResult___fst_exp__h352040 != 8'd255 && + guard__h343939 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -25251,15 +25251,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397770 == 8'd0 && - (sfdin__h397764[56:34] == 23'd0 || guard__h389671 != 2'b0), + _theResult___fst_exp__h397737 == 8'd0 && + (sfdin__h397731[56:34] == 23'd0 || guard__h389638 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h398367 == 8'd255 && - _theResult___fst_sfd__h398368 == 23'd0, + _theResult___fst_exp__h398334 == 8'd255 && + _theResult___fst_sfd__h398335 == 23'd0, 1'd0, - _theResult___fst_exp__h397770 != 8'd255 && - guard__h389671 != 2'b0 } ; + _theResult___fst_exp__h397737 != 8'd255 && + guard__h389638 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -25267,15 +25267,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h443465 == 8'd0 && - (sfdin__h443459[56:34] == 23'd0 || guard__h435366 != 2'b0), + _theResult___fst_exp__h443432 == 8'd0 && + (sfdin__h443426[56:34] == 23'd0 || guard__h435333 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h444062 == 8'd255 && - _theResult___fst_sfd__h444063 == 23'd0, + _theResult___fst_exp__h444029 == 8'd255 && + _theResult___fst_sfd__h444030 == 23'd0, 1'd0, - _theResult___fst_exp__h443465 != 8'd255 && - guard__h435366 != 2'b0 } ; + _theResult___fst_exp__h443432 != 8'd255 && + guard__h435333 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ^ @@ -25283,37 +25283,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755 = { 3'd0, - _theResult___fst_exp__h508982 == 11'd0 && - (sfdin__h508976[56:5] == 52'd0 || guard__h500756 != 2'b0), + _theResult___fst_exp__h508949 == 11'd0 && + (sfdin__h508943[56:5] == 52'd0 || guard__h500723 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509814 == 11'd2047 && - _theResult___fst_sfd__h509815 == 52'd0, + _theResult___fst_exp__h509781 == 11'd2047 && + _theResult___fst_sfd__h509782 == 52'd0, 1'd0, - _theResult___fst_exp__h508982 != 11'd2047 && - guard__h500756 != 2'b0 } ; + _theResult___fst_exp__h508949 != 11'd2047 && + guard__h500723 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796 = { 3'd0, - _theResult___fst_exp__h547835 == 11'd0 && - (sfdin__h547829[56:5] == 52'd0 || guard__h539609 != 2'b0), + _theResult___fst_exp__h547802 == 11'd0 && + (sfdin__h547796[56:5] == 52'd0 || guard__h539576 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h548667 == 11'd2047 && - _theResult___fst_sfd__h548668 == 52'd0, + _theResult___fst_exp__h548634 == 11'd2047 && + _theResult___fst_sfd__h548635 == 52'd0, 1'd0, - _theResult___fst_exp__h547835 != 11'd2047 && - guard__h539609 != 2'b0 } ; + _theResult___fst_exp__h547802 != 11'd2047 && + guard__h539576 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840 = { 3'd0, - _theResult___fst_exp__h587139 == 11'd0 && - (sfdin__h587133[56:5] == 52'd0 || guard__h578913 != 2'b0), + _theResult___fst_exp__h587106 == 11'd0 && + (sfdin__h587100[56:5] == 52'd0 || guard__h578880 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587971 == 11'd2047 && - _theResult___fst_sfd__h587972 == 52'd0, + _theResult___fst_exp__h587938 == 11'd2047 && + _theResult___fst_sfd__h587939 == 52'd0, 1'd0, - _theResult___fst_exp__h587139 != 11'd2047 && - guard__h578913 != 2'b0 } ; + _theResult___fst_exp__h587106 != 11'd2047 && + guard__h578880 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ^ @@ -25331,15 +25331,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369839 == 8'd0 && - (sfdin__h369833[56:34] == 23'd0 || guard__h361611 != 2'b0), + _theResult___fst_exp__h369806 == 8'd0 && + (sfdin__h369800[56:34] == 23'd0 || guard__h361578 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h370436 == 8'd255 && - _theResult___fst_sfd__h370437 == 23'd0, + _theResult___fst_exp__h370403 == 8'd255 && + _theResult___fst_sfd__h370404 == 23'd0, 1'd0, - _theResult___fst_exp__h369839 != 8'd255 && - guard__h361611 != 2'b0 } ; + _theResult___fst_exp__h369806 != 8'd255 && + guard__h361578 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -25347,15 +25347,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h415536 == 8'd0 && - (sfdin__h415530[56:34] == 23'd0 || guard__h407308 != 2'b0), + _theResult___fst_exp__h415503 == 8'd0 && + (sfdin__h415497[56:34] == 23'd0 || guard__h407275 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h416133 == 8'd255 && - _theResult___fst_sfd__h416134 == 23'd0, + _theResult___fst_exp__h416100 == 8'd255 && + _theResult___fst_sfd__h416101 == 23'd0, 1'd0, - _theResult___fst_exp__h415536 != 8'd255 && - guard__h407308 != 2'b0 } ; + _theResult___fst_exp__h415503 != 8'd255 && + guard__h407275 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -25363,15 +25363,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h461231 == 8'd0 && - (sfdin__h461225[56:34] == 23'd0 || guard__h453003 != 2'b0), + _theResult___fst_exp__h461198 == 8'd0 && + (sfdin__h461192[56:34] == 23'd0 || guard__h452970 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461828 == 8'd255 && - _theResult___fst_sfd__h461829 == 23'd0, + _theResult___fst_exp__h461795 == 8'd255 && + _theResult___fst_sfd__h461796 == 23'd0, 1'd0, - _theResult___fst_exp__h461231 != 8'd255 && - guard__h453003 != 2'b0 } ; + _theResult___fst_exp__h461198 != 8'd255 && + guard__h452970 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ^ @@ -25385,37 +25385,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738 = { 3'd0, - _theResult___fst_exp__h499405 == 11'd0 && - guard__h491444 != 2'b0, + _theResult___fst_exp__h499372 == 11'd0 && + guard__h491411 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h500163 == 11'd2047 && - _theResult___fst_sfd__h500164 == 52'd0, + _theResult___fst_exp__h500130 == 11'd2047 && + _theResult___fst_sfd__h500131 == 52'd0, 1'd0, - _theResult___fst_exp__h499405 != 11'd2047 && - guard__h491444 != 2'b0 } ; + _theResult___fst_exp__h499372 != 11'd2047 && + guard__h491411 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779 = { 3'd0, - _theResult___fst_exp__h538258 == 11'd0 && - guard__h530297 != 2'b0, + _theResult___fst_exp__h538225 == 11'd0 && + guard__h530264 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h539016 == 11'd2047 && - _theResult___fst_sfd__h539017 == 52'd0, + _theResult___fst_exp__h538983 == 11'd2047 && + _theResult___fst_sfd__h538984 == 52'd0, 1'd0, - _theResult___fst_exp__h538258 != 11'd2047 && - guard__h530297 != 2'b0 } ; + _theResult___fst_exp__h538225 != 11'd2047 && + guard__h530264 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823 = { 3'd0, - _theResult___fst_exp__h577562 == 11'd0 && - guard__h569601 != 2'b0, + _theResult___fst_exp__h577529 == 11'd0 && + guard__h569568 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h578320 == 11'd2047 && - _theResult___fst_sfd__h578321 == 52'd0, + _theResult___fst_exp__h578287 == 11'd2047 && + _theResult___fst_sfd__h578288 == 52'd0, 1'd0, - _theResult___fst_exp__h577562 != 11'd2047 && - guard__h569601 != 2'b0 } ; + _theResult___fst_exp__h577529 != 11'd2047 && + guard__h569568 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ^ @@ -25451,15 +25451,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360729 == 8'd0 && - guard__h352681 != 2'b0, + _theResult___fst_exp__h360696 == 8'd0 && + guard__h352648 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h361252 == 8'd255 && - _theResult___fst_sfd__h361253 == 23'd0, + _theResult___fst_exp__h361219 == 8'd255 && + _theResult___fst_sfd__h361220 == 23'd0, 1'd0, - _theResult___fst_exp__h360729 != 8'd255 && - guard__h352681 != 2'b0 } ; + _theResult___fst_exp__h360696 != 8'd255 && + guard__h352648 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -25473,15 +25473,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h406426 == 8'd0 && - guard__h398378 != 2'b0, + _theResult___fst_exp__h406393 == 8'd0 && + guard__h398345 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406949 == 8'd255 && - _theResult___fst_sfd__h406950 == 23'd0, + _theResult___fst_exp__h406916 == 8'd255 && + _theResult___fst_sfd__h406917 == 23'd0, 1'd0, - _theResult___fst_exp__h406426 != 8'd255 && - guard__h398378 != 2'b0 } ; + _theResult___fst_exp__h406393 != 8'd255 && + guard__h398345 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -25495,73 +25495,71 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h452121 == 8'd0 && - guard__h444073 != 2'b0, + _theResult___fst_exp__h452088 == 8'd0 && + guard__h444040 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h452644 == 8'd255 && - _theResult___fst_sfd__h452645 == 23'd0, + _theResult___fst_exp__h452611 == 8'd255 && + _theResult___fst_sfd__h452612 == 23'd0, 1'd0, - _theResult___fst_exp__h452121 != 8'd255 && - guard__h444073 != 2'b0 } ; - assign _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739 = - { 1'd0, - csrf_debug_int_pend, - 2'b0, + _theResult___fst_exp__h452088 != 8'd255 && + guard__h444040 != 2'b0 } ; + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735 = + { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, 1'd0, csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1, csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ; - assign _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744 = - { _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739, + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735, csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750 = + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 ; + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135 = - sfd__h519373 >> + sfd__h519340 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650 = - sfd__h480379 >> + sfd__h480346 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365 = - sfd__h558677 >> + sfd__h558644 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h336357 >> + sfd__h336324 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h382059 >> + sfd__h382026 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427754 >> + sfd__h427721 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591 = - medeleg_csr__read__h608188[i__h698137] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 = - mideleg_csr__read__h608283[i__h698297] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587 = + medeleg_csr__read__h608155[i__h698077] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 = + mideleg_csr__read__h608250[i__h698237] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -25967,51 +25965,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006 = 12'd3970 - { 7'd0, - f2_sfd__h519012[22] ? + f2_sfd__h518979[22] ? 5'd0 : - (f2_sfd__h519012[21] ? + (f2_sfd__h518979[21] ? 5'd1 : - (f2_sfd__h519012[20] ? + (f2_sfd__h518979[20] ? 5'd2 : - (f2_sfd__h519012[19] ? + (f2_sfd__h518979[19] ? 5'd3 : - (f2_sfd__h519012[18] ? + (f2_sfd__h518979[18] ? 5'd4 : - (f2_sfd__h519012[17] ? + (f2_sfd__h518979[17] ? 5'd5 : - (f2_sfd__h519012[16] ? + (f2_sfd__h518979[16] ? 5'd6 : - (f2_sfd__h519012[15] ? + (f2_sfd__h518979[15] ? 5'd7 : - (f2_sfd__h519012[14] ? + (f2_sfd__h518979[14] ? 5'd8 : - (f2_sfd__h519012[13] ? + (f2_sfd__h518979[13] ? 5'd9 : - (f2_sfd__h519012[12] ? + (f2_sfd__h518979[12] ? 5'd10 : - (f2_sfd__h519012[11] ? + (f2_sfd__h518979[11] ? 5'd11 : - (f2_sfd__h519012[10] ? + (f2_sfd__h518979[10] ? 5'd12 : - (f2_sfd__h519012[9] ? + (f2_sfd__h518979[9] ? 5'd13 : - (f2_sfd__h519012[8] ? + (f2_sfd__h518979[8] ? 5'd14 : - (f2_sfd__h519012[7] ? + (f2_sfd__h518979[7] ? 5'd15 : - (f2_sfd__h519012[6] ? + (f2_sfd__h518979[6] ? 5'd16 : - (f2_sfd__h519012[5] ? + (f2_sfd__h518979[5] ? 5'd17 : - (f2_sfd__h519012[4] ? + (f2_sfd__h518979[4] ? 5'd18 : - (f2_sfd__h519012[3] ? + (f2_sfd__h518979[3] ? 5'd19 : - (f2_sfd__h519012[2] ? + (f2_sfd__h518979[2] ? 5'd20 : - (f2_sfd__h519012[1] ? + (f2_sfd__h518979[1] ? 5'd21 : - (f2_sfd__h519012[0] ? + (f2_sfd__h518979[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 = @@ -26025,51 +26023,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506 = 12'd3970 - { 7'd0, - f1_sfd__h480018[22] ? + f1_sfd__h479985[22] ? 5'd0 : - (f1_sfd__h480018[21] ? + (f1_sfd__h479985[21] ? 5'd1 : - (f1_sfd__h480018[20] ? + (f1_sfd__h479985[20] ? 5'd2 : - (f1_sfd__h480018[19] ? + (f1_sfd__h479985[19] ? 5'd3 : - (f1_sfd__h480018[18] ? + (f1_sfd__h479985[18] ? 5'd4 : - (f1_sfd__h480018[17] ? + (f1_sfd__h479985[17] ? 5'd5 : - (f1_sfd__h480018[16] ? + (f1_sfd__h479985[16] ? 5'd6 : - (f1_sfd__h480018[15] ? + (f1_sfd__h479985[15] ? 5'd7 : - (f1_sfd__h480018[14] ? + (f1_sfd__h479985[14] ? 5'd8 : - (f1_sfd__h480018[13] ? + (f1_sfd__h479985[13] ? 5'd9 : - (f1_sfd__h480018[12] ? + (f1_sfd__h479985[12] ? 5'd10 : - (f1_sfd__h480018[11] ? + (f1_sfd__h479985[11] ? 5'd11 : - (f1_sfd__h480018[10] ? + (f1_sfd__h479985[10] ? 5'd12 : - (f1_sfd__h480018[9] ? + (f1_sfd__h479985[9] ? 5'd13 : - (f1_sfd__h480018[8] ? + (f1_sfd__h479985[8] ? 5'd14 : - (f1_sfd__h480018[7] ? + (f1_sfd__h479985[7] ? 5'd15 : - (f1_sfd__h480018[6] ? + (f1_sfd__h479985[6] ? 5'd16 : - (f1_sfd__h480018[5] ? + (f1_sfd__h479985[5] ? 5'd17 : - (f1_sfd__h480018[4] ? + (f1_sfd__h479985[4] ? 5'd18 : - (f1_sfd__h480018[3] ? + (f1_sfd__h479985[3] ? 5'd19 : - (f1_sfd__h480018[2] ? + (f1_sfd__h479985[2] ? 5'd20 : - (f1_sfd__h480018[1] ? + (f1_sfd__h479985[1] ? 5'd21 : - (f1_sfd__h480018[0] ? + (f1_sfd__h479985[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 = @@ -26083,51 +26081,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236 = 12'd3970 - { 7'd0, - f3_sfd__h558316[22] ? + f3_sfd__h558283[22] ? 5'd0 : - (f3_sfd__h558316[21] ? + (f3_sfd__h558283[21] ? 5'd1 : - (f3_sfd__h558316[20] ? + (f3_sfd__h558283[20] ? 5'd2 : - (f3_sfd__h558316[19] ? + (f3_sfd__h558283[19] ? 5'd3 : - (f3_sfd__h558316[18] ? + (f3_sfd__h558283[18] ? 5'd4 : - (f3_sfd__h558316[17] ? + (f3_sfd__h558283[17] ? 5'd5 : - (f3_sfd__h558316[16] ? + (f3_sfd__h558283[16] ? 5'd6 : - (f3_sfd__h558316[15] ? + (f3_sfd__h558283[15] ? 5'd7 : - (f3_sfd__h558316[14] ? + (f3_sfd__h558283[14] ? 5'd8 : - (f3_sfd__h558316[13] ? + (f3_sfd__h558283[13] ? 5'd9 : - (f3_sfd__h558316[12] ? + (f3_sfd__h558283[12] ? 5'd10 : - (f3_sfd__h558316[11] ? + (f3_sfd__h558283[11] ? 5'd11 : - (f3_sfd__h558316[10] ? + (f3_sfd__h558283[10] ? 5'd12 : - (f3_sfd__h558316[9] ? + (f3_sfd__h558283[9] ? 5'd13 : - (f3_sfd__h558316[8] ? + (f3_sfd__h558283[8] ? 5'd14 : - (f3_sfd__h558316[7] ? + (f3_sfd__h558283[7] ? 5'd15 : - (f3_sfd__h558316[6] ? + (f3_sfd__h558283[6] ? 5'd16 : - (f3_sfd__h558316[5] ? + (f3_sfd__h558283[5] ? 5'd17 : - (f3_sfd__h558316[4] ? + (f3_sfd__h558283[4] ? 5'd18 : - (f3_sfd__h558316[3] ? + (f3_sfd__h558283[3] ? 5'd19 : - (f3_sfd__h558316[2] ? + (f3_sfd__h558283[2] ? 5'd20 : - (f3_sfd__h558316[1] ? + (f3_sfd__h558283[1] ? 5'd21 : - (f3_sfd__h558316[0] ? + (f3_sfd__h558283[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 = @@ -26149,57 +26147,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h664143 == 1'd1 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 || - (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108) == + k__h664083 == 1'd1 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 || + (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ; assign _dfoo18 = - k__h664143 == 1'd0 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 || - (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108) == + k__h664083 == 1'd0 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 || + (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 ; + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ; assign _dfoo24 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd36 || + rob$deqPort_0_deq_data[186:182] == 5'd19 || + rob$deqPort_0_deq_data[186:182] == 5'd20 ; + assign _dfoo26 = + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo30 = + assign _dfoo32 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) || rob$deqPort_0_deq_data[186:182] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -26274,1421 +26278,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h294400 = + assign _theResult_____2__h294368 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294679 : + next_deqP___1__h294647 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h302396 = + assign _theResult_____2__h302364 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302675 : + next_deqP___1__h302643 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h308390 = + assign _theResult_____2__h308358 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308956 : + next_deqP___1__h308924 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h316244 = + assign _theResult_____2__h316212 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316810 : + next_deqP___1__h316778 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h326588 = + assign _theResult_____2__h326556 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326867 : + next_deqP___1__h326835 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329813 = + assign _theResult_____2__h329781 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h330092 : + next_deqP___1__h330060 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343962 = - (value__h344584 == 54'd0) ? sfd__h336357 : 57'd1 ; - assign _theResult____h361601 = + assign _theResult____h343929 = + (value__h344551 == 54'd0) ? sfd__h336324 : 57'd1 ; + assign _theResult____h361568 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h362214 : - _theResult____h343962 ; - assign _theResult____h389661 = - (value__h390281 == 54'd0) ? sfd__h382059 : 57'd1 ; - assign _theResult____h407298 = + result__h362181 : + _theResult____h343929 ; + assign _theResult____h389628 = + (value__h390248 == 54'd0) ? sfd__h382026 : 57'd1 ; + assign _theResult____h407265 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407911 : - _theResult____h389661 ; - assign _theResult____h435356 = - (value__h435976 == 54'd0) ? sfd__h427754 : 57'd1 ; - assign _theResult____h452993 = + result__h407878 : + _theResult____h389628 ; + assign _theResult____h435323 = + (value__h435943 == 54'd0) ? sfd__h427721 : 57'd1 ; + assign _theResult____h452960 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h453606 : - _theResult____h435356 ; - assign _theResult____h500746 = + result__h453573 : + _theResult____h435323 ; + assign _theResult____h500713 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ^ 12'h800) < 12'd2105) ? - result__h501359 : - ((value__h484962 == 25'd0) ? sfd__h480379 : 57'd1) ; - assign _theResult____h539599 = + result__h501326 : + ((value__h484929 == 25'd0) ? sfd__h480346 : 57'd1) ; + assign _theResult____h539566 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ^ 12'h800) < 12'd2105) ? - result__h540212 : - ((value__h523815 == 25'd0) ? sfd__h519373 : 57'd1) ; - assign _theResult____h578903 = + result__h540179 : + ((value__h523782 == 25'd0) ? sfd__h519340 : 57'd1) ; + assign _theResult____h578870 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ^ 12'h800) < 12'd2105) ? - result__h579516 : - ((value__h563119 == 25'd0) ? sfd__h558677 : 57'd1) ; - assign _theResult____h647786 = + result__h579483 : + ((value__h563086 == 25'd0) ? sfd__h558644 : 57'd1) ; + assign _theResult____h647726 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h648311 : + enabled_ints___1__h648251 : 16'd0 ; - assign _theResult___exp__h352589 = - sfd__h352165[24] ? - ((_theResult___fst_exp__h352073 == 8'd254) ? + assign _theResult___exp__h352556 = + sfd__h352132[24] ? + ((_theResult___fst_exp__h352040 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379106) : - ((_theResult___fst_exp__h352073 == 8'd0 && - sfd__h352165[24:23] == 2'b01) ? + din_inc___2_exp__h379073) : + ((_theResult___fst_exp__h352040 == 8'd0 && + sfd__h352132[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h352073) ; - assign _theResult___exp__h361171 = - sfd__h360747[24] ? - ((_theResult___fst_exp__h360729 == 8'd254) ? + _theResult___fst_exp__h352040) ; + assign _theResult___exp__h361138 = + sfd__h360714[24] ? + ((_theResult___fst_exp__h360696 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379130) : - ((_theResult___fst_exp__h360729 == 8'd0 && - sfd__h360747[24:23] == 2'b01) ? + din_inc___2_exp__h379097) : + ((_theResult___fst_exp__h360696 == 8'd0 && + sfd__h360714[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360729) ; - assign _theResult___exp__h370355 = - sfd__h369931[24] ? - ((_theResult___fst_exp__h369839 == 8'd254) ? + _theResult___fst_exp__h360696) ; + assign _theResult___exp__h370322 = + sfd__h369898[24] ? + ((_theResult___fst_exp__h369806 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379160) : - ((_theResult___fst_exp__h369839 == 8'd0 && - sfd__h369931[24:23] == 2'b01) ? + din_inc___2_exp__h379127) : + ((_theResult___fst_exp__h369806 == 8'd0 && + sfd__h369898[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369839) ; - assign _theResult___exp__h378991 = - sfd__h378543[24] ? - ((_theResult___fst_exp__h378524 == 8'd254) ? + _theResult___fst_exp__h369806) ; + assign _theResult___exp__h378958 = + sfd__h378510[24] ? + ((_theResult___fst_exp__h378491 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379184) : - ((_theResult___fst_exp__h378524 == 8'd0 && - sfd__h378543[24:23] == 2'b01) ? + din_inc___2_exp__h379151) : + ((_theResult___fst_exp__h378491 == 8'd0 && + sfd__h378510[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h378524) ; - assign _theResult___exp__h379093 = + _theResult___fst_exp__h378491) ; + assign _theResult___exp__h379060 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h379084 ; - assign _theResult___exp__h398286 = - sfd__h397862[24] ? - ((_theResult___fst_exp__h397770 == 8'd254) ? + _theResult___fst_exp__h379051 ; + assign _theResult___exp__h398253 = + sfd__h397829[24] ? + ((_theResult___fst_exp__h397737 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424803) : - ((_theResult___fst_exp__h397770 == 8'd0 && - sfd__h397862[24:23] == 2'b01) ? + din_inc___2_exp__h424770) : + ((_theResult___fst_exp__h397737 == 8'd0 && + sfd__h397829[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397770) ; - assign _theResult___exp__h406868 = - sfd__h406444[24] ? - ((_theResult___fst_exp__h406426 == 8'd254) ? + _theResult___fst_exp__h397737) ; + assign _theResult___exp__h406835 = + sfd__h406411[24] ? + ((_theResult___fst_exp__h406393 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424827) : - ((_theResult___fst_exp__h406426 == 8'd0 && - sfd__h406444[24:23] == 2'b01) ? + din_inc___2_exp__h424794) : + ((_theResult___fst_exp__h406393 == 8'd0 && + sfd__h406411[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h406426) ; - assign _theResult___exp__h416052 = - sfd__h415628[24] ? - ((_theResult___fst_exp__h415536 == 8'd254) ? + _theResult___fst_exp__h406393) ; + assign _theResult___exp__h416019 = + sfd__h415595[24] ? + ((_theResult___fst_exp__h415503 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424857) : - ((_theResult___fst_exp__h415536 == 8'd0 && - sfd__h415628[24:23] == 2'b01) ? + din_inc___2_exp__h424824) : + ((_theResult___fst_exp__h415503 == 8'd0 && + sfd__h415595[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h415536) ; - assign _theResult___exp__h424688 = - sfd__h424240[24] ? - ((_theResult___fst_exp__h424221 == 8'd254) ? + _theResult___fst_exp__h415503) ; + assign _theResult___exp__h424655 = + sfd__h424207[24] ? + ((_theResult___fst_exp__h424188 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424881) : - ((_theResult___fst_exp__h424221 == 8'd0 && - sfd__h424240[24:23] == 2'b01) ? + din_inc___2_exp__h424848) : + ((_theResult___fst_exp__h424188 == 8'd0 && + sfd__h424207[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h424221) ; - assign _theResult___exp__h424790 = + _theResult___fst_exp__h424188) ; + assign _theResult___exp__h424757 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424781 ; - assign _theResult___exp__h443981 = - sfd__h443557[24] ? - ((_theResult___fst_exp__h443465 == 8'd254) ? + _theResult___fst_exp__h424748 ; + assign _theResult___exp__h443948 = + sfd__h443524[24] ? + ((_theResult___fst_exp__h443432 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470498) : - ((_theResult___fst_exp__h443465 == 8'd0 && - sfd__h443557[24:23] == 2'b01) ? + din_inc___2_exp__h470465) : + ((_theResult___fst_exp__h443432 == 8'd0 && + sfd__h443524[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h443465) ; - assign _theResult___exp__h452563 = - sfd__h452139[24] ? - ((_theResult___fst_exp__h452121 == 8'd254) ? + _theResult___fst_exp__h443432) ; + assign _theResult___exp__h452530 = + sfd__h452106[24] ? + ((_theResult___fst_exp__h452088 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470522) : - ((_theResult___fst_exp__h452121 == 8'd0 && - sfd__h452139[24:23] == 2'b01) ? + din_inc___2_exp__h470489) : + ((_theResult___fst_exp__h452088 == 8'd0 && + sfd__h452106[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h452121) ; - assign _theResult___exp__h461747 = - sfd__h461323[24] ? - ((_theResult___fst_exp__h461231 == 8'd254) ? + _theResult___fst_exp__h452088) ; + assign _theResult___exp__h461714 = + sfd__h461290[24] ? + ((_theResult___fst_exp__h461198 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470552) : - ((_theResult___fst_exp__h461231 == 8'd0 && - sfd__h461323[24:23] == 2'b01) ? + din_inc___2_exp__h470519) : + ((_theResult___fst_exp__h461198 == 8'd0 && + sfd__h461290[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h461231) ; - assign _theResult___exp__h470383 = - sfd__h469935[24] ? - ((_theResult___fst_exp__h469916 == 8'd254) ? + _theResult___fst_exp__h461198) ; + assign _theResult___exp__h470350 = + sfd__h469902[24] ? + ((_theResult___fst_exp__h469883 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470576) : - ((_theResult___fst_exp__h469916 == 8'd0 && - sfd__h469935[24:23] == 2'b01) ? + din_inc___2_exp__h470543) : + ((_theResult___fst_exp__h469883 == 8'd0 && + sfd__h469902[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469916) ; - assign _theResult___exp__h470485 = + _theResult___fst_exp__h469883) ; + assign _theResult___exp__h470452 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h470476 ; - assign _theResult___exp__h500060 = - sfd__h499423[53] ? - ((_theResult___fst_exp__h499405 == 11'd2046) ? + _theResult___fst_exp__h470443 ; + assign _theResult___exp__h500027 = + sfd__h499390[53] ? + ((_theResult___fst_exp__h499372 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518655) : - ((_theResult___fst_exp__h499405 == 11'd0 && - sfd__h499423[53:52] == 2'b01) ? + din_inc___2_exp__h518622) : + ((_theResult___fst_exp__h499372 == 11'd0 && + sfd__h499390[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h499405) ; - assign _theResult___exp__h509711 = - sfd__h509074[53] ? - ((_theResult___fst_exp__h508982 == 11'd2046) ? + _theResult___fst_exp__h499372) ; + assign _theResult___exp__h509678 = + sfd__h509041[53] ? + ((_theResult___fst_exp__h508949 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518690) : - ((_theResult___fst_exp__h508982 == 11'd0 && - sfd__h509074[53:52] == 2'b01) ? + din_inc___2_exp__h518657) : + ((_theResult___fst_exp__h508949 == 11'd0 && + sfd__h509041[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508982) ; - assign _theResult___exp__h518495 = - sfd__h517834[53] ? - ((_theResult___fst_exp__h517815 == 11'd2046) ? + _theResult___fst_exp__h508949) ; + assign _theResult___exp__h518462 = + sfd__h517801[53] ? + ((_theResult___fst_exp__h517782 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518716) : - ((_theResult___fst_exp__h517815 == 11'd0 && - sfd__h517834[53:52] == 2'b01) ? + din_inc___2_exp__h518683) : + ((_theResult___fst_exp__h517782 == 11'd0 && + sfd__h517801[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517815) ; - assign _theResult___exp__h538913 = - sfd__h538276[53] ? - ((_theResult___fst_exp__h538258 == 11'd2046) ? + _theResult___fst_exp__h517782) ; + assign _theResult___exp__h538880 = + sfd__h538243[53] ? + ((_theResult___fst_exp__h538225 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557508) : - ((_theResult___fst_exp__h538258 == 11'd0 && - sfd__h538276[53:52] == 2'b01) ? + din_inc___2_exp__h557475) : + ((_theResult___fst_exp__h538225 == 11'd0 && + sfd__h538243[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h538258) ; - assign _theResult___exp__h548564 = - sfd__h547927[53] ? - ((_theResult___fst_exp__h547835 == 11'd2046) ? + _theResult___fst_exp__h538225) ; + assign _theResult___exp__h548531 = + sfd__h547894[53] ? + ((_theResult___fst_exp__h547802 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557543) : - ((_theResult___fst_exp__h547835 == 11'd0 && - sfd__h547927[53:52] == 2'b01) ? + din_inc___2_exp__h557510) : + ((_theResult___fst_exp__h547802 == 11'd0 && + sfd__h547894[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547835) ; - assign _theResult___exp__h557348 = - sfd__h556687[53] ? - ((_theResult___fst_exp__h556668 == 11'd2046) ? + _theResult___fst_exp__h547802) ; + assign _theResult___exp__h557315 = + sfd__h556654[53] ? + ((_theResult___fst_exp__h556635 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557569) : - ((_theResult___fst_exp__h556668 == 11'd0 && - sfd__h556687[53:52] == 2'b01) ? + din_inc___2_exp__h557536) : + ((_theResult___fst_exp__h556635 == 11'd0 && + sfd__h556654[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h556668) ; - assign _theResult___exp__h578217 = - sfd__h577580[53] ? - ((_theResult___fst_exp__h577562 == 11'd2046) ? + _theResult___fst_exp__h556635) ; + assign _theResult___exp__h578184 = + sfd__h577547[53] ? + ((_theResult___fst_exp__h577529 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596812) : - ((_theResult___fst_exp__h577562 == 11'd0 && - sfd__h577580[53:52] == 2'b01) ? + din_inc___2_exp__h596779) : + ((_theResult___fst_exp__h577529 == 11'd0 && + sfd__h577547[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h577562) ; - assign _theResult___exp__h587868 = - sfd__h587231[53] ? - ((_theResult___fst_exp__h587139 == 11'd2046) ? + _theResult___fst_exp__h577529) ; + assign _theResult___exp__h587835 = + sfd__h587198[53] ? + ((_theResult___fst_exp__h587106 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596847) : - ((_theResult___fst_exp__h587139 == 11'd0 && - sfd__h587231[53:52] == 2'b01) ? + din_inc___2_exp__h596814) : + ((_theResult___fst_exp__h587106 == 11'd0 && + sfd__h587198[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h587139) ; - assign _theResult___exp__h596652 = - sfd__h595991[53] ? - ((_theResult___fst_exp__h595972 == 11'd2046) ? + _theResult___fst_exp__h587106) ; + assign _theResult___exp__h596619 = + sfd__h595958[53] ? + ((_theResult___fst_exp__h595939 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596873) : - ((_theResult___fst_exp__h595972 == 11'd0 && - sfd__h595991[53:52] == 2'b01) ? + din_inc___2_exp__h596840) : + ((_theResult___fst_exp__h595939 == 11'd0 && + sfd__h595958[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595972) ; - assign _theResult___fst__h601247 = - a__h600825[63] ? a___1__h601252 : a__h600825 ; - assign _theResult___fst_exp__h352073 = - _theResult____h343962[56] ? + _theResult___fst_exp__h595939) ; + assign _theResult___fst__h601214 = + a__h600792[63] ? a___1__h601219 : a__h600792 ; + assign _theResult___fst_exp__h352040 = + _theResult____h343929[56] ? 8'd2 : - _theResult___fst_exp__h352147 ; - assign _theResult___fst_exp__h352138 = + _theResult___fst_exp__h352114 ; + assign _theResult___fst_exp__h352105 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h352144 = - (!_theResult____h343962[56] && !_theResult____h343962[55] && - !_theResult____h343962[54] && - !_theResult____h343962[53] && - !_theResult____h343962[52] && - !_theResult____h343962[51] && - !_theResult____h343962[50] && - !_theResult____h343962[49] && - !_theResult____h343962[48] && - !_theResult____h343962[47] && - !_theResult____h343962[46] && - !_theResult____h343962[45] && - !_theResult____h343962[44] && - !_theResult____h343962[43] && - !_theResult____h343962[42] && - !_theResult____h343962[41] && - !_theResult____h343962[40] && - !_theResult____h343962[39] && - !_theResult____h343962[38] && - !_theResult____h343962[37] && - !_theResult____h343962[36] && - !_theResult____h343962[35] && - !_theResult____h343962[34] && - !_theResult____h343962[33] && - !_theResult____h343962[32] && - !_theResult____h343962[31] && - !_theResult____h343962[30] && - !_theResult____h343962[29] && - !_theResult____h343962[28] && - !_theResult____h343962[27] && - !_theResult____h343962[26] && - !_theResult____h343962[25] && - !_theResult____h343962[24] && - !_theResult____h343962[23] && - !_theResult____h343962[22] && - !_theResult____h343962[21] && - !_theResult____h343962[20] && - !_theResult____h343962[19] && - !_theResult____h343962[18] && - !_theResult____h343962[17] && - !_theResult____h343962[16] && - !_theResult____h343962[15] && - !_theResult____h343962[14] && - !_theResult____h343962[13] && - !_theResult____h343962[12] && - !_theResult____h343962[11] && - !_theResult____h343962[10] && - !_theResult____h343962[9] && - !_theResult____h343962[8] && - !_theResult____h343962[7] && - !_theResult____h343962[6] && - !_theResult____h343962[5] && - !_theResult____h343962[4] && - !_theResult____h343962[3] && - !_theResult____h343962[2] && - !_theResult____h343962[1] && - !_theResult____h343962[0] || + assign _theResult___fst_exp__h352111 = + (!_theResult____h343929[56] && !_theResult____h343929[55] && + !_theResult____h343929[54] && + !_theResult____h343929[53] && + !_theResult____h343929[52] && + !_theResult____h343929[51] && + !_theResult____h343929[50] && + !_theResult____h343929[49] && + !_theResult____h343929[48] && + !_theResult____h343929[47] && + !_theResult____h343929[46] && + !_theResult____h343929[45] && + !_theResult____h343929[44] && + !_theResult____h343929[43] && + !_theResult____h343929[42] && + !_theResult____h343929[41] && + !_theResult____h343929[40] && + !_theResult____h343929[39] && + !_theResult____h343929[38] && + !_theResult____h343929[37] && + !_theResult____h343929[36] && + !_theResult____h343929[35] && + !_theResult____h343929[34] && + !_theResult____h343929[33] && + !_theResult____h343929[32] && + !_theResult____h343929[31] && + !_theResult____h343929[30] && + !_theResult____h343929[29] && + !_theResult____h343929[28] && + !_theResult____h343929[27] && + !_theResult____h343929[26] && + !_theResult____h343929[25] && + !_theResult____h343929[24] && + !_theResult____h343929[23] && + !_theResult____h343929[22] && + !_theResult____h343929[21] && + !_theResult____h343929[20] && + !_theResult____h343929[19] && + !_theResult____h343929[18] && + !_theResult____h343929[17] && + !_theResult____h343929[16] && + !_theResult____h343929[15] && + !_theResult____h343929[14] && + !_theResult____h343929[13] && + !_theResult____h343929[12] && + !_theResult____h343929[11] && + !_theResult____h343929[10] && + !_theResult____h343929[9] && + !_theResult____h343929[8] && + !_theResult____h343929[7] && + !_theResult____h343929[6] && + !_theResult____h343929[5] && + !_theResult____h343929[4] && + !_theResult____h343929[3] && + !_theResult____h343929[2] && + !_theResult____h343929[1] && + !_theResult____h343929[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h352138 ; - assign _theResult___fst_exp__h352147 = - (!_theResult____h343962[56] && _theResult____h343962[55]) ? + _theResult___fst_exp__h352105 ; + assign _theResult___fst_exp__h352114 = + (!_theResult____h343929[56] && _theResult____h343929[55]) ? 8'd1 : - _theResult___fst_exp__h352144 ; - assign _theResult___fst_exp__h352670 = - (_theResult___fst_exp__h352073 == 8'd255) ? - _theResult___fst_exp__h352073 : - _theResult___fst_exp__h352667 ; - assign _theResult___fst_exp__h360720 = + _theResult___fst_exp__h352111 ; + assign _theResult___fst_exp__h352637 = + (_theResult___fst_exp__h352040 == 8'd255) ? + _theResult___fst_exp__h352040 : + _theResult___fst_exp__h352634 ; + assign _theResult___fst_exp__h360687 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360726 = + assign _theResult___fst_exp__h360693 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360720 ; - assign _theResult___fst_exp__h360729 = + _theResult___fst_exp__h360687 ; + assign _theResult___fst_exp__h360696 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360726 : + _theResult___fst_exp__h360693 : 8'd129 ; - assign _theResult___fst_exp__h361252 = - (_theResult___fst_exp__h360729 == 8'd255) ? - _theResult___fst_exp__h360729 : - _theResult___fst_exp__h361249 ; - assign _theResult___fst_exp__h369839 = - _theResult____h361601[56] ? + assign _theResult___fst_exp__h361219 = + (_theResult___fst_exp__h360696 == 8'd255) ? + _theResult___fst_exp__h360696 : + _theResult___fst_exp__h361216 ; + assign _theResult___fst_exp__h369806 = + _theResult____h361568[56] ? 8'd2 : - _theResult___fst_exp__h369913 ; - assign _theResult___fst_exp__h369904 = + _theResult___fst_exp__h369880 ; + assign _theResult___fst_exp__h369871 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369910 = - (!_theResult____h361601[56] && !_theResult____h361601[55] && - !_theResult____h361601[54] && - !_theResult____h361601[53] && - !_theResult____h361601[52] && - !_theResult____h361601[51] && - !_theResult____h361601[50] && - !_theResult____h361601[49] && - !_theResult____h361601[48] && - !_theResult____h361601[47] && - !_theResult____h361601[46] && - !_theResult____h361601[45] && - !_theResult____h361601[44] && - !_theResult____h361601[43] && - !_theResult____h361601[42] && - !_theResult____h361601[41] && - !_theResult____h361601[40] && - !_theResult____h361601[39] && - !_theResult____h361601[38] && - !_theResult____h361601[37] && - !_theResult____h361601[36] && - !_theResult____h361601[35] && - !_theResult____h361601[34] && - !_theResult____h361601[33] && - !_theResult____h361601[32] && - !_theResult____h361601[31] && - !_theResult____h361601[30] && - !_theResult____h361601[29] && - !_theResult____h361601[28] && - !_theResult____h361601[27] && - !_theResult____h361601[26] && - !_theResult____h361601[25] && - !_theResult____h361601[24] && - !_theResult____h361601[23] && - !_theResult____h361601[22] && - !_theResult____h361601[21] && - !_theResult____h361601[20] && - !_theResult____h361601[19] && - !_theResult____h361601[18] && - !_theResult____h361601[17] && - !_theResult____h361601[16] && - !_theResult____h361601[15] && - !_theResult____h361601[14] && - !_theResult____h361601[13] && - !_theResult____h361601[12] && - !_theResult____h361601[11] && - !_theResult____h361601[10] && - !_theResult____h361601[9] && - !_theResult____h361601[8] && - !_theResult____h361601[7] && - !_theResult____h361601[6] && - !_theResult____h361601[5] && - !_theResult____h361601[4] && - !_theResult____h361601[3] && - !_theResult____h361601[2] && - !_theResult____h361601[1] && - !_theResult____h361601[0] || + assign _theResult___fst_exp__h369877 = + (!_theResult____h361568[56] && !_theResult____h361568[55] && + !_theResult____h361568[54] && + !_theResult____h361568[53] && + !_theResult____h361568[52] && + !_theResult____h361568[51] && + !_theResult____h361568[50] && + !_theResult____h361568[49] && + !_theResult____h361568[48] && + !_theResult____h361568[47] && + !_theResult____h361568[46] && + !_theResult____h361568[45] && + !_theResult____h361568[44] && + !_theResult____h361568[43] && + !_theResult____h361568[42] && + !_theResult____h361568[41] && + !_theResult____h361568[40] && + !_theResult____h361568[39] && + !_theResult____h361568[38] && + !_theResult____h361568[37] && + !_theResult____h361568[36] && + !_theResult____h361568[35] && + !_theResult____h361568[34] && + !_theResult____h361568[33] && + !_theResult____h361568[32] && + !_theResult____h361568[31] && + !_theResult____h361568[30] && + !_theResult____h361568[29] && + !_theResult____h361568[28] && + !_theResult____h361568[27] && + !_theResult____h361568[26] && + !_theResult____h361568[25] && + !_theResult____h361568[24] && + !_theResult____h361568[23] && + !_theResult____h361568[22] && + !_theResult____h361568[21] && + !_theResult____h361568[20] && + !_theResult____h361568[19] && + !_theResult____h361568[18] && + !_theResult____h361568[17] && + !_theResult____h361568[16] && + !_theResult____h361568[15] && + !_theResult____h361568[14] && + !_theResult____h361568[13] && + !_theResult____h361568[12] && + !_theResult____h361568[11] && + !_theResult____h361568[10] && + !_theResult____h361568[9] && + !_theResult____h361568[8] && + !_theResult____h361568[7] && + !_theResult____h361568[6] && + !_theResult____h361568[5] && + !_theResult____h361568[4] && + !_theResult____h361568[3] && + !_theResult____h361568[2] && + !_theResult____h361568[1] && + !_theResult____h361568[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369904 ; - assign _theResult___fst_exp__h369913 = - (!_theResult____h361601[56] && _theResult____h361601[55]) ? + _theResult___fst_exp__h369871 ; + assign _theResult___fst_exp__h369880 = + (!_theResult____h361568[56] && _theResult____h361568[55]) ? 8'd1 : - _theResult___fst_exp__h369910 ; - assign _theResult___fst_exp__h370436 = - (_theResult___fst_exp__h369839 == 8'd255) ? - _theResult___fst_exp__h369839 : - _theResult___fst_exp__h370433 ; - assign _theResult___fst_exp__h378476 = + _theResult___fst_exp__h369877 ; + assign _theResult___fst_exp__h370403 = + (_theResult___fst_exp__h369806 == 8'd255) ? + _theResult___fst_exp__h369806 : + _theResult___fst_exp__h370400 ; + assign _theResult___fst_exp__h378443 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h378515 = + assign _theResult___fst_exp__h378482 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h378521 = + assign _theResult___fst_exp__h378488 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h378515 ; - assign _theResult___fst_exp__h378524 = + _theResult___fst_exp__h378482 ; + assign _theResult___fst_exp__h378491 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h378521 : - _theResult___fst_exp__h378476 ; - assign _theResult___fst_exp__h379072 = - (_theResult___fst_exp__h378524 == 8'd255) ? - _theResult___fst_exp__h378524 : - _theResult___fst_exp__h379069 ; - assign _theResult___fst_exp__h379081 = + _theResult___fst_exp__h378488 : + _theResult___fst_exp__h378443 ; + assign _theResult___fst_exp__h379039 = + (_theResult___fst_exp__h378491 == 8'd255) ? + _theResult___fst_exp__h378491 : + _theResult___fst_exp__h379036 ; + assign _theResult___fst_exp__h379048 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h361255 : - _theResult___fst_exp__h343944) : + _theResult___snd_fst_exp__h361222 : + _theResult___fst_exp__h343911) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h379075 : - _theResult___fst_exp__h343944) ; - assign _theResult___fst_exp__h379084 = + _theResult___snd_fst_exp__h379042 : + _theResult___fst_exp__h343911) ; + assign _theResult___fst_exp__h379051 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h379081 ; - assign _theResult___fst_exp__h397770 = - _theResult____h389661[56] ? + _theResult___fst_exp__h379048 ; + assign _theResult___fst_exp__h397737 = + _theResult____h389628[56] ? 8'd2 : - _theResult___fst_exp__h397844 ; - assign _theResult___fst_exp__h397835 = + _theResult___fst_exp__h397811 ; + assign _theResult___fst_exp__h397802 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397841 = - (!_theResult____h389661[56] && !_theResult____h389661[55] && - !_theResult____h389661[54] && - !_theResult____h389661[53] && - !_theResult____h389661[52] && - !_theResult____h389661[51] && - !_theResult____h389661[50] && - !_theResult____h389661[49] && - !_theResult____h389661[48] && - !_theResult____h389661[47] && - !_theResult____h389661[46] && - !_theResult____h389661[45] && - !_theResult____h389661[44] && - !_theResult____h389661[43] && - !_theResult____h389661[42] && - !_theResult____h389661[41] && - !_theResult____h389661[40] && - !_theResult____h389661[39] && - !_theResult____h389661[38] && - !_theResult____h389661[37] && - !_theResult____h389661[36] && - !_theResult____h389661[35] && - !_theResult____h389661[34] && - !_theResult____h389661[33] && - !_theResult____h389661[32] && - !_theResult____h389661[31] && - !_theResult____h389661[30] && - !_theResult____h389661[29] && - !_theResult____h389661[28] && - !_theResult____h389661[27] && - !_theResult____h389661[26] && - !_theResult____h389661[25] && - !_theResult____h389661[24] && - !_theResult____h389661[23] && - !_theResult____h389661[22] && - !_theResult____h389661[21] && - !_theResult____h389661[20] && - !_theResult____h389661[19] && - !_theResult____h389661[18] && - !_theResult____h389661[17] && - !_theResult____h389661[16] && - !_theResult____h389661[15] && - !_theResult____h389661[14] && - !_theResult____h389661[13] && - !_theResult____h389661[12] && - !_theResult____h389661[11] && - !_theResult____h389661[10] && - !_theResult____h389661[9] && - !_theResult____h389661[8] && - !_theResult____h389661[7] && - !_theResult____h389661[6] && - !_theResult____h389661[5] && - !_theResult____h389661[4] && - !_theResult____h389661[3] && - !_theResult____h389661[2] && - !_theResult____h389661[1] && - !_theResult____h389661[0] || + assign _theResult___fst_exp__h397808 = + (!_theResult____h389628[56] && !_theResult____h389628[55] && + !_theResult____h389628[54] && + !_theResult____h389628[53] && + !_theResult____h389628[52] && + !_theResult____h389628[51] && + !_theResult____h389628[50] && + !_theResult____h389628[49] && + !_theResult____h389628[48] && + !_theResult____h389628[47] && + !_theResult____h389628[46] && + !_theResult____h389628[45] && + !_theResult____h389628[44] && + !_theResult____h389628[43] && + !_theResult____h389628[42] && + !_theResult____h389628[41] && + !_theResult____h389628[40] && + !_theResult____h389628[39] && + !_theResult____h389628[38] && + !_theResult____h389628[37] && + !_theResult____h389628[36] && + !_theResult____h389628[35] && + !_theResult____h389628[34] && + !_theResult____h389628[33] && + !_theResult____h389628[32] && + !_theResult____h389628[31] && + !_theResult____h389628[30] && + !_theResult____h389628[29] && + !_theResult____h389628[28] && + !_theResult____h389628[27] && + !_theResult____h389628[26] && + !_theResult____h389628[25] && + !_theResult____h389628[24] && + !_theResult____h389628[23] && + !_theResult____h389628[22] && + !_theResult____h389628[21] && + !_theResult____h389628[20] && + !_theResult____h389628[19] && + !_theResult____h389628[18] && + !_theResult____h389628[17] && + !_theResult____h389628[16] && + !_theResult____h389628[15] && + !_theResult____h389628[14] && + !_theResult____h389628[13] && + !_theResult____h389628[12] && + !_theResult____h389628[11] && + !_theResult____h389628[10] && + !_theResult____h389628[9] && + !_theResult____h389628[8] && + !_theResult____h389628[7] && + !_theResult____h389628[6] && + !_theResult____h389628[5] && + !_theResult____h389628[4] && + !_theResult____h389628[3] && + !_theResult____h389628[2] && + !_theResult____h389628[1] && + !_theResult____h389628[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397835 ; - assign _theResult___fst_exp__h397844 = - (!_theResult____h389661[56] && _theResult____h389661[55]) ? + _theResult___fst_exp__h397802 ; + assign _theResult___fst_exp__h397811 = + (!_theResult____h389628[56] && _theResult____h389628[55]) ? 8'd1 : - _theResult___fst_exp__h397841 ; - assign _theResult___fst_exp__h398367 = - (_theResult___fst_exp__h397770 == 8'd255) ? - _theResult___fst_exp__h397770 : - _theResult___fst_exp__h398364 ; - assign _theResult___fst_exp__h406417 = + _theResult___fst_exp__h397808 ; + assign _theResult___fst_exp__h398334 = + (_theResult___fst_exp__h397737 == 8'd255) ? + _theResult___fst_exp__h397737 : + _theResult___fst_exp__h398331 ; + assign _theResult___fst_exp__h406384 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h406423 = + assign _theResult___fst_exp__h406390 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h406417 ; - assign _theResult___fst_exp__h406426 = + _theResult___fst_exp__h406384 ; + assign _theResult___fst_exp__h406393 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h406423 : + _theResult___fst_exp__h406390 : 8'd129 ; - assign _theResult___fst_exp__h406949 = - (_theResult___fst_exp__h406426 == 8'd255) ? - _theResult___fst_exp__h406426 : - _theResult___fst_exp__h406946 ; - assign _theResult___fst_exp__h415536 = - _theResult____h407298[56] ? + assign _theResult___fst_exp__h406916 = + (_theResult___fst_exp__h406393 == 8'd255) ? + _theResult___fst_exp__h406393 : + _theResult___fst_exp__h406913 ; + assign _theResult___fst_exp__h415503 = + _theResult____h407265[56] ? 8'd2 : - _theResult___fst_exp__h415610 ; - assign _theResult___fst_exp__h415601 = + _theResult___fst_exp__h415577 ; + assign _theResult___fst_exp__h415568 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h415607 = - (!_theResult____h407298[56] && !_theResult____h407298[55] && - !_theResult____h407298[54] && - !_theResult____h407298[53] && - !_theResult____h407298[52] && - !_theResult____h407298[51] && - !_theResult____h407298[50] && - !_theResult____h407298[49] && - !_theResult____h407298[48] && - !_theResult____h407298[47] && - !_theResult____h407298[46] && - !_theResult____h407298[45] && - !_theResult____h407298[44] && - !_theResult____h407298[43] && - !_theResult____h407298[42] && - !_theResult____h407298[41] && - !_theResult____h407298[40] && - !_theResult____h407298[39] && - !_theResult____h407298[38] && - !_theResult____h407298[37] && - !_theResult____h407298[36] && - !_theResult____h407298[35] && - !_theResult____h407298[34] && - !_theResult____h407298[33] && - !_theResult____h407298[32] && - !_theResult____h407298[31] && - !_theResult____h407298[30] && - !_theResult____h407298[29] && - !_theResult____h407298[28] && - !_theResult____h407298[27] && - !_theResult____h407298[26] && - !_theResult____h407298[25] && - !_theResult____h407298[24] && - !_theResult____h407298[23] && - !_theResult____h407298[22] && - !_theResult____h407298[21] && - !_theResult____h407298[20] && - !_theResult____h407298[19] && - !_theResult____h407298[18] && - !_theResult____h407298[17] && - !_theResult____h407298[16] && - !_theResult____h407298[15] && - !_theResult____h407298[14] && - !_theResult____h407298[13] && - !_theResult____h407298[12] && - !_theResult____h407298[11] && - !_theResult____h407298[10] && - !_theResult____h407298[9] && - !_theResult____h407298[8] && - !_theResult____h407298[7] && - !_theResult____h407298[6] && - !_theResult____h407298[5] && - !_theResult____h407298[4] && - !_theResult____h407298[3] && - !_theResult____h407298[2] && - !_theResult____h407298[1] && - !_theResult____h407298[0] || + assign _theResult___fst_exp__h415574 = + (!_theResult____h407265[56] && !_theResult____h407265[55] && + !_theResult____h407265[54] && + !_theResult____h407265[53] && + !_theResult____h407265[52] && + !_theResult____h407265[51] && + !_theResult____h407265[50] && + !_theResult____h407265[49] && + !_theResult____h407265[48] && + !_theResult____h407265[47] && + !_theResult____h407265[46] && + !_theResult____h407265[45] && + !_theResult____h407265[44] && + !_theResult____h407265[43] && + !_theResult____h407265[42] && + !_theResult____h407265[41] && + !_theResult____h407265[40] && + !_theResult____h407265[39] && + !_theResult____h407265[38] && + !_theResult____h407265[37] && + !_theResult____h407265[36] && + !_theResult____h407265[35] && + !_theResult____h407265[34] && + !_theResult____h407265[33] && + !_theResult____h407265[32] && + !_theResult____h407265[31] && + !_theResult____h407265[30] && + !_theResult____h407265[29] && + !_theResult____h407265[28] && + !_theResult____h407265[27] && + !_theResult____h407265[26] && + !_theResult____h407265[25] && + !_theResult____h407265[24] && + !_theResult____h407265[23] && + !_theResult____h407265[22] && + !_theResult____h407265[21] && + !_theResult____h407265[20] && + !_theResult____h407265[19] && + !_theResult____h407265[18] && + !_theResult____h407265[17] && + !_theResult____h407265[16] && + !_theResult____h407265[15] && + !_theResult____h407265[14] && + !_theResult____h407265[13] && + !_theResult____h407265[12] && + !_theResult____h407265[11] && + !_theResult____h407265[10] && + !_theResult____h407265[9] && + !_theResult____h407265[8] && + !_theResult____h407265[7] && + !_theResult____h407265[6] && + !_theResult____h407265[5] && + !_theResult____h407265[4] && + !_theResult____h407265[3] && + !_theResult____h407265[2] && + !_theResult____h407265[1] && + !_theResult____h407265[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h415601 ; - assign _theResult___fst_exp__h415610 = - (!_theResult____h407298[56] && _theResult____h407298[55]) ? + _theResult___fst_exp__h415568 ; + assign _theResult___fst_exp__h415577 = + (!_theResult____h407265[56] && _theResult____h407265[55]) ? 8'd1 : - _theResult___fst_exp__h415607 ; - assign _theResult___fst_exp__h416133 = - (_theResult___fst_exp__h415536 == 8'd255) ? - _theResult___fst_exp__h415536 : - _theResult___fst_exp__h416130 ; - assign _theResult___fst_exp__h424173 = + _theResult___fst_exp__h415574 ; + assign _theResult___fst_exp__h416100 = + (_theResult___fst_exp__h415503 == 8'd255) ? + _theResult___fst_exp__h415503 : + _theResult___fst_exp__h416097 ; + assign _theResult___fst_exp__h424140 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h424212 = + assign _theResult___fst_exp__h424179 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h424218 = + assign _theResult___fst_exp__h424185 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h424212 ; - assign _theResult___fst_exp__h424221 = + _theResult___fst_exp__h424179 ; + assign _theResult___fst_exp__h424188 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h424218 : - _theResult___fst_exp__h424173 ; - assign _theResult___fst_exp__h424769 = - (_theResult___fst_exp__h424221 == 8'd255) ? - _theResult___fst_exp__h424221 : - _theResult___fst_exp__h424766 ; - assign _theResult___fst_exp__h424778 = + _theResult___fst_exp__h424185 : + _theResult___fst_exp__h424140 ; + assign _theResult___fst_exp__h424736 = + (_theResult___fst_exp__h424188 == 8'd255) ? + _theResult___fst_exp__h424188 : + _theResult___fst_exp__h424733 ; + assign _theResult___fst_exp__h424745 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406952 : - _theResult___fst_exp__h389643) : + _theResult___snd_fst_exp__h406919 : + _theResult___fst_exp__h389610) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424772 : - _theResult___fst_exp__h389643) ; - assign _theResult___fst_exp__h424781 = + _theResult___snd_fst_exp__h424739 : + _theResult___fst_exp__h389610) ; + assign _theResult___fst_exp__h424748 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424778 ; - assign _theResult___fst_exp__h443465 = - _theResult____h435356[56] ? + _theResult___fst_exp__h424745 ; + assign _theResult___fst_exp__h443432 = + _theResult____h435323[56] ? 8'd2 : - _theResult___fst_exp__h443539 ; - assign _theResult___fst_exp__h443530 = + _theResult___fst_exp__h443506 ; + assign _theResult___fst_exp__h443497 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h443536 = - (!_theResult____h435356[56] && !_theResult____h435356[55] && - !_theResult____h435356[54] && - !_theResult____h435356[53] && - !_theResult____h435356[52] && - !_theResult____h435356[51] && - !_theResult____h435356[50] && - !_theResult____h435356[49] && - !_theResult____h435356[48] && - !_theResult____h435356[47] && - !_theResult____h435356[46] && - !_theResult____h435356[45] && - !_theResult____h435356[44] && - !_theResult____h435356[43] && - !_theResult____h435356[42] && - !_theResult____h435356[41] && - !_theResult____h435356[40] && - !_theResult____h435356[39] && - !_theResult____h435356[38] && - !_theResult____h435356[37] && - !_theResult____h435356[36] && - !_theResult____h435356[35] && - !_theResult____h435356[34] && - !_theResult____h435356[33] && - !_theResult____h435356[32] && - !_theResult____h435356[31] && - !_theResult____h435356[30] && - !_theResult____h435356[29] && - !_theResult____h435356[28] && - !_theResult____h435356[27] && - !_theResult____h435356[26] && - !_theResult____h435356[25] && - !_theResult____h435356[24] && - !_theResult____h435356[23] && - !_theResult____h435356[22] && - !_theResult____h435356[21] && - !_theResult____h435356[20] && - !_theResult____h435356[19] && - !_theResult____h435356[18] && - !_theResult____h435356[17] && - !_theResult____h435356[16] && - !_theResult____h435356[15] && - !_theResult____h435356[14] && - !_theResult____h435356[13] && - !_theResult____h435356[12] && - !_theResult____h435356[11] && - !_theResult____h435356[10] && - !_theResult____h435356[9] && - !_theResult____h435356[8] && - !_theResult____h435356[7] && - !_theResult____h435356[6] && - !_theResult____h435356[5] && - !_theResult____h435356[4] && - !_theResult____h435356[3] && - !_theResult____h435356[2] && - !_theResult____h435356[1] && - !_theResult____h435356[0] || + assign _theResult___fst_exp__h443503 = + (!_theResult____h435323[56] && !_theResult____h435323[55] && + !_theResult____h435323[54] && + !_theResult____h435323[53] && + !_theResult____h435323[52] && + !_theResult____h435323[51] && + !_theResult____h435323[50] && + !_theResult____h435323[49] && + !_theResult____h435323[48] && + !_theResult____h435323[47] && + !_theResult____h435323[46] && + !_theResult____h435323[45] && + !_theResult____h435323[44] && + !_theResult____h435323[43] && + !_theResult____h435323[42] && + !_theResult____h435323[41] && + !_theResult____h435323[40] && + !_theResult____h435323[39] && + !_theResult____h435323[38] && + !_theResult____h435323[37] && + !_theResult____h435323[36] && + !_theResult____h435323[35] && + !_theResult____h435323[34] && + !_theResult____h435323[33] && + !_theResult____h435323[32] && + !_theResult____h435323[31] && + !_theResult____h435323[30] && + !_theResult____h435323[29] && + !_theResult____h435323[28] && + !_theResult____h435323[27] && + !_theResult____h435323[26] && + !_theResult____h435323[25] && + !_theResult____h435323[24] && + !_theResult____h435323[23] && + !_theResult____h435323[22] && + !_theResult____h435323[21] && + !_theResult____h435323[20] && + !_theResult____h435323[19] && + !_theResult____h435323[18] && + !_theResult____h435323[17] && + !_theResult____h435323[16] && + !_theResult____h435323[15] && + !_theResult____h435323[14] && + !_theResult____h435323[13] && + !_theResult____h435323[12] && + !_theResult____h435323[11] && + !_theResult____h435323[10] && + !_theResult____h435323[9] && + !_theResult____h435323[8] && + !_theResult____h435323[7] && + !_theResult____h435323[6] && + !_theResult____h435323[5] && + !_theResult____h435323[4] && + !_theResult____h435323[3] && + !_theResult____h435323[2] && + !_theResult____h435323[1] && + !_theResult____h435323[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h443530 ; - assign _theResult___fst_exp__h443539 = - (!_theResult____h435356[56] && _theResult____h435356[55]) ? + _theResult___fst_exp__h443497 ; + assign _theResult___fst_exp__h443506 = + (!_theResult____h435323[56] && _theResult____h435323[55]) ? 8'd1 : - _theResult___fst_exp__h443536 ; - assign _theResult___fst_exp__h444062 = - (_theResult___fst_exp__h443465 == 8'd255) ? - _theResult___fst_exp__h443465 : - _theResult___fst_exp__h444059 ; - assign _theResult___fst_exp__h452112 = + _theResult___fst_exp__h443503 ; + assign _theResult___fst_exp__h444029 = + (_theResult___fst_exp__h443432 == 8'd255) ? + _theResult___fst_exp__h443432 : + _theResult___fst_exp__h444026 ; + assign _theResult___fst_exp__h452079 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h452118 = + assign _theResult___fst_exp__h452085 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h452112 ; - assign _theResult___fst_exp__h452121 = + _theResult___fst_exp__h452079 ; + assign _theResult___fst_exp__h452088 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h452118 : + _theResult___fst_exp__h452085 : 8'd129 ; - assign _theResult___fst_exp__h452644 = - (_theResult___fst_exp__h452121 == 8'd255) ? - _theResult___fst_exp__h452121 : - _theResult___fst_exp__h452641 ; - assign _theResult___fst_exp__h461231 = - _theResult____h452993[56] ? + assign _theResult___fst_exp__h452611 = + (_theResult___fst_exp__h452088 == 8'd255) ? + _theResult___fst_exp__h452088 : + _theResult___fst_exp__h452608 ; + assign _theResult___fst_exp__h461198 = + _theResult____h452960[56] ? 8'd2 : - _theResult___fst_exp__h461305 ; - assign _theResult___fst_exp__h461296 = + _theResult___fst_exp__h461272 ; + assign _theResult___fst_exp__h461263 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h461302 = - (!_theResult____h452993[56] && !_theResult____h452993[55] && - !_theResult____h452993[54] && - !_theResult____h452993[53] && - !_theResult____h452993[52] && - !_theResult____h452993[51] && - !_theResult____h452993[50] && - !_theResult____h452993[49] && - !_theResult____h452993[48] && - !_theResult____h452993[47] && - !_theResult____h452993[46] && - !_theResult____h452993[45] && - !_theResult____h452993[44] && - !_theResult____h452993[43] && - !_theResult____h452993[42] && - !_theResult____h452993[41] && - !_theResult____h452993[40] && - !_theResult____h452993[39] && - !_theResult____h452993[38] && - !_theResult____h452993[37] && - !_theResult____h452993[36] && - !_theResult____h452993[35] && - !_theResult____h452993[34] && - !_theResult____h452993[33] && - !_theResult____h452993[32] && - !_theResult____h452993[31] && - !_theResult____h452993[30] && - !_theResult____h452993[29] && - !_theResult____h452993[28] && - !_theResult____h452993[27] && - !_theResult____h452993[26] && - !_theResult____h452993[25] && - !_theResult____h452993[24] && - !_theResult____h452993[23] && - !_theResult____h452993[22] && - !_theResult____h452993[21] && - !_theResult____h452993[20] && - !_theResult____h452993[19] && - !_theResult____h452993[18] && - !_theResult____h452993[17] && - !_theResult____h452993[16] && - !_theResult____h452993[15] && - !_theResult____h452993[14] && - !_theResult____h452993[13] && - !_theResult____h452993[12] && - !_theResult____h452993[11] && - !_theResult____h452993[10] && - !_theResult____h452993[9] && - !_theResult____h452993[8] && - !_theResult____h452993[7] && - !_theResult____h452993[6] && - !_theResult____h452993[5] && - !_theResult____h452993[4] && - !_theResult____h452993[3] && - !_theResult____h452993[2] && - !_theResult____h452993[1] && - !_theResult____h452993[0] || + assign _theResult___fst_exp__h461269 = + (!_theResult____h452960[56] && !_theResult____h452960[55] && + !_theResult____h452960[54] && + !_theResult____h452960[53] && + !_theResult____h452960[52] && + !_theResult____h452960[51] && + !_theResult____h452960[50] && + !_theResult____h452960[49] && + !_theResult____h452960[48] && + !_theResult____h452960[47] && + !_theResult____h452960[46] && + !_theResult____h452960[45] && + !_theResult____h452960[44] && + !_theResult____h452960[43] && + !_theResult____h452960[42] && + !_theResult____h452960[41] && + !_theResult____h452960[40] && + !_theResult____h452960[39] && + !_theResult____h452960[38] && + !_theResult____h452960[37] && + !_theResult____h452960[36] && + !_theResult____h452960[35] && + !_theResult____h452960[34] && + !_theResult____h452960[33] && + !_theResult____h452960[32] && + !_theResult____h452960[31] && + !_theResult____h452960[30] && + !_theResult____h452960[29] && + !_theResult____h452960[28] && + !_theResult____h452960[27] && + !_theResult____h452960[26] && + !_theResult____h452960[25] && + !_theResult____h452960[24] && + !_theResult____h452960[23] && + !_theResult____h452960[22] && + !_theResult____h452960[21] && + !_theResult____h452960[20] && + !_theResult____h452960[19] && + !_theResult____h452960[18] && + !_theResult____h452960[17] && + !_theResult____h452960[16] && + !_theResult____h452960[15] && + !_theResult____h452960[14] && + !_theResult____h452960[13] && + !_theResult____h452960[12] && + !_theResult____h452960[11] && + !_theResult____h452960[10] && + !_theResult____h452960[9] && + !_theResult____h452960[8] && + !_theResult____h452960[7] && + !_theResult____h452960[6] && + !_theResult____h452960[5] && + !_theResult____h452960[4] && + !_theResult____h452960[3] && + !_theResult____h452960[2] && + !_theResult____h452960[1] && + !_theResult____h452960[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h461296 ; - assign _theResult___fst_exp__h461305 = - (!_theResult____h452993[56] && _theResult____h452993[55]) ? + _theResult___fst_exp__h461263 ; + assign _theResult___fst_exp__h461272 = + (!_theResult____h452960[56] && _theResult____h452960[55]) ? 8'd1 : - _theResult___fst_exp__h461302 ; - assign _theResult___fst_exp__h461828 = - (_theResult___fst_exp__h461231 == 8'd255) ? - _theResult___fst_exp__h461231 : - _theResult___fst_exp__h461825 ; - assign _theResult___fst_exp__h469868 = + _theResult___fst_exp__h461269 ; + assign _theResult___fst_exp__h461795 = + (_theResult___fst_exp__h461198 == 8'd255) ? + _theResult___fst_exp__h461198 : + _theResult___fst_exp__h461792 ; + assign _theResult___fst_exp__h469835 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h469907 = + assign _theResult___fst_exp__h469874 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469913 = + assign _theResult___fst_exp__h469880 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469907 ; - assign _theResult___fst_exp__h469916 = + _theResult___fst_exp__h469874 ; + assign _theResult___fst_exp__h469883 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469913 : - _theResult___fst_exp__h469868 ; - assign _theResult___fst_exp__h470464 = - (_theResult___fst_exp__h469916 == 8'd255) ? - _theResult___fst_exp__h469916 : - _theResult___fst_exp__h470461 ; - assign _theResult___fst_exp__h470473 = + _theResult___fst_exp__h469880 : + _theResult___fst_exp__h469835 ; + assign _theResult___fst_exp__h470431 = + (_theResult___fst_exp__h469883 == 8'd255) ? + _theResult___fst_exp__h469883 : + _theResult___fst_exp__h470428 ; + assign _theResult___fst_exp__h470440 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h452647 : - _theResult___fst_exp__h435338) : + _theResult___snd_fst_exp__h452614 : + _theResult___fst_exp__h435305) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h470467 : - _theResult___fst_exp__h435338) ; - assign _theResult___fst_exp__h470476 = + _theResult___snd_fst_exp__h470434 : + _theResult___fst_exp__h435305) ; + assign _theResult___fst_exp__h470443 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h470473 ; - assign _theResult___fst_exp__h484332 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? - 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_exp__h499396 = - 11'd897 - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; - assign _theResult___fst_exp__h499402 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582) ? - 11'd0 : - _theResult___fst_exp__h499396 ; - assign _theResult___fst_exp__h499405 = - (f1_exp__h480017 == 8'd0) ? - _theResult___fst_exp__h499402 : - 11'd897 ; - assign _theResult___fst_exp__h500160 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 ; - assign _theResult___fst_exp__h500163 = - (_theResult___fst_exp__h499405 == 11'd2047) ? - _theResult___fst_exp__h499405 : - _theResult___fst_exp__h500160 ; - assign _theResult___fst_exp__h508982 = - _theResult____h500746[56] ? - 11'd2 : - _theResult___fst_exp__h509056 ; - assign _theResult___fst_exp__h509047 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ; - assign _theResult___fst_exp__h509053 = - (!_theResult____h500746[56] && !_theResult____h500746[55] && - !_theResult____h500746[54] && - !_theResult____h500746[53] && - !_theResult____h500746[52] && - !_theResult____h500746[51] && - !_theResult____h500746[50] && - !_theResult____h500746[49] && - !_theResult____h500746[48] && - !_theResult____h500746[47] && - !_theResult____h500746[46] && - !_theResult____h500746[45] && - !_theResult____h500746[44] && - !_theResult____h500746[43] && - !_theResult____h500746[42] && - !_theResult____h500746[41] && - !_theResult____h500746[40] && - !_theResult____h500746[39] && - !_theResult____h500746[38] && - !_theResult____h500746[37] && - !_theResult____h500746[36] && - !_theResult____h500746[35] && - !_theResult____h500746[34] && - !_theResult____h500746[33] && - !_theResult____h500746[32] && - !_theResult____h500746[31] && - !_theResult____h500746[30] && - !_theResult____h500746[29] && - !_theResult____h500746[28] && - !_theResult____h500746[27] && - !_theResult____h500746[26] && - !_theResult____h500746[25] && - !_theResult____h500746[24] && - !_theResult____h500746[23] && - !_theResult____h500746[22] && - !_theResult____h500746[21] && - !_theResult____h500746[20] && - !_theResult____h500746[19] && - !_theResult____h500746[18] && - !_theResult____h500746[17] && - !_theResult____h500746[16] && - !_theResult____h500746[15] && - !_theResult____h500746[14] && - !_theResult____h500746[13] && - !_theResult____h500746[12] && - !_theResult____h500746[11] && - !_theResult____h500746[10] && - !_theResult____h500746[9] && - !_theResult____h500746[8] && - !_theResult____h500746[7] && - !_theResult____h500746[6] && - !_theResult____h500746[5] && - !_theResult____h500746[4] && - !_theResult____h500746[3] && - !_theResult____h500746[2] && - !_theResult____h500746[1] && - !_theResult____h500746[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894) ? - 11'd0 : - _theResult___fst_exp__h509047 ; - assign _theResult___fst_exp__h509056 = - (!_theResult____h500746[56] && _theResult____h500746[55]) ? - 11'd1 : - _theResult___fst_exp__h509053 ; - assign _theResult___fst_exp__h509811 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 ; - assign _theResult___fst_exp__h509814 = - (_theResult___fst_exp__h508982 == 11'd2047) ? - _theResult___fst_exp__h508982 : - _theResult___fst_exp__h509811 ; - assign _theResult___fst_exp__h517767 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h517806 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; - assign _theResult___fst_exp__h517812 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944) ? - 11'd0 : - _theResult___fst_exp__h517806 ; - assign _theResult___fst_exp__h517815 = - (f1_exp__h480017 == 8'd0) ? - _theResult___fst_exp__h517812 : - _theResult___fst_exp__h517767 ; - assign _theResult___fst_exp__h518595 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 ; - assign _theResult___fst_exp__h518598 = - (_theResult___fst_exp__h517815 == 11'd2047) ? - _theResult___fst_exp__h517815 : - _theResult___fst_exp__h518595 ; - assign _theResult___fst_exp__h518607 = - (f1_exp__h480017 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? - _theResult___snd_fst_exp__h500166 : - _theResult___fst_exp__h484332) : - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? - _theResult___snd_fst_exp__h518601 : - _theResult___fst_exp__h484332) ; - assign _theResult___fst_exp__h518610 = - (f1_exp__h480017 == 8'd0 && f1_sfd__h480018 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h518607 ; - assign _theResult___fst_exp__h523185 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? - 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_exp__h538249 = - 11'd897 - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; - assign _theResult___fst_exp__h538255 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082) ? - 11'd0 : - _theResult___fst_exp__h538249 ; - assign _theResult___fst_exp__h538258 = - (f2_exp__h519011 == 8'd0) ? - _theResult___fst_exp__h538255 : - 11'd897 ; - assign _theResult___fst_exp__h539013 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 ; - assign _theResult___fst_exp__h539016 = - (_theResult___fst_exp__h538258 == 11'd2047) ? - _theResult___fst_exp__h538258 : - _theResult___fst_exp__h539013 ; - assign _theResult___fst_exp__h547835 = - _theResult____h539599[56] ? - 11'd2 : - _theResult___fst_exp__h547909 ; - assign _theResult___fst_exp__h547900 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ; - assign _theResult___fst_exp__h547906 = - (!_theResult____h539599[56] && !_theResult____h539599[55] && - !_theResult____h539599[54] && - !_theResult____h539599[53] && - !_theResult____h539599[52] && - !_theResult____h539599[51] && - !_theResult____h539599[50] && - !_theResult____h539599[49] && - !_theResult____h539599[48] && - !_theResult____h539599[47] && - !_theResult____h539599[46] && - !_theResult____h539599[45] && - !_theResult____h539599[44] && - !_theResult____h539599[43] && - !_theResult____h539599[42] && - !_theResult____h539599[41] && - !_theResult____h539599[40] && - !_theResult____h539599[39] && - !_theResult____h539599[38] && - !_theResult____h539599[37] && - !_theResult____h539599[36] && - !_theResult____h539599[35] && - !_theResult____h539599[34] && - !_theResult____h539599[33] && - !_theResult____h539599[32] && - !_theResult____h539599[31] && - !_theResult____h539599[30] && - !_theResult____h539599[29] && - !_theResult____h539599[28] && - !_theResult____h539599[27] && - !_theResult____h539599[26] && - !_theResult____h539599[25] && - !_theResult____h539599[24] && - !_theResult____h539599[23] && - !_theResult____h539599[22] && - !_theResult____h539599[21] && - !_theResult____h539599[20] && - !_theResult____h539599[19] && - !_theResult____h539599[18] && - !_theResult____h539599[17] && - !_theResult____h539599[16] && - !_theResult____h539599[15] && - !_theResult____h539599[14] && - !_theResult____h539599[13] && - !_theResult____h539599[12] && - !_theResult____h539599[11] && - !_theResult____h539599[10] && - !_theResult____h539599[9] && - !_theResult____h539599[8] && - !_theResult____h539599[7] && - !_theResult____h539599[6] && - !_theResult____h539599[5] && - !_theResult____h539599[4] && - !_theResult____h539599[3] && - !_theResult____h539599[2] && - !_theResult____h539599[1] && - !_theResult____h539599[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379) ? - 11'd0 : - _theResult___fst_exp__h547900 ; - assign _theResult___fst_exp__h547909 = - (!_theResult____h539599[56] && _theResult____h539599[55]) ? - 11'd1 : - _theResult___fst_exp__h547906 ; - assign _theResult___fst_exp__h548664 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 ; - assign _theResult___fst_exp__h548667 = - (_theResult___fst_exp__h547835 == 11'd2047) ? - _theResult___fst_exp__h547835 : - _theResult___fst_exp__h548664 ; - assign _theResult___fst_exp__h556620 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h556659 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; - assign _theResult___fst_exp__h556665 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429) ? - 11'd0 : - _theResult___fst_exp__h556659 ; - assign _theResult___fst_exp__h556668 = - (f2_exp__h519011 == 8'd0) ? - _theResult___fst_exp__h556665 : - _theResult___fst_exp__h556620 ; - assign _theResult___fst_exp__h557448 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 ; - assign _theResult___fst_exp__h557451 = - (_theResult___fst_exp__h556668 == 11'd2047) ? - _theResult___fst_exp__h556668 : - _theResult___fst_exp__h557448 ; - assign _theResult___fst_exp__h557460 = - (f2_exp__h519011 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? - _theResult___snd_fst_exp__h539019 : - _theResult___fst_exp__h523185) : - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? - _theResult___snd_fst_exp__h557454 : - _theResult___fst_exp__h523185) ; - assign _theResult___fst_exp__h557463 = - (f2_exp__h519011 == 8'd0 && f2_sfd__h519012 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h557460 ; - assign _theResult___fst_exp__h562489 = + _theResult___fst_exp__h470440 ; + assign _theResult___fst_exp__h484299 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; - assign _theResult___fst_exp__h577553 = + assign _theResult___fst_exp__h499363 = + 11'd897 - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; + assign _theResult___fst_exp__h499369 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582) ? + 11'd0 : + _theResult___fst_exp__h499363 ; + assign _theResult___fst_exp__h499372 = + (f1_exp__h479984 == 8'd0) ? + _theResult___fst_exp__h499369 : + 11'd897 ; + assign _theResult___fst_exp__h500127 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 ; + assign _theResult___fst_exp__h500130 = + (_theResult___fst_exp__h499372 == 11'd2047) ? + _theResult___fst_exp__h499372 : + _theResult___fst_exp__h500127 ; + assign _theResult___fst_exp__h508949 = + _theResult____h500713[56] ? + 11'd2 : + _theResult___fst_exp__h509023 ; + assign _theResult___fst_exp__h509014 = + 11'd0 - + { 5'd0, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ; + assign _theResult___fst_exp__h509020 = + (!_theResult____h500713[56] && !_theResult____h500713[55] && + !_theResult____h500713[54] && + !_theResult____h500713[53] && + !_theResult____h500713[52] && + !_theResult____h500713[51] && + !_theResult____h500713[50] && + !_theResult____h500713[49] && + !_theResult____h500713[48] && + !_theResult____h500713[47] && + !_theResult____h500713[46] && + !_theResult____h500713[45] && + !_theResult____h500713[44] && + !_theResult____h500713[43] && + !_theResult____h500713[42] && + !_theResult____h500713[41] && + !_theResult____h500713[40] && + !_theResult____h500713[39] && + !_theResult____h500713[38] && + !_theResult____h500713[37] && + !_theResult____h500713[36] && + !_theResult____h500713[35] && + !_theResult____h500713[34] && + !_theResult____h500713[33] && + !_theResult____h500713[32] && + !_theResult____h500713[31] && + !_theResult____h500713[30] && + !_theResult____h500713[29] && + !_theResult____h500713[28] && + !_theResult____h500713[27] && + !_theResult____h500713[26] && + !_theResult____h500713[25] && + !_theResult____h500713[24] && + !_theResult____h500713[23] && + !_theResult____h500713[22] && + !_theResult____h500713[21] && + !_theResult____h500713[20] && + !_theResult____h500713[19] && + !_theResult____h500713[18] && + !_theResult____h500713[17] && + !_theResult____h500713[16] && + !_theResult____h500713[15] && + !_theResult____h500713[14] && + !_theResult____h500713[13] && + !_theResult____h500713[12] && + !_theResult____h500713[11] && + !_theResult____h500713[10] && + !_theResult____h500713[9] && + !_theResult____h500713[8] && + !_theResult____h500713[7] && + !_theResult____h500713[6] && + !_theResult____h500713[5] && + !_theResult____h500713[4] && + !_theResult____h500713[3] && + !_theResult____h500713[2] && + !_theResult____h500713[1] && + !_theResult____h500713[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894) ? + 11'd0 : + _theResult___fst_exp__h509014 ; + assign _theResult___fst_exp__h509023 = + (!_theResult____h500713[56] && _theResult____h500713[55]) ? + 11'd1 : + _theResult___fst_exp__h509020 ; + assign _theResult___fst_exp__h509778 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 ; + assign _theResult___fst_exp__h509781 = + (_theResult___fst_exp__h508949 == 11'd2047) ? + _theResult___fst_exp__h508949 : + _theResult___fst_exp__h509778 ; + assign _theResult___fst_exp__h517734 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == + 11'd0) ? + 11'd1 : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; + assign _theResult___fst_exp__h517773 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; + assign _theResult___fst_exp__h517779 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944) ? + 11'd0 : + _theResult___fst_exp__h517773 ; + assign _theResult___fst_exp__h517782 = + (f1_exp__h479984 == 8'd0) ? + _theResult___fst_exp__h517779 : + _theResult___fst_exp__h517734 ; + assign _theResult___fst_exp__h518562 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 ; + assign _theResult___fst_exp__h518565 = + (_theResult___fst_exp__h517782 == 11'd2047) ? + _theResult___fst_exp__h517782 : + _theResult___fst_exp__h518562 ; + assign _theResult___fst_exp__h518574 = + (f1_exp__h479984 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? + _theResult___snd_fst_exp__h500133 : + _theResult___fst_exp__h484299) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? + _theResult___snd_fst_exp__h518568 : + _theResult___fst_exp__h484299) ; + assign _theResult___fst_exp__h518577 = + (f1_exp__h479984 == 8'd0 && f1_sfd__h479985 == 23'd0) ? + 11'd0 : + _theResult___fst_exp__h518574 ; + assign _theResult___fst_exp__h523152 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? + 11'd2047 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + assign _theResult___fst_exp__h538216 = + 11'd897 - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; + assign _theResult___fst_exp__h538222 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082) ? + 11'd0 : + _theResult___fst_exp__h538216 ; + assign _theResult___fst_exp__h538225 = + (f2_exp__h518978 == 8'd0) ? + _theResult___fst_exp__h538222 : + 11'd897 ; + assign _theResult___fst_exp__h538980 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 ; + assign _theResult___fst_exp__h538983 = + (_theResult___fst_exp__h538225 == 11'd2047) ? + _theResult___fst_exp__h538225 : + _theResult___fst_exp__h538980 ; + assign _theResult___fst_exp__h547802 = + _theResult____h539566[56] ? + 11'd2 : + _theResult___fst_exp__h547876 ; + assign _theResult___fst_exp__h547867 = + 11'd0 - + { 5'd0, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ; + assign _theResult___fst_exp__h547873 = + (!_theResult____h539566[56] && !_theResult____h539566[55] && + !_theResult____h539566[54] && + !_theResult____h539566[53] && + !_theResult____h539566[52] && + !_theResult____h539566[51] && + !_theResult____h539566[50] && + !_theResult____h539566[49] && + !_theResult____h539566[48] && + !_theResult____h539566[47] && + !_theResult____h539566[46] && + !_theResult____h539566[45] && + !_theResult____h539566[44] && + !_theResult____h539566[43] && + !_theResult____h539566[42] && + !_theResult____h539566[41] && + !_theResult____h539566[40] && + !_theResult____h539566[39] && + !_theResult____h539566[38] && + !_theResult____h539566[37] && + !_theResult____h539566[36] && + !_theResult____h539566[35] && + !_theResult____h539566[34] && + !_theResult____h539566[33] && + !_theResult____h539566[32] && + !_theResult____h539566[31] && + !_theResult____h539566[30] && + !_theResult____h539566[29] && + !_theResult____h539566[28] && + !_theResult____h539566[27] && + !_theResult____h539566[26] && + !_theResult____h539566[25] && + !_theResult____h539566[24] && + !_theResult____h539566[23] && + !_theResult____h539566[22] && + !_theResult____h539566[21] && + !_theResult____h539566[20] && + !_theResult____h539566[19] && + !_theResult____h539566[18] && + !_theResult____h539566[17] && + !_theResult____h539566[16] && + !_theResult____h539566[15] && + !_theResult____h539566[14] && + !_theResult____h539566[13] && + !_theResult____h539566[12] && + !_theResult____h539566[11] && + !_theResult____h539566[10] && + !_theResult____h539566[9] && + !_theResult____h539566[8] && + !_theResult____h539566[7] && + !_theResult____h539566[6] && + !_theResult____h539566[5] && + !_theResult____h539566[4] && + !_theResult____h539566[3] && + !_theResult____h539566[2] && + !_theResult____h539566[1] && + !_theResult____h539566[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379) ? + 11'd0 : + _theResult___fst_exp__h547867 ; + assign _theResult___fst_exp__h547876 = + (!_theResult____h539566[56] && _theResult____h539566[55]) ? + 11'd1 : + _theResult___fst_exp__h547873 ; + assign _theResult___fst_exp__h548631 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 ; + assign _theResult___fst_exp__h548634 = + (_theResult___fst_exp__h547802 == 11'd2047) ? + _theResult___fst_exp__h547802 : + _theResult___fst_exp__h548631 ; + assign _theResult___fst_exp__h556587 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == + 11'd0) ? + 11'd1 : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; + assign _theResult___fst_exp__h556626 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; + assign _theResult___fst_exp__h556632 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429) ? + 11'd0 : + _theResult___fst_exp__h556626 ; + assign _theResult___fst_exp__h556635 = + (f2_exp__h518978 == 8'd0) ? + _theResult___fst_exp__h556632 : + _theResult___fst_exp__h556587 ; + assign _theResult___fst_exp__h557415 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 ; + assign _theResult___fst_exp__h557418 = + (_theResult___fst_exp__h556635 == 11'd2047) ? + _theResult___fst_exp__h556635 : + _theResult___fst_exp__h557415 ; + assign _theResult___fst_exp__h557427 = + (f2_exp__h518978 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? + _theResult___snd_fst_exp__h538986 : + _theResult___fst_exp__h523152) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? + _theResult___snd_fst_exp__h557421 : + _theResult___fst_exp__h523152) ; + assign _theResult___fst_exp__h557430 = + (f2_exp__h518978 == 8'd0 && f2_sfd__h518979 == 23'd0) ? + 11'd0 : + _theResult___fst_exp__h557427 ; + assign _theResult___fst_exp__h562456 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? + 11'd2047 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; + assign _theResult___fst_exp__h577520 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ; - assign _theResult___fst_exp__h577559 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___fst_exp__h577526 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312) ? 11'd0 : - _theResult___fst_exp__h577553 ; - assign _theResult___fst_exp__h577562 = - (f3_exp__h558315 == 8'd0) ? - _theResult___fst_exp__h577559 : + _theResult___fst_exp__h577520 ; + assign _theResult___fst_exp__h577529 = + (f3_exp__h558282 == 8'd0) ? + _theResult___fst_exp__h577526 : 11'd897 ; - assign _theResult___fst_exp__h578317 = + assign _theResult___fst_exp__h578284 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 : + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 ; - assign _theResult___fst_exp__h578320 = - (_theResult___fst_exp__h577562 == 11'd2047) ? - _theResult___fst_exp__h577562 : - _theResult___fst_exp__h578317 ; - assign _theResult___fst_exp__h587139 = - _theResult____h578903[56] ? + assign _theResult___fst_exp__h578287 = + (_theResult___fst_exp__h577529 == 11'd2047) ? + _theResult___fst_exp__h577529 : + _theResult___fst_exp__h578284 ; + assign _theResult___fst_exp__h587106 = + _theResult____h578870[56] ? 11'd2 : - _theResult___fst_exp__h587213 ; - assign _theResult___fst_exp__h587204 = + _theResult___fst_exp__h587180 ; + assign _theResult___fst_exp__h587171 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 } ; - assign _theResult___fst_exp__h587210 = - (!_theResult____h578903[56] && !_theResult____h578903[55] && - !_theResult____h578903[54] && - !_theResult____h578903[53] && - !_theResult____h578903[52] && - !_theResult____h578903[51] && - !_theResult____h578903[50] && - !_theResult____h578903[49] && - !_theResult____h578903[48] && - !_theResult____h578903[47] && - !_theResult____h578903[46] && - !_theResult____h578903[45] && - !_theResult____h578903[44] && - !_theResult____h578903[43] && - !_theResult____h578903[42] && - !_theResult____h578903[41] && - !_theResult____h578903[40] && - !_theResult____h578903[39] && - !_theResult____h578903[38] && - !_theResult____h578903[37] && - !_theResult____h578903[36] && - !_theResult____h578903[35] && - !_theResult____h578903[34] && - !_theResult____h578903[33] && - !_theResult____h578903[32] && - !_theResult____h578903[31] && - !_theResult____h578903[30] && - !_theResult____h578903[29] && - !_theResult____h578903[28] && - !_theResult____h578903[27] && - !_theResult____h578903[26] && - !_theResult____h578903[25] && - !_theResult____h578903[24] && - !_theResult____h578903[23] && - !_theResult____h578903[22] && - !_theResult____h578903[21] && - !_theResult____h578903[20] && - !_theResult____h578903[19] && - !_theResult____h578903[18] && - !_theResult____h578903[17] && - !_theResult____h578903[16] && - !_theResult____h578903[15] && - !_theResult____h578903[14] && - !_theResult____h578903[13] && - !_theResult____h578903[12] && - !_theResult____h578903[11] && - !_theResult____h578903[10] && - !_theResult____h578903[9] && - !_theResult____h578903[8] && - !_theResult____h578903[7] && - !_theResult____h578903[6] && - !_theResult____h578903[5] && - !_theResult____h578903[4] && - !_theResult____h578903[3] && - !_theResult____h578903[2] && - !_theResult____h578903[1] && - !_theResult____h578903[0] || + assign _theResult___fst_exp__h587177 = + (!_theResult____h578870[56] && !_theResult____h578870[55] && + !_theResult____h578870[54] && + !_theResult____h578870[53] && + !_theResult____h578870[52] && + !_theResult____h578870[51] && + !_theResult____h578870[50] && + !_theResult____h578870[49] && + !_theResult____h578870[48] && + !_theResult____h578870[47] && + !_theResult____h578870[46] && + !_theResult____h578870[45] && + !_theResult____h578870[44] && + !_theResult____h578870[43] && + !_theResult____h578870[42] && + !_theResult____h578870[41] && + !_theResult____h578870[40] && + !_theResult____h578870[39] && + !_theResult____h578870[38] && + !_theResult____h578870[37] && + !_theResult____h578870[36] && + !_theResult____h578870[35] && + !_theResult____h578870[34] && + !_theResult____h578870[33] && + !_theResult____h578870[32] && + !_theResult____h578870[31] && + !_theResult____h578870[30] && + !_theResult____h578870[29] && + !_theResult____h578870[28] && + !_theResult____h578870[27] && + !_theResult____h578870[26] && + !_theResult____h578870[25] && + !_theResult____h578870[24] && + !_theResult____h578870[23] && + !_theResult____h578870[22] && + !_theResult____h578870[21] && + !_theResult____h578870[20] && + !_theResult____h578870[19] && + !_theResult____h578870[18] && + !_theResult____h578870[17] && + !_theResult____h578870[16] && + !_theResult____h578870[15] && + !_theResult____h578870[14] && + !_theResult____h578870[13] && + !_theResult____h578870[12] && + !_theResult____h578870[11] && + !_theResult____h578870[10] && + !_theResult____h578870[9] && + !_theResult____h578870[8] && + !_theResult____h578870[7] && + !_theResult____h578870[6] && + !_theResult____h578870[5] && + !_theResult____h578870[4] && + !_theResult____h578870[3] && + !_theResult____h578870[2] && + !_theResult____h578870[1] && + !_theResult____h578870[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609) ? 11'd0 : - _theResult___fst_exp__h587204 ; - assign _theResult___fst_exp__h587213 = - (!_theResult____h578903[56] && _theResult____h578903[55]) ? + _theResult___fst_exp__h587171 ; + assign _theResult___fst_exp__h587180 = + (!_theResult____h578870[56] && _theResult____h578870[55]) ? 11'd1 : - _theResult___fst_exp__h587210 ; - assign _theResult___fst_exp__h587968 = + _theResult___fst_exp__h587177 ; + assign _theResult___fst_exp__h587935 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 : + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 ; - assign _theResult___fst_exp__h587971 = - (_theResult___fst_exp__h587139 == 11'd2047) ? - _theResult___fst_exp__h587139 : - _theResult___fst_exp__h587968 ; - assign _theResult___fst_exp__h595924 = + assign _theResult___fst_exp__h587938 = + (_theResult___fst_exp__h587106 == 11'd2047) ? + _theResult___fst_exp__h587106 : + _theResult___fst_exp__h587935 ; + assign _theResult___fst_exp__h595891 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h595963 = + assign _theResult___fst_exp__h595930 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ; - assign _theResult___fst_exp__h595969 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___fst_exp__h595936 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659) ? 11'd0 : - _theResult___fst_exp__h595963 ; - assign _theResult___fst_exp__h595972 = - (f3_exp__h558315 == 8'd0) ? - _theResult___fst_exp__h595969 : - _theResult___fst_exp__h595924 ; - assign _theResult___fst_exp__h596752 = + _theResult___fst_exp__h595930 ; + assign _theResult___fst_exp__h595939 = + (f3_exp__h558282 == 8'd0) ? + _theResult___fst_exp__h595936 : + _theResult___fst_exp__h595891 ; + assign _theResult___fst_exp__h596719 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 : + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 ; - assign _theResult___fst_exp__h596755 = - (_theResult___fst_exp__h595972 == 11'd2047) ? - _theResult___fst_exp__h595972 : - _theResult___fst_exp__h596752 ; - assign _theResult___fst_exp__h596764 = - (f3_exp__h558315 == 8'd0) ? + assign _theResult___fst_exp__h596722 = + (_theResult___fst_exp__h595939 == 11'd2047) ? + _theResult___fst_exp__h595939 : + _theResult___fst_exp__h596719 ; + assign _theResult___fst_exp__h596731 = + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? - _theResult___snd_fst_exp__h578323 : - _theResult___fst_exp__h562489) : + _theResult___snd_fst_exp__h578290 : + _theResult___fst_exp__h562456) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ? - _theResult___snd_fst_exp__h596758 : - _theResult___fst_exp__h562489) ; - assign _theResult___fst_exp__h596767 = - (f3_exp__h558315 == 8'd0 && f3_sfd__h558316 == 23'd0) ? + _theResult___snd_fst_exp__h596725 : + _theResult___fst_exp__h562456) ; + assign _theResult___fst_exp__h596734 = + (f3_exp__h558282 == 8'd0 && f3_sfd__h558283 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h596764 ; - assign _theResult___fst_sfd__h352671 = - (_theResult___fst_exp__h352073 == 8'd255) ? - sfdin__h352067[56:34] : - _theResult___fst_sfd__h352668 ; - assign _theResult___fst_sfd__h361253 = - (_theResult___fst_exp__h360729 == 8'd255) ? - _theResult___snd__h360680[56:34] : - _theResult___fst_sfd__h361250 ; - assign _theResult___fst_sfd__h370437 = - (_theResult___fst_exp__h369839 == 8'd255) ? - sfdin__h369833[56:34] : - _theResult___fst_sfd__h370434 ; - assign _theResult___fst_sfd__h379073 = - (_theResult___fst_exp__h378524 == 8'd255) ? - _theResult___snd__h378470[56:34] : - _theResult___fst_sfd__h379070 ; - assign _theResult___fst_sfd__h379082 = + _theResult___fst_exp__h596731 ; + assign _theResult___fst_sfd__h352638 = + (_theResult___fst_exp__h352040 == 8'd255) ? + sfdin__h352034[56:34] : + _theResult___fst_sfd__h352635 ; + assign _theResult___fst_sfd__h361220 = + (_theResult___fst_exp__h360696 == 8'd255) ? + _theResult___snd__h360647[56:34] : + _theResult___fst_sfd__h361217 ; + assign _theResult___fst_sfd__h370404 = + (_theResult___fst_exp__h369806 == 8'd255) ? + sfdin__h369800[56:34] : + _theResult___fst_sfd__h370401 ; + assign _theResult___fst_sfd__h379040 = + (_theResult___fst_exp__h378491 == 8'd255) ? + _theResult___snd__h378437[56:34] : + _theResult___fst_sfd__h379037 ; + assign _theResult___fst_sfd__h379049 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h361256 : - _theResult___fst_sfd__h343945) : + _theResult___snd_fst_sfd__h361223 : + _theResult___fst_sfd__h343912) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h379076 : - _theResult___fst_sfd__h343945) ; - assign _theResult___fst_sfd__h379088 = + _theResult___snd_fst_sfd__h379043 : + _theResult___fst_sfd__h343912) ; + assign _theResult___fst_sfd__h379055 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -27696,33 +27700,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h379082 ; - assign _theResult___fst_sfd__h398368 = - (_theResult___fst_exp__h397770 == 8'd255) ? - sfdin__h397764[56:34] : - _theResult___fst_sfd__h398365 ; - assign _theResult___fst_sfd__h406950 = - (_theResult___fst_exp__h406426 == 8'd255) ? - _theResult___snd__h406377[56:34] : - _theResult___fst_sfd__h406947 ; - assign _theResult___fst_sfd__h416134 = - (_theResult___fst_exp__h415536 == 8'd255) ? - sfdin__h415530[56:34] : - _theResult___fst_sfd__h416131 ; - assign _theResult___fst_sfd__h424770 = - (_theResult___fst_exp__h424221 == 8'd255) ? - _theResult___snd__h424167[56:34] : - _theResult___fst_sfd__h424767 ; - assign _theResult___fst_sfd__h424779 = + _theResult___fst_sfd__h379049 ; + assign _theResult___fst_sfd__h398335 = + (_theResult___fst_exp__h397737 == 8'd255) ? + sfdin__h397731[56:34] : + _theResult___fst_sfd__h398332 ; + assign _theResult___fst_sfd__h406917 = + (_theResult___fst_exp__h406393 == 8'd255) ? + _theResult___snd__h406344[56:34] : + _theResult___fst_sfd__h406914 ; + assign _theResult___fst_sfd__h416101 = + (_theResult___fst_exp__h415503 == 8'd255) ? + sfdin__h415497[56:34] : + _theResult___fst_sfd__h416098 ; + assign _theResult___fst_sfd__h424737 = + (_theResult___fst_exp__h424188 == 8'd255) ? + _theResult___snd__h424134[56:34] : + _theResult___fst_sfd__h424734 ; + assign _theResult___fst_sfd__h424746 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406953 : - _theResult___fst_sfd__h389644) : + _theResult___snd_fst_sfd__h406920 : + _theResult___fst_sfd__h389611) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424773 : - _theResult___fst_sfd__h389644) ; - assign _theResult___fst_sfd__h424785 = + _theResult___snd_fst_sfd__h424740 : + _theResult___fst_sfd__h389611) ; + assign _theResult___fst_sfd__h424752 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -27730,33 +27734,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424779 ; - assign _theResult___fst_sfd__h444063 = - (_theResult___fst_exp__h443465 == 8'd255) ? - sfdin__h443459[56:34] : - _theResult___fst_sfd__h444060 ; - assign _theResult___fst_sfd__h452645 = - (_theResult___fst_exp__h452121 == 8'd255) ? - _theResult___snd__h452072[56:34] : - _theResult___fst_sfd__h452642 ; - assign _theResult___fst_sfd__h461829 = - (_theResult___fst_exp__h461231 == 8'd255) ? - sfdin__h461225[56:34] : - _theResult___fst_sfd__h461826 ; - assign _theResult___fst_sfd__h470465 = - (_theResult___fst_exp__h469916 == 8'd255) ? - _theResult___snd__h469862[56:34] : - _theResult___fst_sfd__h470462 ; - assign _theResult___fst_sfd__h470474 = + _theResult___fst_sfd__h424746 ; + assign _theResult___fst_sfd__h444030 = + (_theResult___fst_exp__h443432 == 8'd255) ? + sfdin__h443426[56:34] : + _theResult___fst_sfd__h444027 ; + assign _theResult___fst_sfd__h452612 = + (_theResult___fst_exp__h452088 == 8'd255) ? + _theResult___snd__h452039[56:34] : + _theResult___fst_sfd__h452609 ; + assign _theResult___fst_sfd__h461796 = + (_theResult___fst_exp__h461198 == 8'd255) ? + sfdin__h461192[56:34] : + _theResult___fst_sfd__h461793 ; + assign _theResult___fst_sfd__h470432 = + (_theResult___fst_exp__h469883 == 8'd255) ? + _theResult___snd__h469829[56:34] : + _theResult___fst_sfd__h470429 ; + assign _theResult___fst_sfd__h470441 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h452648 : - _theResult___fst_sfd__h435339) : + _theResult___snd_fst_sfd__h452615 : + _theResult___fst_sfd__h435306) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h470468 : - _theResult___fst_sfd__h435339) ; - assign _theResult___fst_sfd__h470480 = + _theResult___snd_fst_sfd__h470435 : + _theResult___fst_sfd__h435306) ; + assign _theResult___fst_sfd__h470447 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -27764,1309 +27768,1309 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h470474 ; - assign _theResult___fst_sfd__h484333 = + _theResult___fst_sfd__h470441 ; + assign _theResult___fst_sfd__h484300 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_sfd__h500161 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + assign _theResult___fst_sfd__h500128 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 : + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 ; - assign _theResult___fst_sfd__h500164 = - (_theResult___fst_exp__h499405 == 11'd2047) ? - _theResult___snd__h499356[56:5] : - _theResult___fst_sfd__h500161 ; - assign _theResult___fst_sfd__h509812 = + assign _theResult___fst_sfd__h500131 = + (_theResult___fst_exp__h499372 == 11'd2047) ? + _theResult___snd__h499323[56:5] : + _theResult___fst_sfd__h500128 ; + assign _theResult___fst_sfd__h509779 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 ; - assign _theResult___fst_sfd__h509815 = - (_theResult___fst_exp__h508982 == 11'd2047) ? - sfdin__h508976[56:5] : - _theResult___fst_sfd__h509812 ; - assign _theResult___fst_sfd__h518596 = + assign _theResult___fst_sfd__h509782 = + (_theResult___fst_exp__h508949 == 11'd2047) ? + sfdin__h508943[56:5] : + _theResult___fst_sfd__h509779 ; + assign _theResult___fst_sfd__h518563 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 : + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 ; - assign _theResult___fst_sfd__h518599 = - (_theResult___fst_exp__h517815 == 11'd2047) ? - _theResult___snd__h517761[56:5] : - _theResult___fst_sfd__h518596 ; - assign _theResult___fst_sfd__h518608 = - (f1_exp__h480017 == 8'd0) ? + assign _theResult___fst_sfd__h518566 = + (_theResult___fst_exp__h517782 == 11'd2047) ? + _theResult___snd__h517728[56:5] : + _theResult___fst_sfd__h518563 ; + assign _theResult___fst_sfd__h518575 = + (f1_exp__h479984 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? - _theResult___snd_fst_sfd__h500167 : - _theResult___fst_sfd__h484333) : + _theResult___snd_fst_sfd__h500134 : + _theResult___fst_sfd__h484300) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? - _theResult___snd_fst_sfd__h518602 : - _theResult___fst_sfd__h484333) ; - assign _theResult___fst_sfd__h518614 = - ((f1_exp__h480017 == 8'd255 || f1_exp__h480017 == 8'd0) && - f1_sfd__h480018 == 23'd0) ? + _theResult___snd_fst_sfd__h518569 : + _theResult___fst_sfd__h484300) ; + assign _theResult___fst_sfd__h518581 = + ((f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) && + f1_sfd__h479985 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h518608 ; - assign _theResult___fst_sfd__h523186 = + _theResult___fst_sfd__h518575 ; + assign _theResult___fst_sfd__h523153 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_sfd__h539014 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; + assign _theResult___fst_sfd__h538981 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 : + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 ; - assign _theResult___fst_sfd__h539017 = - (_theResult___fst_exp__h538258 == 11'd2047) ? - _theResult___snd__h538209[56:5] : - _theResult___fst_sfd__h539014 ; - assign _theResult___fst_sfd__h548665 = + assign _theResult___fst_sfd__h538984 = + (_theResult___fst_exp__h538225 == 11'd2047) ? + _theResult___snd__h538176[56:5] : + _theResult___fst_sfd__h538981 ; + assign _theResult___fst_sfd__h548632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 ; - assign _theResult___fst_sfd__h548668 = - (_theResult___fst_exp__h547835 == 11'd2047) ? - sfdin__h547829[56:5] : - _theResult___fst_sfd__h548665 ; - assign _theResult___fst_sfd__h557449 = + assign _theResult___fst_sfd__h548635 = + (_theResult___fst_exp__h547802 == 11'd2047) ? + sfdin__h547796[56:5] : + _theResult___fst_sfd__h548632 ; + assign _theResult___fst_sfd__h557416 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 : + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 ; - assign _theResult___fst_sfd__h557452 = - (_theResult___fst_exp__h556668 == 11'd2047) ? - _theResult___snd__h556614[56:5] : - _theResult___fst_sfd__h557449 ; - assign _theResult___fst_sfd__h557461 = - (f2_exp__h519011 == 8'd0) ? + assign _theResult___fst_sfd__h557419 = + (_theResult___fst_exp__h556635 == 11'd2047) ? + _theResult___snd__h556581[56:5] : + _theResult___fst_sfd__h557416 ; + assign _theResult___fst_sfd__h557428 = + (f2_exp__h518978 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? - _theResult___snd_fst_sfd__h539020 : - _theResult___fst_sfd__h523186) : + _theResult___snd_fst_sfd__h538987 : + _theResult___fst_sfd__h523153) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? - _theResult___snd_fst_sfd__h557455 : - _theResult___fst_sfd__h523186) ; - assign _theResult___fst_sfd__h557467 = - ((f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + _theResult___snd_fst_sfd__h557422 : + _theResult___fst_sfd__h523153) ; + assign _theResult___fst_sfd__h557434 = + ((f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h557461 ; - assign _theResult___fst_sfd__h562490 = + _theResult___fst_sfd__h557428 ; + assign _theResult___fst_sfd__h562457 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h578318 = + assign _theResult___fst_sfd__h578285 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 : + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 ; - assign _theResult___fst_sfd__h578321 = - (_theResult___fst_exp__h577562 == 11'd2047) ? - _theResult___snd__h577513[56:5] : - _theResult___fst_sfd__h578318 ; - assign _theResult___fst_sfd__h587969 = + assign _theResult___fst_sfd__h578288 = + (_theResult___fst_exp__h577529 == 11'd2047) ? + _theResult___snd__h577480[56:5] : + _theResult___fst_sfd__h578285 ; + assign _theResult___fst_sfd__h587936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 ; - assign _theResult___fst_sfd__h587972 = - (_theResult___fst_exp__h587139 == 11'd2047) ? - sfdin__h587133[56:5] : - _theResult___fst_sfd__h587969 ; - assign _theResult___fst_sfd__h596753 = + assign _theResult___fst_sfd__h587939 = + (_theResult___fst_exp__h587106 == 11'd2047) ? + sfdin__h587100[56:5] : + _theResult___fst_sfd__h587936 ; + assign _theResult___fst_sfd__h596720 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 : + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 ; - assign _theResult___fst_sfd__h596756 = - (_theResult___fst_exp__h595972 == 11'd2047) ? - _theResult___snd__h595918[56:5] : - _theResult___fst_sfd__h596753 ; - assign _theResult___fst_sfd__h596765 = - (f3_exp__h558315 == 8'd0) ? + assign _theResult___fst_sfd__h596723 = + (_theResult___fst_exp__h595939 == 11'd2047) ? + _theResult___snd__h595885[56:5] : + _theResult___fst_sfd__h596720 ; + assign _theResult___fst_sfd__h596732 = + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? - _theResult___snd_fst_sfd__h578324 : - _theResult___fst_sfd__h562490) : + _theResult___snd_fst_sfd__h578291 : + _theResult___fst_sfd__h562457) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ? - _theResult___snd_fst_sfd__h596759 : - _theResult___fst_sfd__h562490) ; - assign _theResult___fst_sfd__h596771 = - ((f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + _theResult___snd_fst_sfd__h596726 : + _theResult___fst_sfd__h562457) ; + assign _theResult___fst_sfd__h596738 = + ((f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h596765 ; - assign _theResult___sfd__h352590 = - sfd__h352165[24] ? - ((_theResult___fst_exp__h352073 == 8'd254) ? + _theResult___fst_sfd__h596732 ; + assign _theResult___sfd__h352557 = + sfd__h352132[24] ? + ((_theResult___fst_exp__h352040 == 8'd254) ? 23'd0 : - sfd__h352165[23:1]) : - sfd__h352165[22:0] ; - assign _theResult___sfd__h361172 = - sfd__h360747[24] ? - ((_theResult___fst_exp__h360729 == 8'd254) ? + sfd__h352132[23:1]) : + sfd__h352132[22:0] ; + assign _theResult___sfd__h361139 = + sfd__h360714[24] ? + ((_theResult___fst_exp__h360696 == 8'd254) ? 23'd0 : - sfd__h360747[23:1]) : - sfd__h360747[22:0] ; - assign _theResult___sfd__h370356 = - sfd__h369931[24] ? - ((_theResult___fst_exp__h369839 == 8'd254) ? + sfd__h360714[23:1]) : + sfd__h360714[22:0] ; + assign _theResult___sfd__h370323 = + sfd__h369898[24] ? + ((_theResult___fst_exp__h369806 == 8'd254) ? 23'd0 : - sfd__h369931[23:1]) : - sfd__h369931[22:0] ; - assign _theResult___sfd__h378992 = - sfd__h378543[24] ? - ((_theResult___fst_exp__h378524 == 8'd254) ? + sfd__h369898[23:1]) : + sfd__h369898[22:0] ; + assign _theResult___sfd__h378959 = + sfd__h378510[24] ? + ((_theResult___fst_exp__h378491 == 8'd254) ? 23'd0 : - sfd__h378543[23:1]) : - sfd__h378543[22:0] ; - assign _theResult___sfd__h379094 = + sfd__h378510[23:1]) : + sfd__h378510[22:0] ; + assign _theResult___sfd__h379061 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h336307 : - _theResult___fst_sfd__h379088 ; - assign _theResult___sfd__h398287 = - sfd__h397862[24] ? - ((_theResult___fst_exp__h397770 == 8'd254) ? + _theResult___snd_fst_sfd__h336274 : + _theResult___fst_sfd__h379055 ; + assign _theResult___sfd__h398254 = + sfd__h397829[24] ? + ((_theResult___fst_exp__h397737 == 8'd254) ? 23'd0 : - sfd__h397862[23:1]) : - sfd__h397862[22:0] ; - assign _theResult___sfd__h406869 = - sfd__h406444[24] ? - ((_theResult___fst_exp__h406426 == 8'd254) ? + sfd__h397829[23:1]) : + sfd__h397829[22:0] ; + assign _theResult___sfd__h406836 = + sfd__h406411[24] ? + ((_theResult___fst_exp__h406393 == 8'd254) ? 23'd0 : - sfd__h406444[23:1]) : - sfd__h406444[22:0] ; - assign _theResult___sfd__h416053 = - sfd__h415628[24] ? - ((_theResult___fst_exp__h415536 == 8'd254) ? + sfd__h406411[23:1]) : + sfd__h406411[22:0] ; + assign _theResult___sfd__h416020 = + sfd__h415595[24] ? + ((_theResult___fst_exp__h415503 == 8'd254) ? 23'd0 : - sfd__h415628[23:1]) : - sfd__h415628[22:0] ; - assign _theResult___sfd__h424689 = - sfd__h424240[24] ? - ((_theResult___fst_exp__h424221 == 8'd254) ? + sfd__h415595[23:1]) : + sfd__h415595[22:0] ; + assign _theResult___sfd__h424656 = + sfd__h424207[24] ? + ((_theResult___fst_exp__h424188 == 8'd254) ? 23'd0 : - sfd__h424240[23:1]) : - sfd__h424240[22:0] ; - assign _theResult___sfd__h424791 = + sfd__h424207[23:1]) : + sfd__h424207[22:0] ; + assign _theResult___sfd__h424758 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h382009 : - _theResult___fst_sfd__h424785 ; - assign _theResult___sfd__h443982 = - sfd__h443557[24] ? - ((_theResult___fst_exp__h443465 == 8'd254) ? + _theResult___snd_fst_sfd__h381976 : + _theResult___fst_sfd__h424752 ; + assign _theResult___sfd__h443949 = + sfd__h443524[24] ? + ((_theResult___fst_exp__h443432 == 8'd254) ? 23'd0 : - sfd__h443557[23:1]) : - sfd__h443557[22:0] ; - assign _theResult___sfd__h452564 = - sfd__h452139[24] ? - ((_theResult___fst_exp__h452121 == 8'd254) ? + sfd__h443524[23:1]) : + sfd__h443524[22:0] ; + assign _theResult___sfd__h452531 = + sfd__h452106[24] ? + ((_theResult___fst_exp__h452088 == 8'd254) ? 23'd0 : - sfd__h452139[23:1]) : - sfd__h452139[22:0] ; - assign _theResult___sfd__h461748 = - sfd__h461323[24] ? - ((_theResult___fst_exp__h461231 == 8'd254) ? + sfd__h452106[23:1]) : + sfd__h452106[22:0] ; + assign _theResult___sfd__h461715 = + sfd__h461290[24] ? + ((_theResult___fst_exp__h461198 == 8'd254) ? 23'd0 : - sfd__h461323[23:1]) : - sfd__h461323[22:0] ; - assign _theResult___sfd__h470384 = - sfd__h469935[24] ? - ((_theResult___fst_exp__h469916 == 8'd254) ? + sfd__h461290[23:1]) : + sfd__h461290[22:0] ; + assign _theResult___sfd__h470351 = + sfd__h469902[24] ? + ((_theResult___fst_exp__h469883 == 8'd254) ? 23'd0 : - sfd__h469935[23:1]) : - sfd__h469935[22:0] ; - assign _theResult___sfd__h470486 = + sfd__h469902[23:1]) : + sfd__h469902[22:0] ; + assign _theResult___sfd__h470453 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427704 : - _theResult___fst_sfd__h470480 ; - assign _theResult___sfd__h500061 = - sfd__h499423[53] ? - ((_theResult___fst_exp__h499405 == 11'd2046) ? + _theResult___snd_fst_sfd__h427671 : + _theResult___fst_sfd__h470447 ; + assign _theResult___sfd__h500028 = + sfd__h499390[53] ? + ((_theResult___fst_exp__h499372 == 11'd2046) ? 52'd0 : - sfd__h499423[52:1]) : - sfd__h499423[51:0] ; - assign _theResult___sfd__h509712 = - sfd__h509074[53] ? - ((_theResult___fst_exp__h508982 == 11'd2046) ? + sfd__h499390[52:1]) : + sfd__h499390[51:0] ; + assign _theResult___sfd__h509679 = + sfd__h509041[53] ? + ((_theResult___fst_exp__h508949 == 11'd2046) ? 52'd0 : - sfd__h509074[52:1]) : - sfd__h509074[51:0] ; - assign _theResult___sfd__h518496 = - sfd__h517834[53] ? - ((_theResult___fst_exp__h517815 == 11'd2046) ? + sfd__h509041[52:1]) : + sfd__h509041[51:0] ; + assign _theResult___sfd__h518463 = + sfd__h517801[53] ? + ((_theResult___fst_exp__h517782 == 11'd2046) ? 52'd0 : - sfd__h517834[52:1]) : - sfd__h517834[51:0] ; - assign _theResult___sfd__h538914 = - sfd__h538276[53] ? - ((_theResult___fst_exp__h538258 == 11'd2046) ? + sfd__h517801[52:1]) : + sfd__h517801[51:0] ; + assign _theResult___sfd__h538881 = + sfd__h538243[53] ? + ((_theResult___fst_exp__h538225 == 11'd2046) ? 52'd0 : - sfd__h538276[52:1]) : - sfd__h538276[51:0] ; - assign _theResult___sfd__h548565 = - sfd__h547927[53] ? - ((_theResult___fst_exp__h547835 == 11'd2046) ? + sfd__h538243[52:1]) : + sfd__h538243[51:0] ; + assign _theResult___sfd__h548532 = + sfd__h547894[53] ? + ((_theResult___fst_exp__h547802 == 11'd2046) ? 52'd0 : - sfd__h547927[52:1]) : - sfd__h547927[51:0] ; - assign _theResult___sfd__h557349 = - sfd__h556687[53] ? - ((_theResult___fst_exp__h556668 == 11'd2046) ? + sfd__h547894[52:1]) : + sfd__h547894[51:0] ; + assign _theResult___sfd__h557316 = + sfd__h556654[53] ? + ((_theResult___fst_exp__h556635 == 11'd2046) ? 52'd0 : - sfd__h556687[52:1]) : - sfd__h556687[51:0] ; - assign _theResult___sfd__h578218 = - sfd__h577580[53] ? - ((_theResult___fst_exp__h577562 == 11'd2046) ? + sfd__h556654[52:1]) : + sfd__h556654[51:0] ; + assign _theResult___sfd__h578185 = + sfd__h577547[53] ? + ((_theResult___fst_exp__h577529 == 11'd2046) ? 52'd0 : - sfd__h577580[52:1]) : - sfd__h577580[51:0] ; - assign _theResult___sfd__h587869 = - sfd__h587231[53] ? - ((_theResult___fst_exp__h587139 == 11'd2046) ? + sfd__h577547[52:1]) : + sfd__h577547[51:0] ; + assign _theResult___sfd__h587836 = + sfd__h587198[53] ? + ((_theResult___fst_exp__h587106 == 11'd2046) ? 52'd0 : - sfd__h587231[52:1]) : - sfd__h587231[51:0] ; - assign _theResult___sfd__h596653 = - sfd__h595991[53] ? - ((_theResult___fst_exp__h595972 == 11'd2046) ? + sfd__h587198[52:1]) : + sfd__h587198[51:0] ; + assign _theResult___sfd__h596620 = + sfd__h595958[53] ? + ((_theResult___fst_exp__h595939 == 11'd2046) ? 52'd0 : - sfd__h595991[52:1]) : - sfd__h595991[51:0] ; - assign _theResult___snd__h352084 = { _theResult____h343962[55:0], 1'd0 } ; - assign _theResult___snd__h352095 = - (!_theResult____h343962[56] && _theResult____h343962[55]) ? - _theResult___snd__h352097 : - _theResult___snd__h352107 ; - assign _theResult___snd__h352097 = { _theResult____h343962[54:0], 2'd0 } ; - assign _theResult___snd__h352107 = - (!_theResult____h343962[56] && !_theResult____h343962[55] && - !_theResult____h343962[54] && - !_theResult____h343962[53] && - !_theResult____h343962[52] && - !_theResult____h343962[51] && - !_theResult____h343962[50] && - !_theResult____h343962[49] && - !_theResult____h343962[48] && - !_theResult____h343962[47] && - !_theResult____h343962[46] && - !_theResult____h343962[45] && - !_theResult____h343962[44] && - !_theResult____h343962[43] && - !_theResult____h343962[42] && - !_theResult____h343962[41] && - !_theResult____h343962[40] && - !_theResult____h343962[39] && - !_theResult____h343962[38] && - !_theResult____h343962[37] && - !_theResult____h343962[36] && - !_theResult____h343962[35] && - !_theResult____h343962[34] && - !_theResult____h343962[33] && - !_theResult____h343962[32] && - !_theResult____h343962[31] && - !_theResult____h343962[30] && - !_theResult____h343962[29] && - !_theResult____h343962[28] && - !_theResult____h343962[27] && - !_theResult____h343962[26] && - !_theResult____h343962[25] && - !_theResult____h343962[24] && - !_theResult____h343962[23] && - !_theResult____h343962[22] && - !_theResult____h343962[21] && - !_theResult____h343962[20] && - !_theResult____h343962[19] && - !_theResult____h343962[18] && - !_theResult____h343962[17] && - !_theResult____h343962[16] && - !_theResult____h343962[15] && - !_theResult____h343962[14] && - !_theResult____h343962[13] && - !_theResult____h343962[12] && - !_theResult____h343962[11] && - !_theResult____h343962[10] && - !_theResult____h343962[9] && - !_theResult____h343962[8] && - !_theResult____h343962[7] && - !_theResult____h343962[6] && - !_theResult____h343962[5] && - !_theResult____h343962[4] && - !_theResult____h343962[3] && - !_theResult____h343962[2] && - !_theResult____h343962[1] && - !_theResult____h343962[0]) ? - _theResult____h343962 : - _theResult___snd__h352113 ; - assign _theResult___snd__h352113 = + sfd__h595958[52:1]) : + sfd__h595958[51:0] ; + assign _theResult___snd__h352051 = { _theResult____h343929[55:0], 1'd0 } ; + assign _theResult___snd__h352062 = + (!_theResult____h343929[56] && _theResult____h343929[55]) ? + _theResult___snd__h352064 : + _theResult___snd__h352074 ; + assign _theResult___snd__h352064 = { _theResult____h343929[54:0], 2'd0 } ; + assign _theResult___snd__h352074 = + (!_theResult____h343929[56] && !_theResult____h343929[55] && + !_theResult____h343929[54] && + !_theResult____h343929[53] && + !_theResult____h343929[52] && + !_theResult____h343929[51] && + !_theResult____h343929[50] && + !_theResult____h343929[49] && + !_theResult____h343929[48] && + !_theResult____h343929[47] && + !_theResult____h343929[46] && + !_theResult____h343929[45] && + !_theResult____h343929[44] && + !_theResult____h343929[43] && + !_theResult____h343929[42] && + !_theResult____h343929[41] && + !_theResult____h343929[40] && + !_theResult____h343929[39] && + !_theResult____h343929[38] && + !_theResult____h343929[37] && + !_theResult____h343929[36] && + !_theResult____h343929[35] && + !_theResult____h343929[34] && + !_theResult____h343929[33] && + !_theResult____h343929[32] && + !_theResult____h343929[31] && + !_theResult____h343929[30] && + !_theResult____h343929[29] && + !_theResult____h343929[28] && + !_theResult____h343929[27] && + !_theResult____h343929[26] && + !_theResult____h343929[25] && + !_theResult____h343929[24] && + !_theResult____h343929[23] && + !_theResult____h343929[22] && + !_theResult____h343929[21] && + !_theResult____h343929[20] && + !_theResult____h343929[19] && + !_theResult____h343929[18] && + !_theResult____h343929[17] && + !_theResult____h343929[16] && + !_theResult____h343929[15] && + !_theResult____h343929[14] && + !_theResult____h343929[13] && + !_theResult____h343929[12] && + !_theResult____h343929[11] && + !_theResult____h343929[10] && + !_theResult____h343929[9] && + !_theResult____h343929[8] && + !_theResult____h343929[7] && + !_theResult____h343929[6] && + !_theResult____h343929[5] && + !_theResult____h343929[4] && + !_theResult____h343929[3] && + !_theResult____h343929[2] && + !_theResult____h343929[1] && + !_theResult____h343929[0]) ? + _theResult____h343929 : + _theResult___snd__h352080 ; + assign _theResult___snd__h352080 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h352136 = - _theResult____h343962 << + assign _theResult___snd__h352103 = + _theResult____h343929 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360680 = + assign _theResult___snd__h360647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360689 : - _theResult___snd__h360682 ; - assign _theResult___snd__h360682 = + _theResult___snd__h360656 : + _theResult___snd__h360649 ; + assign _theResult___snd__h360649 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360689 = + assign _theResult___snd__h360656 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h336357 : - _theResult___snd__h360695 ; - assign _theResult___snd__h360695 = + sfd__h336324 : + _theResult___snd__h360662 ; + assign _theResult___snd__h360662 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h360718 = - sfd__h336357 << + assign _theResult___snd__h360685 = + sfd__h336324 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369850 = { _theResult____h361601[55:0], 1'd0 } ; - assign _theResult___snd__h369861 = - (!_theResult____h361601[56] && _theResult____h361601[55]) ? - _theResult___snd__h369863 : - _theResult___snd__h369873 ; - assign _theResult___snd__h369863 = { _theResult____h361601[54:0], 2'd0 } ; - assign _theResult___snd__h369873 = - (!_theResult____h361601[56] && !_theResult____h361601[55] && - !_theResult____h361601[54] && - !_theResult____h361601[53] && - !_theResult____h361601[52] && - !_theResult____h361601[51] && - !_theResult____h361601[50] && - !_theResult____h361601[49] && - !_theResult____h361601[48] && - !_theResult____h361601[47] && - !_theResult____h361601[46] && - !_theResult____h361601[45] && - !_theResult____h361601[44] && - !_theResult____h361601[43] && - !_theResult____h361601[42] && - !_theResult____h361601[41] && - !_theResult____h361601[40] && - !_theResult____h361601[39] && - !_theResult____h361601[38] && - !_theResult____h361601[37] && - !_theResult____h361601[36] && - !_theResult____h361601[35] && - !_theResult____h361601[34] && - !_theResult____h361601[33] && - !_theResult____h361601[32] && - !_theResult____h361601[31] && - !_theResult____h361601[30] && - !_theResult____h361601[29] && - !_theResult____h361601[28] && - !_theResult____h361601[27] && - !_theResult____h361601[26] && - !_theResult____h361601[25] && - !_theResult____h361601[24] && - !_theResult____h361601[23] && - !_theResult____h361601[22] && - !_theResult____h361601[21] && - !_theResult____h361601[20] && - !_theResult____h361601[19] && - !_theResult____h361601[18] && - !_theResult____h361601[17] && - !_theResult____h361601[16] && - !_theResult____h361601[15] && - !_theResult____h361601[14] && - !_theResult____h361601[13] && - !_theResult____h361601[12] && - !_theResult____h361601[11] && - !_theResult____h361601[10] && - !_theResult____h361601[9] && - !_theResult____h361601[8] && - !_theResult____h361601[7] && - !_theResult____h361601[6] && - !_theResult____h361601[5] && - !_theResult____h361601[4] && - !_theResult____h361601[3] && - !_theResult____h361601[2] && - !_theResult____h361601[1] && - !_theResult____h361601[0]) ? - _theResult____h361601 : - _theResult___snd__h369879 ; - assign _theResult___snd__h369879 = + assign _theResult___snd__h369817 = { _theResult____h361568[55:0], 1'd0 } ; + assign _theResult___snd__h369828 = + (!_theResult____h361568[56] && _theResult____h361568[55]) ? + _theResult___snd__h369830 : + _theResult___snd__h369840 ; + assign _theResult___snd__h369830 = { _theResult____h361568[54:0], 2'd0 } ; + assign _theResult___snd__h369840 = + (!_theResult____h361568[56] && !_theResult____h361568[55] && + !_theResult____h361568[54] && + !_theResult____h361568[53] && + !_theResult____h361568[52] && + !_theResult____h361568[51] && + !_theResult____h361568[50] && + !_theResult____h361568[49] && + !_theResult____h361568[48] && + !_theResult____h361568[47] && + !_theResult____h361568[46] && + !_theResult____h361568[45] && + !_theResult____h361568[44] && + !_theResult____h361568[43] && + !_theResult____h361568[42] && + !_theResult____h361568[41] && + !_theResult____h361568[40] && + !_theResult____h361568[39] && + !_theResult____h361568[38] && + !_theResult____h361568[37] && + !_theResult____h361568[36] && + !_theResult____h361568[35] && + !_theResult____h361568[34] && + !_theResult____h361568[33] && + !_theResult____h361568[32] && + !_theResult____h361568[31] && + !_theResult____h361568[30] && + !_theResult____h361568[29] && + !_theResult____h361568[28] && + !_theResult____h361568[27] && + !_theResult____h361568[26] && + !_theResult____h361568[25] && + !_theResult____h361568[24] && + !_theResult____h361568[23] && + !_theResult____h361568[22] && + !_theResult____h361568[21] && + !_theResult____h361568[20] && + !_theResult____h361568[19] && + !_theResult____h361568[18] && + !_theResult____h361568[17] && + !_theResult____h361568[16] && + !_theResult____h361568[15] && + !_theResult____h361568[14] && + !_theResult____h361568[13] && + !_theResult____h361568[12] && + !_theResult____h361568[11] && + !_theResult____h361568[10] && + !_theResult____h361568[9] && + !_theResult____h361568[8] && + !_theResult____h361568[7] && + !_theResult____h361568[6] && + !_theResult____h361568[5] && + !_theResult____h361568[4] && + !_theResult____h361568[3] && + !_theResult____h361568[2] && + !_theResult____h361568[1] && + !_theResult____h361568[0]) ? + _theResult____h361568 : + _theResult___snd__h369846 ; + assign _theResult___snd__h369846 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h369902 = - _theResult____h361601 << + assign _theResult___snd__h369869 = + _theResult____h361568 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h378470 = + assign _theResult___snd__h378437 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h378484 : - _theResult___snd__h360682 ; - assign _theResult___snd__h378484 = + _theResult___snd__h378451 : + _theResult___snd__h360649 ; + assign _theResult___snd__h378451 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h336357 : - _theResult___snd__h378490 ; - assign _theResult___snd__h378490 = + sfd__h336324 : + _theResult___snd__h378457 ; + assign _theResult___snd__h378457 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h378508 = - sfd__h336357 << + assign _theResult___snd__h378475 = + sfd__h336324 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397781 = { _theResult____h389661[55:0], 1'd0 } ; - assign _theResult___snd__h397792 = - (!_theResult____h389661[56] && _theResult____h389661[55]) ? - _theResult___snd__h397794 : - _theResult___snd__h397804 ; - assign _theResult___snd__h397794 = { _theResult____h389661[54:0], 2'd0 } ; - assign _theResult___snd__h397804 = - (!_theResult____h389661[56] && !_theResult____h389661[55] && - !_theResult____h389661[54] && - !_theResult____h389661[53] && - !_theResult____h389661[52] && - !_theResult____h389661[51] && - !_theResult____h389661[50] && - !_theResult____h389661[49] && - !_theResult____h389661[48] && - !_theResult____h389661[47] && - !_theResult____h389661[46] && - !_theResult____h389661[45] && - !_theResult____h389661[44] && - !_theResult____h389661[43] && - !_theResult____h389661[42] && - !_theResult____h389661[41] && - !_theResult____h389661[40] && - !_theResult____h389661[39] && - !_theResult____h389661[38] && - !_theResult____h389661[37] && - !_theResult____h389661[36] && - !_theResult____h389661[35] && - !_theResult____h389661[34] && - !_theResult____h389661[33] && - !_theResult____h389661[32] && - !_theResult____h389661[31] && - !_theResult____h389661[30] && - !_theResult____h389661[29] && - !_theResult____h389661[28] && - !_theResult____h389661[27] && - !_theResult____h389661[26] && - !_theResult____h389661[25] && - !_theResult____h389661[24] && - !_theResult____h389661[23] && - !_theResult____h389661[22] && - !_theResult____h389661[21] && - !_theResult____h389661[20] && - !_theResult____h389661[19] && - !_theResult____h389661[18] && - !_theResult____h389661[17] && - !_theResult____h389661[16] && - !_theResult____h389661[15] && - !_theResult____h389661[14] && - !_theResult____h389661[13] && - !_theResult____h389661[12] && - !_theResult____h389661[11] && - !_theResult____h389661[10] && - !_theResult____h389661[9] && - !_theResult____h389661[8] && - !_theResult____h389661[7] && - !_theResult____h389661[6] && - !_theResult____h389661[5] && - !_theResult____h389661[4] && - !_theResult____h389661[3] && - !_theResult____h389661[2] && - !_theResult____h389661[1] && - !_theResult____h389661[0]) ? - _theResult____h389661 : - _theResult___snd__h397810 ; - assign _theResult___snd__h397810 = + assign _theResult___snd__h397748 = { _theResult____h389628[55:0], 1'd0 } ; + assign _theResult___snd__h397759 = + (!_theResult____h389628[56] && _theResult____h389628[55]) ? + _theResult___snd__h397761 : + _theResult___snd__h397771 ; + assign _theResult___snd__h397761 = { _theResult____h389628[54:0], 2'd0 } ; + assign _theResult___snd__h397771 = + (!_theResult____h389628[56] && !_theResult____h389628[55] && + !_theResult____h389628[54] && + !_theResult____h389628[53] && + !_theResult____h389628[52] && + !_theResult____h389628[51] && + !_theResult____h389628[50] && + !_theResult____h389628[49] && + !_theResult____h389628[48] && + !_theResult____h389628[47] && + !_theResult____h389628[46] && + !_theResult____h389628[45] && + !_theResult____h389628[44] && + !_theResult____h389628[43] && + !_theResult____h389628[42] && + !_theResult____h389628[41] && + !_theResult____h389628[40] && + !_theResult____h389628[39] && + !_theResult____h389628[38] && + !_theResult____h389628[37] && + !_theResult____h389628[36] && + !_theResult____h389628[35] && + !_theResult____h389628[34] && + !_theResult____h389628[33] && + !_theResult____h389628[32] && + !_theResult____h389628[31] && + !_theResult____h389628[30] && + !_theResult____h389628[29] && + !_theResult____h389628[28] && + !_theResult____h389628[27] && + !_theResult____h389628[26] && + !_theResult____h389628[25] && + !_theResult____h389628[24] && + !_theResult____h389628[23] && + !_theResult____h389628[22] && + !_theResult____h389628[21] && + !_theResult____h389628[20] && + !_theResult____h389628[19] && + !_theResult____h389628[18] && + !_theResult____h389628[17] && + !_theResult____h389628[16] && + !_theResult____h389628[15] && + !_theResult____h389628[14] && + !_theResult____h389628[13] && + !_theResult____h389628[12] && + !_theResult____h389628[11] && + !_theResult____h389628[10] && + !_theResult____h389628[9] && + !_theResult____h389628[8] && + !_theResult____h389628[7] && + !_theResult____h389628[6] && + !_theResult____h389628[5] && + !_theResult____h389628[4] && + !_theResult____h389628[3] && + !_theResult____h389628[2] && + !_theResult____h389628[1] && + !_theResult____h389628[0]) ? + _theResult____h389628 : + _theResult___snd__h397777 ; + assign _theResult___snd__h397777 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h397833 = - _theResult____h389661 << + assign _theResult___snd__h397800 = + _theResult____h389628 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h406377 = + assign _theResult___snd__h406344 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h406386 : - _theResult___snd__h406379 ; - assign _theResult___snd__h406379 = + _theResult___snd__h406353 : + _theResult___snd__h406346 ; + assign _theResult___snd__h406346 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h406386 = + assign _theResult___snd__h406353 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h382059 : - _theResult___snd__h406392 ; - assign _theResult___snd__h406392 = + sfd__h382026 : + _theResult___snd__h406359 ; + assign _theResult___snd__h406359 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h406415 = - sfd__h382059 << + assign _theResult___snd__h406382 = + sfd__h382026 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h415547 = { _theResult____h407298[55:0], 1'd0 } ; - assign _theResult___snd__h415558 = - (!_theResult____h407298[56] && _theResult____h407298[55]) ? - _theResult___snd__h415560 : - _theResult___snd__h415570 ; - assign _theResult___snd__h415560 = { _theResult____h407298[54:0], 2'd0 } ; - assign _theResult___snd__h415570 = - (!_theResult____h407298[56] && !_theResult____h407298[55] && - !_theResult____h407298[54] && - !_theResult____h407298[53] && - !_theResult____h407298[52] && - !_theResult____h407298[51] && - !_theResult____h407298[50] && - !_theResult____h407298[49] && - !_theResult____h407298[48] && - !_theResult____h407298[47] && - !_theResult____h407298[46] && - !_theResult____h407298[45] && - !_theResult____h407298[44] && - !_theResult____h407298[43] && - !_theResult____h407298[42] && - !_theResult____h407298[41] && - !_theResult____h407298[40] && - !_theResult____h407298[39] && - !_theResult____h407298[38] && - !_theResult____h407298[37] && - !_theResult____h407298[36] && - !_theResult____h407298[35] && - !_theResult____h407298[34] && - !_theResult____h407298[33] && - !_theResult____h407298[32] && - !_theResult____h407298[31] && - !_theResult____h407298[30] && - !_theResult____h407298[29] && - !_theResult____h407298[28] && - !_theResult____h407298[27] && - !_theResult____h407298[26] && - !_theResult____h407298[25] && - !_theResult____h407298[24] && - !_theResult____h407298[23] && - !_theResult____h407298[22] && - !_theResult____h407298[21] && - !_theResult____h407298[20] && - !_theResult____h407298[19] && - !_theResult____h407298[18] && - !_theResult____h407298[17] && - !_theResult____h407298[16] && - !_theResult____h407298[15] && - !_theResult____h407298[14] && - !_theResult____h407298[13] && - !_theResult____h407298[12] && - !_theResult____h407298[11] && - !_theResult____h407298[10] && - !_theResult____h407298[9] && - !_theResult____h407298[8] && - !_theResult____h407298[7] && - !_theResult____h407298[6] && - !_theResult____h407298[5] && - !_theResult____h407298[4] && - !_theResult____h407298[3] && - !_theResult____h407298[2] && - !_theResult____h407298[1] && - !_theResult____h407298[0]) ? - _theResult____h407298 : - _theResult___snd__h415576 ; - assign _theResult___snd__h415576 = + assign _theResult___snd__h415514 = { _theResult____h407265[55:0], 1'd0 } ; + assign _theResult___snd__h415525 = + (!_theResult____h407265[56] && _theResult____h407265[55]) ? + _theResult___snd__h415527 : + _theResult___snd__h415537 ; + assign _theResult___snd__h415527 = { _theResult____h407265[54:0], 2'd0 } ; + assign _theResult___snd__h415537 = + (!_theResult____h407265[56] && !_theResult____h407265[55] && + !_theResult____h407265[54] && + !_theResult____h407265[53] && + !_theResult____h407265[52] && + !_theResult____h407265[51] && + !_theResult____h407265[50] && + !_theResult____h407265[49] && + !_theResult____h407265[48] && + !_theResult____h407265[47] && + !_theResult____h407265[46] && + !_theResult____h407265[45] && + !_theResult____h407265[44] && + !_theResult____h407265[43] && + !_theResult____h407265[42] && + !_theResult____h407265[41] && + !_theResult____h407265[40] && + !_theResult____h407265[39] && + !_theResult____h407265[38] && + !_theResult____h407265[37] && + !_theResult____h407265[36] && + !_theResult____h407265[35] && + !_theResult____h407265[34] && + !_theResult____h407265[33] && + !_theResult____h407265[32] && + !_theResult____h407265[31] && + !_theResult____h407265[30] && + !_theResult____h407265[29] && + !_theResult____h407265[28] && + !_theResult____h407265[27] && + !_theResult____h407265[26] && + !_theResult____h407265[25] && + !_theResult____h407265[24] && + !_theResult____h407265[23] && + !_theResult____h407265[22] && + !_theResult____h407265[21] && + !_theResult____h407265[20] && + !_theResult____h407265[19] && + !_theResult____h407265[18] && + !_theResult____h407265[17] && + !_theResult____h407265[16] && + !_theResult____h407265[15] && + !_theResult____h407265[14] && + !_theResult____h407265[13] && + !_theResult____h407265[12] && + !_theResult____h407265[11] && + !_theResult____h407265[10] && + !_theResult____h407265[9] && + !_theResult____h407265[8] && + !_theResult____h407265[7] && + !_theResult____h407265[6] && + !_theResult____h407265[5] && + !_theResult____h407265[4] && + !_theResult____h407265[3] && + !_theResult____h407265[2] && + !_theResult____h407265[1] && + !_theResult____h407265[0]) ? + _theResult____h407265 : + _theResult___snd__h415543 ; + assign _theResult___snd__h415543 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h415599 = - _theResult____h407298 << + assign _theResult___snd__h415566 = + _theResult____h407265 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h424167 = + assign _theResult___snd__h424134 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h424181 : - _theResult___snd__h406379 ; - assign _theResult___snd__h424181 = + _theResult___snd__h424148 : + _theResult___snd__h406346 ; + assign _theResult___snd__h424148 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h382059 : - _theResult___snd__h424187 ; - assign _theResult___snd__h424187 = + sfd__h382026 : + _theResult___snd__h424154 ; + assign _theResult___snd__h424154 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h424205 = - sfd__h382059 << + assign _theResult___snd__h424172 = + sfd__h382026 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h443476 = { _theResult____h435356[55:0], 1'd0 } ; - assign _theResult___snd__h443487 = - (!_theResult____h435356[56] && _theResult____h435356[55]) ? - _theResult___snd__h443489 : - _theResult___snd__h443499 ; - assign _theResult___snd__h443489 = { _theResult____h435356[54:0], 2'd0 } ; - assign _theResult___snd__h443499 = - (!_theResult____h435356[56] && !_theResult____h435356[55] && - !_theResult____h435356[54] && - !_theResult____h435356[53] && - !_theResult____h435356[52] && - !_theResult____h435356[51] && - !_theResult____h435356[50] && - !_theResult____h435356[49] && - !_theResult____h435356[48] && - !_theResult____h435356[47] && - !_theResult____h435356[46] && - !_theResult____h435356[45] && - !_theResult____h435356[44] && - !_theResult____h435356[43] && - !_theResult____h435356[42] && - !_theResult____h435356[41] && - !_theResult____h435356[40] && - !_theResult____h435356[39] && - !_theResult____h435356[38] && - !_theResult____h435356[37] && - !_theResult____h435356[36] && - !_theResult____h435356[35] && - !_theResult____h435356[34] && - !_theResult____h435356[33] && - !_theResult____h435356[32] && - !_theResult____h435356[31] && - !_theResult____h435356[30] && - !_theResult____h435356[29] && - !_theResult____h435356[28] && - !_theResult____h435356[27] && - !_theResult____h435356[26] && - !_theResult____h435356[25] && - !_theResult____h435356[24] && - !_theResult____h435356[23] && - !_theResult____h435356[22] && - !_theResult____h435356[21] && - !_theResult____h435356[20] && - !_theResult____h435356[19] && - !_theResult____h435356[18] && - !_theResult____h435356[17] && - !_theResult____h435356[16] && - !_theResult____h435356[15] && - !_theResult____h435356[14] && - !_theResult____h435356[13] && - !_theResult____h435356[12] && - !_theResult____h435356[11] && - !_theResult____h435356[10] && - !_theResult____h435356[9] && - !_theResult____h435356[8] && - !_theResult____h435356[7] && - !_theResult____h435356[6] && - !_theResult____h435356[5] && - !_theResult____h435356[4] && - !_theResult____h435356[3] && - !_theResult____h435356[2] && - !_theResult____h435356[1] && - !_theResult____h435356[0]) ? - _theResult____h435356 : - _theResult___snd__h443505 ; - assign _theResult___snd__h443505 = + assign _theResult___snd__h443443 = { _theResult____h435323[55:0], 1'd0 } ; + assign _theResult___snd__h443454 = + (!_theResult____h435323[56] && _theResult____h435323[55]) ? + _theResult___snd__h443456 : + _theResult___snd__h443466 ; + assign _theResult___snd__h443456 = { _theResult____h435323[54:0], 2'd0 } ; + assign _theResult___snd__h443466 = + (!_theResult____h435323[56] && !_theResult____h435323[55] && + !_theResult____h435323[54] && + !_theResult____h435323[53] && + !_theResult____h435323[52] && + !_theResult____h435323[51] && + !_theResult____h435323[50] && + !_theResult____h435323[49] && + !_theResult____h435323[48] && + !_theResult____h435323[47] && + !_theResult____h435323[46] && + !_theResult____h435323[45] && + !_theResult____h435323[44] && + !_theResult____h435323[43] && + !_theResult____h435323[42] && + !_theResult____h435323[41] && + !_theResult____h435323[40] && + !_theResult____h435323[39] && + !_theResult____h435323[38] && + !_theResult____h435323[37] && + !_theResult____h435323[36] && + !_theResult____h435323[35] && + !_theResult____h435323[34] && + !_theResult____h435323[33] && + !_theResult____h435323[32] && + !_theResult____h435323[31] && + !_theResult____h435323[30] && + !_theResult____h435323[29] && + !_theResult____h435323[28] && + !_theResult____h435323[27] && + !_theResult____h435323[26] && + !_theResult____h435323[25] && + !_theResult____h435323[24] && + !_theResult____h435323[23] && + !_theResult____h435323[22] && + !_theResult____h435323[21] && + !_theResult____h435323[20] && + !_theResult____h435323[19] && + !_theResult____h435323[18] && + !_theResult____h435323[17] && + !_theResult____h435323[16] && + !_theResult____h435323[15] && + !_theResult____h435323[14] && + !_theResult____h435323[13] && + !_theResult____h435323[12] && + !_theResult____h435323[11] && + !_theResult____h435323[10] && + !_theResult____h435323[9] && + !_theResult____h435323[8] && + !_theResult____h435323[7] && + !_theResult____h435323[6] && + !_theResult____h435323[5] && + !_theResult____h435323[4] && + !_theResult____h435323[3] && + !_theResult____h435323[2] && + !_theResult____h435323[1] && + !_theResult____h435323[0]) ? + _theResult____h435323 : + _theResult___snd__h443472 ; + assign _theResult___snd__h443472 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h443528 = - _theResult____h435356 << + assign _theResult___snd__h443495 = + _theResult____h435323 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h452072 = + assign _theResult___snd__h452039 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h452081 : - _theResult___snd__h452074 ; - assign _theResult___snd__h452074 = + _theResult___snd__h452048 : + _theResult___snd__h452041 ; + assign _theResult___snd__h452041 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h452081 = + assign _theResult___snd__h452048 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427754 : - _theResult___snd__h452087 ; - assign _theResult___snd__h452087 = + sfd__h427721 : + _theResult___snd__h452054 ; + assign _theResult___snd__h452054 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h452110 = - sfd__h427754 << + assign _theResult___snd__h452077 = + sfd__h427721 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h461242 = { _theResult____h452993[55:0], 1'd0 } ; - assign _theResult___snd__h461253 = - (!_theResult____h452993[56] && _theResult____h452993[55]) ? - _theResult___snd__h461255 : - _theResult___snd__h461265 ; - assign _theResult___snd__h461255 = { _theResult____h452993[54:0], 2'd0 } ; - assign _theResult___snd__h461265 = - (!_theResult____h452993[56] && !_theResult____h452993[55] && - !_theResult____h452993[54] && - !_theResult____h452993[53] && - !_theResult____h452993[52] && - !_theResult____h452993[51] && - !_theResult____h452993[50] && - !_theResult____h452993[49] && - !_theResult____h452993[48] && - !_theResult____h452993[47] && - !_theResult____h452993[46] && - !_theResult____h452993[45] && - !_theResult____h452993[44] && - !_theResult____h452993[43] && - !_theResult____h452993[42] && - !_theResult____h452993[41] && - !_theResult____h452993[40] && - !_theResult____h452993[39] && - !_theResult____h452993[38] && - !_theResult____h452993[37] && - !_theResult____h452993[36] && - !_theResult____h452993[35] && - !_theResult____h452993[34] && - !_theResult____h452993[33] && - !_theResult____h452993[32] && - !_theResult____h452993[31] && - !_theResult____h452993[30] && - !_theResult____h452993[29] && - !_theResult____h452993[28] && - !_theResult____h452993[27] && - !_theResult____h452993[26] && - !_theResult____h452993[25] && - !_theResult____h452993[24] && - !_theResult____h452993[23] && - !_theResult____h452993[22] && - !_theResult____h452993[21] && - !_theResult____h452993[20] && - !_theResult____h452993[19] && - !_theResult____h452993[18] && - !_theResult____h452993[17] && - !_theResult____h452993[16] && - !_theResult____h452993[15] && - !_theResult____h452993[14] && - !_theResult____h452993[13] && - !_theResult____h452993[12] && - !_theResult____h452993[11] && - !_theResult____h452993[10] && - !_theResult____h452993[9] && - !_theResult____h452993[8] && - !_theResult____h452993[7] && - !_theResult____h452993[6] && - !_theResult____h452993[5] && - !_theResult____h452993[4] && - !_theResult____h452993[3] && - !_theResult____h452993[2] && - !_theResult____h452993[1] && - !_theResult____h452993[0]) ? - _theResult____h452993 : - _theResult___snd__h461271 ; - assign _theResult___snd__h461271 = + assign _theResult___snd__h461209 = { _theResult____h452960[55:0], 1'd0 } ; + assign _theResult___snd__h461220 = + (!_theResult____h452960[56] && _theResult____h452960[55]) ? + _theResult___snd__h461222 : + _theResult___snd__h461232 ; + assign _theResult___snd__h461222 = { _theResult____h452960[54:0], 2'd0 } ; + assign _theResult___snd__h461232 = + (!_theResult____h452960[56] && !_theResult____h452960[55] && + !_theResult____h452960[54] && + !_theResult____h452960[53] && + !_theResult____h452960[52] && + !_theResult____h452960[51] && + !_theResult____h452960[50] && + !_theResult____h452960[49] && + !_theResult____h452960[48] && + !_theResult____h452960[47] && + !_theResult____h452960[46] && + !_theResult____h452960[45] && + !_theResult____h452960[44] && + !_theResult____h452960[43] && + !_theResult____h452960[42] && + !_theResult____h452960[41] && + !_theResult____h452960[40] && + !_theResult____h452960[39] && + !_theResult____h452960[38] && + !_theResult____h452960[37] && + !_theResult____h452960[36] && + !_theResult____h452960[35] && + !_theResult____h452960[34] && + !_theResult____h452960[33] && + !_theResult____h452960[32] && + !_theResult____h452960[31] && + !_theResult____h452960[30] && + !_theResult____h452960[29] && + !_theResult____h452960[28] && + !_theResult____h452960[27] && + !_theResult____h452960[26] && + !_theResult____h452960[25] && + !_theResult____h452960[24] && + !_theResult____h452960[23] && + !_theResult____h452960[22] && + !_theResult____h452960[21] && + !_theResult____h452960[20] && + !_theResult____h452960[19] && + !_theResult____h452960[18] && + !_theResult____h452960[17] && + !_theResult____h452960[16] && + !_theResult____h452960[15] && + !_theResult____h452960[14] && + !_theResult____h452960[13] && + !_theResult____h452960[12] && + !_theResult____h452960[11] && + !_theResult____h452960[10] && + !_theResult____h452960[9] && + !_theResult____h452960[8] && + !_theResult____h452960[7] && + !_theResult____h452960[6] && + !_theResult____h452960[5] && + !_theResult____h452960[4] && + !_theResult____h452960[3] && + !_theResult____h452960[2] && + !_theResult____h452960[1] && + !_theResult____h452960[0]) ? + _theResult____h452960 : + _theResult___snd__h461238 ; + assign _theResult___snd__h461238 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h461294 = - _theResult____h452993 << + assign _theResult___snd__h461261 = + _theResult____h452960 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469862 = + assign _theResult___snd__h469829 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469876 : - _theResult___snd__h452074 ; - assign _theResult___snd__h469876 = + _theResult___snd__h469843 : + _theResult___snd__h452041 ; + assign _theResult___snd__h469843 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427754 : - _theResult___snd__h469882 ; - assign _theResult___snd__h469882 = + sfd__h427721 : + _theResult___snd__h469849 ; + assign _theResult___snd__h469849 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h469900 = - sfd__h427754 << + assign _theResult___snd__h469867 = + sfd__h427721 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h499356 = - (f1_exp__h480017 == 8'd0) ? - _theResult___snd__h499365 : - _theResult___snd__h499358 ; - assign _theResult___snd__h499358 = { f1_sfd__h480018, 34'd0 } ; - assign _theResult___snd__h499365 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && + assign _theResult___snd__h499323 = + (f1_exp__h479984 == 8'd0) ? + _theResult___snd__h499332 : + _theResult___snd__h499325 ; + assign _theResult___snd__h499325 = { f1_sfd__h479985, 34'd0 } ; + assign _theResult___snd__h499332 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ? - sfd__h480379 : - _theResult___snd__h499371 ; - assign _theResult___snd__h499371 = + sfd__h480346 : + _theResult___snd__h499338 ; + assign _theResult___snd__h499338 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h499394 = - sfd__h480379 << + assign _theResult___snd__h499361 = + sfd__h480346 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 ; - assign _theResult___snd__h508993 = { _theResult____h500746[55:0], 1'd0 } ; - assign _theResult___snd__h509004 = - (!_theResult____h500746[56] && _theResult____h500746[55]) ? - _theResult___snd__h509006 : - _theResult___snd__h509016 ; - assign _theResult___snd__h509006 = { _theResult____h500746[54:0], 2'd0 } ; - assign _theResult___snd__h509016 = - (!_theResult____h500746[56] && !_theResult____h500746[55] && - !_theResult____h500746[54] && - !_theResult____h500746[53] && - !_theResult____h500746[52] && - !_theResult____h500746[51] && - !_theResult____h500746[50] && - !_theResult____h500746[49] && - !_theResult____h500746[48] && - !_theResult____h500746[47] && - !_theResult____h500746[46] && - !_theResult____h500746[45] && - !_theResult____h500746[44] && - !_theResult____h500746[43] && - !_theResult____h500746[42] && - !_theResult____h500746[41] && - !_theResult____h500746[40] && - !_theResult____h500746[39] && - !_theResult____h500746[38] && - !_theResult____h500746[37] && - !_theResult____h500746[36] && - !_theResult____h500746[35] && - !_theResult____h500746[34] && - !_theResult____h500746[33] && - !_theResult____h500746[32] && - !_theResult____h500746[31] && - !_theResult____h500746[30] && - !_theResult____h500746[29] && - !_theResult____h500746[28] && - !_theResult____h500746[27] && - !_theResult____h500746[26] && - !_theResult____h500746[25] && - !_theResult____h500746[24] && - !_theResult____h500746[23] && - !_theResult____h500746[22] && - !_theResult____h500746[21] && - !_theResult____h500746[20] && - !_theResult____h500746[19] && - !_theResult____h500746[18] && - !_theResult____h500746[17] && - !_theResult____h500746[16] && - !_theResult____h500746[15] && - !_theResult____h500746[14] && - !_theResult____h500746[13] && - !_theResult____h500746[12] && - !_theResult____h500746[11] && - !_theResult____h500746[10] && - !_theResult____h500746[9] && - !_theResult____h500746[8] && - !_theResult____h500746[7] && - !_theResult____h500746[6] && - !_theResult____h500746[5] && - !_theResult____h500746[4] && - !_theResult____h500746[3] && - !_theResult____h500746[2] && - !_theResult____h500746[1] && - !_theResult____h500746[0]) ? - _theResult____h500746 : - _theResult___snd__h509022 ; - assign _theResult___snd__h509022 = + assign _theResult___snd__h508960 = { _theResult____h500713[55:0], 1'd0 } ; + assign _theResult___snd__h508971 = + (!_theResult____h500713[56] && _theResult____h500713[55]) ? + _theResult___snd__h508973 : + _theResult___snd__h508983 ; + assign _theResult___snd__h508973 = { _theResult____h500713[54:0], 2'd0 } ; + assign _theResult___snd__h508983 = + (!_theResult____h500713[56] && !_theResult____h500713[55] && + !_theResult____h500713[54] && + !_theResult____h500713[53] && + !_theResult____h500713[52] && + !_theResult____h500713[51] && + !_theResult____h500713[50] && + !_theResult____h500713[49] && + !_theResult____h500713[48] && + !_theResult____h500713[47] && + !_theResult____h500713[46] && + !_theResult____h500713[45] && + !_theResult____h500713[44] && + !_theResult____h500713[43] && + !_theResult____h500713[42] && + !_theResult____h500713[41] && + !_theResult____h500713[40] && + !_theResult____h500713[39] && + !_theResult____h500713[38] && + !_theResult____h500713[37] && + !_theResult____h500713[36] && + !_theResult____h500713[35] && + !_theResult____h500713[34] && + !_theResult____h500713[33] && + !_theResult____h500713[32] && + !_theResult____h500713[31] && + !_theResult____h500713[30] && + !_theResult____h500713[29] && + !_theResult____h500713[28] && + !_theResult____h500713[27] && + !_theResult____h500713[26] && + !_theResult____h500713[25] && + !_theResult____h500713[24] && + !_theResult____h500713[23] && + !_theResult____h500713[22] && + !_theResult____h500713[21] && + !_theResult____h500713[20] && + !_theResult____h500713[19] && + !_theResult____h500713[18] && + !_theResult____h500713[17] && + !_theResult____h500713[16] && + !_theResult____h500713[15] && + !_theResult____h500713[14] && + !_theResult____h500713[13] && + !_theResult____h500713[12] && + !_theResult____h500713[11] && + !_theResult____h500713[10] && + !_theResult____h500713[9] && + !_theResult____h500713[8] && + !_theResult____h500713[7] && + !_theResult____h500713[6] && + !_theResult____h500713[5] && + !_theResult____h500713[4] && + !_theResult____h500713[3] && + !_theResult____h500713[2] && + !_theResult____h500713[1] && + !_theResult____h500713[0]) ? + _theResult____h500713 : + _theResult___snd__h508989 ; + assign _theResult___snd__h508989 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h509045 = - _theResult____h500746 << + assign _theResult___snd__h509012 = + _theResult____h500713 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 ; - assign _theResult___snd__h517761 = - (f1_exp__h480017 == 8'd0) ? - _theResult___snd__h517775 : - _theResult___snd__h499358 ; - assign _theResult___snd__h517775 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && + assign _theResult___snd__h517728 = + (f1_exp__h479984 == 8'd0) ? + _theResult___snd__h517742 : + _theResult___snd__h499325 ; + assign _theResult___snd__h517742 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ? - sfd__h480379 : - _theResult___snd__h517781 ; - assign _theResult___snd__h517781 = + sfd__h480346 : + _theResult___snd__h517748 ; + assign _theResult___snd__h517748 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h517799 = - sfd__h480379 << + assign _theResult___snd__h517766 = + sfd__h480346 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 ; - assign _theResult___snd__h538209 = - (f2_exp__h519011 == 8'd0) ? - _theResult___snd__h538218 : - _theResult___snd__h538211 ; - assign _theResult___snd__h538211 = { f2_sfd__h519012, 34'd0 } ; - assign _theResult___snd__h538218 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && + assign _theResult___snd__h538176 = + (f2_exp__h518978 == 8'd0) ? + _theResult___snd__h538185 : + _theResult___snd__h538178 ; + assign _theResult___snd__h538178 = { f2_sfd__h518979, 34'd0 } ; + assign _theResult___snd__h538185 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ? - sfd__h519373 : - _theResult___snd__h538224 ; - assign _theResult___snd__h538224 = + sfd__h519340 : + _theResult___snd__h538191 ; + assign _theResult___snd__h538191 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h538247 = - sfd__h519373 << + assign _theResult___snd__h538214 = + sfd__h519340 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 ; - assign _theResult___snd__h547846 = { _theResult____h539599[55:0], 1'd0 } ; - assign _theResult___snd__h547857 = - (!_theResult____h539599[56] && _theResult____h539599[55]) ? - _theResult___snd__h547859 : - _theResult___snd__h547869 ; - assign _theResult___snd__h547859 = { _theResult____h539599[54:0], 2'd0 } ; - assign _theResult___snd__h547869 = - (!_theResult____h539599[56] && !_theResult____h539599[55] && - !_theResult____h539599[54] && - !_theResult____h539599[53] && - !_theResult____h539599[52] && - !_theResult____h539599[51] && - !_theResult____h539599[50] && - !_theResult____h539599[49] && - !_theResult____h539599[48] && - !_theResult____h539599[47] && - !_theResult____h539599[46] && - !_theResult____h539599[45] && - !_theResult____h539599[44] && - !_theResult____h539599[43] && - !_theResult____h539599[42] && - !_theResult____h539599[41] && - !_theResult____h539599[40] && - !_theResult____h539599[39] && - !_theResult____h539599[38] && - !_theResult____h539599[37] && - !_theResult____h539599[36] && - !_theResult____h539599[35] && - !_theResult____h539599[34] && - !_theResult____h539599[33] && - !_theResult____h539599[32] && - !_theResult____h539599[31] && - !_theResult____h539599[30] && - !_theResult____h539599[29] && - !_theResult____h539599[28] && - !_theResult____h539599[27] && - !_theResult____h539599[26] && - !_theResult____h539599[25] && - !_theResult____h539599[24] && - !_theResult____h539599[23] && - !_theResult____h539599[22] && - !_theResult____h539599[21] && - !_theResult____h539599[20] && - !_theResult____h539599[19] && - !_theResult____h539599[18] && - !_theResult____h539599[17] && - !_theResult____h539599[16] && - !_theResult____h539599[15] && - !_theResult____h539599[14] && - !_theResult____h539599[13] && - !_theResult____h539599[12] && - !_theResult____h539599[11] && - !_theResult____h539599[10] && - !_theResult____h539599[9] && - !_theResult____h539599[8] && - !_theResult____h539599[7] && - !_theResult____h539599[6] && - !_theResult____h539599[5] && - !_theResult____h539599[4] && - !_theResult____h539599[3] && - !_theResult____h539599[2] && - !_theResult____h539599[1] && - !_theResult____h539599[0]) ? - _theResult____h539599 : - _theResult___snd__h547875 ; - assign _theResult___snd__h547875 = + assign _theResult___snd__h547813 = { _theResult____h539566[55:0], 1'd0 } ; + assign _theResult___snd__h547824 = + (!_theResult____h539566[56] && _theResult____h539566[55]) ? + _theResult___snd__h547826 : + _theResult___snd__h547836 ; + assign _theResult___snd__h547826 = { _theResult____h539566[54:0], 2'd0 } ; + assign _theResult___snd__h547836 = + (!_theResult____h539566[56] && !_theResult____h539566[55] && + !_theResult____h539566[54] && + !_theResult____h539566[53] && + !_theResult____h539566[52] && + !_theResult____h539566[51] && + !_theResult____h539566[50] && + !_theResult____h539566[49] && + !_theResult____h539566[48] && + !_theResult____h539566[47] && + !_theResult____h539566[46] && + !_theResult____h539566[45] && + !_theResult____h539566[44] && + !_theResult____h539566[43] && + !_theResult____h539566[42] && + !_theResult____h539566[41] && + !_theResult____h539566[40] && + !_theResult____h539566[39] && + !_theResult____h539566[38] && + !_theResult____h539566[37] && + !_theResult____h539566[36] && + !_theResult____h539566[35] && + !_theResult____h539566[34] && + !_theResult____h539566[33] && + !_theResult____h539566[32] && + !_theResult____h539566[31] && + !_theResult____h539566[30] && + !_theResult____h539566[29] && + !_theResult____h539566[28] && + !_theResult____h539566[27] && + !_theResult____h539566[26] && + !_theResult____h539566[25] && + !_theResult____h539566[24] && + !_theResult____h539566[23] && + !_theResult____h539566[22] && + !_theResult____h539566[21] && + !_theResult____h539566[20] && + !_theResult____h539566[19] && + !_theResult____h539566[18] && + !_theResult____h539566[17] && + !_theResult____h539566[16] && + !_theResult____h539566[15] && + !_theResult____h539566[14] && + !_theResult____h539566[13] && + !_theResult____h539566[12] && + !_theResult____h539566[11] && + !_theResult____h539566[10] && + !_theResult____h539566[9] && + !_theResult____h539566[8] && + !_theResult____h539566[7] && + !_theResult____h539566[6] && + !_theResult____h539566[5] && + !_theResult____h539566[4] && + !_theResult____h539566[3] && + !_theResult____h539566[2] && + !_theResult____h539566[1] && + !_theResult____h539566[0]) ? + _theResult____h539566 : + _theResult___snd__h547842 ; + assign _theResult___snd__h547842 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h547898 = - _theResult____h539599 << + assign _theResult___snd__h547865 = + _theResult____h539566 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 ; - assign _theResult___snd__h556614 = - (f2_exp__h519011 == 8'd0) ? - _theResult___snd__h556628 : - _theResult___snd__h538211 ; - assign _theResult___snd__h556628 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && + assign _theResult___snd__h556581 = + (f2_exp__h518978 == 8'd0) ? + _theResult___snd__h556595 : + _theResult___snd__h538178 ; + assign _theResult___snd__h556595 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ? - sfd__h519373 : - _theResult___snd__h556634 ; - assign _theResult___snd__h556634 = + sfd__h519340 : + _theResult___snd__h556601 ; + assign _theResult___snd__h556601 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h556652 = - sfd__h519373 << + assign _theResult___snd__h556619 = + sfd__h519340 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428 ; - assign _theResult___snd__h577513 = - (f3_exp__h558315 == 8'd0) ? - _theResult___snd__h577522 : - _theResult___snd__h577515 ; - assign _theResult___snd__h577515 = { f3_sfd__h558316, 34'd0 } ; - assign _theResult___snd__h577522 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___snd__h577480 = + (f3_exp__h558282 == 8'd0) ? + _theResult___snd__h577489 : + _theResult___snd__h577482 ; + assign _theResult___snd__h577482 = { f3_sfd__h558283, 34'd0 } ; + assign _theResult___snd__h577489 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ? - sfd__h558677 : - _theResult___snd__h577528 ; - assign _theResult___snd__h577528 = + sfd__h558644 : + _theResult___snd__h577495 ; + assign _theResult___snd__h577495 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h577551 = - sfd__h558677 << + assign _theResult___snd__h577518 = + sfd__h558644 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 ; - assign _theResult___snd__h587150 = { _theResult____h578903[55:0], 1'd0 } ; - assign _theResult___snd__h587161 = - (!_theResult____h578903[56] && _theResult____h578903[55]) ? - _theResult___snd__h587163 : - _theResult___snd__h587173 ; - assign _theResult___snd__h587163 = { _theResult____h578903[54:0], 2'd0 } ; - assign _theResult___snd__h587173 = - (!_theResult____h578903[56] && !_theResult____h578903[55] && - !_theResult____h578903[54] && - !_theResult____h578903[53] && - !_theResult____h578903[52] && - !_theResult____h578903[51] && - !_theResult____h578903[50] && - !_theResult____h578903[49] && - !_theResult____h578903[48] && - !_theResult____h578903[47] && - !_theResult____h578903[46] && - !_theResult____h578903[45] && - !_theResult____h578903[44] && - !_theResult____h578903[43] && - !_theResult____h578903[42] && - !_theResult____h578903[41] && - !_theResult____h578903[40] && - !_theResult____h578903[39] && - !_theResult____h578903[38] && - !_theResult____h578903[37] && - !_theResult____h578903[36] && - !_theResult____h578903[35] && - !_theResult____h578903[34] && - !_theResult____h578903[33] && - !_theResult____h578903[32] && - !_theResult____h578903[31] && - !_theResult____h578903[30] && - !_theResult____h578903[29] && - !_theResult____h578903[28] && - !_theResult____h578903[27] && - !_theResult____h578903[26] && - !_theResult____h578903[25] && - !_theResult____h578903[24] && - !_theResult____h578903[23] && - !_theResult____h578903[22] && - !_theResult____h578903[21] && - !_theResult____h578903[20] && - !_theResult____h578903[19] && - !_theResult____h578903[18] && - !_theResult____h578903[17] && - !_theResult____h578903[16] && - !_theResult____h578903[15] && - !_theResult____h578903[14] && - !_theResult____h578903[13] && - !_theResult____h578903[12] && - !_theResult____h578903[11] && - !_theResult____h578903[10] && - !_theResult____h578903[9] && - !_theResult____h578903[8] && - !_theResult____h578903[7] && - !_theResult____h578903[6] && - !_theResult____h578903[5] && - !_theResult____h578903[4] && - !_theResult____h578903[3] && - !_theResult____h578903[2] && - !_theResult____h578903[1] && - !_theResult____h578903[0]) ? - _theResult____h578903 : - _theResult___snd__h587179 ; - assign _theResult___snd__h587179 = + assign _theResult___snd__h587117 = { _theResult____h578870[55:0], 1'd0 } ; + assign _theResult___snd__h587128 = + (!_theResult____h578870[56] && _theResult____h578870[55]) ? + _theResult___snd__h587130 : + _theResult___snd__h587140 ; + assign _theResult___snd__h587130 = { _theResult____h578870[54:0], 2'd0 } ; + assign _theResult___snd__h587140 = + (!_theResult____h578870[56] && !_theResult____h578870[55] && + !_theResult____h578870[54] && + !_theResult____h578870[53] && + !_theResult____h578870[52] && + !_theResult____h578870[51] && + !_theResult____h578870[50] && + !_theResult____h578870[49] && + !_theResult____h578870[48] && + !_theResult____h578870[47] && + !_theResult____h578870[46] && + !_theResult____h578870[45] && + !_theResult____h578870[44] && + !_theResult____h578870[43] && + !_theResult____h578870[42] && + !_theResult____h578870[41] && + !_theResult____h578870[40] && + !_theResult____h578870[39] && + !_theResult____h578870[38] && + !_theResult____h578870[37] && + !_theResult____h578870[36] && + !_theResult____h578870[35] && + !_theResult____h578870[34] && + !_theResult____h578870[33] && + !_theResult____h578870[32] && + !_theResult____h578870[31] && + !_theResult____h578870[30] && + !_theResult____h578870[29] && + !_theResult____h578870[28] && + !_theResult____h578870[27] && + !_theResult____h578870[26] && + !_theResult____h578870[25] && + !_theResult____h578870[24] && + !_theResult____h578870[23] && + !_theResult____h578870[22] && + !_theResult____h578870[21] && + !_theResult____h578870[20] && + !_theResult____h578870[19] && + !_theResult____h578870[18] && + !_theResult____h578870[17] && + !_theResult____h578870[16] && + !_theResult____h578870[15] && + !_theResult____h578870[14] && + !_theResult____h578870[13] && + !_theResult____h578870[12] && + !_theResult____h578870[11] && + !_theResult____h578870[10] && + !_theResult____h578870[9] && + !_theResult____h578870[8] && + !_theResult____h578870[7] && + !_theResult____h578870[6] && + !_theResult____h578870[5] && + !_theResult____h578870[4] && + !_theResult____h578870[3] && + !_theResult____h578870[2] && + !_theResult____h578870[1] && + !_theResult____h578870[0]) ? + _theResult____h578870 : + _theResult___snd__h587146 ; + assign _theResult___snd__h587146 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h587202 = - _theResult____h578903 << + assign _theResult___snd__h587169 = + _theResult____h578870 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 ; - assign _theResult___snd__h595918 = - (f3_exp__h558315 == 8'd0) ? - _theResult___snd__h595932 : - _theResult___snd__h577515 ; - assign _theResult___snd__h595932 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___snd__h595885 = + (f3_exp__h558282 == 8'd0) ? + _theResult___snd__h595899 : + _theResult___snd__h577482 ; + assign _theResult___snd__h595899 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ? - sfd__h558677 : - _theResult___snd__h595938 ; - assign _theResult___snd__h595938 = + sfd__h558644 : + _theResult___snd__h595905 ; + assign _theResult___snd__h595905 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h595956 = - sfd__h558677 << + assign _theResult___snd__h595923 = + sfd__h558644 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658 ; - assign _theResult___snd__h601248 = - b__h600826[63] ? b___1__h601297 : b__h600826 ; - assign _theResult___snd_fst_exp__h361255 = + assign _theResult___snd__h601215 = + b__h600793[63] ? b___1__h601264 : b__h600793 ; + assign _theResult___snd_fst_exp__h361222 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352670 : - _theResult___fst_exp__h361252 ; - assign _theResult___snd_fst_exp__h379075 = + _theResult___fst_exp__h352637 : + _theResult___fst_exp__h361219 ; + assign _theResult___snd_fst_exp__h379042 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h370436 : - _theResult___fst_exp__h379072 ; - assign _theResult___snd_fst_exp__h406952 = + _theResult___fst_exp__h370403 : + _theResult___fst_exp__h379039 ; + assign _theResult___snd_fst_exp__h406919 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h398367 : - _theResult___fst_exp__h406949 ; - assign _theResult___snd_fst_exp__h424772 = + _theResult___fst_exp__h398334 : + _theResult___fst_exp__h406916 ; + assign _theResult___snd_fst_exp__h424739 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h416133 : - _theResult___fst_exp__h424769 ; - assign _theResult___snd_fst_exp__h452647 = + _theResult___fst_exp__h416100 : + _theResult___fst_exp__h424736 ; + assign _theResult___snd_fst_exp__h452614 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h444062 : - _theResult___fst_exp__h452644 ; - assign _theResult___snd_fst_exp__h470467 = + _theResult___fst_exp__h444029 : + _theResult___fst_exp__h452611 ; + assign _theResult___snd_fst_exp__h470434 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461828 : - _theResult___fst_exp__h470464 ; - assign _theResult___snd_fst_exp__h500166 = + _theResult___fst_exp__h461795 : + _theResult___fst_exp__h470431 ; + assign _theResult___snd_fst_exp__h500133 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ? 11'd0 : - _theResult___fst_exp__h500163 ; - assign _theResult___snd_fst_exp__h518601 = + _theResult___fst_exp__h500130 ; + assign _theResult___snd_fst_exp__h518568 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? - _theResult___fst_exp__h509814 : - _theResult___fst_exp__h518598 ; - assign _theResult___snd_fst_exp__h539019 = + _theResult___fst_exp__h509781 : + _theResult___fst_exp__h518565 ; + assign _theResult___snd_fst_exp__h538986 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? 11'd0 : - _theResult___fst_exp__h539016 ; - assign _theResult___snd_fst_exp__h557454 = + _theResult___fst_exp__h538983 ; + assign _theResult___snd_fst_exp__h557421 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? - _theResult___fst_exp__h548667 : - _theResult___fst_exp__h557451 ; - assign _theResult___snd_fst_exp__h578323 = + _theResult___fst_exp__h548634 : + _theResult___fst_exp__h557418 ; + assign _theResult___snd_fst_exp__h578290 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? 11'd0 : - _theResult___fst_exp__h578320 ; - assign _theResult___snd_fst_exp__h596758 = + _theResult___fst_exp__h578287 ; + assign _theResult___snd_fst_exp__h596725 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? - _theResult___fst_exp__h587971 : - _theResult___fst_exp__h596755 ; - assign _theResult___snd_fst_sfd__h336307 = + _theResult___fst_exp__h587938 : + _theResult___fst_exp__h596722 ; + assign _theResult___snd_fst_sfd__h336274 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h361256 = + assign _theResult___snd_fst_sfd__h361223 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352671 : - _theResult___fst_sfd__h361253 ; - assign _theResult___snd_fst_sfd__h379076 = + _theResult___fst_sfd__h352638 : + _theResult___fst_sfd__h361220 ; + assign _theResult___snd_fst_sfd__h379043 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h370437 : - _theResult___fst_sfd__h379073 ; - assign _theResult___snd_fst_sfd__h382009 = + _theResult___fst_sfd__h370404 : + _theResult___fst_sfd__h379040 ; + assign _theResult___snd_fst_sfd__h381976 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406953 = + assign _theResult___snd_fst_sfd__h406920 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h398368 : - _theResult___fst_sfd__h406950 ; - assign _theResult___snd_fst_sfd__h424773 = + _theResult___fst_sfd__h398335 : + _theResult___fst_sfd__h406917 ; + assign _theResult___snd_fst_sfd__h424740 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h416134 : - _theResult___fst_sfd__h424770 ; - assign _theResult___snd_fst_sfd__h427704 = + _theResult___fst_sfd__h416101 : + _theResult___fst_sfd__h424737 ; + assign _theResult___snd_fst_sfd__h427671 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h452648 = + assign _theResult___snd_fst_sfd__h452615 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h444063 : - _theResult___fst_sfd__h452645 ; - assign _theResult___snd_fst_sfd__h470468 = + _theResult___fst_sfd__h444030 : + _theResult___fst_sfd__h452612 ; + assign _theResult___snd_fst_sfd__h470435 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461829 : - _theResult___fst_sfd__h470465 ; - assign _theResult___snd_fst_sfd__h480333 = - (f1_sfd__h480018 == 23'd0) ? + _theResult___fst_sfd__h461796 : + _theResult___fst_sfd__h470432 ; + assign _theResult___snd_fst_sfd__h480300 = + (f1_sfd__h479985 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h480081 ; - assign _theResult___snd_fst_sfd__h500167 = + out___1_sfd__h480048 ; + assign _theResult___snd_fst_sfd__h500134 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ? 52'd0 : - _theResult___fst_sfd__h500164 ; - assign _theResult___snd_fst_sfd__h518602 = + _theResult___fst_sfd__h500131 ; + assign _theResult___snd_fst_sfd__h518569 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? - _theResult___fst_sfd__h509815 : - _theResult___fst_sfd__h518599 ; - assign _theResult___snd_fst_sfd__h519327 = - (f2_sfd__h519012 == 23'd0) ? + _theResult___fst_sfd__h509782 : + _theResult___fst_sfd__h518566 ; + assign _theResult___snd_fst_sfd__h519294 = + (f2_sfd__h518979 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h519075 ; - assign _theResult___snd_fst_sfd__h539020 = + out___1_sfd__h519042 ; + assign _theResult___snd_fst_sfd__h538987 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? 52'd0 : - _theResult___fst_sfd__h539017 ; - assign _theResult___snd_fst_sfd__h557455 = + _theResult___fst_sfd__h538984 ; + assign _theResult___snd_fst_sfd__h557422 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? - _theResult___fst_sfd__h548668 : - _theResult___fst_sfd__h557452 ; - assign _theResult___snd_fst_sfd__h558631 = - (f3_sfd__h558316 == 23'd0) ? + _theResult___fst_sfd__h548635 : + _theResult___fst_sfd__h557419 ; + assign _theResult___snd_fst_sfd__h558598 = + (f3_sfd__h558283 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h558379 ; - assign _theResult___snd_fst_sfd__h578324 = + out___1_sfd__h558346 ; + assign _theResult___snd_fst_sfd__h578291 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? 52'd0 : - _theResult___fst_sfd__h578321 ; - assign _theResult___snd_fst_sfd__h596759 = + _theResult___fst_sfd__h578288 ; + assign _theResult___snd_fst_sfd__h596726 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? - _theResult___fst_sfd__h587972 : - _theResult___fst_sfd__h596756 ; - assign a___1__h600966 = + _theResult___fst_sfd__h587939 : + _theResult___fst_sfd__h596723 ; + assign a___1__h600933 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 } ; - assign a___1__h601252 = 64'd0 - a__h600825 ; - assign a__h600825 = + assign a___1__h601219 = 64'd0 - a__h600792 ; + assign a__h600792 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h600966 : + a___1__h600933 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h600967 = + assign b___1__h600934 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h601297 = 64'd0 - b__h600826 ; - assign b__h600826 = + assign b___1__h601264 = 64'd0 - b__h600793 ; + assign b__h600793 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h600967 : + b___1__h600934 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h700740 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h700943 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h698122 = - commitStage_commitTrap[4] ? i__h698297 : i__h698137 ; - assign commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 = + assign base__h700680 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h700883 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h698062 = + commitStage_commitTrap[4] ? i__h698237 : i__h698077 ; + assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 = commitStage_commitTrap[4] && commitStage_commitTrap[3:0] != 4'd0 && commitStage_commitTrap[3:0] != 4'd1 && @@ -29080,44 +29084,44 @@ module mkCore(CLK, !commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534 = - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 = + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168 = + assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207 = + assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181 = + assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213 = + assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189 = + assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217 = + assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230 = + assign coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 = (coreFix_aluExe_0_dispToRegQ$first[131] || sbCons$lazyLookup_0_get[3] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202) && + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199) && (sbCons$lazyLookup_0_get[2] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227) ; - assign coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623 = + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224) ; + assign coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 = coreFix_aluExe_0_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_0_set && (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334 = @@ -29146,7 +29150,7 @@ module mkCore(CLK, (sbCons$lazyLookup_1_get[2] || IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376 && IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11393) ; - assign coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978 = + assign coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 = coreFix_aluExe_1_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_1_set && (coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 && @@ -29235,9 +29239,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29245,9 +29249,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29255,9 +29259,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29265,9 +29269,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29275,19 +29279,19 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) ; + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) ; assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -29317,7 +29321,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252683 ; + y__h252650 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -29605,7 +29609,7 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981 = + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29615,9 +29619,9 @@ module mkCore(CLK, fetchStage$pipelines_0_first[75] && fetchStage$pipelines_0_first[74]) || fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976 || - csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978) ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 = + (fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 || + csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ; + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29629,7 +29633,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 = + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -29641,32 +29645,32 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 = - csrf_prv_reg_read__2730_ULE_1___d14571 && + assign csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 = + csrf_prv_reg_read__2727_ULE_1___d14567 && (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591) ; - assign csrf_prv_reg_read__2730_ULE_1___d14571 = csrf_prv_reg <= 2'd1 ; - assign csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ; + assign csrf_prv_reg_read__2727_ULE_1___d14567 = csrf_prv_reg <= 2'd1 ; + assign csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974 = csrf_prv_reg < - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[9:8] ; - assign csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428 = + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[9:8] ; + assign csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365 ; - assign data73159_BITS_31_TO_0__q13 = data__h473159[31:0] ; - assign data___1__h472885 = + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 ; + assign data73126_BITS_31_TO_0__q13 = data__h473126[31:0] ; + assign data___1__h472852 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h473693 = - { {32{data73159_BITS_31_TO_0__q13[31]}}, - data73159_BITS_31_TO_0__q13 } ; - assign data__h473159 = + assign data___1__h473660 = + { {32{data73126_BITS_31_TO_0__q13[31]}}, + data73126_BITS_31_TO_0__q13 } ; + assign data__h473126 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h473073 : - x_remainder__h473074 ; - assign dcsr_cause__h697642 = + x_quotient__h473040 : + x_remainder__h473041 ; + assign dcsr_cause__h697582 = (commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd14) ? 3'd3 : @@ -29683,232 +29687,232 @@ module mkCore(CLK, commitStage_commitTrap[3:0] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h379106 = _theResult___fst_exp__h352073 + 8'd1 ; - assign din_inc___2_exp__h379130 = _theResult___fst_exp__h360729 + 8'd1 ; - assign din_inc___2_exp__h379160 = _theResult___fst_exp__h369839 + 8'd1 ; - assign din_inc___2_exp__h379184 = _theResult___fst_exp__h378524 + 8'd1 ; - assign din_inc___2_exp__h424803 = _theResult___fst_exp__h397770 + 8'd1 ; - assign din_inc___2_exp__h424827 = _theResult___fst_exp__h406426 + 8'd1 ; - assign din_inc___2_exp__h424857 = _theResult___fst_exp__h415536 + 8'd1 ; - assign din_inc___2_exp__h424881 = _theResult___fst_exp__h424221 + 8'd1 ; - assign din_inc___2_exp__h470498 = _theResult___fst_exp__h443465 + 8'd1 ; - assign din_inc___2_exp__h470522 = _theResult___fst_exp__h452121 + 8'd1 ; - assign din_inc___2_exp__h470552 = _theResult___fst_exp__h461231 + 8'd1 ; - assign din_inc___2_exp__h470576 = _theResult___fst_exp__h469916 + 8'd1 ; - assign din_inc___2_exp__h518655 = _theResult___fst_exp__h499405 + 11'd1 ; - assign din_inc___2_exp__h518690 = _theResult___fst_exp__h508982 + 11'd1 ; - assign din_inc___2_exp__h518716 = _theResult___fst_exp__h517815 + 11'd1 ; - assign din_inc___2_exp__h557508 = _theResult___fst_exp__h538258 + 11'd1 ; - assign din_inc___2_exp__h557543 = _theResult___fst_exp__h547835 + 11'd1 ; - assign din_inc___2_exp__h557569 = _theResult___fst_exp__h556668 + 11'd1 ; - assign din_inc___2_exp__h596812 = _theResult___fst_exp__h577562 + 11'd1 ; - assign din_inc___2_exp__h596847 = _theResult___fst_exp__h587139 + 11'd1 ; - assign din_inc___2_exp__h596873 = _theResult___fst_exp__h595972 + 11'd1 ; - assign enabled_ints___1__h648311 = pend_ints__h647784 & y__h648323 ; - assign enabled_ints__h648358 = - pend_ints__h647784 & - { r1__read_BITS_13_TO_0___h648334, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655 = + assign din_inc___2_exp__h379073 = _theResult___fst_exp__h352040 + 8'd1 ; + assign din_inc___2_exp__h379097 = _theResult___fst_exp__h360696 + 8'd1 ; + assign din_inc___2_exp__h379127 = _theResult___fst_exp__h369806 + 8'd1 ; + assign din_inc___2_exp__h379151 = _theResult___fst_exp__h378491 + 8'd1 ; + assign din_inc___2_exp__h424770 = _theResult___fst_exp__h397737 + 8'd1 ; + assign din_inc___2_exp__h424794 = _theResult___fst_exp__h406393 + 8'd1 ; + assign din_inc___2_exp__h424824 = _theResult___fst_exp__h415503 + 8'd1 ; + assign din_inc___2_exp__h424848 = _theResult___fst_exp__h424188 + 8'd1 ; + assign din_inc___2_exp__h470465 = _theResult___fst_exp__h443432 + 8'd1 ; + assign din_inc___2_exp__h470489 = _theResult___fst_exp__h452088 + 8'd1 ; + assign din_inc___2_exp__h470519 = _theResult___fst_exp__h461198 + 8'd1 ; + assign din_inc___2_exp__h470543 = _theResult___fst_exp__h469883 + 8'd1 ; + assign din_inc___2_exp__h518622 = _theResult___fst_exp__h499372 + 11'd1 ; + assign din_inc___2_exp__h518657 = _theResult___fst_exp__h508949 + 11'd1 ; + assign din_inc___2_exp__h518683 = _theResult___fst_exp__h517782 + 11'd1 ; + assign din_inc___2_exp__h557475 = _theResult___fst_exp__h538225 + 11'd1 ; + assign din_inc___2_exp__h557510 = _theResult___fst_exp__h547802 + 11'd1 ; + assign din_inc___2_exp__h557536 = _theResult___fst_exp__h556635 + 11'd1 ; + assign din_inc___2_exp__h596779 = _theResult___fst_exp__h577529 + 11'd1 ; + assign din_inc___2_exp__h596814 = _theResult___fst_exp__h587106 + 11'd1 ; + assign din_inc___2_exp__h596840 = _theResult___fst_exp__h595939 + 11'd1 ; + assign enabled_ints___1__h648251 = pend_ints__h647724 & y__h648263 ; + assign enabled_ints__h648298 = + pend_ints__h647724 & + { r1__read_BITS_13_TO_0___h648274, csrf_mideleg_1_0_reg } ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811) ; - assign f1_exp80017_MINUS_127__q136 = f1_exp__h480017 - 8'd127 ; - assign f1_exp__h480017 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807) ; + assign f1_exp79984_MINUS_127__q136 = f1_exp__h479984 - 8'd127 ; + assign f1_exp__h479984 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h480018 = + assign f1_sfd__h479985 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp19011_MINUS_127__q176 = f2_exp__h519011 - 8'd127 ; - assign f2_exp__h519011 = + assign f2_exp18978_MINUS_127__q176 = f2_exp__h518978 - 8'd127 ; + assign f2_exp__h518978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h519012 = + assign f2_sfd__h518979 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp58315_MINUS_127__q153 = f3_exp__h558315 - 8'd127 ; - assign f3_exp__h558315 = + assign f3_exp58282_MINUS_127__q153 = f3_exp__h558282 - 8'd127 ; + assign f3_exp__h558282 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h558316 = + assign f3_sfd__h558283 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408 = + assign f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h607196 = { 56'd0, x__h610340 } ; - assign fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999 = + assign fcsr_csr__read__h607163 = { 56'd0, x__h610293 } ; + assign fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995) && + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991) && (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939 = + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009 = + assign fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883 || + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894 || + (fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906 || - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005) && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 = + fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 || + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001) && + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 = + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 || + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961) ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215 = + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973) ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073 = + assign fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976 = + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h651965 != 5'd0 || - imm__h651966 != 32'd0) && - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[11:10] == + rs1__h651905 != 5'd0 || + imm__h651906 != 32'd0) && + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 = + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374) ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765 = + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935 = + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 ; - assign fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ; + assign fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -29920,22 +29924,22 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756 = + assign fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 = fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894 = + assign fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906 = + assign fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -29947,116 +29951,116 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13619[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 || + checkForException___d13615[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900 ; - assign fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598 = + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 ; + assign fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h714186 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_fst__h714129 : - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 ; - assign fflags_csr__read__h607171 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h607182 = { 61'd0, csrf_frm_reg } ; - assign guard__h343972 = - { IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h352067[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352681 = - { IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h360680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361611 = - { IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h369833[32:0], 23'd0 } != 56'd0 } ; - assign guard__h362209 = x__h362311 != 57'd0 ; - assign guard__h370447 = - { IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h378470[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389671 = - { IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h397764[32:0], 23'd0 } != 56'd0 } ; - assign guard__h398378 = - { IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h406377[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407308 = - { IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h415530[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407906 = x__h408008 != 57'd0 ; - assign guard__h416144 = - { IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h424167[32:0], 23'd0 } != 56'd0 } ; - assign guard__h435366 = - { IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h443459[32:0], 23'd0 } != 56'd0 } ; - assign guard__h444073 = - { IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h452072[32:0], 23'd0 } != 56'd0 } ; - assign guard__h453003 = - { IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h461225[32:0], 23'd0 } != 56'd0 } ; - assign guard__h453601 = x__h453703 != 57'd0 ; - assign guard__h461839 = - { IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h469862[32:0], 23'd0 } != 56'd0 } ; - assign guard__h491444 = - { IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h499356[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500756 = - { IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h508976[3:0], 52'd0 } != 56'd0 } ; - assign guard__h501354 = x__h501454 != 57'd0 ; - assign guard__h509825 = - { IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h517761[3:0], 52'd0 } != 56'd0 } ; - assign guard__h530297 = - { IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h538209[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539609 = - { IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h547829[3:0], 52'd0 } != 56'd0 } ; - assign guard__h540207 = x__h540307 != 57'd0 ; - assign guard__h548678 = - { IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h556614[3:0], 52'd0 } != 56'd0 } ; - assign guard__h569601 = - { IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h577513[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578913 = - { IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h587133[3:0], 52'd0 } != 56'd0 } ; - assign guard__h579511 = x__h579611 != 57'd0 ; - assign guard__h587982 = - { IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h595918[3:0], 52'd0 } != 56'd0 } ; - assign idx__h678765 = + assign fflags__h714091 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_fst__h714034 : + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 ; + assign fflags_csr__read__h607138 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h607149 = { 61'd0, csrf_frm_reg } ; + assign guard__h343939 = + { IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h352034[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352648 = + { IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h360647[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361578 = + { IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h369800[32:0], 23'd0 } != 56'd0 } ; + assign guard__h362176 = x__h362278 != 57'd0 ; + assign guard__h370414 = + { IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h378437[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389638 = + { IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h397731[32:0], 23'd0 } != 56'd0 } ; + assign guard__h398345 = + { IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h406344[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407275 = + { IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h415497[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407873 = x__h407975 != 57'd0 ; + assign guard__h416111 = + { IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h424134[32:0], 23'd0 } != 56'd0 } ; + assign guard__h435333 = + { IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h443426[32:0], 23'd0 } != 56'd0 } ; + assign guard__h444040 = + { IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h452039[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452970 = + { IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h461192[32:0], 23'd0 } != 56'd0 } ; + assign guard__h453568 = x__h453670 != 57'd0 ; + assign guard__h461806 = + { IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h469829[32:0], 23'd0 } != 56'd0 } ; + assign guard__h491411 = + { IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h499323[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500723 = + { IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h508943[3:0], 52'd0 } != 56'd0 } ; + assign guard__h501321 = x__h501421 != 57'd0 ; + assign guard__h509792 = + { IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h517728[3:0], 52'd0 } != 56'd0 } ; + assign guard__h530264 = + { IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h538176[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539576 = + { IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h547796[3:0], 52'd0 } != 56'd0 } ; + assign guard__h540174 = x__h540274 != 57'd0 ; + assign guard__h548645 = + { IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h556581[3:0], 52'd0 } != 56'd0 } ; + assign guard__h569568 = + { IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h577480[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578880 = + { IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h587100[3:0], 52'd0 } != 56'd0 } ; + assign guard__h579478 = x__h579578 != 57'd0 ; + assign guard__h587949 = + { IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h595885[3:0], 52'd0 } != 56'd0 } ; + assign idx__h678705 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691 ; - assign imm__h651966 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 ; + assign imm__h651906 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h664143 = + assign k__h664083 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign mcause_csr__read__h608843 = - { r1__read__h611868, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h608588 = - { r1__read__h611855, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h608188 = - { r1__read__h611691, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h608283 = - { r1__read__h611708, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h608414 = - { r1__read__h611732, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h609083 = - { r1__read__h611874, csrf_software_int_pend_vec_0 } ; + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign mcause_csr__read__h608803 = + { r1__read__h611814, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h608548 = + { r1__read__h611801, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h608155 = + { r1__read__h611644, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h608250 = + { r1__read__h611661, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h608374 = + { r1__read__h611685, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h609036 = + { r1__read__h611820, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30089,18 +30093,18 @@ module mkCore(CLK, !mmio_dataRespQ_deqReq_lat_0$whas && !mmio_dataRespQ_deqReq_rl) && mmio_dataRespQ_full ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984) ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 && (fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30111,13 +30115,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -30140,292 +30144,292 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h75940 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h608040 = { r1__read__h611566, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h608496 = - { r1__read__h611850, csrf_mtvec_mode_low_reg } ; - assign n___1__h196409 = + assign msip__h75907 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h608007 = { r1__read__h611519, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h608456 = + { r1__read__h611796, csrf_mtvec_mode_low_reg } ; + assign n___1__h196376 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h195006[63:56], + x__h194973[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h195006[55:48], + x__h194973[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h195006[47:40], + x__h194973[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h195006[39:32], + x__h194973[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h195006[31:24], + x__h194973[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h195006[23:16], + x__h194973[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h195006[15:8], + x__h194973[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h195006[7:0] } ; - assign n__read__h609187 = + x__h194973[7:0] } ; + assign n__read__h609140 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h609378 = + assign n__read__h609331 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6636 = + assign n__read__h6604 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6750 : + upd__h6718 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h710013 = + assign n__read__h709918 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294679 = + assign next_deqP___1__h294647 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302675 = + assign next_deqP___1__h302643 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308956 = + assign next_deqP___1__h308924 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316810 = + assign next_deqP___1__h316778 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326867 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h330092 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h709359 = + assign next_deqP___1__h326835 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h330060 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h709264 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h480081 = { f1_sfd__h480018, 29'd0 } ; - assign out___1_sfd__h519075 = { f2_sfd__h519012, 29'd0 } ; - assign out___1_sfd__h558379 = { f3_sfd__h558316, 29'd0 } ; - assign out_exp__h352592 = - sfdin__h352067[34] ? - _theResult___exp__h352589 : - _theResult___fst_exp__h352073 ; - assign out_exp__h361174 = - _theResult___snd__h360680[34] ? - _theResult___exp__h361171 : - _theResult___fst_exp__h360729 ; - assign out_exp__h370358 = - sfdin__h369833[34] ? - _theResult___exp__h370355 : - _theResult___fst_exp__h369839 ; - assign out_exp__h378994 = - _theResult___snd__h378470[34] ? - _theResult___exp__h378991 : - _theResult___fst_exp__h378524 ; - assign out_exp__h398289 = - sfdin__h397764[34] ? - _theResult___exp__h398286 : - _theResult___fst_exp__h397770 ; - assign out_exp__h406871 = - _theResult___snd__h406377[34] ? - _theResult___exp__h406868 : - _theResult___fst_exp__h406426 ; - assign out_exp__h416055 = - sfdin__h415530[34] ? - _theResult___exp__h416052 : - _theResult___fst_exp__h415536 ; - assign out_exp__h424691 = - _theResult___snd__h424167[34] ? - _theResult___exp__h424688 : - _theResult___fst_exp__h424221 ; - assign out_exp__h443984 = - sfdin__h443459[34] ? - _theResult___exp__h443981 : - _theResult___fst_exp__h443465 ; - assign out_exp__h452566 = - _theResult___snd__h452072[34] ? - _theResult___exp__h452563 : - _theResult___fst_exp__h452121 ; - assign out_exp__h461750 = - sfdin__h461225[34] ? - _theResult___exp__h461747 : - _theResult___fst_exp__h461231 ; - assign out_exp__h470386 = - _theResult___snd__h469862[34] ? - _theResult___exp__h470383 : - _theResult___fst_exp__h469916 ; - assign out_exp__h500063 = - _theResult___snd__h499356[5] ? - _theResult___exp__h500060 : - _theResult___fst_exp__h499405 ; - assign out_exp__h509714 = - sfdin__h508976[5] ? - _theResult___exp__h509711 : - _theResult___fst_exp__h508982 ; - assign out_exp__h518498 = - _theResult___snd__h517761[5] ? - _theResult___exp__h518495 : - _theResult___fst_exp__h517815 ; - assign out_exp__h538916 = - _theResult___snd__h538209[5] ? - _theResult___exp__h538913 : - _theResult___fst_exp__h538258 ; - assign out_exp__h548567 = - sfdin__h547829[5] ? - _theResult___exp__h548564 : - _theResult___fst_exp__h547835 ; - assign out_exp__h557351 = - _theResult___snd__h556614[5] ? - _theResult___exp__h557348 : - _theResult___fst_exp__h556668 ; - assign out_exp__h578220 = - _theResult___snd__h577513[5] ? - _theResult___exp__h578217 : - _theResult___fst_exp__h577562 ; - assign out_exp__h587871 = - sfdin__h587133[5] ? - _theResult___exp__h587868 : - _theResult___fst_exp__h587139 ; - assign out_exp__h596655 = - _theResult___snd__h595918[5] ? - _theResult___exp__h596652 : - _theResult___fst_exp__h595972 ; - assign out_f_exp__h379370 = - (_theResult___exp__h379093 == 8'd255 && - _theResult___sfd__h379094 != 23'd0 || + assign out___1_sfd__h480048 = { f1_sfd__h479985, 29'd0 } ; + assign out___1_sfd__h519042 = { f2_sfd__h518979, 29'd0 } ; + assign out___1_sfd__h558346 = { f3_sfd__h558283, 29'd0 } ; + assign out_exp__h352559 = + sfdin__h352034[34] ? + _theResult___exp__h352556 : + _theResult___fst_exp__h352040 ; + assign out_exp__h361141 = + _theResult___snd__h360647[34] ? + _theResult___exp__h361138 : + _theResult___fst_exp__h360696 ; + assign out_exp__h370325 = + sfdin__h369800[34] ? + _theResult___exp__h370322 : + _theResult___fst_exp__h369806 ; + assign out_exp__h378961 = + _theResult___snd__h378437[34] ? + _theResult___exp__h378958 : + _theResult___fst_exp__h378491 ; + assign out_exp__h398256 = + sfdin__h397731[34] ? + _theResult___exp__h398253 : + _theResult___fst_exp__h397737 ; + assign out_exp__h406838 = + _theResult___snd__h406344[34] ? + _theResult___exp__h406835 : + _theResult___fst_exp__h406393 ; + assign out_exp__h416022 = + sfdin__h415497[34] ? + _theResult___exp__h416019 : + _theResult___fst_exp__h415503 ; + assign out_exp__h424658 = + _theResult___snd__h424134[34] ? + _theResult___exp__h424655 : + _theResult___fst_exp__h424188 ; + assign out_exp__h443951 = + sfdin__h443426[34] ? + _theResult___exp__h443948 : + _theResult___fst_exp__h443432 ; + assign out_exp__h452533 = + _theResult___snd__h452039[34] ? + _theResult___exp__h452530 : + _theResult___fst_exp__h452088 ; + assign out_exp__h461717 = + sfdin__h461192[34] ? + _theResult___exp__h461714 : + _theResult___fst_exp__h461198 ; + assign out_exp__h470353 = + _theResult___snd__h469829[34] ? + _theResult___exp__h470350 : + _theResult___fst_exp__h469883 ; + assign out_exp__h500030 = + _theResult___snd__h499323[5] ? + _theResult___exp__h500027 : + _theResult___fst_exp__h499372 ; + assign out_exp__h509681 = + sfdin__h508943[5] ? + _theResult___exp__h509678 : + _theResult___fst_exp__h508949 ; + assign out_exp__h518465 = + _theResult___snd__h517728[5] ? + _theResult___exp__h518462 : + _theResult___fst_exp__h517782 ; + assign out_exp__h538883 = + _theResult___snd__h538176[5] ? + _theResult___exp__h538880 : + _theResult___fst_exp__h538225 ; + assign out_exp__h548534 = + sfdin__h547796[5] ? + _theResult___exp__h548531 : + _theResult___fst_exp__h547802 ; + assign out_exp__h557318 = + _theResult___snd__h556581[5] ? + _theResult___exp__h557315 : + _theResult___fst_exp__h556635 ; + assign out_exp__h578187 = + _theResult___snd__h577480[5] ? + _theResult___exp__h578184 : + _theResult___fst_exp__h577529 ; + assign out_exp__h587838 = + sfdin__h587100[5] ? + _theResult___exp__h587835 : + _theResult___fst_exp__h587106 ; + assign out_exp__h596622 = + _theResult___snd__h595885[5] ? + _theResult___exp__h596619 : + _theResult___fst_exp__h595939 ; + assign out_f_exp__h379337 = + (_theResult___exp__h379060 == 8'd255 && + _theResult___sfd__h379061 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h379084 ; - assign out_f_exp__h425067 = - (_theResult___exp__h424790 == 8'd255 && - _theResult___sfd__h424791 != 23'd0 || + _theResult___fst_exp__h379051 ; + assign out_f_exp__h425034 = + (_theResult___exp__h424757 == 8'd255 && + _theResult___sfd__h424758 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424781 ; - assign out_f_exp__h470762 = - (_theResult___exp__h470485 == 8'd255 && - _theResult___sfd__h470486 != 23'd0 || + _theResult___fst_exp__h424748 ; + assign out_f_exp__h470729 = + (_theResult___exp__h470452 == 8'd255 && + _theResult___sfd__h470453 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h470476 ; - assign out_f_sfd__h379371 = - (_theResult___exp__h379093 == 8'd255 && - _theResult___sfd__h379094 != 23'd0) ? + _theResult___fst_exp__h470443 ; + assign out_f_sfd__h379338 = + (_theResult___exp__h379060 == 8'd255 && + _theResult___sfd__h379061 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h379094 ; - assign out_f_sfd__h425068 = - (_theResult___exp__h424790 == 8'd255 && - _theResult___sfd__h424791 != 23'd0) ? + _theResult___sfd__h379061 ; + assign out_f_sfd__h425035 = + (_theResult___exp__h424757 == 8'd255 && + _theResult___sfd__h424758 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424791 ; - assign out_f_sfd__h470763 = - (_theResult___exp__h470485 == 8'd255 && - _theResult___sfd__h470486 != 23'd0) ? + _theResult___sfd__h424758 ; + assign out_f_sfd__h470730 = + (_theResult___exp__h470452 == 8'd255 && + _theResult___sfd__h470453 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h470486 ; - assign out_sfd__h352593 = - sfdin__h352067[34] ? - _theResult___sfd__h352590 : - sfdin__h352067[56:34] ; - assign out_sfd__h361175 = - _theResult___snd__h360680[34] ? - _theResult___sfd__h361172 : - _theResult___snd__h360680[56:34] ; - assign out_sfd__h370359 = - sfdin__h369833[34] ? - _theResult___sfd__h370356 : - sfdin__h369833[56:34] ; - assign out_sfd__h378995 = - _theResult___snd__h378470[34] ? - _theResult___sfd__h378992 : - _theResult___snd__h378470[56:34] ; - assign out_sfd__h398290 = - sfdin__h397764[34] ? - _theResult___sfd__h398287 : - sfdin__h397764[56:34] ; - assign out_sfd__h406872 = - _theResult___snd__h406377[34] ? - _theResult___sfd__h406869 : - _theResult___snd__h406377[56:34] ; - assign out_sfd__h416056 = - sfdin__h415530[34] ? - _theResult___sfd__h416053 : - sfdin__h415530[56:34] ; - assign out_sfd__h424692 = - _theResult___snd__h424167[34] ? - _theResult___sfd__h424689 : - _theResult___snd__h424167[56:34] ; - assign out_sfd__h443985 = - sfdin__h443459[34] ? - _theResult___sfd__h443982 : - sfdin__h443459[56:34] ; - assign out_sfd__h452567 = - _theResult___snd__h452072[34] ? - _theResult___sfd__h452564 : - _theResult___snd__h452072[56:34] ; - assign out_sfd__h461751 = - sfdin__h461225[34] ? - _theResult___sfd__h461748 : - sfdin__h461225[56:34] ; - assign out_sfd__h470387 = - _theResult___snd__h469862[34] ? - _theResult___sfd__h470384 : - _theResult___snd__h469862[56:34] ; - assign out_sfd__h500064 = - _theResult___snd__h499356[5] ? - _theResult___sfd__h500061 : - _theResult___snd__h499356[56:5] ; - assign out_sfd__h509715 = - sfdin__h508976[5] ? - _theResult___sfd__h509712 : - sfdin__h508976[56:5] ; - assign out_sfd__h518499 = - _theResult___snd__h517761[5] ? - _theResult___sfd__h518496 : - _theResult___snd__h517761[56:5] ; - assign out_sfd__h538917 = - _theResult___snd__h538209[5] ? - _theResult___sfd__h538914 : - _theResult___snd__h538209[56:5] ; - assign out_sfd__h548568 = - sfdin__h547829[5] ? - _theResult___sfd__h548565 : - sfdin__h547829[56:5] ; - assign out_sfd__h557352 = - _theResult___snd__h556614[5] ? - _theResult___sfd__h557349 : - _theResult___snd__h556614[56:5] ; - assign out_sfd__h578221 = - _theResult___snd__h577513[5] ? - _theResult___sfd__h578218 : - _theResult___snd__h577513[56:5] ; - assign out_sfd__h587872 = - sfdin__h587133[5] ? - _theResult___sfd__h587869 : - sfdin__h587133[56:5] ; - assign out_sfd__h596656 = - _theResult___snd__h595918[5] ? - _theResult___sfd__h596653 : - _theResult___snd__h595918[56:5] ; - assign pend_ints__h647784 = - { _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744, + _theResult___sfd__h470453 ; + assign out_sfd__h352560 = + sfdin__h352034[34] ? + _theResult___sfd__h352557 : + sfdin__h352034[56:34] ; + assign out_sfd__h361142 = + _theResult___snd__h360647[34] ? + _theResult___sfd__h361139 : + _theResult___snd__h360647[56:34] ; + assign out_sfd__h370326 = + sfdin__h369800[34] ? + _theResult___sfd__h370323 : + sfdin__h369800[56:34] ; + assign out_sfd__h378962 = + _theResult___snd__h378437[34] ? + _theResult___sfd__h378959 : + _theResult___snd__h378437[56:34] ; + assign out_sfd__h398257 = + sfdin__h397731[34] ? + _theResult___sfd__h398254 : + sfdin__h397731[56:34] ; + assign out_sfd__h406839 = + _theResult___snd__h406344[34] ? + _theResult___sfd__h406836 : + _theResult___snd__h406344[56:34] ; + assign out_sfd__h416023 = + sfdin__h415497[34] ? + _theResult___sfd__h416020 : + sfdin__h415497[56:34] ; + assign out_sfd__h424659 = + _theResult___snd__h424134[34] ? + _theResult___sfd__h424656 : + _theResult___snd__h424134[56:34] ; + assign out_sfd__h443952 = + sfdin__h443426[34] ? + _theResult___sfd__h443949 : + sfdin__h443426[56:34] ; + assign out_sfd__h452534 = + _theResult___snd__h452039[34] ? + _theResult___sfd__h452531 : + _theResult___snd__h452039[56:34] ; + assign out_sfd__h461718 = + sfdin__h461192[34] ? + _theResult___sfd__h461715 : + sfdin__h461192[56:34] ; + assign out_sfd__h470354 = + _theResult___snd__h469829[34] ? + _theResult___sfd__h470351 : + _theResult___snd__h469829[56:34] ; + assign out_sfd__h500031 = + _theResult___snd__h499323[5] ? + _theResult___sfd__h500028 : + _theResult___snd__h499323[56:5] ; + assign out_sfd__h509682 = + sfdin__h508943[5] ? + _theResult___sfd__h509679 : + sfdin__h508943[56:5] ; + assign out_sfd__h518466 = + _theResult___snd__h517728[5] ? + _theResult___sfd__h518463 : + _theResult___snd__h517728[56:5] ; + assign out_sfd__h538884 = + _theResult___snd__h538176[5] ? + _theResult___sfd__h538881 : + _theResult___snd__h538176[56:5] ; + assign out_sfd__h548535 = + sfdin__h547796[5] ? + _theResult___sfd__h548532 : + sfdin__h547796[56:5] ; + assign out_sfd__h557319 = + _theResult___snd__h556581[5] ? + _theResult___sfd__h557316 : + _theResult___snd__h556581[56:5] ; + assign out_sfd__h578188 = + _theResult___snd__h577480[5] ? + _theResult___sfd__h578185 : + _theResult___snd__h577480[56:5] ; + assign out_sfd__h587839 = + sfdin__h587100[5] ? + _theResult___sfd__h587836 : + sfdin__h587100[56:5] ; + assign out_sfd__h596623 = + _theResult___snd__h595885[5] ? + _theResult___sfd__h596620 : + _theResult___snd__h595885[56:5] ; + assign pend_ints__h647724 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h715821 = csrf_prv_reg ; - assign prv__h715865 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473758 = + assign prv__h715726 = csrf_prv_reg ; + assign prv__h715770 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473725 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h648334 = + assign r1__read_BITS_13_TO_0___h648274 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30433,137 +30437,134 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h651834 = csrf_fs_reg ; - assign r1__read_BIT_20___h652494 = csrf_tw_reg ; - assign r1__read__h610355 = { r1__read__h610357, csrf_ie_vec_1 } ; - assign r1__read__h610357 = { r1__read__h610359, 2'b0 } ; - assign r1__read__h610359 = { r1__read__h610361, csrf_prev_ie_vec_0 } ; - assign r1__read__h610361 = { r1__read__h610363, csrf_prev_ie_vec_1 } ; - assign r1__read__h610363 = { r1__read__h610365, 2'b0 } ; - assign r1__read__h610365 = { r1__read__h610367, csrf_spp_reg } ; - assign r1__read__h610367 = { r1__read__h610369, 4'b0 } ; - assign r1__read__h610369 = { r1__read__h610371, csrf_fs_reg } ; - assign r1__read__h610371 = { r1__read__h610373, 2'd0 } ; - assign r1__read__h610373 = { r1__read__h610375, 1'b0 } ; - assign r1__read__h610375 = { r1__read__h610377, csrf_sum_reg } ; - assign r1__read__h610377 = { r1__read__h610379, csrf_mxr_reg } ; - assign r1__read__h610379 = { r1__read__h610381, 12'b0 } ; - assign r1__read__h610381 = { r1__read__h610383, 2'b10 } ; - assign r1__read__h610383 = { r__h610387, 29'b0 } ; - assign r1__read__h610759 = - { r1__read__h610761, csrf_software_int_en_vec_1 } ; - assign r1__read__h610761 = { r1__read__h610763, 2'b0 } ; - assign r1__read__h610763 = { r1__read__h610765, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610765 = { r1__read__h610767, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610767 = { r1__read__h610769, 2'b0 } ; - assign r1__read__h610769 = - { r1__read__h610771, csrf_external_int_en_vec_0 } ; - assign r1__read__h610771 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h611289 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h611294 = { r1__read__h611296, csrf_scounteren_tm_reg } ; - assign r1__read__h611296 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h611307 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h611313 = - { r1__read__h611315, csrf_software_int_pend_vec_1 } ; - assign r1__read__h611315 = { r1__read__h611317, 2'b0 } ; - assign r1__read__h611317 = - { r1__read__h611319, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h611319 = - { r1__read__h611321, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h611321 = { r1__read__h611323, 2'b0 } ; - assign r1__read__h611323 = - { r1__read__h611325, csrf_external_int_pend_vec_0 } ; - assign r1__read__h611325 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h611543 = { vm_mode_reg__read__h611549, 16'd0 } ; - assign r1__read__h611566 = { r1__read__h611568, csrf_ie_vec_1 } ; - assign r1__read__h611568 = { r1__read__h611570, 1'b0 } ; - assign r1__read__h611570 = { r1__read__h611572, csrf_ie_vec_3 } ; - assign r1__read__h611572 = { r1__read__h611574, csrf_prev_ie_vec_0 } ; - assign r1__read__h611574 = { r1__read__h611576, csrf_prev_ie_vec_1 } ; - assign r1__read__h611576 = { r1__read__h611578, 1'b0 } ; - assign r1__read__h611578 = { r1__read__h611580, csrf_prev_ie_vec_3 } ; - assign r1__read__h611580 = { r1__read__h611582, csrf_spp_reg } ; - assign r1__read__h611582 = { r1__read__h611584, 2'b0 } ; - assign r1__read__h611584 = { r1__read__h611586, csrf_mpp_reg } ; - assign r1__read__h611586 = { r1__read__h611588, csrf_fs_reg } ; - assign r1__read__h611588 = { r1__read__h611590, 2'd0 } ; - assign r1__read__h611590 = { r1__read__h611592, csrf_mprv_reg } ; - assign r1__read__h611592 = { r1__read__h611594, csrf_sum_reg } ; - assign r1__read__h611594 = { r1__read__h611596, csrf_mxr_reg } ; - assign r1__read__h611596 = { r1__read__h611598, csrf_tvm_reg } ; - assign r1__read__h611598 = { r1__read__h611600, csrf_tw_reg } ; - assign r1__read__h611600 = { r1__read__h611602, csrf_tsr_reg } ; - assign r1__read__h611602 = { r1__read__h611604, 9'b0 } ; - assign r1__read__h611604 = { r1__read__h611606, 2'b10 } ; - assign r1__read__h611606 = { r1__read__h611608, 2'b10 } ; - assign r1__read__h611608 = { r__h610387, 27'b0 } ; - assign r1__read__h611691 = { r1__read__h611693, 1'b0 } ; - assign r1__read__h611693 = { r1__read__h611695, csrf_medeleg_13_11_reg } ; + assign r1__read_BITS_13_TO_12___h651774 = csrf_fs_reg ; + assign r1__read_BIT_20___h652434 = csrf_tw_reg ; + assign r1__read__h610308 = { r1__read__h610310, csrf_ie_vec_1 } ; + assign r1__read__h610310 = { r1__read__h610312, 2'b0 } ; + assign r1__read__h610312 = { r1__read__h610314, csrf_prev_ie_vec_0 } ; + assign r1__read__h610314 = { r1__read__h610316, csrf_prev_ie_vec_1 } ; + assign r1__read__h610316 = { r1__read__h610318, 2'b0 } ; + assign r1__read__h610318 = { r1__read__h610320, csrf_spp_reg } ; + assign r1__read__h610320 = { r1__read__h610322, 4'b0 } ; + assign r1__read__h610322 = { r1__read__h610324, csrf_fs_reg } ; + assign r1__read__h610324 = { r1__read__h610326, 2'd0 } ; + assign r1__read__h610326 = { r1__read__h610328, 1'b0 } ; + assign r1__read__h610328 = { r1__read__h610330, csrf_sum_reg } ; + assign r1__read__h610330 = { r1__read__h610332, csrf_mxr_reg } ; + assign r1__read__h610332 = { r1__read__h610334, 12'b0 } ; + assign r1__read__h610334 = { r1__read__h610336, 2'b10 } ; + assign r1__read__h610336 = { r__h610340, 29'b0 } ; + assign r1__read__h610712 = + { r1__read__h610714, csrf_software_int_en_vec_1 } ; + assign r1__read__h610714 = { r1__read__h610716, 2'b0 } ; + assign r1__read__h610716 = { r1__read__h610718, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610718 = { r1__read__h610720, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610720 = { r1__read__h610722, 2'b0 } ; + assign r1__read__h610722 = + { r1__read__h610724, csrf_external_int_en_vec_0 } ; + assign r1__read__h610724 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h611242 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h611247 = { r1__read__h611249, csrf_scounteren_tm_reg } ; + assign r1__read__h611249 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h611260 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h611266 = + { r1__read__h611268, csrf_software_int_pend_vec_1 } ; + assign r1__read__h611268 = { r1__read__h611270, 2'b0 } ; + assign r1__read__h611270 = + { r1__read__h611272, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h611272 = + { r1__read__h611274, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h611274 = { r1__read__h611276, 2'b0 } ; + assign r1__read__h611276 = + { r1__read__h611278, csrf_external_int_pend_vec_0 } ; + assign r1__read__h611278 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h611496 = { vm_mode_reg__read__h611502, 16'd0 } ; + assign r1__read__h611519 = { r1__read__h611521, csrf_ie_vec_1 } ; + assign r1__read__h611521 = { r1__read__h611523, 1'b0 } ; + assign r1__read__h611523 = { r1__read__h611525, csrf_ie_vec_3 } ; + assign r1__read__h611525 = { r1__read__h611527, csrf_prev_ie_vec_0 } ; + assign r1__read__h611527 = { r1__read__h611529, csrf_prev_ie_vec_1 } ; + assign r1__read__h611529 = { r1__read__h611531, 1'b0 } ; + assign r1__read__h611531 = { r1__read__h611533, csrf_prev_ie_vec_3 } ; + assign r1__read__h611533 = { r1__read__h611535, csrf_spp_reg } ; + assign r1__read__h611535 = { r1__read__h611537, 2'b0 } ; + assign r1__read__h611537 = { r1__read__h611539, csrf_mpp_reg } ; + assign r1__read__h611539 = { r1__read__h611541, csrf_fs_reg } ; + assign r1__read__h611541 = { r1__read__h611543, 2'd0 } ; + assign r1__read__h611543 = { r1__read__h611545, csrf_mprv_reg } ; + assign r1__read__h611545 = { r1__read__h611547, csrf_sum_reg } ; + assign r1__read__h611547 = { r1__read__h611549, csrf_mxr_reg } ; + assign r1__read__h611549 = { r1__read__h611551, csrf_tvm_reg } ; + assign r1__read__h611551 = { r1__read__h611553, csrf_tw_reg } ; + assign r1__read__h611553 = { r1__read__h611555, csrf_tsr_reg } ; + assign r1__read__h611555 = { r1__read__h611557, 9'b0 } ; + assign r1__read__h611557 = { r1__read__h611559, 2'b10 } ; + assign r1__read__h611559 = { r1__read__h611561, 2'b10 } ; + assign r1__read__h611561 = { r__h610340, 27'b0 } ; + assign r1__read__h611644 = { r1__read__h611646, 1'b0 } ; + assign r1__read__h611646 = { r1__read__h611648, csrf_medeleg_13_11_reg } ; + assign r1__read__h611648 = { r1__read__h611650, 1'b0 } ; + assign r1__read__h611650 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h611661 = { r1__read__h611663, 1'b0 } ; + assign r1__read__h611663 = { r1__read__h611665, csrf_mideleg_5_3_reg } ; + assign r1__read__h611665 = { r1__read__h611667, 1'b0 } ; + assign r1__read__h611667 = { r1__read__h611669, csrf_mideleg_9_7_reg } ; + assign r1__read__h611669 = { r1__read__h611671, 1'b0 } ; + assign r1__read__h611671 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h611685 = + { r1__read__h611687, csrf_software_int_en_vec_1 } ; + assign r1__read__h611687 = { r1__read__h611689, 1'b0 } ; + assign r1__read__h611689 = + { r1__read__h611691, csrf_software_int_en_vec_3 } ; + assign r1__read__h611691 = { r1__read__h611693, csrf_timer_int_en_vec_0 } ; + assign r1__read__h611693 = { r1__read__h611695, csrf_timer_int_en_vec_1 } ; assign r1__read__h611695 = { r1__read__h611697, 1'b0 } ; - assign r1__read__h611697 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h611708 = { r1__read__h611710, 1'b0 } ; - assign r1__read__h611710 = { r1__read__h611712, csrf_mideleg_5_3_reg } ; - assign r1__read__h611712 = { r1__read__h611714, 1'b0 } ; - assign r1__read__h611714 = { r1__read__h611716, csrf_mideleg_9_7_reg } ; - assign r1__read__h611716 = { r1__read__h611718, 1'b0 } ; - assign r1__read__h611718 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h611732 = - { r1__read__h611734, csrf_software_int_en_vec_1 } ; - assign r1__read__h611734 = { r1__read__h611736, 1'b0 } ; - assign r1__read__h611736 = - { r1__read__h611738, csrf_software_int_en_vec_3 } ; - assign r1__read__h611738 = { r1__read__h611740, csrf_timer_int_en_vec_0 } ; - assign r1__read__h611740 = { r1__read__h611742, csrf_timer_int_en_vec_1 } ; - assign r1__read__h611742 = { r1__read__h611744, 1'b0 } ; - assign r1__read__h611744 = { r1__read__h611746, csrf_timer_int_en_vec_3 } ; - assign r1__read__h611746 = - { r1__read__h611748, csrf_external_int_en_vec_0 } ; - assign r1__read__h611748 = - { r1__read__h611750, csrf_external_int_en_vec_1 } ; - assign r1__read__h611750 = { r1__read__h611752, 1'b0 } ; - assign r1__read__h611752 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h611850 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h611855 = { r1__read__h611857, csrf_mcounteren_tm_reg } ; - assign r1__read__h611857 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h611868 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h611874 = - { r1__read__h611876, csrf_software_int_pend_vec_1 } ; - assign r1__read__h611876 = { r1__read__h611878, 1'b0 } ; - assign r1__read__h611878 = - { r1__read__h611880, csrf_software_int_pend_vec_3 } ; - assign r1__read__h611880 = - { r1__read__h611882, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h611882 = - { r1__read__h611884, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h611884 = { r1__read__h611886, 1'b0 } ; - assign r1__read__h611886 = - { r1__read__h611888, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h611888 = - { r1__read__h611890, csrf_external_int_pend_vec_0 } ; - assign r1__read__h611890 = - { r1__read__h611892, csrf_external_int_pend_vec_1 } ; - assign r1__read__h611892 = { r1__read__h611894, 1'b0 } ; - assign r1__read__h611894 = - { r1__read__h611896, csrf_external_int_pend_vec_3 } ; - assign r1__read__h611896 = { r1__read__h611898, 2'b0 } ; - assign r1__read__h611898 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h479638 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h479639 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473784 = + assign r1__read__h611697 = { r1__read__h611699, csrf_timer_int_en_vec_3 } ; + assign r1__read__h611699 = + { r1__read__h611701, csrf_external_int_en_vec_0 } ; + assign r1__read__h611701 = + { r1__read__h611703, csrf_external_int_en_vec_1 } ; + assign r1__read__h611703 = { r1__read__h611705, 1'b0 } ; + assign r1__read__h611705 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h611796 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h611801 = { r1__read__h611803, csrf_mcounteren_tm_reg } ; + assign r1__read__h611803 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h611814 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h611820 = + { r1__read__h611822, csrf_software_int_pend_vec_1 } ; + assign r1__read__h611822 = { r1__read__h611824, 1'b0 } ; + assign r1__read__h611824 = + { r1__read__h611826, csrf_software_int_pend_vec_3 } ; + assign r1__read__h611826 = + { r1__read__h611828, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h611828 = + { r1__read__h611830, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h611830 = { r1__read__h611832, 1'b0 } ; + assign r1__read__h611832 = + { r1__read__h611834, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h611834 = + { r1__read__h611836, csrf_external_int_pend_vec_0 } ; + assign r1__read__h611836 = + { r1__read__h611838, csrf_external_int_pend_vec_1 } ; + assign r1__read__h611838 = { r1__read__h611840, 1'b0 } ; + assign r1__read__h611840 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign rVal1__h479605 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h479606 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473751 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h610387 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862 = + assign r__h610340 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943 = + assign regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) && - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 = + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) && + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30574,8 +30575,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30586,64 +30587,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 && + NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30654,8 +30655,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30666,8 +30667,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30678,8 +30679,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30690,85 +30691,85 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167 = - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && (!fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 = renameStage_rg_m_halt_req[4] || !fetchStage$pipelines_0_first[68] && - (IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15]) ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233 = - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004 || + (IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 || (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095) == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 : + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091) == 4'd3 ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677 || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714 || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428 ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 = + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h678634 = + assign renaming_spec_bits__h678574 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h675097 : + y_avValue_fst__h675037 : specTagManager$currentSpecBits ; - assign res_data__h335746 = { 32'hFFFFFFFF, x__h335761 } ; - assign res_data__h335751 = + assign res_data__h335713 = { 32'hFFFFFFFF, x__h335728 } ; + assign res_data__h335718 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -30781,8 +30782,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h381448 = { 32'hFFFFFFFF, x__h381463 } ; - assign res_data__h381453 = + assign res_data__h381415 = { 32'hFFFFFFFF, x__h381430 } ; + assign res_data__h381420 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -30795,8 +30796,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h427143 = { 32'hFFFFFFFF, x__h427158 } ; - assign res_data__h427148 = + assign res_data__h427110 = { 32'hFFFFFFFF, x__h427125 } ; + assign res_data__h427115 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -30809,7 +30810,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335747 = + assign res_fflags__h335714 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -30877,7 +30878,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h381449 = + assign res_fflags__h381416 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -30888,8 +30889,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590, @@ -30901,8 +30901,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601, @@ -30914,8 +30913,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617, @@ -30927,8 +30925,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630, @@ -30940,12 +30937,11 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h427144 = + assign res_fflags__h427111 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31013,49 +31009,49 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289850 = + assign resp_addr__h289818 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h362214 = + assign result__h362181 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h362209 } ; - assign result__h407911 = + guard__h362176 } ; + assign result__h407878 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407906 } ; - assign result__h453606 = + guard__h407873 } ; + assign result__h453573 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h453601 } ; - assign result__h501359 = + guard__h453568 } ; + assign result__h501326 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[0] | - guard__h501354 } ; - assign result__h540212 = + guard__h501321 } ; + assign result__h540179 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[0] | - guard__h540207 } ; - assign result__h579516 = + guard__h540174 } ; + assign result__h579483 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[0] | - guard__h579511 } ; - assign result__h643363 = w__h643358 & y__h643392 ; - assign result__h643414 = ~x__h643413 ; - assign rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252 = + guard__h579478 } ; + assign result__h643303 = w__h643298 & y__h643332 ; + assign result__h643354 = ~x__h643353 ; + assign rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693 = + assign rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 = rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688 ; - assign rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243 = + NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 ; + assign rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && @@ -31063,19 +31059,19 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306 = + assign rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 : CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q270 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h651965 = + assign rs1__h651905 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h607897 = { r1__read__h611543, csrf_ppn_reg } ; + assign satp_csr__read__h607864 = { r1__read__h611496, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -31095,461 +31091,463 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 && IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ; - assign sbIdx__h156904 = + assign sbIdx__h156870 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h607695 = - { r1__read__h611307, csrf_scause_code_reg } ; - assign scounteren_csr__read__h607557 = - { r1__read__h611294, csrf_scounteren_cy_reg } ; - assign sfd__h336357 = { value__h344584, 3'd0 } ; - assign sfd__h352165 = + assign scause_csr__read__h607662 = + { r1__read__h611260, csrf_scause_code_reg } ; + assign scounteren_csr__read__h607524 = + { r1__read__h611247, csrf_scounteren_cy_reg } ; + assign sfd__h336324 = { value__h344551, 3'd0 } ; + assign sfd__h352132 = { 1'b0, - _theResult___fst_exp__h352073 != 8'd0, - sfdin__h352067[56:34] } + + _theResult___fst_exp__h352040 != 8'd0, + sfdin__h352034[56:34] } + 25'd1 ; - assign sfd__h360747 = + assign sfd__h360714 = { 1'b0, - _theResult___fst_exp__h360729 != 8'd0, - _theResult___snd__h360680[56:34] } + + _theResult___fst_exp__h360696 != 8'd0, + _theResult___snd__h360647[56:34] } + 25'd1 ; - assign sfd__h369931 = + assign sfd__h369898 = { 1'b0, - _theResult___fst_exp__h369839 != 8'd0, - sfdin__h369833[56:34] } + + _theResult___fst_exp__h369806 != 8'd0, + sfdin__h369800[56:34] } + 25'd1 ; - assign sfd__h378543 = + assign sfd__h378510 = { 1'b0, - _theResult___fst_exp__h378524 != 8'd0, - _theResult___snd__h378470[56:34] } + + _theResult___fst_exp__h378491 != 8'd0, + _theResult___snd__h378437[56:34] } + 25'd1 ; - assign sfd__h382059 = { value__h390281, 3'd0 } ; - assign sfd__h397862 = + assign sfd__h382026 = { value__h390248, 3'd0 } ; + assign sfd__h397829 = { 1'b0, - _theResult___fst_exp__h397770 != 8'd0, - sfdin__h397764[56:34] } + + _theResult___fst_exp__h397737 != 8'd0, + sfdin__h397731[56:34] } + 25'd1 ; - assign sfd__h406444 = + assign sfd__h406411 = { 1'b0, - _theResult___fst_exp__h406426 != 8'd0, - _theResult___snd__h406377[56:34] } + + _theResult___fst_exp__h406393 != 8'd0, + _theResult___snd__h406344[56:34] } + 25'd1 ; - assign sfd__h415628 = + assign sfd__h415595 = { 1'b0, - _theResult___fst_exp__h415536 != 8'd0, - sfdin__h415530[56:34] } + + _theResult___fst_exp__h415503 != 8'd0, + sfdin__h415497[56:34] } + 25'd1 ; - assign sfd__h424240 = + assign sfd__h424207 = { 1'b0, - _theResult___fst_exp__h424221 != 8'd0, - _theResult___snd__h424167[56:34] } + + _theResult___fst_exp__h424188 != 8'd0, + _theResult___snd__h424134[56:34] } + 25'd1 ; - assign sfd__h427754 = { value__h435976, 3'd0 } ; - assign sfd__h443557 = + assign sfd__h427721 = { value__h435943, 3'd0 } ; + assign sfd__h443524 = { 1'b0, - _theResult___fst_exp__h443465 != 8'd0, - sfdin__h443459[56:34] } + + _theResult___fst_exp__h443432 != 8'd0, + sfdin__h443426[56:34] } + 25'd1 ; - assign sfd__h452139 = + assign sfd__h452106 = { 1'b0, - _theResult___fst_exp__h452121 != 8'd0, - _theResult___snd__h452072[56:34] } + + _theResult___fst_exp__h452088 != 8'd0, + _theResult___snd__h452039[56:34] } + 25'd1 ; - assign sfd__h461323 = + assign sfd__h461290 = { 1'b0, - _theResult___fst_exp__h461231 != 8'd0, - sfdin__h461225[56:34] } + + _theResult___fst_exp__h461198 != 8'd0, + sfdin__h461192[56:34] } + 25'd1 ; - assign sfd__h469935 = + assign sfd__h469902 = { 1'b0, - _theResult___fst_exp__h469916 != 8'd0, - _theResult___snd__h469862[56:34] } + + _theResult___fst_exp__h469883 != 8'd0, + _theResult___snd__h469829[56:34] } + 25'd1 ; - assign sfd__h480379 = { value__h484962, 32'd0 } ; - assign sfd__h499423 = + assign sfd__h480346 = { value__h484929, 32'd0 } ; + assign sfd__h499390 = { 1'b0, - _theResult___fst_exp__h499405 != 11'd0, - _theResult___snd__h499356[56:5] } + + _theResult___fst_exp__h499372 != 11'd0, + _theResult___snd__h499323[56:5] } + 54'd1 ; - assign sfd__h509074 = + assign sfd__h509041 = { 1'b0, - _theResult___fst_exp__h508982 != 11'd0, - sfdin__h508976[56:5] } + + _theResult___fst_exp__h508949 != 11'd0, + sfdin__h508943[56:5] } + 54'd1 ; - assign sfd__h517834 = + assign sfd__h517801 = { 1'b0, - _theResult___fst_exp__h517815 != 11'd0, - _theResult___snd__h517761[56:5] } + + _theResult___fst_exp__h517782 != 11'd0, + _theResult___snd__h517728[56:5] } + 54'd1 ; - assign sfd__h519373 = { value__h523815, 32'd0 } ; - assign sfd__h538276 = + assign sfd__h519340 = { value__h523782, 32'd0 } ; + assign sfd__h538243 = { 1'b0, - _theResult___fst_exp__h538258 != 11'd0, - _theResult___snd__h538209[56:5] } + + _theResult___fst_exp__h538225 != 11'd0, + _theResult___snd__h538176[56:5] } + 54'd1 ; - assign sfd__h547927 = + assign sfd__h547894 = { 1'b0, - _theResult___fst_exp__h547835 != 11'd0, - sfdin__h547829[56:5] } + + _theResult___fst_exp__h547802 != 11'd0, + sfdin__h547796[56:5] } + 54'd1 ; - assign sfd__h556687 = + assign sfd__h556654 = { 1'b0, - _theResult___fst_exp__h556668 != 11'd0, - _theResult___snd__h556614[56:5] } + + _theResult___fst_exp__h556635 != 11'd0, + _theResult___snd__h556581[56:5] } + 54'd1 ; - assign sfd__h558677 = { value__h563119, 32'd0 } ; - assign sfd__h577580 = + assign sfd__h558644 = { value__h563086, 32'd0 } ; + assign sfd__h577547 = { 1'b0, - _theResult___fst_exp__h577562 != 11'd0, - _theResult___snd__h577513[56:5] } + + _theResult___fst_exp__h577529 != 11'd0, + _theResult___snd__h577480[56:5] } + 54'd1 ; - assign sfd__h587231 = + assign sfd__h587198 = { 1'b0, - _theResult___fst_exp__h587139 != 11'd0, - sfdin__h587133[56:5] } + + _theResult___fst_exp__h587106 != 11'd0, + sfdin__h587100[56:5] } + 54'd1 ; - assign sfd__h595991 = + assign sfd__h595958 = { 1'b0, - _theResult___fst_exp__h595972 != 11'd0, - _theResult___snd__h595918[56:5] } + + _theResult___fst_exp__h595939 != 11'd0, + _theResult___snd__h595885[56:5] } + 54'd1 ; - assign sfdin__h352067 = - _theResult____h343962[56] ? - _theResult___snd__h352084 : - _theResult___snd__h352095 ; - assign sfdin__h369833 = - _theResult____h361601[56] ? - _theResult___snd__h369850 : - _theResult___snd__h369861 ; - assign sfdin__h397764 = - _theResult____h389661[56] ? - _theResult___snd__h397781 : - _theResult___snd__h397792 ; - assign sfdin__h415530 = - _theResult____h407298[56] ? - _theResult___snd__h415547 : - _theResult___snd__h415558 ; - assign sfdin__h443459 = - _theResult____h435356[56] ? - _theResult___snd__h443476 : - _theResult___snd__h443487 ; - assign sfdin__h461225 = - _theResult____h452993[56] ? - _theResult___snd__h461242 : - _theResult___snd__h461253 ; - assign sfdin__h508976 = - _theResult____h500746[56] ? - _theResult___snd__h508993 : - _theResult___snd__h509004 ; - assign sfdin__h547829 = - _theResult____h539599[56] ? - _theResult___snd__h547846 : - _theResult___snd__h547857 ; - assign sfdin__h587133 = - _theResult____h578903[56] ? - _theResult___snd__h587150 : - _theResult___snd__h587161 ; - assign shiftData__h181173 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181305 ; - assign sie_csr__read__h607461 = - { r1__read__h610759, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h607834 = - { r1__read__h611313, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h681761 = specTagManager$currentSpecBits | y__h681774 ; - assign sstatus_csr__read__h607392 = { r1__read__h610355, csrf_ie_vec_0 } ; - assign stvec_csr__read__h607504 = - { r1__read__h611289, csrf_stvec_mode_low_reg } ; - assign upd__h4024 = + assign sfdin__h352034 = + _theResult____h343929[56] ? + _theResult___snd__h352051 : + _theResult___snd__h352062 ; + assign sfdin__h369800 = + _theResult____h361568[56] ? + _theResult___snd__h369817 : + _theResult___snd__h369828 ; + assign sfdin__h397731 = + _theResult____h389628[56] ? + _theResult___snd__h397748 : + _theResult___snd__h397759 ; + assign sfdin__h415497 = + _theResult____h407265[56] ? + _theResult___snd__h415514 : + _theResult___snd__h415525 ; + assign sfdin__h443426 = + _theResult____h435323[56] ? + _theResult___snd__h443443 : + _theResult___snd__h443454 ; + assign sfdin__h461192 = + _theResult____h452960[56] ? + _theResult___snd__h461209 : + _theResult___snd__h461220 ; + assign sfdin__h508943 = + _theResult____h500713[56] ? + _theResult___snd__h508960 : + _theResult___snd__h508971 ; + assign sfdin__h547796 = + _theResult____h539566[56] ? + _theResult___snd__h547813 : + _theResult___snd__h547824 ; + assign sfdin__h587100 = + _theResult____h578870[56] ? + _theResult___snd__h587117 : + _theResult___snd__h587128 ; + assign shiftData__h181140 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181272 ; + assign sie_csr__read__h607428 = + { r1__read__h610712, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h607801 = + { r1__read__h611266, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h681701 = specTagManager$currentSpecBits | y__h681714 ; + assign sstatus_csr__read__h607359 = { r1__read__h610308, csrf_ie_vec_0 } ; + assign stvec_csr__read__h607471 = + { r1__read__h611242, csrf_stvec_mode_low_reg } ; + assign upd__h3992 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5341 = n__read__h6636 + 64'd1 ; - assign upd__h6750 = + assign upd__h5309 = n__read__h6604 + 64'd1 ; + assign upd__h6718 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h710124 = + assign upd__h710029 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h293820 = + assign v__h293788 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h294051 : + v__h294019 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h294051 = + assign v__h294019 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h297165 = + assign v__h297133 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297683 : + v__h297651 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297683 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307679 = + assign v__h297651 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307647 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307910 : + v__h307878 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307910 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h311555 = + assign v__h307878 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h311523 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311786 : + v__h311754 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311786 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h326156 = + assign v__h311754 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h326124 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h326387 : + v__h326355 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h326387 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h329381 = + assign v__h326355 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h329349 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h329612 : + v__h329580 : coreFix_memExe_forwardQ_enqP ; - assign v__h329612 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h601760 = + assign v__h329580 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h601727 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h601770 : + v__h601737 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h601770 = + assign v__h601737 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h602405 = v__h601760 - 2'd1 ; - assign v__h605779 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h606684 ; - assign v__h630099 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h630852 ; - assign vaddr__h181168 = + assign v__h602372 = v__h601727 - 2'd1 ; + assign v__h605746 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h606651 ; + assign v__h630040 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h630793 ; + assign vaddr__h181135 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12 } ; - assign value__h344584 = + assign value_BIT_52___h399003 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != + 11'd0 ; + assign value__h344551 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h390281 = + assign value__h390248 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0, + value_BIT_52___h399003, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435976 = + assign value__h435943 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484962 = { 1'b0, f1_exp__h480017 != 8'd0, f1_sfd__h480018 } ; - assign value__h523815 = { 1'b0, f2_exp__h519011 != 8'd0, f2_sfd__h519012 } ; - assign value__h563119 = { 1'b0, f3_exp__h558315 != 8'd0, f3_sfd__h558316 } ; - assign vm_mode_reg__read__h611549 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h643358 = + assign value__h484929 = { 1'b0, f1_exp__h479984 != 8'd0, f1_sfd__h479985 } ; + assign value__h523782 = { 1'b0, f2_exp__h518978 != 8'd0, f2_sfd__h518979 } ; + assign value__h563086 = { 1'b0, f3_exp__h558282 != 8'd0, f3_sfd__h558283 } ; + assign vm_mode_reg__read__h611502 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h643298 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h643414 : + result__h643354 : 12'd4095 ; - assign x__h153478 = + assign x__h153444 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153484 = + assign x__h153450 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157025 = { 3'd0, sbIdx__h156904 } ; - assign x__h157031 = + assign x__h156991 = { 3'd0, sbIdx__h156870 } ; + assign x__h156997 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h159841 = + assign x__h159807 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h159845 = + assign x__h159811 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161693 = + assign x__h161659 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181082 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180170 ; - assign x__h181083 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180776 ; - assign x__h181305 = { vaddr__h181168[2:0], 3'b0 } ; - assign x__h18203 = + assign x__h181049 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180137 ; + assign x__h181050 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180743 ; + assign x__h181272 = { vaddr__h181135[2:0], 3'b0 } ; + assign x__h18170 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h191559 = + assign x__h191526 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190796[63:32] : - curData__h190796[31:0] ; - assign x__h20741 = + curData__h190763[63:32] : + curData__h190763[31:0] ; + assign x__h20708 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h285158 = + assign x__h285126 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h285170 = + assign x__h285138 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h287024 = + assign x__h286992 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h300030 = + assign x__h299998 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335761 = - { (_theResult___exp__h379093 != 8'd255 || - _theResult___sfd__h379094 == 23'd0) && + assign x__h335728 = + { (_theResult___exp__h379060 != 8'd255 || + _theResult___sfd__h379061 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h379370, - out_f_sfd__h379371 } ; + out_f_exp__h379337, + out_f_sfd__h379338 } ; + assign x__h362278 = + sfd__h336324 << (x__h362311[11] ? 12'hAAA : x__h362311) ; assign x__h362311 = - sfd__h336357 << (x__h362344[11] ? 12'hAAA : x__h362344) ; - assign x__h362344 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h381463 = - { (_theResult___exp__h424790 != 8'd255 || - _theResult___sfd__h424791 == 23'd0) && + assign x__h381430 = + { (_theResult___exp__h424757 != 8'd255 || + _theResult___sfd__h424758 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h425067, - out_f_sfd__h425068 } ; + out_f_exp__h425034, + out_f_sfd__h425035 } ; + assign x__h407975 = + sfd__h382026 << (x__h408008[11] ? 12'hAAA : x__h408008) ; assign x__h408008 = - sfd__h382059 << (x__h408041[11] ? 12'hAAA : x__h408041) ; - assign x__h408041 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h427158 = - { (_theResult___exp__h470485 != 8'd255 || - _theResult___sfd__h470486 == 23'd0) && + assign x__h427125 = + { (_theResult___exp__h470452 != 8'd255 || + _theResult___sfd__h470453 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470762, - out_f_sfd__h470763 } ; + out_f_exp__h470729, + out_f_sfd__h470730 } ; + assign x__h453670 = + sfd__h427721 << (x__h453703[11] ? 12'hAAA : x__h453703) ; assign x__h453703 = - sfd__h427754 << (x__h453736[11] ? 12'hAAA : x__h453736) ; - assign x__h453736 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; - assign x__h46110 = + assign x__h46077 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h479547 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476683 ; - assign x__h479548 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477291 ; - assign x__h479549 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477893 ; - assign x__h48646 = + assign x__h479514 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476650 ; + assign x__h479515 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477258 ; + assign x__h479516 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477860 ; + assign x__h48613 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h501454 = sfd__h480379 << x__h501487 ; - assign x__h501487 = + assign x__h501421 = sfd__h480346 << x__h501454 ; + assign x__h501454 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ; - assign x__h540307 = sfd__h519373 << x__h540340 ; - assign x__h540340 = + assign x__h540274 = sfd__h519340 << x__h540307 ; + assign x__h540307 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ; - assign x__h579611 = sfd__h558677 << x__h579644 ; - assign x__h579644 = + assign x__h579578 = sfd__h558644 << x__h579611 ; + assign x__h579611 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ; - assign x__h601261 = a__h600825[63] ^ b__h600826[63] ; - assign x__h610340 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h614583 = + assign x__h601228 = a__h600792[63] ^ b__h600793[63] ; + assign x__h610293 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h614524 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h606894 : - v__h605779 ; - assign x__h614584 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h612440 ; - assign x__h636445 = + rVal1__h606861 : + v__h605746 ; + assign x__h614525 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h612381 ; + assign x__h636385 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h631060 : - v__h630099 ; - assign x__h636446 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634312 ; - assign x__h643362 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h643413 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h692296 = + rVal1__h631001 : + v__h630040 ; + assign x__h636386 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634252 ; + assign x__h643302 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h643353 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h692236 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h700755 = { cause_code__h698122, 2'b0 } ; - assign x__h709419 = { 1'b0, csrf_spp_reg } ; - assign x__h712792 = commitStage_rg_serialnum + y__h712818 ; - assign x__h714428 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_snd_snd_snd_fst__h714252 : - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 ; - assign x__h76055 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311953 = + assign x__h700695 = { cause_code__h698062, 2'b0 } ; + assign x__h709324 = { 1'b0, csrf_spp_reg } ; + assign x__h712697 = commitStage_rg_serialnum + y__h712723 ; + assign x__h714333 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_snd_snd_snd_fst__h714157 : + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 ; + assign x__h76022 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h311921 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65904 = + assign x_data__h65871 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h671111 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h686042 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h651649 = csrf_frm_reg ; - assign x_quotient__h473073 = + assign x_data_imm__h671051 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h685982 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h651589 = csrf_frm_reg ; + assign x_quotient__h473040 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473758 : + q___1__h473725 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h607301 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h473074 = + assign x_reg_ifc__read__h607268 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h473041 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473784 : + r___1__h473751 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252683 = + assign y__h252650 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h643392 = ~x__h643362 ; - assign y__h648323 = + assign y__h643332 = ~x__h643302 ; + assign y__h648263 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -31558,74 +31556,74 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h681774 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h712818 = + assign y__h681714 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h712723 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h712833 : + y_avValue_snd_snd_snd_snd_snd__h712738 : 64'd0 ; - assign y__h714209 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_snd_snd_snd_snd_snd__h714258 : - y__h712818 ; - assign y_avValue__h180170 = + assign y__h714114 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_snd_snd_snd_snd_snd__h714163 : + y__h712723 ; + assign y_avValue__h180137 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180776 = + assign y_avValue__h180743 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476683 = + assign y_avValue__h476650 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h477291 = + assign y_avValue__h477258 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477893 = + assign y_avValue__h477860 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h606684 = + assign y_avValue__h606651 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754 ; - assign y_avValue__h612440 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 ; + assign y_avValue__h612381 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766 ; - assign y_avValue__h630852 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 ? + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 ; + assign y_avValue__h630793 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400 ; - assign y_avValue__h634312 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 ? + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 ; + assign y_avValue__h634252 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412 ; - assign y_avValue__h699008 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 ; + assign y_avValue__h698948 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h700740 + { 58'd0, x__h700755 } : - base__h700740 ; - assign y_avValue__h700777 = + base__h700680 + { 58'd0, x__h700695 } : + base__h700680 ; + assign y_avValue__h700717 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h700943 + { 58'd0, x__h700755 } : - base__h700943 ; - assign y_avValue_fst__h675034 = + base__h700883 + { 58'd0, x__h700695 } : + base__h700883 ; + assign y_avValue_fst__h674974 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h681761 : + spec_bits__h681701 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h675063 = - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ? - y_avValue_fst__h675034 : + assign y_avValue_fst__h675003 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ? + y_avValue_fst__h674974 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h675097 = + assign y_avValue_fst__h675037 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359) ? - y_avValue_fst__h675063 : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ? + y_avValue_fst__h675003 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h712379 = + assign y_avValue_fst__h712284 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31639,10 +31637,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h714101 = - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 | + assign y_avValue_fst__h714006 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h714129 = + assign y_avValue_fst__h714034 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31654,9 +31652,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 : - y_avValue_fst__h714101 ; - assign y_avValue_snd_snd_snd_fst__h712827 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 : + y_avValue_fst__h714006 ; + assign y_avValue_snd_snd_snd_fst__h712732 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31670,7 +31668,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h714252 = + assign y_avValue_snd_snd_snd_fst__h714157 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31682,12 +31680,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 : - y_avValue_snd_snd_snd_fst__h714281 ; - assign y_avValue_snd_snd_snd_fst__h714281 = - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 + + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 : + y_avValue_snd_snd_snd_fst__h714186 ; + assign y_avValue_snd_snd_snd_fst__h714186 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h712833 = + assign y_avValue_snd_snd_snd_snd_snd__h712738 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31701,7 +31699,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h714258 = + assign y_avValue_snd_snd_snd_snd_snd__h714163 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31713,9 +31711,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - y__h712818 : - y_avValue_snd_snd_snd_snd_snd__h714287 ; - assign y_avValue_snd_snd_snd_snd_snd__h714287 = y__h712818 + 64'd1 ; + y__h712723 : + y_avValue_snd_snd_snd_snd_snd__h714192 ; + assign y_avValue_snd_snd_snd_snd_snd__h714192 = y__h712723 + 64'd1 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[153:142]) @@ -31908,28 +31906,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -31945,28 +31943,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -31976,10 +31974,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287946 = + addr__h287914 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287946 = + addr__h287914 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -31988,36 +31986,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h699161 = commitStage_commitTrap[132:69]; - default: trap_val__h699161 = + 4'd0, 4'd3: trap_val__h699101 = commitStage_commitTrap[132:69]; + default: trap_val__h699101 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -32032,222 +32030,336 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h289495 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h289495 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h718266 = fflags_csr__read__h607171; - 12'd2: data_out__h718266 = frm_csr__read__h607182; - 12'd3: data_out__h718266 = fcsr_csr__read__h607196; - 12'd256: data_out__h718266 = sstatus_csr__read__h607392; - 12'd260: data_out__h718266 = sie_csr__read__h607461; - 12'd261: data_out__h718266 = stvec_csr__read__h607504; - 12'd262: data_out__h718266 = scounteren_csr__read__h607557; - 12'd320: data_out__h718266 = csrf_sscratch_csr; - 12'd321: data_out__h718266 = csrf_sepc_csr; - 12'd322: data_out__h718266 = scause_csr__read__h607695; - 12'd323: data_out__h718266 = csrf_stval_csr; - 12'd324: data_out__h718266 = sip_csr__read__h607834; - 12'd384: data_out__h718266 = satp_csr__read__h607897; - 12'd768: data_out__h718266 = mstatus_csr__read__h608040; - 12'd769: data_out__h718266 = 64'h800000000014112D; - 12'd770: data_out__h718266 = medeleg_csr__read__h608188; - 12'd771: data_out__h718266 = mideleg_csr__read__h608283; - 12'd772: data_out__h718266 = mie_csr__read__h608414; - 12'd773: data_out__h718266 = mtvec_csr__read__h608496; - 12'd774: data_out__h718266 = mcounteren_csr__read__h608588; - 12'd832: data_out__h718266 = csrf_mscratch_csr; - 12'd833: data_out__h718266 = csrf_mepc_csr; - 12'd834: data_out__h718266 = mcause_csr__read__h608843; - 12'd835: data_out__h718266 = csrf_mtval_csr; - 12'd836: data_out__h718266 = mip_csr__read__h609083; - 12'd1968: data_out__h718266 = csrf_rg_dcsr; - 12'd1969: data_out__h718266 = csrf_rg_dpc; - 12'd1970: data_out__h718266 = csrf_rg_dscratch0; - 12'd1971: data_out__h718266 = csrf_rg_dscratch1; + 12'd1: data_out__h718171 = fflags_csr__read__h607138; + 12'd2: data_out__h718171 = frm_csr__read__h607149; + 12'd3: data_out__h718171 = fcsr_csr__read__h607163; + 12'd256: data_out__h718171 = sstatus_csr__read__h607359; + 12'd260: data_out__h718171 = sie_csr__read__h607428; + 12'd261: data_out__h718171 = stvec_csr__read__h607471; + 12'd262: data_out__h718171 = scounteren_csr__read__h607524; + 12'd320: data_out__h718171 = csrf_sscratch_csr; + 12'd321: data_out__h718171 = csrf_sepc_csr; + 12'd322: data_out__h718171 = scause_csr__read__h607662; + 12'd323: data_out__h718171 = csrf_stval_csr; + 12'd324: data_out__h718171 = sip_csr__read__h607801; + 12'd384: data_out__h718171 = satp_csr__read__h607864; + 12'd768: data_out__h718171 = mstatus_csr__read__h608007; + 12'd769: data_out__h718171 = 64'h800000000014112D; + 12'd770: data_out__h718171 = medeleg_csr__read__h608155; + 12'd771: data_out__h718171 = mideleg_csr__read__h608250; + 12'd772: data_out__h718171 = mie_csr__read__h608374; + 12'd773: data_out__h718171 = mtvec_csr__read__h608456; + 12'd774: data_out__h718171 = mcounteren_csr__read__h608548; + 12'd832: data_out__h718171 = csrf_mscratch_csr; + 12'd833: data_out__h718171 = csrf_mepc_csr; + 12'd834: data_out__h718171 = mcause_csr__read__h608803; + 12'd835: data_out__h718171 = csrf_mtval_csr; + 12'd836: data_out__h718171 = mip_csr__read__h609036; + 12'd1968: data_out__h718171 = csrf_rg_dcsr; + 12'd1969: data_out__h718171 = csrf_rg_dpc; + 12'd1970: data_out__h718171 = csrf_rg_dscratch0; + 12'd1971: data_out__h718171 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h718266 = 64'd0; - 12'd2049: data_out__h718266 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: data_out__h718266 = n__read__h609187; - 12'd2818, 12'd3074: data_out__h718266 = n__read__h609378; - 12'd3073: data_out__h718266 = csrf_time_reg; - default: data_out__h718266 = 64'b0; + data_out__h718171 = 64'd0; + 12'd2049: data_out__h718171 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: data_out__h718171 = n__read__h609140; + 12'd2818, 12'd3074: data_out__h718171 = n__read__h609331; + 12'd3073: data_out__h718171 = csrf_time_reg; + default: data_out__h718171 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h606894 = fflags_csr__read__h607171; - 12'd2: rVal1__h606894 = frm_csr__read__h607182; - 12'd3: rVal1__h606894 = fcsr_csr__read__h607196; - 12'd256: rVal1__h606894 = sstatus_csr__read__h607392; - 12'd260: rVal1__h606894 = sie_csr__read__h607461; - 12'd261: rVal1__h606894 = stvec_csr__read__h607504; - 12'd262: rVal1__h606894 = scounteren_csr__read__h607557; - 12'd320: rVal1__h606894 = csrf_sscratch_csr; - 12'd321: rVal1__h606894 = csrf_sepc_csr; - 12'd322: rVal1__h606894 = scause_csr__read__h607695; - 12'd323: rVal1__h606894 = csrf_stval_csr; - 12'd324: rVal1__h606894 = sip_csr__read__h607834; - 12'd384: rVal1__h606894 = satp_csr__read__h607897; - 12'd768: rVal1__h606894 = mstatus_csr__read__h608040; - 12'd769: rVal1__h606894 = 64'h800000000014112D; - 12'd770: rVal1__h606894 = medeleg_csr__read__h608188; - 12'd771: rVal1__h606894 = mideleg_csr__read__h608283; - 12'd772: rVal1__h606894 = mie_csr__read__h608414; - 12'd773: rVal1__h606894 = mtvec_csr__read__h608496; - 12'd774: rVal1__h606894 = mcounteren_csr__read__h608588; - 12'd832: rVal1__h606894 = csrf_mscratch_csr; - 12'd833: rVal1__h606894 = csrf_mepc_csr; - 12'd834: rVal1__h606894 = mcause_csr__read__h608843; - 12'd835: rVal1__h606894 = csrf_mtval_csr; - 12'd836: rVal1__h606894 = mip_csr__read__h609083; - 12'd1968: rVal1__h606894 = csrf_rg_dcsr; - 12'd1969: rVal1__h606894 = csrf_rg_dpc; - 12'd1970: rVal1__h606894 = csrf_rg_dscratch0; - 12'd1971: rVal1__h606894 = csrf_rg_dscratch1; + 12'd1: rVal1__h606861 = fflags_csr__read__h607138; + 12'd2: rVal1__h606861 = frm_csr__read__h607149; + 12'd3: rVal1__h606861 = fcsr_csr__read__h607163; + 12'd256: rVal1__h606861 = sstatus_csr__read__h607359; + 12'd260: rVal1__h606861 = sie_csr__read__h607428; + 12'd261: rVal1__h606861 = stvec_csr__read__h607471; + 12'd262: rVal1__h606861 = scounteren_csr__read__h607524; + 12'd320: rVal1__h606861 = csrf_sscratch_csr; + 12'd321: rVal1__h606861 = csrf_sepc_csr; + 12'd322: rVal1__h606861 = scause_csr__read__h607662; + 12'd323: rVal1__h606861 = csrf_stval_csr; + 12'd324: rVal1__h606861 = sip_csr__read__h607801; + 12'd384: rVal1__h606861 = satp_csr__read__h607864; + 12'd768: rVal1__h606861 = mstatus_csr__read__h608007; + 12'd769: rVal1__h606861 = 64'h800000000014112D; + 12'd770: rVal1__h606861 = medeleg_csr__read__h608155; + 12'd771: rVal1__h606861 = mideleg_csr__read__h608250; + 12'd772: rVal1__h606861 = mie_csr__read__h608374; + 12'd773: rVal1__h606861 = mtvec_csr__read__h608456; + 12'd774: rVal1__h606861 = mcounteren_csr__read__h608548; + 12'd832: rVal1__h606861 = csrf_mscratch_csr; + 12'd833: rVal1__h606861 = csrf_mepc_csr; + 12'd834: rVal1__h606861 = mcause_csr__read__h608803; + 12'd835: rVal1__h606861 = csrf_mtval_csr; + 12'd836: rVal1__h606861 = mip_csr__read__h609036; + 12'd1968: rVal1__h606861 = csrf_rg_dcsr; + 12'd1969: rVal1__h606861 = csrf_rg_dpc; + 12'd1970: rVal1__h606861 = csrf_rg_dscratch0; + 12'd1971: rVal1__h606861 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h606894 = 64'd0; - 12'd2049: rVal1__h606894 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: rVal1__h606894 = n__read__h609187; - 12'd2818, 12'd3074: rVal1__h606894 = n__read__h609378; - 12'd3073: rVal1__h606894 = csrf_time_reg; - default: rVal1__h606894 = 64'b0; + rVal1__h606861 = 64'd0; + 12'd2049: rVal1__h606861 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: rVal1__h606861 = n__read__h609140; + 12'd2818, 12'd3074: rVal1__h606861 = n__read__h609331; + 12'd3073: rVal1__h606861 = csrf_time_reg; + default: rVal1__h606861 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h631060 = fflags_csr__read__h607171; - 12'd2: rVal1__h631060 = frm_csr__read__h607182; - 12'd3: rVal1__h631060 = fcsr_csr__read__h607196; - 12'd256: rVal1__h631060 = sstatus_csr__read__h607392; - 12'd260: rVal1__h631060 = sie_csr__read__h607461; - 12'd261: rVal1__h631060 = stvec_csr__read__h607504; - 12'd262: rVal1__h631060 = scounteren_csr__read__h607557; - 12'd320: rVal1__h631060 = csrf_sscratch_csr; - 12'd321: rVal1__h631060 = csrf_sepc_csr; - 12'd322: rVal1__h631060 = scause_csr__read__h607695; - 12'd323: rVal1__h631060 = csrf_stval_csr; - 12'd324: rVal1__h631060 = sip_csr__read__h607834; - 12'd384: rVal1__h631060 = satp_csr__read__h607897; - 12'd768: rVal1__h631060 = mstatus_csr__read__h608040; - 12'd769: rVal1__h631060 = 64'h800000000014112D; - 12'd770: rVal1__h631060 = medeleg_csr__read__h608188; - 12'd771: rVal1__h631060 = mideleg_csr__read__h608283; - 12'd772: rVal1__h631060 = mie_csr__read__h608414; - 12'd773: rVal1__h631060 = mtvec_csr__read__h608496; - 12'd774: rVal1__h631060 = mcounteren_csr__read__h608588; - 12'd832: rVal1__h631060 = csrf_mscratch_csr; - 12'd833: rVal1__h631060 = csrf_mepc_csr; - 12'd834: rVal1__h631060 = mcause_csr__read__h608843; - 12'd835: rVal1__h631060 = csrf_mtval_csr; - 12'd836: rVal1__h631060 = mip_csr__read__h609083; - 12'd1968: rVal1__h631060 = csrf_rg_dcsr; - 12'd1969: rVal1__h631060 = csrf_rg_dpc; - 12'd1970: rVal1__h631060 = csrf_rg_dscratch0; - 12'd1971: rVal1__h631060 = csrf_rg_dscratch1; + 12'd1: rVal1__h631001 = fflags_csr__read__h607138; + 12'd2: rVal1__h631001 = frm_csr__read__h607149; + 12'd3: rVal1__h631001 = fcsr_csr__read__h607163; + 12'd256: rVal1__h631001 = sstatus_csr__read__h607359; + 12'd260: rVal1__h631001 = sie_csr__read__h607428; + 12'd261: rVal1__h631001 = stvec_csr__read__h607471; + 12'd262: rVal1__h631001 = scounteren_csr__read__h607524; + 12'd320: rVal1__h631001 = csrf_sscratch_csr; + 12'd321: rVal1__h631001 = csrf_sepc_csr; + 12'd322: rVal1__h631001 = scause_csr__read__h607662; + 12'd323: rVal1__h631001 = csrf_stval_csr; + 12'd324: rVal1__h631001 = sip_csr__read__h607801; + 12'd384: rVal1__h631001 = satp_csr__read__h607864; + 12'd768: rVal1__h631001 = mstatus_csr__read__h608007; + 12'd769: rVal1__h631001 = 64'h800000000014112D; + 12'd770: rVal1__h631001 = medeleg_csr__read__h608155; + 12'd771: rVal1__h631001 = mideleg_csr__read__h608250; + 12'd772: rVal1__h631001 = mie_csr__read__h608374; + 12'd773: rVal1__h631001 = mtvec_csr__read__h608456; + 12'd774: rVal1__h631001 = mcounteren_csr__read__h608548; + 12'd832: rVal1__h631001 = csrf_mscratch_csr; + 12'd833: rVal1__h631001 = csrf_mepc_csr; + 12'd834: rVal1__h631001 = mcause_csr__read__h608803; + 12'd835: rVal1__h631001 = csrf_mtval_csr; + 12'd836: rVal1__h631001 = mip_csr__read__h609036; + 12'd1968: rVal1__h631001 = csrf_rg_dcsr; + 12'd1969: rVal1__h631001 = csrf_rg_dpc; + 12'd1970: rVal1__h631001 = csrf_rg_dscratch0; + 12'd1971: rVal1__h631001 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h631060 = 64'd0; - 12'd2049: rVal1__h631060 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: rVal1__h631060 = n__read__h609187; - 12'd2818, 12'd3074: rVal1__h631060 = n__read__h609378; - 12'd3073: rVal1__h631060 = csrf_time_reg; - default: rVal1__h631060 = 64'b0; + rVal1__h631001 = 64'd0; + 12'd2049: rVal1__h631001 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: rVal1__h631001 = n__read__h609140; + 12'd2818, 12'd3074: rVal1__h631001 = n__read__h609331; + 12'd3073: rVal1__h631001 = csrf_time_reg; + default: rVal1__h631001 = 64'b0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h343911 = 8'd255; + 3'd2: + _theResult___fst_exp__h343911 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h343911 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h343911 = 8'd254; + default: _theResult___fst_exp__h343911 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h343912 = 23'd0; + 3'd2: + _theResult___fst_sfd__h343912 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h343912 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h343912 = 23'd8388607; + default: _theResult___fst_sfd__h343912 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h389611 = 23'd0; + 3'd2: + _theResult___fst_sfd__h389611 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h389611 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h389611 = 23'd8388607; + default: _theResult___fst_sfd__h389611 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h389610 = 8'd255; + 3'd2: + _theResult___fst_exp__h389610 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h389610 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h389610 = 8'd254; + default: _theResult___fst_exp__h389610 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h435305 = 8'd255; + 3'd2: + _theResult___fst_exp__h435305 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h435305 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h435305 = 8'd254; + default: _theResult___fst_exp__h435305 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h435306 = 23'd0; + 3'd2: + _theResult___fst_sfd__h435306 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h435306 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h435306 = 23'd8388607; + default: _theResult___fst_sfd__h435306 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -32256,221 +32368,107 @@ module mkCore(CLK, 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343944 = 8'd255; - 3'd2: - _theResult___fst_exp__h343944 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h343944 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h343944 = 8'd254; - default: _theResult___fst_exp__h343944 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343945 = 23'd0; - 3'd2: - _theResult___fst_sfd__h343945 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h343945 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h343945 = 23'd8388607; - default: _theResult___fst_sfd__h343945 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h389643 = 8'd255; - 3'd2: - _theResult___fst_exp__h389643 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h389643 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h389643 = 8'd254; - default: _theResult___fst_exp__h389643 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h389644 = 23'd0; - 3'd2: - _theResult___fst_sfd__h389644 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h389644 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h389644 = 23'd8388607; - default: _theResult___fst_sfd__h389644 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h435338 = 8'd255; - 3'd2: - _theResult___fst_exp__h435338 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h435338 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h435338 = 8'd254; - default: _theResult___fst_exp__h435338 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h435339 = 23'd0; - 3'd2: - _theResult___fst_sfd__h435339 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h435339 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h435339 = 23'd8388607; - default: _theResult___fst_sfd__h435339 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -32512,16 +32510,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h698137 = commitStage_commitTrap[3:0]; - default: i__h698137 = 4'd15; + i__h698077 = commitStage_commitTrap[3:0]; + default: i__h698077 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h698297 = commitStage_commitTrap[3:0]; - default: i__h698297 = 4'd15; + i__h698237 = commitStage_commitTrap[3:0]; + default: i__h698237 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -32749,446 +32747,394 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h352681 or - _theResult___fst_exp__h360729 or - out_exp__h361174 or _theResult___exp__h361171) + always@(guard__h352648 or + _theResult___fst_exp__h360696 or + out_exp__h361141 or _theResult___exp__h361138) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - _theResult___fst_exp__h360729; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + _theResult___fst_exp__h360696; 2'b10: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - out_exp__h361174; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + out_exp__h361141; 2'b11: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - _theResult___exp__h361171; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + _theResult___exp__h361138; endcase end - always@(guard__h352681 or - _theResult___fst_exp__h360729 or _theResult___exp__h361171) + always@(guard__h352648 or + _theResult___fst_exp__h360696 or _theResult___exp__h361138) begin - case (guard__h352681) + case (guard__h352648) 2'b0: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 = - _theResult___fst_exp__h360729; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 = + _theResult___fst_exp__h360696; 2'b01, 2'b10, 2'b11: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 = - _theResult___exp__h361171; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 = + _theResult___exp__h361138; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 or - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 or + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 or + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360729) + _theResult___fst_exp__h360696) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h361249 = - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32; + _theResult___fst_exp__h361216 = + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32; 3'd1: - _theResult___fst_exp__h361249 = - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33; + _theResult___fst_exp__h361216 = + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33; 3'd2: - _theResult___fst_exp__h361249 = + _theResult___fst_exp__h361216 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h361249 = + _theResult___fst_exp__h361216 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h361249 = _theResult___fst_exp__h360729; - default: _theResult___fst_exp__h361249 = 8'd0; + 3'd4: _theResult___fst_exp__h361216 = _theResult___fst_exp__h360696; + default: _theResult___fst_exp__h361216 = 8'd0; endcase end - always@(guard__h343972 or - _theResult___fst_exp__h352073 or - out_exp__h352592 or _theResult___exp__h352589) + always@(guard__h343939 or + _theResult___fst_exp__h352040 or + out_exp__h352559 or _theResult___exp__h352556) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - _theResult___fst_exp__h352073; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + _theResult___fst_exp__h352040; 2'b10: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - out_exp__h352592; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + out_exp__h352559; 2'b11: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - _theResult___exp__h352589; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + _theResult___exp__h352556; endcase end - always@(guard__h343972 or - _theResult___fst_exp__h352073 or _theResult___exp__h352589) + always@(guard__h343939 or + _theResult___fst_exp__h352040 or _theResult___exp__h352556) begin - case (guard__h343972) + case (guard__h343939) 2'b0: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 = - _theResult___fst_exp__h352073; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 = + _theResult___fst_exp__h352040; 2'b01, 2'b10, 2'b11: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 = - _theResult___exp__h352589; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 = + _theResult___exp__h352556; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 or - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 or + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 or + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h352073) + _theResult___fst_exp__h352040) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352667 = - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34; + _theResult___fst_exp__h352634 = + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34; 3'd1: - _theResult___fst_exp__h352667 = - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35; + _theResult___fst_exp__h352634 = + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35; 3'd2: - _theResult___fst_exp__h352667 = + _theResult___fst_exp__h352634 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352667 = + _theResult___fst_exp__h352634 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352667 = _theResult___fst_exp__h352073; - default: _theResult___fst_exp__h352667 = 8'd0; + 3'd4: _theResult___fst_exp__h352634 = _theResult___fst_exp__h352040; + default: _theResult___fst_exp__h352634 = 8'd0; endcase end - always@(guard__h361611 or - _theResult___fst_exp__h369839 or - out_exp__h370358 or _theResult___exp__h370355) + always@(guard__h361578 or + _theResult___fst_exp__h369806 or + out_exp__h370325 or _theResult___exp__h370322) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - _theResult___fst_exp__h369839; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + _theResult___fst_exp__h369806; 2'b10: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - out_exp__h370358; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + out_exp__h370325; 2'b11: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - _theResult___exp__h370355; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + _theResult___exp__h370322; endcase end - always@(guard__h361611 or - _theResult___fst_exp__h369839 or _theResult___exp__h370355) + always@(guard__h361578 or + _theResult___fst_exp__h369806 or _theResult___exp__h370322) begin - case (guard__h361611) + case (guard__h361578) 2'b0: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 = - _theResult___fst_exp__h369839; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 = + _theResult___fst_exp__h369806; 2'b01, 2'b10, 2'b11: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 = - _theResult___exp__h370355; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 = + _theResult___exp__h370322; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 or - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 or + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 or + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369839) + _theResult___fst_exp__h369806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h370433 = - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40; + _theResult___fst_exp__h370400 = + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40; 3'd1: - _theResult___fst_exp__h370433 = - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41; + _theResult___fst_exp__h370400 = + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41; 3'd2: - _theResult___fst_exp__h370433 = + _theResult___fst_exp__h370400 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h370433 = + _theResult___fst_exp__h370400 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h370433 = _theResult___fst_exp__h369839; - default: _theResult___fst_exp__h370433 = 8'd0; + 3'd4: _theResult___fst_exp__h370400 = _theResult___fst_exp__h369806; + default: _theResult___fst_exp__h370400 = 8'd0; endcase end - always@(guard__h370447 or - _theResult___fst_exp__h378524 or - out_exp__h378994 or _theResult___exp__h378991) + always@(guard__h370414 or + _theResult___fst_exp__h378491 or + out_exp__h378961 or _theResult___exp__h378958) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - _theResult___fst_exp__h378524; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + _theResult___fst_exp__h378491; 2'b10: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - out_exp__h378994; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + out_exp__h378961; 2'b11: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - _theResult___exp__h378991; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + _theResult___exp__h378958; endcase end - always@(guard__h370447 or - _theResult___fst_exp__h378524 or _theResult___exp__h378991) + always@(guard__h370414 or + _theResult___fst_exp__h378491 or _theResult___exp__h378958) begin - case (guard__h370447) + case (guard__h370414) 2'b0: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 = - _theResult___fst_exp__h378524; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 = + _theResult___fst_exp__h378491; 2'b01, 2'b10, 2'b11: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 = - _theResult___exp__h378991; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 = + _theResult___exp__h378958; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 or - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 or + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 or + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h378524) + _theResult___fst_exp__h378491) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h379069 = - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45; + _theResult___fst_exp__h379036 = + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45; 3'd1: - _theResult___fst_exp__h379069 = - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46; + _theResult___fst_exp__h379036 = + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46; 3'd2: - _theResult___fst_exp__h379069 = + _theResult___fst_exp__h379036 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h379069 = + _theResult___fst_exp__h379036 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h379069 = _theResult___fst_exp__h378524; - default: _theResult___fst_exp__h379069 = 8'd0; + 3'd4: _theResult___fst_exp__h379036 = _theResult___fst_exp__h378491; + default: _theResult___fst_exp__h379036 = 8'd0; endcase end - always@(guard__h352681 or - _theResult___snd__h360680 or - out_sfd__h361175 or _theResult___sfd__h361172) + always@(guard__h352648 or + _theResult___snd__h360647 or + out_sfd__h361142 or _theResult___sfd__h361139) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - _theResult___snd__h360680[56:34]; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + _theResult___snd__h360647[56:34]; 2'b10: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - out_sfd__h361175; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + out_sfd__h361142; 2'b11: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - _theResult___sfd__h361172; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + _theResult___sfd__h361139; endcase end - always@(guard__h352681 or - _theResult___snd__h360680 or _theResult___sfd__h361172) + always@(guard__h352648 or + _theResult___snd__h360647 or _theResult___sfd__h361139) begin - case (guard__h352681) + case (guard__h352648) 2'b0: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 = - _theResult___snd__h360680[56:34]; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 = + _theResult___snd__h360647[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 = - _theResult___sfd__h361172; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 = + _theResult___sfd__h361139; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 or - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 or + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 or + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360680) + _theResult___snd__h360647) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h361250 = - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47; + _theResult___fst_sfd__h361217 = + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h361250 = - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48; + _theResult___fst_sfd__h361217 = + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h361250 = + _theResult___fst_sfd__h361217 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h361250 = + _theResult___fst_sfd__h361217 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h361250 = _theResult___snd__h360680[56:34]; - default: _theResult___fst_sfd__h361250 = 23'd0; + 3'd4: _theResult___fst_sfd__h361217 = _theResult___snd__h360647[56:34]; + default: _theResult___fst_sfd__h361217 = 23'd0; endcase end - always@(guard__h343972 or - sfdin__h352067 or out_sfd__h352593 or _theResult___sfd__h352590) + always@(guard__h343939 or + sfdin__h352034 or out_sfd__h352560 or _theResult___sfd__h352557) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - sfdin__h352067[56:34]; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + sfdin__h352034[56:34]; 2'b10: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h352593; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h352560; 2'b11: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h352590; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h352557; endcase end - always@(guard__h343972 or sfdin__h352067 or _theResult___sfd__h352590) + always@(guard__h343939 or sfdin__h352034 or _theResult___sfd__h352557) begin - case (guard__h343972) + case (guard__h343939) 2'b0: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 = - sfdin__h352067[56:34]; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 = + sfdin__h352034[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h352590; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h352557; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 or - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 or + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 or + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h352067) + sfdin__h352034) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352668 = - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h352635 = + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h352668 = - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h352635 = + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h352668 = + _theResult___fst_sfd__h352635 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352668 = + _theResult___fst_sfd__h352635 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352668 = sfdin__h352067[56:34]; - default: _theResult___fst_sfd__h352668 = 23'd0; + 3'd4: _theResult___fst_sfd__h352635 = sfdin__h352034[56:34]; + default: _theResult___fst_sfd__h352635 = 23'd0; endcase end - always@(guard__h361611 or - sfdin__h369833 or out_sfd__h370359 or _theResult___sfd__h370356) + always@(guard__h361578 or + sfdin__h369800 or out_sfd__h370326 or _theResult___sfd__h370323) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - sfdin__h369833[56:34]; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + sfdin__h369800[56:34]; 2'b10: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h370359; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h370326; 2'b11: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h370356; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h370323; endcase end - always@(guard__h361611 or sfdin__h369833 or _theResult___sfd__h370356) + always@(guard__h361578 or sfdin__h369800 or _theResult___sfd__h370323) begin - case (guard__h361611) + case (guard__h361578) 2'b0: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 = - sfdin__h369833[56:34]; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 = + sfdin__h369800[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h370356; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h370323; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 or - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 or + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 or + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369833) + sfdin__h369800) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h370434 = - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h370401 = + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h370434 = - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h370401 = + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h370434 = + _theResult___fst_sfd__h370401 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h370434 = + _theResult___fst_sfd__h370401 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h370434 = sfdin__h369833[56:34]; - default: _theResult___fst_sfd__h370434 = 23'd0; + 3'd4: _theResult___fst_sfd__h370401 = sfdin__h369800[56:34]; + default: _theResult___fst_sfd__h370401 = 23'd0; endcase end - always@(guard__h370447 or - _theResult___snd__h378470 or - out_sfd__h378995 or _theResult___sfd__h378992) - begin - case (guard__h370447) - 2'b0, 2'b01: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - _theResult___snd__h378470[56:34]; - 2'b10: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - out_sfd__h378995; - 2'b11: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - _theResult___sfd__h378992; - endcase - end - always@(guard__h370447 or - _theResult___snd__h378470 or _theResult___sfd__h378992) - begin - case (guard__h370447) - 2'b0: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 = - _theResult___snd__h378470[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 = - _theResult___sfd__h378992; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 or - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h378470) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h379070 = - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53; - 3'd1: - _theResult___fst_sfd__h379070 = - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54; - 3'd2: - _theResult___fst_sfd__h379070 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; - 3'd3: - _theResult___fst_sfd__h379070 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h379070 = _theResult___snd__h378470[56:34]; - default: _theResult___fst_sfd__h379070 = 23'd0; - endcase - end - always@(guard__h343972 or + always@(guard__h343939 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01, 2'b10: - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h343972 == 2'b11 && + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + guard__h343939 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h343972) + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or + guard__h343939) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343972 == 2'b0) ? + (guard__h343939 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343972 == 2'b01 || guard__h343972 == 2'b10 || - guard__h343972 == 2'b11) && + (guard__h343939 == 2'b01 || guard__h343939 == 2'b10 || + guard__h343939 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -33199,34 +33145,86 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343972 or + always@(guard__h370414 or + _theResult___snd__h378437 or + out_sfd__h378962 or _theResult___sfd__h378959) + begin + case (guard__h370414) + 2'b0, 2'b01: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + _theResult___snd__h378437[56:34]; + 2'b10: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + out_sfd__h378962; + 2'b11: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + _theResult___sfd__h378959; + endcase + end + always@(guard__h370414 or + _theResult___snd__h378437 or _theResult___sfd__h378959) + begin + case (guard__h370414) + 2'b0: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 = + _theResult___snd__h378437[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 = + _theResult___sfd__h378959; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 or + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or + _theResult___snd__h378437) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h379037 = + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54; + 3'd1: + _theResult___fst_sfd__h379037 = + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55; + 3'd2: + _theResult___fst_sfd__h379037 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; + 3'd3: + _theResult___fst_sfd__h379037 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; + 3'd4: _theResult___fst_sfd__h379037 = _theResult___snd__h378437[56:34]; + default: _theResult___fst_sfd__h379037 = 23'd0; + endcase + end + always@(guard__h343939 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01, 2'b10: - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h343972 != 2'b11 || + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h343939 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h343972) + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h343939) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343972 == 2'b0) ? + (guard__h343939 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343972 != 2'b01 && guard__h343972 != 2'b10 && - guard__h343972 != 2'b11 || + guard__h343939 != 2'b01 && guard__h343939 != 2'b10 && + guard__h343939 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -33237,34 +33235,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352681 or + always@(guard__h352648 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01, 2'b10: - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h352681 == 2'b11 && + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h352648 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h352681) + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h352648) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352681 == 2'b0) ? + (guard__h352648 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352681 == 2'b01 || guard__h352681 == 2'b10 || - guard__h352681 == 2'b11) && + (guard__h352648 == 2'b01 || guard__h352648 == 2'b10 || + guard__h352648 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -33275,34 +33273,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352681 or + always@(guard__h352648 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01, 2'b10: - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h352681 != 2'b11 || + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h352648 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h352681) + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h352648) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352681 == 2'b0) ? + (guard__h352648 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352681 != 2'b01 && guard__h352681 != 2'b10 && - guard__h352681 != 2'b11 || + guard__h352648 != 2'b01 && guard__h352648 != 2'b10 && + guard__h352648 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -33313,34 +33311,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h361611 or + always@(guard__h361578 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01, 2'b10: - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h361611 == 2'b11 && + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h361578 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h361611) + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h361578) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h361611 == 2'b0) ? + (guard__h361578 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h361611 == 2'b01 || guard__h361611 == 2'b10 || - guard__h361611 == 2'b11) && + (guard__h361578 == 2'b01 || guard__h361578 == 2'b10 || + guard__h361578 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -33351,34 +33349,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h361611 or + always@(guard__h361578 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01, 2'b10: - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h361611 != 2'b11 || + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h361578 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h361611) + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h361578) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h361611 == 2'b0) ? + (guard__h361578 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h361611 != 2'b01 && guard__h361611 != 2'b10 && - guard__h361611 != 2'b11 || + guard__h361578 != 2'b01 && guard__h361578 != 2'b10 && + guard__h361578 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -33389,34 +33387,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h370447 or + always@(guard__h370414 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01, 2'b10: - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h370447 == 2'b11 && + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h370414 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h370447) + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h370414) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h370447 == 2'b0) ? + (guard__h370414 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h370447 == 2'b01 || guard__h370447 == 2'b10 || - guard__h370447 == 2'b11) && + (guard__h370414 == 2'b01 || guard__h370414 == 2'b10 || + guard__h370414 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -33427,34 +33425,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h370447 or + always@(guard__h370414 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01, 2'b10: - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h370447 != 2'b11 || + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h370414 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h370447) + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h370414) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h370447 == 2'b0) ? + (guard__h370414 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h370447 != 2'b01 && guard__h370447 != 2'b10 && - guard__h370447 != 2'b11 || + guard__h370414 != 2'b01 && guard__h370414 != 2'b10 && + guard__h370414 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -33491,446 +33489,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h398378 or - _theResult___fst_exp__h406426 or - out_exp__h406871 or _theResult___exp__h406868) + always@(guard__h398345 or + _theResult___fst_exp__h406393 or + out_exp__h406838 or _theResult___exp__h406835) begin - case (guard__h398378) + case (guard__h398345) 2'b0, 2'b01: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - _theResult___fst_exp__h406426; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + _theResult___fst_exp__h406393; 2'b10: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - out_exp__h406871; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + out_exp__h406838; 2'b11: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - _theResult___exp__h406868; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + _theResult___exp__h406835; endcase end - always@(guard__h398378 or - _theResult___fst_exp__h406426 or _theResult___exp__h406868) + always@(guard__h398345 or + _theResult___fst_exp__h406393 or _theResult___exp__h406835) begin - case (guard__h398378) + case (guard__h398345) 2'b0: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 = - _theResult___fst_exp__h406426; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 = + _theResult___fst_exp__h406393; 2'b01, 2'b10, 2'b11: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 = - _theResult___exp__h406868; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 = + _theResult___exp__h406835; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 or - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 or + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 or + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h406426) + _theResult___fst_exp__h406393) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406946 = - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67; + _theResult___fst_exp__h406913 = + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67; 3'd1: - _theResult___fst_exp__h406946 = - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68; + _theResult___fst_exp__h406913 = + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68; 3'd2: - _theResult___fst_exp__h406946 = + _theResult___fst_exp__h406913 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406946 = + _theResult___fst_exp__h406913 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406946 = _theResult___fst_exp__h406426; - default: _theResult___fst_exp__h406946 = 8'd0; + 3'd4: _theResult___fst_exp__h406913 = _theResult___fst_exp__h406393; + default: _theResult___fst_exp__h406913 = 8'd0; endcase end - always@(guard__h389671 or - _theResult___fst_exp__h397770 or - out_exp__h398289 or _theResult___exp__h398286) + always@(guard__h389638 or + _theResult___fst_exp__h397737 or + out_exp__h398256 or _theResult___exp__h398253) begin - case (guard__h389671) + case (guard__h389638) 2'b0, 2'b01: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - _theResult___fst_exp__h397770; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + _theResult___fst_exp__h397737; 2'b10: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - out_exp__h398289; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + out_exp__h398256; 2'b11: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - _theResult___exp__h398286; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + _theResult___exp__h398253; endcase end - always@(guard__h389671 or - _theResult___fst_exp__h397770 or _theResult___exp__h398286) + always@(guard__h389638 or + _theResult___fst_exp__h397737 or _theResult___exp__h398253) begin - case (guard__h389671) + case (guard__h389638) 2'b0: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 = - _theResult___fst_exp__h397770; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 = + _theResult___fst_exp__h397737; 2'b01, 2'b10, 2'b11: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 = - _theResult___exp__h398286; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 = + _theResult___exp__h398253; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 or - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 or + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 or + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397770) + _theResult___fst_exp__h397737) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h398364 = - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69; + _theResult___fst_exp__h398331 = + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69; 3'd1: - _theResult___fst_exp__h398364 = - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70; + _theResult___fst_exp__h398331 = + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70; 3'd2: - _theResult___fst_exp__h398364 = + _theResult___fst_exp__h398331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h398364 = + _theResult___fst_exp__h398331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h398364 = _theResult___fst_exp__h397770; - default: _theResult___fst_exp__h398364 = 8'd0; + 3'd4: _theResult___fst_exp__h398331 = _theResult___fst_exp__h397737; + default: _theResult___fst_exp__h398331 = 8'd0; endcase end - always@(guard__h407308 or - _theResult___fst_exp__h415536 or - out_exp__h416055 or _theResult___exp__h416052) + always@(guard__h407275 or + _theResult___fst_exp__h415503 or + out_exp__h416022 or _theResult___exp__h416019) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - _theResult___fst_exp__h415536; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + _theResult___fst_exp__h415503; 2'b10: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - out_exp__h416055; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + out_exp__h416022; 2'b11: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - _theResult___exp__h416052; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + _theResult___exp__h416019; endcase end - always@(guard__h407308 or - _theResult___fst_exp__h415536 or _theResult___exp__h416052) + always@(guard__h407275 or + _theResult___fst_exp__h415503 or _theResult___exp__h416019) begin - case (guard__h407308) + case (guard__h407275) 2'b0: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 = - _theResult___fst_exp__h415536; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 = + _theResult___fst_exp__h415503; 2'b01, 2'b10, 2'b11: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 = - _theResult___exp__h416052; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 = + _theResult___exp__h416019; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 or - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 or + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 or + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h415536) + _theResult___fst_exp__h415503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h416130 = - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75; + _theResult___fst_exp__h416097 = + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75; 3'd1: - _theResult___fst_exp__h416130 = - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76; + _theResult___fst_exp__h416097 = + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76; 3'd2: - _theResult___fst_exp__h416130 = + _theResult___fst_exp__h416097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h416130 = + _theResult___fst_exp__h416097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h416130 = _theResult___fst_exp__h415536; - default: _theResult___fst_exp__h416130 = 8'd0; + 3'd4: _theResult___fst_exp__h416097 = _theResult___fst_exp__h415503; + default: _theResult___fst_exp__h416097 = 8'd0; endcase end - always@(guard__h416144 or - _theResult___fst_exp__h424221 or - out_exp__h424691 or _theResult___exp__h424688) + always@(guard__h416111 or + _theResult___fst_exp__h424188 or + out_exp__h424658 or _theResult___exp__h424655) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - _theResult___fst_exp__h424221; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + _theResult___fst_exp__h424188; 2'b10: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - out_exp__h424691; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + out_exp__h424658; 2'b11: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - _theResult___exp__h424688; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + _theResult___exp__h424655; endcase end - always@(guard__h416144 or - _theResult___fst_exp__h424221 or _theResult___exp__h424688) + always@(guard__h416111 or + _theResult___fst_exp__h424188 or _theResult___exp__h424655) begin - case (guard__h416144) + case (guard__h416111) 2'b0: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 = - _theResult___fst_exp__h424221; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 = + _theResult___fst_exp__h424188; 2'b01, 2'b10, 2'b11: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 = - _theResult___exp__h424688; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 = + _theResult___exp__h424655; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 or - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 or + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 or + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h424221) + _theResult___fst_exp__h424188) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424766 = - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80; + _theResult___fst_exp__h424733 = + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80; 3'd1: - _theResult___fst_exp__h424766 = - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81; + _theResult___fst_exp__h424733 = + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81; 3'd2: - _theResult___fst_exp__h424766 = + _theResult___fst_exp__h424733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424766 = + _theResult___fst_exp__h424733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424766 = _theResult___fst_exp__h424221; - default: _theResult___fst_exp__h424766 = 8'd0; + 3'd4: _theResult___fst_exp__h424733 = _theResult___fst_exp__h424188; + default: _theResult___fst_exp__h424733 = 8'd0; endcase end - always@(guard__h389671 or - sfdin__h397764 or out_sfd__h398290 or _theResult___sfd__h398287) + always@(guard__h398345 or + _theResult___snd__h406344 or + out_sfd__h406839 or _theResult___sfd__h406836) begin - case (guard__h389671) + case (guard__h398345) 2'b0, 2'b01: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - sfdin__h397764[56:34]; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + _theResult___snd__h406344[56:34]; 2'b10: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h398290; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + out_sfd__h406839; 2'b11: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h398287; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + _theResult___sfd__h406836; endcase end - always@(guard__h389671 or sfdin__h397764 or _theResult___sfd__h398287) + always@(guard__h398345 or + _theResult___snd__h406344 or _theResult___sfd__h406836) begin - case (guard__h389671) + case (guard__h398345) 2'b0: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 = - sfdin__h397764[56:34]; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 = + _theResult___snd__h406344[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h398287; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 = + _theResult___sfd__h406836; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 or - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397764) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h398365 = - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h398365 = - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h398365 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; - 3'd3: - _theResult___fst_sfd__h398365 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h398365 = sfdin__h397764[56:34]; - default: _theResult___fst_sfd__h398365 = 23'd0; - endcase - end - always@(guard__h398378 or - _theResult___snd__h406377 or - out_sfd__h406872 or _theResult___sfd__h406869) - begin - case (guard__h398378) - 2'b0, 2'b01: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - _theResult___snd__h406377[56:34]; - 2'b10: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - out_sfd__h406872; - 2'b11: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - _theResult___sfd__h406869; - endcase - end - always@(guard__h398378 or - _theResult___snd__h406377 or _theResult___sfd__h406869) - begin - case (guard__h398378) - 2'b0: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 = - _theResult___snd__h406377[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 = - _theResult___sfd__h406869; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 or - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 or + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 or + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h406377) + _theResult___snd__h406344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406947 = - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84; + _theResult___fst_sfd__h406914 = + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h406947 = - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85; + _theResult___fst_sfd__h406914 = + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h406947 = + _theResult___fst_sfd__h406914 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406947 = + _theResult___fst_sfd__h406914 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406947 = _theResult___snd__h406377[56:34]; - default: _theResult___fst_sfd__h406947 = 23'd0; + 3'd4: _theResult___fst_sfd__h406914 = _theResult___snd__h406344[56:34]; + default: _theResult___fst_sfd__h406914 = 23'd0; endcase end - always@(guard__h407308 or - sfdin__h415530 or out_sfd__h416056 or _theResult___sfd__h416053) + always@(guard__h389638 or + sfdin__h397731 or out_sfd__h398257 or _theResult___sfd__h398254) begin - case (guard__h407308) + case (guard__h389638) 2'b0, 2'b01: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - sfdin__h415530[56:34]; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + sfdin__h397731[56:34]; 2'b10: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h416056; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h398257; 2'b11: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h416053; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h398254; endcase end - always@(guard__h407308 or sfdin__h415530 or _theResult___sfd__h416053) + always@(guard__h389638 or sfdin__h397731 or _theResult___sfd__h398254) begin - case (guard__h407308) + case (guard__h389638) 2'b0: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 = - sfdin__h415530[56:34]; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 = + sfdin__h397731[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h416053; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h398254; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 or - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 or + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 or + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or + sfdin__h397731) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h398332 = + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h398332 = + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h398332 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; + 3'd3: + _theResult___fst_sfd__h398332 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; + 3'd4: _theResult___fst_sfd__h398332 = sfdin__h397731[56:34]; + default: _theResult___fst_sfd__h398332 = 23'd0; + endcase + end + always@(guard__h407275 or + sfdin__h415497 or out_sfd__h416023 or _theResult___sfd__h416020) + begin + case (guard__h407275) + 2'b0, 2'b01: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + sfdin__h415497[56:34]; + 2'b10: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h416023; + 2'b11: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h416020; + endcase + end + always@(guard__h407275 or sfdin__h415497 or _theResult___sfd__h416020) + begin + case (guard__h407275) + 2'b0: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 = + sfdin__h415497[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h416020; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 or + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h415530) + sfdin__h415497) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h416131 = - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h416098 = + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h416131 = - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h416098 = + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h416131 = + _theResult___fst_sfd__h416098 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h416131 = + _theResult___fst_sfd__h416098 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h416131 = sfdin__h415530[56:34]; - default: _theResult___fst_sfd__h416131 = 23'd0; + 3'd4: _theResult___fst_sfd__h416098 = sfdin__h415497[56:34]; + default: _theResult___fst_sfd__h416098 = 23'd0; endcase end - always@(guard__h416144 or - _theResult___snd__h424167 or - out_sfd__h424692 or _theResult___sfd__h424689) + always@(guard__h416111 or + _theResult___snd__h424134 or + out_sfd__h424659 or _theResult___sfd__h424656) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - _theResult___snd__h424167[56:34]; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + _theResult___snd__h424134[56:34]; 2'b10: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - out_sfd__h424692; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + out_sfd__h424659; 2'b11: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - _theResult___sfd__h424689; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + _theResult___sfd__h424656; endcase end - always@(guard__h416144 or - _theResult___snd__h424167 or _theResult___sfd__h424689) + always@(guard__h416111 or + _theResult___snd__h424134 or _theResult___sfd__h424656) begin - case (guard__h416144) + case (guard__h416111) 2'b0: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 = - _theResult___snd__h424167[56:34]; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 = + _theResult___snd__h424134[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 = - _theResult___sfd__h424689; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 = + _theResult___sfd__h424656; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 or - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 or + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 or + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h424167) + _theResult___snd__h424134) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424767 = - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88; + _theResult___fst_sfd__h424734 = + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h424767 = - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89; + _theResult___fst_sfd__h424734 = + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h424767 = + _theResult___fst_sfd__h424734 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424767 = + _theResult___fst_sfd__h424734 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424767 = _theResult___snd__h424167[56:34]; - default: _theResult___fst_sfd__h424767 = 23'd0; + 3'd4: _theResult___fst_sfd__h424734 = _theResult___snd__h424134[56:34]; + default: _theResult___fst_sfd__h424734 = 23'd0; endcase end - always@(guard__h389671 or + always@(guard__h389638 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389671) + case (guard__h389638) 2'b0, 2'b01, 2'b10: - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h389671 == 2'b11 && + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h389638 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h389671) + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h389638) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389671 == 2'b0) ? + (guard__h389638 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389671 == 2'b01 || guard__h389671 == 2'b10 || - guard__h389671 == 2'b11) && + (guard__h389638 == 2'b01 || guard__h389638 == 2'b10 || + guard__h389638 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -33941,72 +33939,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h398378 or + always@(guard__h389638 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h398378) + case (guard__h389638) 2'b0, 2'b01, 2'b10: - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - guard__h398378 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or - guard__h398378) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h398378 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h398378 == 2'b01 || guard__h398378 == 2'b10 || - guard__h398378 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h389671 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h389671) - 2'b0, 2'b01, 2'b10: - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - guard__h389671 != 2'b11 || + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h389638 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or - guard__h389671) + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h389638) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389671 == 2'b0) ? + (guard__h389638 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389671 != 2'b01 && guard__h389671 != 2'b10 && - guard__h389671 != 2'b11 || + guard__h389638 != 2'b01 && guard__h389638 != 2'b10 && + guard__h389638 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -34017,34 +33977,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h398378 or + always@(guard__h398345 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h398378) + case (guard__h398345) 2'b0, 2'b01, 2'b10: - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h398345 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h398345) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + (guard__h398345 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + (guard__h398345 == 2'b01 || guard__h398345 == 2'b10 || + guard__h398345 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h398345 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h398345) + 2'b0, 2'b01, 2'b10: + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h398378 != 2'b11 || + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h398345 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h398378) + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h398345) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h398378 == 2'b0) ? + (guard__h398345 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h398378 != 2'b01 && guard__h398378 != 2'b10 && - guard__h398378 != 2'b11 || + guard__h398345 != 2'b01 && guard__h398345 != 2'b10 && + guard__h398345 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -34055,34 +34053,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h407308 or + always@(guard__h407275 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01, 2'b10: - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h407308 == 2'b11 && + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h407275 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h407308) + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h407275) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h407308 == 2'b0) ? + (guard__h407275 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h407308 == 2'b01 || guard__h407308 == 2'b10 || - guard__h407308 == 2'b11) && + (guard__h407275 == 2'b01 || guard__h407275 == 2'b10 || + guard__h407275 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -34093,34 +34091,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h407308 or + always@(guard__h407275 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01, 2'b10: - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h407308 != 2'b11 || + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h407275 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h407308) + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h407275) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h407308 == 2'b0) ? + (guard__h407275 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h407308 != 2'b01 && guard__h407308 != 2'b10 && - guard__h407308 != 2'b11 || + guard__h407275 != 2'b01 && guard__h407275 != 2'b10 && + guard__h407275 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -34131,34 +34129,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h416144 or + always@(guard__h416111 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01, 2'b10: - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h416144 == 2'b11 && + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h416111 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h416144) + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h416111) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h416144 == 2'b0) ? + (guard__h416111 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h416144 == 2'b01 || guard__h416144 == 2'b10 || - guard__h416144 == 2'b11) && + (guard__h416111 == 2'b01 || guard__h416111 == 2'b10 || + guard__h416111 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -34169,34 +34167,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h416144 or + always@(guard__h416111 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01, 2'b10: - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h416144 != 2'b11 || + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h416111 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h416144) + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h416111) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h416144 == 2'b0) ? + (guard__h416111 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h416144 != 2'b01 && guard__h416144 != 2'b10 && - guard__h416144 != 2'b11 || + guard__h416111 != 2'b01 && guard__h416111 != 2'b10 && + guard__h416111 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -34233,484 +34231,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h444073 or - _theResult___fst_exp__h452121 or - out_exp__h452566 or _theResult___exp__h452563) + always@(guard__h444040 or + _theResult___fst_exp__h452088 or + out_exp__h452533 or _theResult___exp__h452530) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - _theResult___fst_exp__h452121; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + _theResult___fst_exp__h452088; 2'b10: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - out_exp__h452566; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + out_exp__h452533; 2'b11: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - _theResult___exp__h452563; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + _theResult___exp__h452530; endcase end - always@(guard__h444073 or - _theResult___fst_exp__h452121 or _theResult___exp__h452563) + always@(guard__h444040 or + _theResult___fst_exp__h452088 or _theResult___exp__h452530) begin - case (guard__h444073) + case (guard__h444040) 2'b0: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 = - _theResult___fst_exp__h452121; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 = + _theResult___fst_exp__h452088; 2'b01, 2'b10, 2'b11: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 = - _theResult___exp__h452563; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 = + _theResult___exp__h452530; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 or - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 or + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 or + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h452121) + _theResult___fst_exp__h452088) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h452641 = - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102; + _theResult___fst_exp__h452608 = + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102; 3'd1: - _theResult___fst_exp__h452641 = - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103; + _theResult___fst_exp__h452608 = + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103; 3'd2: - _theResult___fst_exp__h452641 = + _theResult___fst_exp__h452608 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h452641 = + _theResult___fst_exp__h452608 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h452641 = _theResult___fst_exp__h452121; - default: _theResult___fst_exp__h452641 = 8'd0; + 3'd4: _theResult___fst_exp__h452608 = _theResult___fst_exp__h452088; + default: _theResult___fst_exp__h452608 = 8'd0; endcase end - always@(guard__h435366 or - _theResult___fst_exp__h443465 or - out_exp__h443984 or _theResult___exp__h443981) + always@(guard__h435333 or + _theResult___fst_exp__h443432 or + out_exp__h443951 or _theResult___exp__h443948) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - _theResult___fst_exp__h443465; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + _theResult___fst_exp__h443432; 2'b10: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - out_exp__h443984; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + out_exp__h443951; 2'b11: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - _theResult___exp__h443981; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + _theResult___exp__h443948; endcase end - always@(guard__h435366 or - _theResult___fst_exp__h443465 or _theResult___exp__h443981) + always@(guard__h435333 or + _theResult___fst_exp__h443432 or _theResult___exp__h443948) begin - case (guard__h435366) + case (guard__h435333) 2'b0: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 = - _theResult___fst_exp__h443465; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 = + _theResult___fst_exp__h443432; 2'b01, 2'b10, 2'b11: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 = - _theResult___exp__h443981; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 = + _theResult___exp__h443948; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 or - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 or + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 or + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h443465) + _theResult___fst_exp__h443432) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h444059 = - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104; + _theResult___fst_exp__h444026 = + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104; 3'd1: - _theResult___fst_exp__h444059 = - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105; + _theResult___fst_exp__h444026 = + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105; 3'd2: - _theResult___fst_exp__h444059 = + _theResult___fst_exp__h444026 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h444059 = + _theResult___fst_exp__h444026 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h444059 = _theResult___fst_exp__h443465; - default: _theResult___fst_exp__h444059 = 8'd0; + 3'd4: _theResult___fst_exp__h444026 = _theResult___fst_exp__h443432; + default: _theResult___fst_exp__h444026 = 8'd0; endcase end - always@(guard__h453003 or - _theResult___fst_exp__h461231 or - out_exp__h461750 or _theResult___exp__h461747) + always@(guard__h452970 or + _theResult___fst_exp__h461198 or + out_exp__h461717 or _theResult___exp__h461714) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - _theResult___fst_exp__h461231; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + _theResult___fst_exp__h461198; 2'b10: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - out_exp__h461750; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + out_exp__h461717; 2'b11: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - _theResult___exp__h461747; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + _theResult___exp__h461714; endcase end - always@(guard__h453003 or - _theResult___fst_exp__h461231 or _theResult___exp__h461747) + always@(guard__h452970 or + _theResult___fst_exp__h461198 or _theResult___exp__h461714) begin - case (guard__h453003) + case (guard__h452970) 2'b0: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 = - _theResult___fst_exp__h461231; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 = + _theResult___fst_exp__h461198; 2'b01, 2'b10, 2'b11: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 = - _theResult___exp__h461747; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 = + _theResult___exp__h461714; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 or - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 or + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 or + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h461231) + _theResult___fst_exp__h461198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461825 = - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110; + _theResult___fst_exp__h461792 = + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110; 3'd1: - _theResult___fst_exp__h461825 = - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111; + _theResult___fst_exp__h461792 = + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111; 3'd2: - _theResult___fst_exp__h461825 = + _theResult___fst_exp__h461792 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461825 = + _theResult___fst_exp__h461792 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461825 = _theResult___fst_exp__h461231; - default: _theResult___fst_exp__h461825 = 8'd0; + 3'd4: _theResult___fst_exp__h461792 = _theResult___fst_exp__h461198; + default: _theResult___fst_exp__h461792 = 8'd0; endcase end - always@(guard__h461839 or - _theResult___fst_exp__h469916 or - out_exp__h470386 or _theResult___exp__h470383) + always@(guard__h461806 or + _theResult___fst_exp__h469883 or + out_exp__h470353 or _theResult___exp__h470350) begin - case (guard__h461839) + case (guard__h461806) 2'b0, 2'b01: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - _theResult___fst_exp__h469916; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + _theResult___fst_exp__h469883; 2'b10: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - out_exp__h470386; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + out_exp__h470353; 2'b11: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - _theResult___exp__h470383; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + _theResult___exp__h470350; endcase end - always@(guard__h461839 or - _theResult___fst_exp__h469916 or _theResult___exp__h470383) + always@(guard__h461806 or + _theResult___fst_exp__h469883 or _theResult___exp__h470350) begin - case (guard__h461839) + case (guard__h461806) 2'b0: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 = - _theResult___fst_exp__h469916; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 = + _theResult___fst_exp__h469883; 2'b01, 2'b10, 2'b11: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 = - _theResult___exp__h470383; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 = + _theResult___exp__h470350; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 or - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 or + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 or + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469916) + _theResult___fst_exp__h469883) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h470461 = - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115; + _theResult___fst_exp__h470428 = + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115; 3'd1: - _theResult___fst_exp__h470461 = - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116; + _theResult___fst_exp__h470428 = + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116; 3'd2: - _theResult___fst_exp__h470461 = + _theResult___fst_exp__h470428 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h470461 = + _theResult___fst_exp__h470428 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h470461 = _theResult___fst_exp__h469916; - default: _theResult___fst_exp__h470461 = 8'd0; + 3'd4: _theResult___fst_exp__h470428 = _theResult___fst_exp__h469883; + default: _theResult___fst_exp__h470428 = 8'd0; endcase end - always@(guard__h444073 or - _theResult___snd__h452072 or - out_sfd__h452567 or _theResult___sfd__h452564) + always@(guard__h444040 or + _theResult___snd__h452039 or + out_sfd__h452534 or _theResult___sfd__h452531) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - _theResult___snd__h452072[56:34]; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + _theResult___snd__h452039[56:34]; 2'b10: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - out_sfd__h452567; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + out_sfd__h452534; 2'b11: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - _theResult___sfd__h452564; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + _theResult___sfd__h452531; endcase end - always@(guard__h444073 or - _theResult___snd__h452072 or _theResult___sfd__h452564) + always@(guard__h444040 or + _theResult___snd__h452039 or _theResult___sfd__h452531) begin - case (guard__h444073) + case (guard__h444040) 2'b0: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 = - _theResult___snd__h452072[56:34]; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 = + _theResult___snd__h452039[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 = - _theResult___sfd__h452564; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 = + _theResult___sfd__h452531; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 or - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 or + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 or + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h452072) + _theResult___snd__h452039) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h452642 = - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117; + _theResult___fst_sfd__h452609 = + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h452642 = - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118; + _theResult___fst_sfd__h452609 = + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h452642 = + _theResult___fst_sfd__h452609 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h452642 = + _theResult___fst_sfd__h452609 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h452642 = _theResult___snd__h452072[56:34]; - default: _theResult___fst_sfd__h452642 = 23'd0; + 3'd4: _theResult___fst_sfd__h452609 = _theResult___snd__h452039[56:34]; + default: _theResult___fst_sfd__h452609 = 23'd0; endcase end - always@(guard__h435366 or - sfdin__h443459 or out_sfd__h443985 or _theResult___sfd__h443982) + always@(guard__h435333 or + sfdin__h443426 or out_sfd__h443952 or _theResult___sfd__h443949) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - sfdin__h443459[56:34]; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + sfdin__h443426[56:34]; 2'b10: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h443985; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h443952; 2'b11: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h443982; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h443949; endcase end - always@(guard__h435366 or sfdin__h443459 or _theResult___sfd__h443982) + always@(guard__h435333 or sfdin__h443426 or _theResult___sfd__h443949) begin - case (guard__h435366) + case (guard__h435333) 2'b0: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 = - sfdin__h443459[56:34]; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 = + sfdin__h443426[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h443982; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h443949; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 or - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 or + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 or + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h443459) + sfdin__h443426) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h444060 = - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h444027 = + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h444060 = - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h444027 = + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h444060 = + _theResult___fst_sfd__h444027 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h444060 = + _theResult___fst_sfd__h444027 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h444060 = sfdin__h443459[56:34]; - default: _theResult___fst_sfd__h444060 = 23'd0; + 3'd4: _theResult___fst_sfd__h444027 = sfdin__h443426[56:34]; + default: _theResult___fst_sfd__h444027 = 23'd0; endcase end - always@(guard__h453003 or - sfdin__h461225 or out_sfd__h461751 or _theResult___sfd__h461748) + always@(guard__h452970 or + sfdin__h461192 or out_sfd__h461718 or _theResult___sfd__h461715) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - sfdin__h461225[56:34]; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + sfdin__h461192[56:34]; 2'b10: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h461751; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h461718; 2'b11: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h461748; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h461715; endcase end - always@(guard__h453003 or sfdin__h461225 or _theResult___sfd__h461748) + always@(guard__h452970 or sfdin__h461192 or _theResult___sfd__h461715) begin - case (guard__h453003) + case (guard__h452970) 2'b0: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 = - sfdin__h461225[56:34]; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 = + sfdin__h461192[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h461748; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h461715; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 or - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 or + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 or + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h461225) + sfdin__h461192) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461826 = - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h461793 = + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h461826 = - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h461793 = + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h461826 = + _theResult___fst_sfd__h461793 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461826 = + _theResult___fst_sfd__h461793 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461826 = sfdin__h461225[56:34]; - default: _theResult___fst_sfd__h461826 = 23'd0; + 3'd4: _theResult___fst_sfd__h461793 = sfdin__h461192[56:34]; + default: _theResult___fst_sfd__h461793 = 23'd0; endcase end - always@(guard__h461839 or - _theResult___snd__h469862 or - out_sfd__h470387 or _theResult___sfd__h470384) + always@(guard__h461806 or + _theResult___snd__h469829 or + out_sfd__h470354 or _theResult___sfd__h470351) begin - case (guard__h461839) + case (guard__h461806) 2'b0, 2'b01: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - _theResult___snd__h469862[56:34]; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + _theResult___snd__h469829[56:34]; 2'b10: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - out_sfd__h470387; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + out_sfd__h470354; 2'b11: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - _theResult___sfd__h470384; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + _theResult___sfd__h470351; endcase end - always@(guard__h461839 or - _theResult___snd__h469862 or _theResult___sfd__h470384) + always@(guard__h461806 or + _theResult___snd__h469829 or _theResult___sfd__h470351) begin - case (guard__h461839) + case (guard__h461806) 2'b0: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 = - _theResult___snd__h469862[56:34]; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 = + _theResult___snd__h469829[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 = - _theResult___sfd__h470384; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 = + _theResult___sfd__h470351; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 or - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 or + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 or + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469862) + _theResult___snd__h469829) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h470462 = - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123; + _theResult___fst_sfd__h470429 = + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123; 3'd1: - _theResult___fst_sfd__h470462 = - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124; + _theResult___fst_sfd__h470429 = + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124; 3'd2: - _theResult___fst_sfd__h470462 = + _theResult___fst_sfd__h470429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h470462 = + _theResult___fst_sfd__h470429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h470462 = _theResult___snd__h469862[56:34]; - default: _theResult___fst_sfd__h470462 = 23'd0; + 3'd4: _theResult___fst_sfd__h470429 = _theResult___snd__h469829[56:34]; + default: _theResult___fst_sfd__h470429 = 23'd0; endcase end - always@(guard__h435366 or + always@(guard__h435333 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01, 2'b10: - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - guard__h435366 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or - guard__h435366) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h435366 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h435366 == 2'b01 || guard__h435366 == 2'b10 || - guard__h435366 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h435366 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h435366) - 2'b0, 2'b01, 2'b10: - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h435366 != 2'b11 || + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h435333 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h435366) + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h435333) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h435366 == 2'b0) ? + (guard__h435333 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h435366 != 2'b01 && guard__h435366 != 2'b10 && - guard__h435366 != 2'b11 || + guard__h435333 != 2'b01 && guard__h435333 != 2'b10 && + guard__h435333 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -34721,34 +34681,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h444073 or + always@(guard__h435333 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h444073) + case (guard__h435333) 2'b0, 2'b01, 2'b10: - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = - guard__h444073 == 2'b11 && + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h435333 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or - guard__h444073) + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h435333) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + (guard__h435333 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h435333 == 2'b01 || guard__h435333 == 2'b10 || + guard__h435333 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h444040 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h444040) + 2'b0, 2'b01, 2'b10: + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + guard__h444040 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + guard__h444040) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h444073 == 2'b0) ? + (guard__h444040 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h444073 == 2'b01 || guard__h444073 == 2'b10 || - guard__h444073 == 2'b11) && + (guard__h444040 == 2'b01 || guard__h444040 == 2'b10 || + guard__h444040 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -34759,34 +34757,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h444073 or + always@(guard__h444040 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01, 2'b10: - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h444073 != 2'b11 || + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h444040 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h444073) + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h444040) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h444073 == 2'b0) ? + (guard__h444040 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h444073 != 2'b01 && guard__h444073 != 2'b10 && - guard__h444073 != 2'b11 || + guard__h444040 != 2'b01 && guard__h444040 != 2'b10 && + guard__h444040 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -34797,34 +34795,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h453003 or + always@(guard__h452970 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01, 2'b10: - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h453003 == 2'b11 && + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h452970 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h453003) + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h452970) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h453003 == 2'b0) ? + (guard__h452970 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h453003 == 2'b01 || guard__h453003 == 2'b10 || - guard__h453003 == 2'b11) && + (guard__h452970 == 2'b01 || guard__h452970 == 2'b10 || + guard__h452970 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -34835,72 +34833,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h453003 or + always@(guard__h461806 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h453003) + case (guard__h461806) 2'b0, 2'b01, 2'b10: - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h453003 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h453003) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h453003 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h453003 != 2'b01 && guard__h453003 != 2'b10 && - guard__h453003 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h461839 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h461839) - 2'b0, 2'b01, 2'b10: - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h461839 == 2'b11 && + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + guard__h461806 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h461839) + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or + guard__h461806) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461839 == 2'b0) ? + (guard__h461806 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461839 == 2'b01 || guard__h461839 == 2'b10 || - guard__h461839 == 2'b11) && + (guard__h461806 == 2'b01 || guard__h461806 == 2'b10 || + guard__h461806 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -34911,34 +34871,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461839 or + always@(guard__h452970 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461839) + case (guard__h452970) 2'b0, 2'b01, 2'b10: - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h461839 != 2'b11 || + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + guard__h452970 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h461839) + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or + guard__h452970) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + (guard__h452970 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h452970 != 2'b01 && guard__h452970 != 2'b10 && + guard__h452970 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h461806 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h461806) + 2'b0, 2'b01, 2'b10: + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h461806 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h461806) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461839 == 2'b0) ? + (guard__h461806 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461839 != 2'b01 && guard__h461839 != 2'b10 && - guard__h461839 != 2'b11 || + guard__h461806 != 2'b01 && guard__h461806 != 2'b10 && + guard__h461806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -34995,28 +34993,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h491444 or - _theResult___fst_exp__h499405 or _theResult___exp__h500060) + always@(guard__h491411 or + _theResult___fst_exp__h499372 or _theResult___exp__h500027) begin - case (guard__h491444) + case (guard__h491411) 2'b0: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143 = - _theResult___fst_exp__h499405; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 = + _theResult___fst_exp__h499372; 2'b01, 2'b10, 2'b11: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143 = - _theResult___exp__h500060; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 = + _theResult___exp__h500027; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h499405 or + _theResult___fst_exp__h499372 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 or - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143) + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = - _theResult___fst_exp__h499405; + _theResult___fst_exp__h499372; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012; @@ -35025,44 +35023,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = 11'd0; endcase end - always@(guard__h491444 or - _theResult___fst_exp__h499405 or - out_exp__h500063 or _theResult___exp__h500060) + always@(guard__h491411 or + _theResult___fst_exp__h499372 or + out_exp__h500030 or _theResult___exp__h500027) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - _theResult___fst_exp__h499405; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + _theResult___fst_exp__h499372; 2'b10: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - out_exp__h500063; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + out_exp__h500030; 2'b11: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - _theResult___exp__h500060; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + _theResult___exp__h500027; endcase end - always@(guard__h491444 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h491411 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01, 2'b10: - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h491444 == 2'b11 && + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h491411 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491444) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491411) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35072,12 +35070,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h491444 == 2'b0) ? + (guard__h491411 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h491444 == 2'b01 || guard__h491444 == 2'b10 || - guard__h491444 == 2'b11) && + (guard__h491411 == 2'b01 || guard__h491411 == 2'b10 || + guard__h491411 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35088,23 +35086,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509825 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500723 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509825) + case (guard__h500723) 2'b0, 2'b01, 2'b10: - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h509825 == 2'b11 && + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h500723 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509825) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500723) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35114,12 +35112,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h509825 == 2'b0) ? + (guard__h500723 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509825 == 2'b01 || guard__h509825 == 2'b10 || - guard__h509825 == 2'b11) && + (guard__h500723 == 2'b01 || guard__h500723 == 2'b10 || + guard__h500723 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35130,23 +35128,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500756 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500756) + case (guard__h509792) 2'b0, 2'b01, 2'b10: - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h500756 == 2'b11 && + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h509792 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500756) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35156,12 +35154,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h500756 == 2'b0) ? + (guard__h509792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500756 == 2'b01 || guard__h500756 == 2'b10 || - guard__h500756 == 2'b11) && + (guard__h509792 == 2'b01 || guard__h509792 == 2'b10 || + guard__h509792 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35172,28 +35170,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h569601 or - _theResult___fst_exp__h577562 or _theResult___exp__h578217) + always@(guard__h569568 or + _theResult___fst_exp__h577529 or _theResult___exp__h578184) begin - case (guard__h569601) + case (guard__h569568) 2'b0: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160 = - _theResult___fst_exp__h577562; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 = + _theResult___fst_exp__h577529; 2'b01, 2'b10, 2'b11: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160 = - _theResult___exp__h578217; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 = + _theResult___exp__h578184; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h577562 or + _theResult___fst_exp__h577529 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 or - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160) + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = - _theResult___fst_exp__h577562; + _theResult___fst_exp__h577529; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727; @@ -35202,42 +35200,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = 11'd0; endcase end - always@(guard__h569601 or - _theResult___fst_exp__h577562 or - out_exp__h578220 or _theResult___exp__h578217) + always@(guard__h569568 or + _theResult___fst_exp__h577529 or + out_exp__h578187 or _theResult___exp__h578184) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - _theResult___fst_exp__h577562; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + _theResult___fst_exp__h577529; 2'b10: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - out_exp__h578220; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + out_exp__h578187; 2'b11: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - _theResult___exp__h578217; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + _theResult___exp__h578184; endcase end - always@(guard__h569601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h569601) + case (guard__h578880) 2'b0, 2'b01, 2'b10: - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h569601 == 2'b11 && + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h578880 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35246,12 +35244,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h569601 == 2'b0) ? + (guard__h578880 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h569601 == 2'b01 || guard__h569601 == 2'b10 || - guard__h569601 == 2'b11) && + (guard__h578880 == 2'b01 || guard__h578880 == 2'b10 || + guard__h578880 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35262,21 +35260,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578913) + case (guard__h569568) 2'b0, 2'b01, 2'b10: - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h578913 == 2'b11 && + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h569568 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35285,12 +35283,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h578913 == 2'b0) ? + (guard__h569568 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578913 == 2'b01 || guard__h578913 == 2'b10 || - guard__h578913 == 2'b11) && + (guard__h569568 == 2'b01 || guard__h569568 == 2'b10 || + guard__h569568 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35301,21 +35299,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01, 2'b10: - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h587982 == 2'b11 && + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h587949 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35324,12 +35322,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h587982 == 2'b0) ? + (guard__h587949 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587982 == 2'b01 || guard__h587982 == 2'b10 || - guard__h587982 == 2'b11) && + (guard__h587949 == 2'b01 || guard__h587949 == 2'b10 || + guard__h587949 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35340,21 +35338,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578913) + case (guard__h578880) 2'b0, 2'b01, 2'b10: - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h578913 != 2'b11 || + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h578880 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35363,12 +35361,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h578913 == 2'b0) ? + (guard__h578880 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578913 != 2'b01 && guard__h578913 != 2'b10 && - guard__h578913 != 2'b11 || + guard__h578880 != 2'b01 && guard__h578880 != 2'b10 && + guard__h578880 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35379,21 +35377,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01, 2'b10: - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h587982 != 2'b11 || + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h587949 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35402,12 +35400,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h587982 == 2'b0) ? + (guard__h587949 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587982 != 2'b01 && guard__h587982 != 2'b10 && - guard__h587982 != 2'b11 || + guard__h587949 != 2'b01 && guard__h587949 != 2'b10 && + guard__h587949 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35418,21 +35416,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h569601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01, 2'b10: - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h569601 != 2'b11 || + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h569568 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35441,12 +35439,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h569601 == 2'b0) ? + (guard__h569568 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h569601 != 2'b01 && guard__h569601 != 2'b10 && - guard__h569601 != 2'b11 || + guard__h569568 != 2'b01 && guard__h569568 != 2'b10 && + guard__h569568 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35457,28 +35455,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h530297 or - _theResult___fst_exp__h538258 or _theResult___exp__h538913) + always@(guard__h530264 or + _theResult___fst_exp__h538225 or _theResult___exp__h538880) begin - case (guard__h530297) + case (guard__h530264) 2'b0: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183 = - _theResult___fst_exp__h538258; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 = + _theResult___fst_exp__h538225; 2'b01, 2'b10, 2'b11: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183 = - _theResult___exp__h538913; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 = + _theResult___exp__h538880; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h538258 or + _theResult___fst_exp__h538225 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 or - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183) + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = - _theResult___fst_exp__h538258; + _theResult___fst_exp__h538225; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497; @@ -35487,49 +35485,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = 11'd0; endcase end - always@(guard__h530297 or - _theResult___fst_exp__h538258 or - out_exp__h538916 or _theResult___exp__h538913) + always@(guard__h530264 or + _theResult___fst_exp__h538225 or + out_exp__h538883 or _theResult___exp__h538880) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - _theResult___fst_exp__h538258; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + _theResult___fst_exp__h538225; 2'b10: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - out_exp__h538916; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + out_exp__h538883; 2'b11: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - _theResult___exp__h538913; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + _theResult___exp__h538880; endcase end - always@(guard__h539609 or - _theResult___fst_exp__h547835 or _theResult___exp__h548564) + always@(guard__h539576 or + _theResult___fst_exp__h547802 or _theResult___exp__h548531) begin - case (guard__h539609) + case (guard__h539576) 2'b0: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185 = - _theResult___fst_exp__h547835; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 = + _theResult___fst_exp__h547802; 2'b01, 2'b10, 2'b11: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185 = - _theResult___exp__h548564; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 = + _theResult___exp__h548531; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547835 or + _theResult___fst_exp__h547802 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 or - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185) + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = - _theResult___fst_exp__h547835; + _theResult___fst_exp__h547802; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535; @@ -35538,49 +35536,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = 11'd0; endcase end - always@(guard__h539609 or - _theResult___fst_exp__h547835 or - out_exp__h548567 or _theResult___exp__h548564) + always@(guard__h539576 or + _theResult___fst_exp__h547802 or + out_exp__h548534 or _theResult___exp__h548531) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - _theResult___fst_exp__h547835; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + _theResult___fst_exp__h547802; 2'b10: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - out_exp__h548567; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + out_exp__h548534; 2'b11: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - _theResult___exp__h548564; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + _theResult___exp__h548531; endcase end - always@(guard__h548678 or - _theResult___fst_exp__h556668 or _theResult___exp__h557348) + always@(guard__h548645 or + _theResult___fst_exp__h556635 or _theResult___exp__h557315) begin - case (guard__h548678) + case (guard__h548645) 2'b0: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187 = - _theResult___fst_exp__h556668; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 = + _theResult___fst_exp__h556635; 2'b01, 2'b10, 2'b11: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187 = - _theResult___exp__h557348; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 = + _theResult___exp__h557315; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h556668 or + _theResult___fst_exp__h556635 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 or - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187) + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = - _theResult___fst_exp__h556668; + _theResult___fst_exp__h556635; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566; @@ -35589,100 +35587,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = 11'd0; endcase end - always@(guard__h548678 or - _theResult___fst_exp__h556668 or - out_exp__h557351 or _theResult___exp__h557348) + always@(guard__h548645 or + _theResult___fst_exp__h556635 or + out_exp__h557318 or _theResult___exp__h557315) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - _theResult___fst_exp__h556668; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + _theResult___fst_exp__h556635; 2'b10: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - out_exp__h557351; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + out_exp__h557318; 2'b11: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - _theResult___exp__h557348; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + _theResult___exp__h557315; endcase end - always@(guard__h578913 or - _theResult___fst_exp__h587139 or _theResult___exp__h587868) + always@(guard__h587949 or + _theResult___fst_exp__h595939 or _theResult___exp__h596619) begin - case (guard__h578913) + case (guard__h587949) 2'b0: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189 = - _theResult___fst_exp__h587139; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 = + _theResult___fst_exp__h595939; 2'b01, 2'b10, 2'b11: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189 = - _theResult___exp__h587868; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 = + _theResult___exp__h596619; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h587139 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 or - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - _theResult___fst_exp__h587139; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - 11'd0; - endcase - end - always@(guard__h578913 or - _theResult___fst_exp__h587139 or - out_exp__h587871 or _theResult___exp__h587868) - begin - case (guard__h578913) - 2'b0, 2'b01: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - _theResult___fst_exp__h587139; - 2'b10: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - out_exp__h587871; - 2'b11: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - _theResult___exp__h587868; - endcase - end - always@(guard__h587982 or - _theResult___fst_exp__h595972 or _theResult___exp__h596652) - begin - case (guard__h587982) - 2'b0: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191 = - _theResult___fst_exp__h595972; - 2'b01, 2'b10, 2'b11: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191 = - _theResult___exp__h596652; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595972 or + _theResult___fst_exp__h595939 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 or - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191) + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = - _theResult___fst_exp__h595972; + _theResult___fst_exp__h595939; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796; @@ -35691,44 +35638,95 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = 11'd0; endcase end - always@(guard__h587982 or - _theResult___fst_exp__h595972 or - out_exp__h596655 or _theResult___exp__h596652) + always@(guard__h587949 or + _theResult___fst_exp__h595939 or + out_exp__h596622 or _theResult___exp__h596619) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - _theResult___fst_exp__h595972; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + _theResult___fst_exp__h595939; 2'b10: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - out_exp__h596655; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + out_exp__h596622; 2'b11: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - _theResult___exp__h596652; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + _theResult___exp__h596619; endcase end - always@(guard__h530297 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or + _theResult___fst_exp__h587106 or _theResult___exp__h587835) begin - case (guard__h530297) + case (guard__h578880) + 2'b0: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 = + _theResult___fst_exp__h587106; + 2'b01, 2'b10, 2'b11: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 = + _theResult___exp__h587835; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h587106 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 or + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + _theResult___fst_exp__h587106; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + 11'd0; + endcase + end + always@(guard__h578880 or + _theResult___fst_exp__h587106 or + out_exp__h587838 or _theResult___exp__h587835) + begin + case (guard__h578880) + 2'b0, 2'b01: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + _theResult___fst_exp__h587106; + 2'b10: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + out_exp__h587838; + 2'b11: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + _theResult___exp__h587835; + endcase + end + always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h530264) 2'b0, 2'b01, 2'b10: - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h530297 == 2'b11 && + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h530264 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530297) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35738,12 +35736,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h530297 == 2'b0) ? + (guard__h530264 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h530297 == 2'b01 || guard__h530297 == 2'b10 || - guard__h530297 == 2'b11) && + (guard__h530264 == 2'b01 || guard__h530264 == 2'b10 || + guard__h530264 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35754,23 +35752,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h548678 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h548678) + case (guard__h539576) 2'b0, 2'b01, 2'b10: - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h548678 == 2'b11 && + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h539576 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548678) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35780,12 +35778,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h548678 == 2'b0) ? + (guard__h539576 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h548678 == 2'b01 || guard__h548678 == 2'b10 || - guard__h548678 == 2'b11) && + (guard__h539576 == 2'b01 || guard__h539576 == 2'b10 || + guard__h539576 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35796,23 +35794,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h539609 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h539609) + case (guard__h548645) 2'b0, 2'b01, 2'b10: - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h539609 == 2'b11 && + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h548645 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539609) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35822,12 +35820,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h539609 == 2'b0) ? + (guard__h548645 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h539609 == 2'b01 || guard__h539609 == 2'b10 || - guard__h539609 == 2'b11) && + (guard__h548645 == 2'b01 || guard__h548645 == 2'b10 || + guard__h548645 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35838,23 +35836,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h539609 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01, 2'b10: - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h539609 != 2'b11 || + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h539576 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539609) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35864,12 +35862,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h539609 == 2'b0) ? + (guard__h539576 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h539609 != 2'b01 && guard__h539609 != 2'b10 && - guard__h539609 != 2'b11 || + guard__h539576 != 2'b01 && guard__h539576 != 2'b10 && + guard__h539576 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35880,23 +35878,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h548678 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01, 2'b10: - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h548678 != 2'b11 || + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h548645 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548678) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35906,12 +35904,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h548678 == 2'b0) ? + (guard__h548645 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h548678 != 2'b01 && guard__h548678 != 2'b10 && - guard__h548678 != 2'b11 || + guard__h548645 != 2'b01 && guard__h548645 != 2'b10 && + guard__h548645 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35922,23 +35920,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h530297 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01, 2'b10: - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h530297 != 2'b11 || + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h530264 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530297) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35948,12 +35946,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h530297 == 2'b0) ? + (guard__h530264 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h530297 != 2'b01 && guard__h530297 != 2'b10 && - guard__h530297 != 2'b11 || + guard__h530264 != 2'b01 && guard__h530264 != 2'b10 && + guard__h530264 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35964,28 +35962,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h530297 or - _theResult___snd__h538209 or _theResult___sfd__h538914) + always@(guard__h530264 or + _theResult___snd__h538176 or _theResult___sfd__h538881) begin - case (guard__h530297) + case (guard__h530264) 2'b0: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205 = - _theResult___snd__h538209[56:5]; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 = + _theResult___snd__h538176[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205 = - _theResult___sfd__h538914; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 = + _theResult___sfd__h538881; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h538209 or + _theResult___snd__h538176 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 or - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205) + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = - _theResult___snd__h538209[56:5]; + _theResult___snd__h538176[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592; @@ -35994,48 +35992,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = 52'd0; endcase end - always@(guard__h530297 or - _theResult___snd__h538209 or - out_sfd__h538917 or _theResult___sfd__h538914) + always@(guard__h530264 or + _theResult___snd__h538176 or + out_sfd__h538884 or _theResult___sfd__h538881) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - _theResult___snd__h538209[56:5]; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + _theResult___snd__h538176[56:5]; 2'b10: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - out_sfd__h538917; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + out_sfd__h538884; 2'b11: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - _theResult___sfd__h538914; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + _theResult___sfd__h538881; endcase end - always@(guard__h539609 or sfdin__h547829 or _theResult___sfd__h548565) + always@(guard__h539576 or sfdin__h547796 or _theResult___sfd__h548532) begin - case (guard__h539609) + case (guard__h539576) 2'b0: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h547829[56:5]; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h547796[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h548565; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h548532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547829 or + sfdin__h547796 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 or - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207) + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = - sfdin__h547829[56:5]; + sfdin__h547796[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618; @@ -36044,48 +36042,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = 52'd0; endcase end - always@(guard__h539609 or - sfdin__h547829 or out_sfd__h548568 or _theResult___sfd__h548565) + always@(guard__h539576 or + sfdin__h547796 or out_sfd__h548535 or _theResult___sfd__h548532) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h547829[56:5]; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h547796[56:5]; 2'b10: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h548568; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h548535; 2'b11: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h548565; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h548532; endcase end - always@(guard__h548678 or - _theResult___snd__h556614 or _theResult___sfd__h557349) + always@(guard__h548645 or + _theResult___snd__h556581 or _theResult___sfd__h557316) begin - case (guard__h548678) + case (guard__h548645) 2'b0: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209 = - _theResult___snd__h556614[56:5]; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 = + _theResult___snd__h556581[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209 = - _theResult___sfd__h557349; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 = + _theResult___sfd__h557316; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h556614 or + _theResult___snd__h556581 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 or - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209) + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = - _theResult___snd__h556614[56:5]; + _theResult___snd__h556581[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637; @@ -36094,49 +36092,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = 52'd0; endcase end - always@(guard__h548678 or - _theResult___snd__h556614 or - out_sfd__h557352 or _theResult___sfd__h557349) + always@(guard__h548645 or + _theResult___snd__h556581 or + out_sfd__h557319 or _theResult___sfd__h557316) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - _theResult___snd__h556614[56:5]; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + _theResult___snd__h556581[56:5]; 2'b10: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - out_sfd__h557352; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + out_sfd__h557319; 2'b11: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - _theResult___sfd__h557349; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + _theResult___sfd__h557316; endcase end - always@(guard__h500756 or - _theResult___fst_exp__h508982 or _theResult___exp__h509711) + always@(guard__h500723 or + _theResult___fst_exp__h508949 or _theResult___exp__h509678) begin - case (guard__h500756) + case (guard__h500723) 2'b0: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211 = - _theResult___fst_exp__h508982; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 = + _theResult___fst_exp__h508949; 2'b01, 2'b10, 2'b11: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211 = - _theResult___exp__h509711; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 = + _theResult___exp__h509678; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508982 or + _theResult___fst_exp__h508949 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 or - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211) + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = - _theResult___fst_exp__h508982; + _theResult___fst_exp__h508949; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055; @@ -36145,49 +36143,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = 11'd0; endcase end - always@(guard__h500756 or - _theResult___fst_exp__h508982 or - out_exp__h509714 or _theResult___exp__h509711) + always@(guard__h500723 or + _theResult___fst_exp__h508949 or + out_exp__h509681 or _theResult___exp__h509678) begin - case (guard__h500756) + case (guard__h500723) 2'b0, 2'b01: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - _theResult___fst_exp__h508982; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + _theResult___fst_exp__h508949; 2'b10: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - out_exp__h509714; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + out_exp__h509681; 2'b11: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - _theResult___exp__h509711; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + _theResult___exp__h509678; endcase end - always@(guard__h509825 or - _theResult___fst_exp__h517815 or _theResult___exp__h518495) + always@(guard__h509792 or + _theResult___fst_exp__h517782 or _theResult___exp__h518462) begin - case (guard__h509825) + case (guard__h509792) 2'b0: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213 = - _theResult___fst_exp__h517815; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 = + _theResult___fst_exp__h517782; 2'b01, 2'b10, 2'b11: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213 = - _theResult___exp__h518495; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 = + _theResult___exp__h518462; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517815 or + _theResult___fst_exp__h517782 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 or - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213) + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = - _theResult___fst_exp__h517815; + _theResult___fst_exp__h517782; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086; @@ -36196,49 +36194,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = 11'd0; endcase end - always@(guard__h509825 or - _theResult___fst_exp__h517815 or - out_exp__h518498 or _theResult___exp__h518495) + always@(guard__h509792 or + _theResult___fst_exp__h517782 or + out_exp__h518465 or _theResult___exp__h518462) begin - case (guard__h509825) + case (guard__h509792) 2'b0, 2'b01: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - _theResult___fst_exp__h517815; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + _theResult___fst_exp__h517782; 2'b10: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - out_exp__h518498; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + out_exp__h518465; 2'b11: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - _theResult___exp__h518495; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + _theResult___exp__h518462; endcase end - always@(guard__h491444 or - _theResult___snd__h499356 or _theResult___sfd__h500061) + always@(guard__h491411 or + _theResult___snd__h499323 or _theResult___sfd__h500028) begin - case (guard__h491444) + case (guard__h491411) 2'b0: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215 = - _theResult___snd__h499356[56:5]; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 = + _theResult___snd__h499323[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215 = - _theResult___sfd__h500061; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 = + _theResult___sfd__h500028; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h499356 or + _theResult___snd__h499323 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 or - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215) + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = - _theResult___snd__h499356[56:5]; + _theResult___snd__h499323[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112; @@ -36247,48 +36245,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = 52'd0; endcase end - always@(guard__h491444 or - _theResult___snd__h499356 or - out_sfd__h500064 or _theResult___sfd__h500061) + always@(guard__h491411 or + _theResult___snd__h499323 or + out_sfd__h500031 or _theResult___sfd__h500028) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - _theResult___snd__h499356[56:5]; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + _theResult___snd__h499323[56:5]; 2'b10: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - out_sfd__h500064; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + out_sfd__h500031; 2'b11: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - _theResult___sfd__h500061; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + _theResult___sfd__h500028; endcase end - always@(guard__h500756 or sfdin__h508976 or _theResult___sfd__h509712) + always@(guard__h500723 or sfdin__h508943 or _theResult___sfd__h509679) begin - case (guard__h500756) + case (guard__h500723) 2'b0: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h508976[56:5]; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h508943[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h509712; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h509679; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508976 or + sfdin__h508943 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 or - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217) + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = - sfdin__h508976[56:5]; + sfdin__h508943[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139; @@ -36297,48 +36295,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = 52'd0; endcase end - always@(guard__h500756 or - sfdin__h508976 or out_sfd__h509715 or _theResult___sfd__h509712) + always@(guard__h500723 or + sfdin__h508943 or out_sfd__h509682 or _theResult___sfd__h509679) begin - case (guard__h500756) + case (guard__h500723) 2'b0, 2'b01: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h508976[56:5]; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h508943[56:5]; 2'b10: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h509715; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h509682; 2'b11: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h509712; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h509679; endcase end - always@(guard__h509825 or - _theResult___snd__h517761 or _theResult___sfd__h518496) + always@(guard__h509792 or + _theResult___snd__h517728 or _theResult___sfd__h518463) begin - case (guard__h509825) + case (guard__h509792) 2'b0: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219 = - _theResult___snd__h517761[56:5]; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 = + _theResult___snd__h517728[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219 = - _theResult___sfd__h518496; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 = + _theResult___sfd__h518463; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517761 or + _theResult___snd__h517728 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 or - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219) + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = - _theResult___snd__h517761[56:5]; + _theResult___snd__h517728[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158; @@ -36347,49 +36345,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = 52'd0; endcase end - always@(guard__h509825 or - _theResult___snd__h517761 or - out_sfd__h518499 or _theResult___sfd__h518496) + always@(guard__h509792 or + _theResult___snd__h517728 or + out_sfd__h518466 or _theResult___sfd__h518463) begin - case (guard__h509825) + case (guard__h509792) 2'b0, 2'b01: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - _theResult___snd__h517761[56:5]; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + _theResult___snd__h517728[56:5]; 2'b10: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - out_sfd__h518499; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + out_sfd__h518466; 2'b11: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - _theResult___sfd__h518496; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + _theResult___sfd__h518463; endcase end - always@(guard__h569601 or - _theResult___snd__h577513 or _theResult___sfd__h578218) + always@(guard__h569568 or + _theResult___snd__h577480 or _theResult___sfd__h578185) begin - case (guard__h569601) + case (guard__h569568) 2'b0: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221 = - _theResult___snd__h577513[56:5]; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 = + _theResult___snd__h577480[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221 = - _theResult___sfd__h578218; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 = + _theResult___sfd__h578185; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h577513 or + _theResult___snd__h577480 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 or - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221) + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = - _theResult___snd__h577513[56:5]; + _theResult___snd__h577480[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822; @@ -36398,48 +36396,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = 52'd0; endcase end - always@(guard__h569601 or - _theResult___snd__h577513 or - out_sfd__h578221 or _theResult___sfd__h578218) + always@(guard__h569568 or + _theResult___snd__h577480 or + out_sfd__h578188 or _theResult___sfd__h578185) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - _theResult___snd__h577513[56:5]; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + _theResult___snd__h577480[56:5]; 2'b10: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - out_sfd__h578221; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + out_sfd__h578188; 2'b11: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - _theResult___sfd__h578218; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + _theResult___sfd__h578185; endcase end - always@(guard__h578913 or sfdin__h587133 or _theResult___sfd__h587869) + always@(guard__h578880 or sfdin__h587100 or _theResult___sfd__h587836) begin - case (guard__h578913) + case (guard__h578880) 2'b0: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h587133[56:5]; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h587100[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h587869; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h587836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h587133 or + sfdin__h587100 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 or - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223) + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = - sfdin__h587133[56:5]; + sfdin__h587100[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848; @@ -36448,24 +36446,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = 52'd0; endcase end - always@(guard__h578913 or - sfdin__h587133 or out_sfd__h587872 or _theResult___sfd__h587869) + always@(guard__h578880 or + sfdin__h587100 or out_sfd__h587839 or _theResult___sfd__h587836) begin - case (guard__h578913) + case (guard__h578880) 2'b0, 2'b01: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h587133[56:5]; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h587100[56:5]; 2'b10: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h587872; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h587839; 2'b11: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h587869; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h587836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36500,28 +36498,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849; endcase end - always@(guard__h587982 or - _theResult___snd__h595918 or _theResult___sfd__h596653) + always@(guard__h587949 or + _theResult___snd__h595885 or _theResult___sfd__h596620) begin - case (guard__h587982) + case (guard__h587949) 2'b0: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225 = - _theResult___snd__h595918[56:5]; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 = + _theResult___snd__h595885[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225 = - _theResult___sfd__h596653; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 = + _theResult___sfd__h596620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595918 or + _theResult___snd__h595885 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 or - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225) + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = - _theResult___snd__h595918[56:5]; + _theResult___snd__h595885[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867; @@ -36530,25 +36528,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = 52'd0; endcase end - always@(guard__h587982 or - _theResult___snd__h595918 or - out_sfd__h596656 or _theResult___sfd__h596653) + always@(guard__h587949 or + _theResult___snd__h595885 or + out_sfd__h596623 or _theResult___sfd__h596620) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - _theResult___snd__h595918[56:5]; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + _theResult___snd__h595885[56:5]; 2'b10: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - out_sfd__h596656; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + out_sfd__h596623; 2'b11: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - _theResult___sfd__h596653; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + _theResult___sfd__h596620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36794,9 +36792,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 = + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 = fetchStage$pipelines_0_first[172:161]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 = 12'd2303; endcase end @@ -36804,15 +36802,15 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[67:64]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = fetchStage$pipelines_0_first[67:64]; 4'd11: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd10; + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd10; 4'd12: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd11; + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd11; 4'd13: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd12; + default: IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd13; endcase end @@ -36830,41 +36828,41 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = fetchStage$pipelines_0_first[194:174]; 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = { fetchStage$pipelines_0_first[194:192], 9'h0AA, fetchStage$pipelines_0_first[182:178], CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, fetchStage$pipelines_0_first[174] }; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = 21'd1485482; endcase end - always@(checkForException___d12946) + always@(checkForException___d12942) begin - case (checkForException___d12946[3:0]) + case (checkForException___d12942[3:0]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = - checkForException___d12946[3:0]; - 4'd11: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10; - 4'd12: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11; - 4'd13: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12; - default: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = + CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = + checkForException___d12942[3:0]; + 4'd11: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10; + 4'd12: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11; + 4'd13: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12; + default: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd13; endcase end - always@(k__h664143 or + always@(k__h664083 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h664143) + case (k__h664083) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -36873,65 +36871,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end - always@(k__h664143 or + always@(k__h664083 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h664143) + case (k__h664083) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414 or + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410; 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; endcase end always@(fetchStage$pipelines_0_first or @@ -36939,32 +36937,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_1_first) @@ -37030,36 +37028,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = 21'd1485482; endcase end - always@(idx__h678765 or + always@(idx__h678705 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 or + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 or + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h678765) + case (idx__h678705) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37075,61 +37073,61 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765 or + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 || + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761; 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end always@(fetchStage$pipelines_1_first or @@ -37144,31 +37142,43 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 or - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777 or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819 or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 or + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 or + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801) + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773; 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659; + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655; + endcase + end + always@(k__h664083 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h664083) + 1'd0: + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + coreFix_aluExe_1_rsAlu$RDY_enq; endcase end always@(fetchStage$pipelines_0_first or @@ -37176,141 +37186,129 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = coreFix_memExe_lsq$RDY_enqSt; endcase end - always@(k__h664143 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h664143) - 1'd0: - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849 or + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849; + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end - always@(idx__h678765 or + always@(idx__h678705 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h678765) + case (idx__h678705) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939 or + always@(fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939) + case (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37326,79 +37324,79 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); - endcase - end - always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974) + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986; + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 or - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943 or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 or + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 || - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 || + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 || + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 || + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953; endcase end always@(fetchStage$pipelines_0_first or @@ -37406,9 +37404,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37417,9 +37415,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37428,9 +37426,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37439,9 +37437,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37450,9 +37448,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37461,9 +37459,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37472,9 +37470,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37483,9 +37481,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37519,86 +37517,86 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd0; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd1; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd2; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd8; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd9; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd10; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd11; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd12; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd13; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd14; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd15; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd16; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd17; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd18; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd19; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd20; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd21; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd22; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd23; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd24; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd25; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd26; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd27; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd28; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd29; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd29; 12'd1968: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd36; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd36; 12'd1969: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd37; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd37; 12'd1970: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd38; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd38; 12'd1971: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd39; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd39; 12'd2048: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd6; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd7; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd30; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd31; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd3; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd4; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd5; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd32; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd33; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd34; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd40; endcase end @@ -38970,7 +38968,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0; csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -39392,9 +39389,6 @@ module mkCore(CLK, if (csrInstOrInterruptInflight_rl$EN) csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY csrInstOrInterruptInflight_rl$D_IN; - if (csrf_debug_int_pend$EN) - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY - csrf_debug_int_pend$D_IN; if (csrf_external_int_en_vec_0$EN) csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_external_int_en_vec_0$D_IN; @@ -39833,7 +39827,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full = 1'h0; coreFix_memExe_waitLrScAmoMMIOResp = 3'h2; csrInstOrInterruptInflight_rl = 1'h0; - csrf_debug_int_pend = 1'h0; csrf_external_int_en_vec_0 = 1'h0; csrf_external_int_en_vec_1 = 1'h0; csrf_external_int_en_vec_3 = 1'h0; @@ -40217,7 +40210,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == 6'd6) + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -40329,7 +40322,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] != 5'd19 && rob$deqPort_1_deq_data[186:182] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - x__h712792, + x__h712697, rob$deqPort_1_deq_data[282:219], rob$deqPort_1_deq_data[218:187], " iType:"); @@ -40488,7 +40481,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h601760 == 2'd0) + v__h601727 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 76997ba..b23200e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -7,9 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const -// RDY_set_htif_addrs O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg +// RDY_start O 1 // cpu_imem_master_awvalid O 1 // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg @@ -22,7 +20,6 @@ // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg @@ -51,7 +48,6 @@ // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg // cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg @@ -68,19 +64,22 @@ // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg -// RDY_dm_dmi_read_addr O 1 -// dm_dmi_read_data O 32 -// RDY_dm_dmi_read_data O 1 -// RDY_dm_dmi_write O 1 -// RDY_dm_ndm_reset_req_get_get O 1 reg +// RDY_dmi_read_addr O 1 +// dmi_read_data O 32 +// RDY_dmi_read_data O 1 +// RDY_dmi_write O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg // tv_verifier_info_get_get O 608 reg // RDY_tv_verifier_info_get_get O 1 reg +// RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused -// set_htif_addrs_tohost_addr I 64 reg -// set_htif_addrs_fromhost_addr I 64 reg +// start_tohost_addr I 64 +// start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -119,26 +118,24 @@ // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 -// dm_dmi_read_addr_dm_addr I 7 -// dm_dmi_write_dm_addr I 7 -// dm_dmi_write_dm_word I 32 +// nmi_req_set_not_clear I 1 unused +// dmi_read_addr_dm_addr I 7 +// dmi_write_dm_addr I 7 +// dmi_write_dm_word I 32 +// ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 -// EN_set_htif_addrs I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// EN_dm_dmi_read_addr I 1 -// EN_dm_dmi_write I 1 -// EN_dm_ndm_reset_req_get_get I 1 -// EN_dm_dmi_read_data I 1 +// EN_start I 1 +// EN_dmi_read_addr I 1 +// EN_dmi_write I 1 +// EN_ndm_reset_client_response_put I 1 +// EN_dmi_read_data I 1 +// EN_ndm_reset_client_request_get I 1 // EN_tv_verifier_info_get_get I 1 // // Combinational paths from inputs to outputs: // (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data -// (dm_dmi_read_addr_dm_addr, -// EN_dm_dmi_read_addr, -// EN_dm_dmi_read_data) -> dm_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -155,7 +152,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkCoreW(CLK, +module mkCoreW(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -163,16 +161,10 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, - set_htif_addrs_tohost_addr, - set_htif_addrs_fromhost_addr, - EN_set_htif_addrs, - RDY_set_htif_addrs, - - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start, cpu_imem_master_awvalid, @@ -200,8 +192,6 @@ module mkCoreW(CLK, cpu_imem_master_wvalid, - cpu_imem_master_wid, - cpu_imem_master_wdata, cpu_imem_master_wstrb, @@ -274,8 +264,6 @@ module mkCoreW(CLK, cpu_dmem_master_wvalid, - cpu_dmem_master_wid, - cpu_dmem_master_wdata, cpu_dmem_master_wstrb, @@ -354,27 +342,33 @@ module mkCoreW(CLK, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, + nmi_req_set_not_clear, - dm_dmi_read_addr_dm_addr, - EN_dm_dmi_read_addr, - RDY_dm_dmi_read_addr, + dmi_read_addr_dm_addr, + EN_dmi_read_addr, + RDY_dmi_read_addr, - EN_dm_dmi_read_data, - dm_dmi_read_data, - RDY_dm_dmi_read_data, + EN_dmi_read_data, + dmi_read_data, + RDY_dmi_read_data, - dm_dmi_write_dm_addr, - dm_dmi_write_dm_word, - EN_dm_dmi_write, - RDY_dm_dmi_write, + dmi_write_dm_addr, + dmi_write_dm_word, + EN_dmi_write, + RDY_dmi_write, - EN_dm_ndm_reset_req_get_get, - RDY_dm_ndm_reset_req_get_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put, EN_tv_verifier_info_get_get, tv_verifier_info_get_get, RDY_tv_verifier_info_get_get); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -384,19 +378,11 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // action method set_htif_addrs - input [63 : 0] set_htif_addrs_tohost_addr; - input [63 : 0] set_htif_addrs_fromhost_addr; - input EN_set_htif_addrs; - output RDY_set_htif_addrs; - - // action method cpu_reset_server_request_put - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // action method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; @@ -439,9 +425,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; @@ -553,9 +536,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid output cpu_dmem_master_wvalid; - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - // value method cpu_dmem_master_m_wdata output [63 : 0] cpu_dmem_master_wdata; @@ -674,28 +654,34 @@ module mkCoreW(CLK, // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; + // action method nmi_req + input nmi_req_set_not_clear; - // action method dm_dmi_read_addr - input [6 : 0] dm_dmi_read_addr_dm_addr; - input EN_dm_dmi_read_addr; - output RDY_dm_dmi_read_addr; + // action method dmi_read_addr + input [6 : 0] dmi_read_addr_dm_addr; + input EN_dmi_read_addr; + output RDY_dmi_read_addr; - // actionvalue method dm_dmi_read_data - input EN_dm_dmi_read_data; - output [31 : 0] dm_dmi_read_data; - output RDY_dm_dmi_read_data; + // actionvalue method dmi_read_data + input EN_dmi_read_data; + output [31 : 0] dmi_read_data; + output RDY_dmi_read_data; - // action method dm_dmi_write - input [6 : 0] dm_dmi_write_dm_addr; - input [31 : 0] dm_dmi_write_dm_word; - input EN_dm_dmi_write; - output RDY_dm_dmi_write; + // action method dmi_write + input [6 : 0] dmi_write_dm_addr; + input [31 : 0] dmi_write_dm_word; + input EN_dmi_write; + output RDY_dmi_write; - // action method dm_ndm_reset_req_get_get - input EN_dm_ndm_reset_req_get_get; - output RDY_dm_ndm_reset_req_get_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // actionvalue method tv_verifier_info_get_get input EN_tv_verifier_info_get_get; @@ -710,7 +696,7 @@ module mkCoreW(CLK, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; - wire [31 : 0] dm_dmi_read_data; + wire [31 : 0] dmi_read_data; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, @@ -725,7 +711,6 @@ module mkCoreW(CLK, cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, - cpu_dmem_master_wid, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, @@ -733,8 +718,7 @@ module mkCoreW(CLK, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; + cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, @@ -747,14 +731,13 @@ module mkCoreW(CLK, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_dm_dmi_read_addr, - RDY_dm_dmi_read_data, - RDY_dm_dmi_write, - RDY_dm_ndm_reset_req_get_get, - RDY_set_htif_addrs, + wire RDY_dmi_read_addr, + RDY_dmi_read_data, + RDY_dmi_write, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_set_verbosity, + RDY_start, RDY_tv_verifier_info_get_get, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, @@ -771,13 +754,19 @@ module mkCoreW(CLK, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, - cpu_imem_master_wvalid; + cpu_imem_master_wvalid, + ndm_reset_client_request_get; // register rg_fromhost_addr reg [63 : 0] rg_fromhost_addr; wire [63 : 0] rg_fromhost_addr$D_IN; wire rg_fromhost_addr$EN; + // register rg_hart0_reset_delay + reg [7 : 0] rg_hart0_reset_delay; + wire [7 : 0] rg_hart0_reset_delay$D_IN; + wire rg_hart0_reset_delay$EN; + // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; @@ -809,8 +798,7 @@ module mkCoreW(CLK, debug_module$master_awqos, debug_module$master_awregion, debug_module$master_bid, - debug_module$master_rid, - debug_module$master_wid; + debug_module$master_rid; wire [2 : 0] debug_module$master_arprot, debug_module$master_arsize, debug_module$master_awprot, @@ -822,7 +810,6 @@ module mkCoreW(CLK, wire debug_module$EN_dmi_read_addr, debug_module$EN_dmi_read_data, debug_module$EN_dmi_write, - debug_module$EN_get_ndm_reset_req_get, debug_module$EN_hart0_client_run_halt_request_get, debug_module$EN_hart0_client_run_halt_response_put, debug_module$EN_hart0_csr_mem_client_request_get, @@ -830,23 +817,29 @@ module mkCoreW(CLK, debug_module$EN_hart0_fpr_mem_client_request_get, debug_module$EN_hart0_fpr_mem_client_response_put, debug_module$EN_hart0_get_other_req_get, - debug_module$EN_hart0_get_reset_req_get, debug_module$EN_hart0_gpr_mem_client_request_get, debug_module$EN_hart0_gpr_mem_client_response_put, + debug_module$EN_hart0_reset_client_request_get, + debug_module$EN_hart0_reset_client_response_put, + debug_module$EN_ndm_reset_client_request_get, + debug_module$EN_ndm_reset_client_response_put, debug_module$RDY_dmi_read_addr, debug_module$RDY_dmi_read_data, debug_module$RDY_dmi_write, - debug_module$RDY_get_ndm_reset_req_get, debug_module$RDY_hart0_client_run_halt_request_get, debug_module$RDY_hart0_client_run_halt_response_put, debug_module$RDY_hart0_csr_mem_client_request_get, debug_module$RDY_hart0_csr_mem_client_response_put, debug_module$RDY_hart0_get_other_req_get, - debug_module$RDY_hart0_get_reset_req_get, debug_module$RDY_hart0_gpr_mem_client_request_get, debug_module$RDY_hart0_gpr_mem_client_response_put, + debug_module$RDY_hart0_reset_client_request_get, + debug_module$RDY_hart0_reset_client_response_put, + debug_module$RDY_ndm_reset_client_request_get, + debug_module$RDY_ndm_reset_client_response_put, debug_module$hart0_client_run_halt_request_get, debug_module$hart0_client_run_halt_response_put, + debug_module$hart0_reset_client_response_put, debug_module$master_arlock, debug_module$master_arready, debug_module$master_arvalid, @@ -860,7 +853,9 @@ module mkCoreW(CLK, debug_module$master_rvalid, debug_module$master_wlast, debug_module$master_wready, - debug_module$master_wvalid; + debug_module$master_wvalid, + debug_module$ndm_reset_client_request_get, + debug_module$ndm_reset_client_response_put; // ports of submodule dm_csr_tap wire [426 : 0] dm_csr_tap$trace_data_out_get; @@ -895,6 +890,9 @@ module mkCoreW(CLK, dm_gpr_tap_ifc$RDY_server_response_get, dm_gpr_tap_ifc$RDY_trace_data_out_get; + // ports of submodule dm_hart0_reset_controller + wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST; + // ports of submodule dm_mem_tap wire [426 : 0] dm_mem_tap$trace_data_out_get; wire [63 : 0] dm_mem_tap$master_araddr, @@ -921,7 +919,6 @@ module mkCoreW(CLK, dm_mem_tap$master_awregion, dm_mem_tap$master_bid, dm_mem_tap$master_rid, - dm_mem_tap$master_wid, dm_mem_tap$slave_arcache, dm_mem_tap$slave_arid, dm_mem_tap$slave_arqos, @@ -931,8 +928,7 @@ module mkCoreW(CLK, dm_mem_tap$slave_awqos, dm_mem_tap$slave_awregion, dm_mem_tap$slave_bid, - dm_mem_tap$slave_rid, - dm_mem_tap$slave_wid; + dm_mem_tap$slave_rid; wire [2 : 0] dm_mem_tap$master_arprot, dm_mem_tap$master_arsize, dm_mem_tap$master_awprot, @@ -980,29 +976,6 @@ module mkCoreW(CLK, dm_mem_tap$slave_wready, dm_mem_tap$slave_wvalid; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_requestor - wire f_reset_requestor$CLR, - f_reset_requestor$DEQ, - f_reset_requestor$D_IN, - f_reset_requestor$D_OUT, - f_reset_requestor$EMPTY_N, - f_reset_requestor$ENQ, - f_reset_requestor$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, fabric_2x3$v_from_masters_0_awaddr, @@ -1050,7 +1023,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, @@ -1061,7 +1033,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_1_awregion, fabric_2x3$v_from_masters_1_bid, fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_from_masters_1_wid, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, @@ -1072,7 +1043,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, @@ -1083,7 +1053,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, @@ -1093,8 +1062,7 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; + fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, @@ -1137,7 +1105,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, @@ -1209,6 +1176,9 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_wready, fabric_2x3$v_to_slaves_2_wvalid; + // ports of submodule hart0_reset + wire hart0_reset$RST_OUT; + // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, @@ -1229,7 +1199,6 @@ module mkCoreW(CLK, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, - plic$axi4_slave_wid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1244,8 +1213,6 @@ module mkCoreW(CLK, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, @@ -1320,7 +1287,6 @@ module mkCoreW(CLK, proc$debug_module_mem_server_awregion, proc$debug_module_mem_server_bid, proc$debug_module_mem_server_rid, - proc$debug_module_mem_server_wid, proc$hart0_put_other_req_put, proc$master0_arcache, proc$master0_arid, @@ -1332,7 +1298,6 @@ module mkCoreW(CLK, proc$master0_awregion, proc$master0_bid, proc$master0_rid, - proc$master0_wid, proc$master1_arcache, proc$master1_arid, proc$master1_arqos, @@ -1343,7 +1308,6 @@ module mkCoreW(CLK, proc$master1_awregion, proc$master1_bid, proc$master1_rid, - proc$master1_wid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1378,8 +1342,6 @@ module mkCoreW(CLK, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, - proc$EN_hart0_server_reset_request_put, - proc$EN_hart0_server_reset_response_get, proc$EN_set_verbosity, proc$EN_start, proc$EN_v_to_TV_0_get, @@ -1390,12 +1352,9 @@ module mkCoreW(CLK, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, - proc$RDY_hart0_server_reset_request_put, - proc$RDY_hart0_server_reset_response_get, proc$RDY_start, proc$RDY_v_to_TV_0_get, proc$RDY_v_to_TV_1_get, - proc$debug_external_interrupt_req_set_not_clear, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, proc$debug_module_mem_server_arvalid, @@ -1462,7 +1421,6 @@ module mkCoreW(CLK, tv_encode$EN_v_cpu_in_1_put, tv_encode$RDY_dm_in_put, tv_encode$RDY_out_get, - tv_encode$RDY_reset, tv_encode$RDY_v_cpu_in_0_put, tv_encode$RDY_v_cpu_in_1_put; @@ -1514,9 +1472,8 @@ module mkCoreW(CLK, CAN_FIRE_RL_mkConnectionGetPut_2, CAN_FIRE_RL_mkConnectionGetPut_3, CAN_FIRE_RL_mkConnectionGetPut_4, - CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, + CAN_FIRE_RL_rl_dm_hart0_reset, + CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_merge_dm_csr_trace_data, CAN_FIRE_RL_rl_merge_dm_gpr_trace_data, CAN_FIRE_RL_rl_merge_dm_mem_trace_data, @@ -1531,7 +1488,6 @@ module mkCoreW(CLK, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_rd_data_channel_4, CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_non_maskable_interrupt, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, @@ -1575,15 +1531,14 @@ module mkCoreW(CLK, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_debug_external_interrupt_req, - CAN_FIRE_dm_dmi_read_addr, - CAN_FIRE_dm_dmi_read_data, - CAN_FIRE_dm_dmi_write, - CAN_FIRE_dm_ndm_reset_req_get_get, - CAN_FIRE_set_htif_addrs, + CAN_FIRE_dmi_read_addr, + CAN_FIRE_dmi_read_data, + CAN_FIRE_dmi_write, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, + CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, + CAN_FIRE_start, CAN_FIRE_tv_verifier_info_get_get, WILL_FIRE_RL_ClientServerRequest, WILL_FIRE_RL_ClientServerRequest_1, @@ -1600,9 +1555,8 @@ module mkCoreW(CLK, WILL_FIRE_RL_mkConnectionGetPut_2, WILL_FIRE_RL_mkConnectionGetPut_3, WILL_FIRE_RL_mkConnectionGetPut_4, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, + WILL_FIRE_RL_rl_dm_hart0_reset, + WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_merge_dm_csr_trace_data, WILL_FIRE_RL_rl_merge_dm_gpr_trace_data, WILL_FIRE_RL_rl_merge_dm_mem_trace_data, @@ -1617,7 +1571,6 @@ module mkCoreW(CLK, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_rd_data_channel_4, WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_non_maskable_interrupt, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, @@ -1661,64 +1614,54 @@ module mkCoreW(CLK, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_debug_external_interrupt_req, - WILL_FIRE_dm_dmi_read_addr, - WILL_FIRE_dm_dmi_read_data, - WILL_FIRE_dm_dmi_write, - WILL_FIRE_dm_ndm_reset_req_get_get, - WILL_FIRE_set_htif_addrs, + WILL_FIRE_dmi_read_addr, + WILL_FIRE_dmi_read_data, + WILL_FIRE_dmi_write, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, + WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, + WILL_FIRE_start, WILL_FIRE_tv_verifier_info_get_get; + // inputs to muxes for submodule ports + wire [7 : 0] MUX_rg_hart0_reset_delay$write_1__VAL_1; + wire MUX_proc$start_1__SEL_1; + // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h7205; - reg [31 : 0] v__h7403; - reg [31 : 0] v__h7674; - reg [31 : 0] v__h7199; - reg [31 : 0] v__h7397; - reg [31 : 0] v__h7668; + reg [31 : 0] v__h6860; + reg [31 : 0] v__h7003; + reg [31 : 0] v__h15013; + reg [31 : 0] v__h6854; + reg [31 : 0] v__h6997; + reg [31 : 0] v__h15007; // synopsys translate_on // remaining internal signals - reg [63 : 0] x__h5725, x__h6650; + reg [63 : 0] x__h5570, x__h6495; reg [11 : 0] CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1, - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5; - reg [4 : 0] CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6; + reg [4 : 0] CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5, CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10, - x1_avValue_rd__h5432, - x1_avValue_rd__h6363; + x1_avValue_rd__h5277, + x1_avValue_rd__h6208; reg [3 : 0] CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2, CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7; + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7, + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8; reg [1 : 0] CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4, - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8; - wire tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113; + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // action method set_htif_addrs - assign RDY_set_htif_addrs = 1'd1 ; - assign CAN_FIRE_set_htif_addrs = 1'd1 ; - assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // action method cpu_reset_server_response_get - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; + // action method start + assign RDY_start = proc$RDY_start ; + assign CAN_FIRE_start = proc$RDY_start ; + assign WILL_FIRE_start = EN_start ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = proc$master0_awvalid ; @@ -1760,9 +1703,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = proc$master0_wvalid ; - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = proc$master0_wid ; - // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = proc$master0_wdata ; @@ -1867,9 +1807,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - // value method cpu_dmem_master_m_wdata assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; @@ -1998,32 +1935,43 @@ module mkCoreW(CLK, assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method nmi_req + assign CAN_FIRE_nmi_req = 1'd1 ; + assign WILL_FIRE_nmi_req = 1'd1 ; - // action method dm_dmi_read_addr - assign RDY_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign CAN_FIRE_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign WILL_FIRE_dm_dmi_read_addr = EN_dm_dmi_read_addr ; + // action method dmi_read_addr + assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ; - // actionvalue method dm_dmi_read_data - assign dm_dmi_read_data = debug_module$dmi_read_data ; - assign RDY_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign CAN_FIRE_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign WILL_FIRE_dm_dmi_read_data = EN_dm_dmi_read_data ; + // actionvalue method dmi_read_data + assign dmi_read_data = debug_module$dmi_read_data ; + assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ; - // action method dm_dmi_write - assign RDY_dm_dmi_write = debug_module$RDY_dmi_write ; - assign CAN_FIRE_dm_dmi_write = debug_module$RDY_dmi_write ; - assign WILL_FIRE_dm_dmi_write = EN_dm_dmi_write ; + // action method dmi_write + assign RDY_dmi_write = debug_module$RDY_dmi_write ; + assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ; + assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method dm_ndm_reset_req_get_get - assign RDY_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_dm_ndm_reset_req_get_get = EN_dm_ndm_reset_req_get_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + debug_module$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // actionvalue method tv_verifier_info_get_get assign tv_verifier_info_get_get = tv_encode$out_get ; @@ -2033,7 +1981,7 @@ module mkCoreW(CLK, // submodule debug_module mkDebug_Module debug_module(.CLK(CLK), - .RST_N(RST_N), + .RST_N(RST_N_dm_power_on_reset), .dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr), .dmi_write_dm_addr(debug_module$dmi_write_dm_addr), .dmi_write_dm_word(debug_module$dmi_write_dm_word), @@ -2041,6 +1989,7 @@ module mkCoreW(CLK, .hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put), .hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put), .hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put), + .hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put), .master_arready(debug_module$master_arready), .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), @@ -2052,10 +2001,12 @@ module mkCoreW(CLK, .master_rresp(debug_module$master_rresp), .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), + .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), .EN_dmi_read_data(debug_module$EN_dmi_read_data), .EN_dmi_write(debug_module$EN_dmi_write), - .EN_hart0_get_reset_req_get(debug_module$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get), @@ -2065,12 +2016,15 @@ module mkCoreW(CLK, .EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put), .EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get), .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), - .EN_get_ndm_reset_req_get(debug_module$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), .RDY_dmi_write(debug_module$RDY_dmi_write), - .RDY_hart0_get_reset_req_get(debug_module$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(), + .RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put), @@ -2085,7 +2039,9 @@ module mkCoreW(CLK, .hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put), - .RDY_get_ndm_reset_req_get(debug_module$RDY_get_ndm_reset_req_get), + .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), .master_awvalid(debug_module$master_awvalid), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), @@ -2098,7 +2054,6 @@ module mkCoreW(CLK, .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), .master_wvalid(debug_module$master_wvalid), - .master_wid(debug_module$master_wid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), @@ -2154,6 +2109,15 @@ module mkCoreW(CLK, .trace_data_out_get(dm_gpr_tap_ifc$trace_data_out_get), .RDY_trace_data_out_get(dm_gpr_tap_ifc$RDY_trace_data_out_get)); + // submodule dm_hart0_reset_controller + MakeResetA #(.RSTDELAY(32'd10), + .init(1'd1)) dm_hart0_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(dm_hart0_reset_controller$OUT_RST)); + // submodule dm_mem_tap mkDM_Mem_Tap dm_mem_tap(.CLK(CLK), .RST_N(RST_N), @@ -2193,7 +2157,6 @@ module mkCoreW(CLK, .slave_bready(dm_mem_tap$slave_bready), .slave_rready(dm_mem_tap$slave_rready), .slave_wdata(dm_mem_tap$slave_wdata), - .slave_wid(dm_mem_tap$slave_wid), .slave_wlast(dm_mem_tap$slave_wlast), .slave_wstrb(dm_mem_tap$slave_wstrb), .slave_wvalid(dm_mem_tap$slave_wvalid), @@ -2221,7 +2184,6 @@ module mkCoreW(CLK, .master_awqos(dm_mem_tap$master_awqos), .master_awregion(dm_mem_tap$master_awregion), .master_wvalid(dm_mem_tap$master_wvalid), - .master_wid(dm_mem_tap$master_wid), .master_wdata(dm_mem_tap$master_wdata), .master_wstrb(dm_mem_tap$master_wstrb), .master_wlast(dm_mem_tap$master_wlast), @@ -2241,35 +2203,6 @@ module mkCoreW(CLK, .trace_data_out_get(dm_mem_tap$trace_data_out_get), .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_requestor - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_requestor(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_requestor$D_IN), - .ENQ(f_reset_requestor$ENQ), - .DEQ(f_reset_requestor$DEQ), - .CLR(f_reset_requestor$CLR), - .D_OUT(f_reset_requestor$D_OUT), - .FULL_N(f_reset_requestor$FULL_N), - .EMPTY_N(f_reset_requestor$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), .RST_N(RST_N), @@ -2299,7 +2232,6 @@ module mkCoreW(CLK, .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), @@ -2328,7 +2260,6 @@ module mkCoreW(CLK, .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), @@ -2367,7 +2298,7 @@ module mkCoreW(CLK, .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), + .RDY_reset(), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), @@ -2403,7 +2334,6 @@ module mkCoreW(CLK, .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), @@ -2432,7 +2362,6 @@ module mkCoreW(CLK, .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), @@ -2461,7 +2390,6 @@ module mkCoreW(CLK, .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), @@ -2479,6 +2407,11 @@ module mkCoreW(CLK, .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); + // submodule hart0_reset + ResetEither hart0_reset(.A_RST(RST_N), + .B_RST(dm_hart0_reset_controller$OUT_RST), + .RST_OUT(hart0_reset$RST_OUT)); + // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), @@ -2507,7 +2440,6 @@ module mkCoreW(CLK, .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), @@ -2537,8 +2469,8 @@ module mkCoreW(CLK, .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), + .RDY_server_reset_request_put(), + .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), @@ -2556,8 +2488,7 @@ module mkCoreW(CLK, // submodule proc mkProc proc(.CLK(CLK), - .RST_N(RST_N), - .debug_external_interrupt_req_set_not_clear(proc$debug_external_interrupt_req_set_not_clear), + .RST_N(hart0_reset$RST_OUT), .debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr), .debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst), .debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache), @@ -2583,7 +2514,6 @@ module mkCoreW(CLK, .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), - .debug_module_mem_server_wid(proc$debug_module_mem_server_wid), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), @@ -2621,8 +2551,6 @@ module mkCoreW(CLK, .start_fromhostAddr(proc$start_fromhostAddr), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), - .EN_hart0_server_reset_request_put(proc$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(proc$EN_hart0_server_reset_response_get), .EN_start(proc$EN_start), .EN_set_verbosity(proc$EN_set_verbosity), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), @@ -2636,8 +2564,6 @@ module mkCoreW(CLK, .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), .EN_v_to_TV_0_get(proc$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(proc$EN_v_to_TV_1_get), - .RDY_hart0_server_reset_request_put(proc$RDY_hart0_server_reset_request_put), - .RDY_hart0_server_reset_response_get(proc$RDY_hart0_server_reset_response_get), .RDY_start(proc$RDY_start), .master0_awvalid(proc$master0_awvalid), .master0_awid(proc$master0_awid), @@ -2651,7 +2577,6 @@ module mkCoreW(CLK, .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), .master0_wvalid(proc$master0_wvalid), - .master0_wid(proc$master0_wid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), @@ -2680,7 +2605,6 @@ module mkCoreW(CLK, .master1_awqos(proc$master1_awqos), .master1_awregion(proc$master1_awregion), .master1_wvalid(proc$master1_wvalid), - .master1_wid(proc$master1_wid), .master1_wdata(proc$master1_wdata), .master1_wstrb(proc$master1_wstrb), .master1_wlast(proc$master1_wlast), @@ -2784,7 +2708,7 @@ module mkCoreW(CLK, .EN_v_cpu_in_1_put(tv_encode$EN_v_cpu_in_1_put), .EN_dm_in_put(tv_encode$EN_dm_in_put), .EN_out_get(tv_encode$EN_out_get), - .RDY_reset(tv_encode$RDY_reset), + .RDY_reset(), .RDY_v_cpu_in_0_put(tv_encode$RDY_v_cpu_in_0_put), .RDY_v_cpu_in_1_put(tv_encode$RDY_v_cpu_in_1_put), .RDY_dm_in_put(tv_encode$RDY_dm_in_put), @@ -2835,16 +2759,31 @@ module mkCoreW(CLK, .FULL_N(v_td2_to_td_1_f_out$FULL_N), .EMPTY_N(v_td2_to_td_1_f_out$EMPTY_N)); + // rule RL_rl_dm_hart0_reset + assign CAN_FIRE_RL_rl_dm_hart0_reset = + debug_module$RDY_hart0_reset_client_request_get && + rg_hart0_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ; + + // rule RL_rl_dm_hart0_reset_wait + assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = + (rg_hart0_reset_delay != 8'd1 || + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && + rg_hart0_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = + CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; + // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - debug_module$RDY_hart0_client_run_halt_request_get && - proc$RDY_hart0_run_halt_server_request_put ; + proc$RDY_hart0_run_halt_server_request_put && + debug_module$RDY_hart0_client_run_halt_request_get ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - debug_module$RDY_hart0_client_run_halt_response_put && - proc$RDY_hart0_run_halt_server_response_get ; + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2886,6 +2825,10 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; + // rule RL_rl_wr_response_channel + assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; + // rule RL_rl_rd_addr_channel assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; @@ -2896,22 +2839,22 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2924,22 +2867,22 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -3042,55 +2985,20 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_from_dm_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode$RDY_reset && - debug_module$RDY_hart0_get_reset_req_get && - proc$RDY_hart0_server_reset_request_put && - f_reset_requestor$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start && - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && proc$RDY_start && - proc$RDY_hart0_server_reset_response_get && - f_reset_requestor$EMPTY_N && - (!f_reset_requestor$D_OUT || f_reset_rsps$FULL_N) ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; - // rule RL_rl_relay_non_maskable_interrupt - assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - // rule RL_v_td2_to_td_0_rl_xform assign CAN_FIRE_RL_v_td2_to_td_0_rl_xform = v_td2_to_td_0_f_in$EMPTY_N && v_td2_to_td_0_f_out$FULL_N ; @@ -3103,18 +3011,34 @@ module mkCoreW(CLK, assign WILL_FIRE_RL_v_td2_to_td_1_rl_xform = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; + // inputs to muxes for submodule ports + assign MUX_proc$start_1__SEL_1 = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 ; + assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = + rg_hart0_reset_delay - 8'd1 ; + // register rg_fromhost_addr - assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; - assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + assign rg_fromhost_addr$D_IN = start_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_start ; + + // register rg_hart0_reset_delay + assign rg_hart0_reset_delay$D_IN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait ? + MUX_rg_hart0_reset_delay$write_1__VAL_1 : + 8'd210 ; + assign rg_hart0_reset_delay$EN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait || + WILL_FIRE_RL_rl_dm_hart0_reset ; // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_htif_addrs ; + assign rg_tohost_addr$D_IN = start_tohost_addr ; + assign rg_tohost_addr$EN = EN_start ; // submodule debug_module - assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; - assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; - assign debug_module$dmi_write_dm_word = dm_dmi_write_dm_word ; + assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ; + assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ; + assign debug_module$dmi_write_dm_word = dmi_write_dm_word ; assign debug_module$hart0_client_run_halt_response_put = proc$hart0_run_halt_server_response_get ; assign debug_module$hart0_csr_mem_client_response_put = @@ -3122,6 +3046,7 @@ module mkCoreW(CLK, assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ; assign debug_module$hart0_gpr_mem_client_response_put = dm_gpr_tap_ifc$server_response_get ; + assign debug_module$hart0_reset_client_response_put = 1'd1 ; assign debug_module$master_arready = dm_mem_tap$slave_arready ; assign debug_module$master_awready = dm_mem_tap$slave_awready ; assign debug_module$master_bid = dm_mem_tap$slave_bid ; @@ -3133,11 +3058,15 @@ module mkCoreW(CLK, assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; assign debug_module$master_wready = dm_mem_tap$slave_wready ; - assign debug_module$EN_dmi_read_addr = EN_dm_dmi_read_addr ; - assign debug_module$EN_dmi_read_data = EN_dm_dmi_read_data ; - assign debug_module$EN_dmi_write = EN_dm_dmi_write ; - assign debug_module$EN_hart0_get_reset_req_get = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; + assign debug_module$ndm_reset_client_response_put = + ndm_reset_client_response_put ; + assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; + assign debug_module$EN_dmi_read_data = EN_dmi_read_data ; + assign debug_module$EN_dmi_write = EN_dmi_write ; + assign debug_module$EN_hart0_reset_client_request_get = + CAN_FIRE_RL_rl_dm_hart0_reset ; + assign debug_module$EN_hart0_reset_client_response_put = + MUX_proc$start_1__SEL_1 ; assign debug_module$EN_hart0_client_run_halt_request_get = CAN_FIRE_RL_ClientServerRequest ; assign debug_module$EN_hart0_client_run_halt_response_put = @@ -3154,7 +3083,10 @@ module mkCoreW(CLK, CAN_FIRE_RL_ClientServerRequest_3 ; assign debug_module$EN_hart0_csr_mem_client_response_put = CAN_FIRE_RL_ClientServerResponse_3 ; - assign debug_module$EN_get_ndm_reset_req_get = EN_dm_ndm_reset_req_get_get ; + assign debug_module$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign debug_module$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule dm_csr_tap assign dm_csr_tap$client_response_put = @@ -3188,6 +3120,9 @@ module mkCoreW(CLK, assign dm_gpr_tap_ifc$EN_trace_data_out_get = CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ; + // submodule dm_hart0_reset_controller + assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; + // submodule dm_mem_tap assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; @@ -3225,36 +3160,12 @@ module mkCoreW(CLK, assign dm_mem_tap$slave_bready = debug_module$master_bready ; assign dm_mem_tap$slave_rready = debug_module$master_rready ; assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; - assign dm_mem_tap$slave_wid = debug_module$master_wid ; assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; assign dm_mem_tap$EN_trace_data_out_get = WILL_FIRE_RL_rl_merge_dm_mem_trace_data ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_requestor - assign f_reset_requestor$D_IN = - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; - assign f_reset_requestor$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign f_reset_requestor$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign f_reset_requestor$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_complete && - f_reset_requestor$D_OUT ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ; @@ -3282,7 +3193,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ; assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ; assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ; - assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ; assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ; @@ -3311,7 +3221,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wid = dm_mem_tap$master_wid ; assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; @@ -3353,9 +3262,7 @@ module mkCoreW(CLK, proc$debug_module_mem_server_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = proc$debug_module_mem_server_wready ; - assign fabric_2x3$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign fabric_2x3$EN_reset = 1'b0 ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule plic @@ -3384,7 +3291,6 @@ module mkCoreW(CLK, assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; @@ -3425,16 +3331,11 @@ module mkCoreW(CLK, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$EN_server_reset_request_put = 1'b0 ; + assign plic$EN_server_reset_response_get = 1'b0 ; + assign plic$EN_set_addr_map = EN_start ; // submodule proc - assign proc$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; assign proc$debug_module_mem_server_araddr = fabric_2x3$v_to_slaves_2_araddr ; assign proc$debug_module_mem_server_arburst = @@ -3478,7 +3379,6 @@ module mkCoreW(CLK, assign proc$debug_module_mem_server_rready = fabric_2x3$v_to_slaves_2_rready ; assign proc$debug_module_mem_server_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign proc$debug_module_mem_server_wid = fabric_2x3$v_to_slaves_2_wid ; assign proc$debug_module_mem_server_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign proc$debug_module_mem_server_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign proc$debug_module_mem_server_wvalid = @@ -3519,15 +3419,17 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_fromhostAddr = + MUX_proc$start_1__SEL_1 ? + rg_fromhost_addr : + start_fromhost_addr ; assign proc$start_startpc = 64'h0000000070000000 ; - assign proc$start_tohostAddr = rg_tohost_addr ; - assign proc$EN_hart0_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign proc$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign proc$start_tohostAddr = + MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; + assign proc$EN_start = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 || + EN_start ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; @@ -3574,9 +3476,7 @@ module mkCoreW(CLK, end assign tv_encode$v_cpu_in_0_put = v_td2_to_td_0_f_out$D_OUT ; assign tv_encode$v_cpu_in_1_put = v_td2_to_td_1_f_out$D_OUT ; - assign tv_encode$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign tv_encode$EN_reset = 1'b0 ; assign tv_encode$EN_v_cpu_in_0_put = CAN_FIRE_RL_mkConnectionGetPut_2 ; assign tv_encode$EN_v_cpu_in_1_put = CAN_FIRE_RL_mkConnectionGetPut_4 ; assign tv_encode$EN_dm_in_put = @@ -3608,12 +3508,12 @@ module mkCoreW(CLK, // submodule v_td2_to_td_0_f_out assign v_td2_to_td_0_f_out$D_IN = { v_td2_to_td_0_f_in$D_OUT[319:256], - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5, v_td2_to_td_0_f_in$D_OUT[255:192], v_td2_to_td_0_f_in$D_OUT[161:160] == 2'b11, v_td2_to_td_0_f_in$D_OUT[191:160], - x1_avValue_rd__h5432, - x__h5725, + x1_avValue_rd__h5277, + x__h5570, 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; assign v_td2_to_td_0_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_0_rl_xform ; assign v_td2_to_td_0_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_2 ; @@ -3623,17 +3523,17 @@ module mkCoreW(CLK, assign v_td2_to_td_1_f_in$D_IN = { proc$v_to_TV_1_get[319:154], proc$v_to_TV_1_get[154] ? - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 : + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 : 12'hAAA, proc$v_to_TV_1_get[141], proc$v_to_TV_1_get[141] ? { proc$v_to_TV_1_get[140], proc$v_to_TV_1_get[140] ? - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 : - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 } : + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 : + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 } : 5'h0A, proc$v_to_TV_1_get[135:72], - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8, + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9, proc$v_to_TV_1_get[69:0] } ; assign v_td2_to_td_1_f_in$ENQ = CAN_FIRE_RL_mkConnectionGetPut_3 ; assign v_td2_to_td_1_f_in$DEQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; @@ -3646,44 +3546,40 @@ module mkCoreW(CLK, v_td2_to_td_1_f_in$D_OUT[255:192], v_td2_to_td_1_f_in$D_OUT[161:160] == 2'b11, v_td2_to_td_1_f_in$D_OUT[191:160], - x1_avValue_rd__h6363, - x__h6650, + x1_avValue_rd__h6208, + x__h6495, 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; assign v_td2_to_td_1_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; assign v_td2_to_td_1_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_4 ; assign v_td2_to_td_1_f_out$CLR = 1'b0 ; // remaining internal signals - assign tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 = - tv_encode$RDY_reset && proc$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N && - f_reset_requestor$FULL_N ; always@(v_td2_to_td_0_f_in$D_OUT) begin case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h5432 = 5'd0; - default: x1_avValue_rd__h5432 = 5'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h5277 = 5'd0; + default: x1_avValue_rd__h5277 = 5'd0; endcase end always@(v_td2_to_td_0_f_in$D_OUT) begin case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h5725 = 64'd0; - default: x__h5725 = 64'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x__h5570 = 64'd0; + default: x__h5570 = 64'd0; endcase end always@(v_td2_to_td_1_f_in$D_OUT) begin case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h6363 = 5'd0; - default: x1_avValue_rd__h6363 = 5'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h6208 = 5'd0; + default: x1_avValue_rd__h6208 = 5'd0; endcase end always@(v_td2_to_td_1_f_in$D_OUT) begin case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h6650 = 64'd0; - default: x__h6650 = 64'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x__h6495 = 64'd0; + default: x__h6495 = 64'd0; endcase end always@(proc$v_to_TV_0_get) @@ -3774,6 +3670,18 @@ module mkCoreW(CLK, default: CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4 = 2'd2; endcase end + always@(v_td2_to_td_0_f_in$D_OUT) + begin + case (v_td2_to_td_0_f_in$D_OUT[159:155]) + 5'd2, 5'd6, 5'd7: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd13; + 5'd3, 5'd8, 5'd9, 5'd11: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd6; + 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd5; + default: CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd6; + endcase + end always@(proc$v_to_TV_1_get) begin case (proc$v_to_TV_1_get[153:142]) @@ -3817,9 +3725,9 @@ module mkCoreW(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 = proc$v_to_TV_1_get[153:142]; - default: CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = + default: CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 = 12'd2303; endcase end @@ -3827,9 +3735,9 @@ module mkCoreW(CLK, begin case (proc$v_to_TV_1_get[139:136]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = 4'd15; + default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = 4'd15; endcase end always@(proc$v_to_TV_1_get) @@ -3848,30 +3756,18 @@ module mkCoreW(CLK, 4'd11, 4'd12, 4'd13: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 = proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = 4'd15; + default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 = 4'd15; endcase end always@(proc$v_to_TV_1_get) begin case (proc$v_to_TV_1_get[71:70]) 2'd0, 2'd1: - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9 = proc$v_to_TV_1_get[71:70]; - default: CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = 2'd2; - endcase - end - always@(v_td2_to_td_0_f_in$D_OUT) - begin - case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd2, 5'd6, 5'd7: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd13; - 5'd3, 5'd8, 5'd9, 5'd11: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; - 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd5; - default: CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; + default: CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9 = 2'd2; endcase end always@(v_td2_to_td_1_f_in$D_OUT) @@ -3894,12 +3790,16 @@ module mkCoreW(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; end else begin if (rg_fromhost_addr$EN) rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_hart0_reset_delay$EN) + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY + rg_hart0_reset_delay$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; end @@ -3911,6 +3811,7 @@ module mkCoreW(CLK, initial begin rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_hart0_reset_delay = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS @@ -3923,36 +3824,55 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h7205 = $stime; - #0; - end - v__h7199 = v__h7205 / 32'd10; + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + begin + v__h6860 = $stime; + #0; + end + v__h6854 = v__h6860 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h7199); + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", + v__h6854, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - begin - v__h7403 = $stime; - #0; - end - v__h7397 = v__h7403 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + begin + v__h7003 = $stime; + #0; + end + v__h6997 = v__h7003 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h7397); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h6997, + 64'h0000000070000000, + rg_tohost_addr, + rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h7674 = $stime; - #0; - end - v__h7668 = v__h7674 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + begin + v__h15013 = $stime; + #0; + end + v__h15007 = v__h15013 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h7668); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)", + v__h15007, + 64'h0000000070000000, + start_tohost_addr, + start_fromhost_addr); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v index c78345f..b6bd69d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v @@ -306,27 +306,27 @@ module mkDM_Abstract_Commands(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2815; - reg [31 : 0] v__h3054; - reg [31 : 0] v__h3179; - reg [31 : 0] v__h3506; - reg [31 : 0] v__h3623; - reg [31 : 0] v__h3336; - reg [31 : 0] v__h4114; - reg [31 : 0] v__h2809; - reg [31 : 0] v__h3048; - reg [31 : 0] v__h3173; - reg [31 : 0] v__h3330; - reg [31 : 0] v__h3500; - reg [31 : 0] v__h3617; - reg [31 : 0] v__h4108; + reg [31 : 0] v__h2853; + reg [31 : 0] v__h3092; + reg [31 : 0] v__h3217; + reg [31 : 0] v__h3544; + reg [31 : 0] v__h3661; + reg [31 : 0] v__h3374; + reg [31 : 0] v__h4152; + reg [31 : 0] v__h2847; + reg [31 : 0] v__h3086; + reg [31 : 0] v__h3211; + reg [31 : 0] v__h3368; + reg [31 : 0] v__h3538; + reg [31 : 0] v__h3655; + reg [31 : 0] v__h4146; // synopsys translate_on // remaining internal signals - wire [63 : 0] req_data__h860; - wire [31 : 0] virt_rg_abstractcs__h706, virt_rg_command__h770; - wire [15 : 0] regno__h2639; - wire [12 : 0] x__h1321, x__h1746; + wire [63 : 0] req_data__h896; + wire [31 : 0] virt_rg_abstractcs__h742, virt_rg_command__h806; + wire [15 : 0] regno__h2677; + wire [12 : 0] x__h1357, x__h1782; wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61, @@ -352,12 +352,12 @@ module mkDM_Abstract_Commands(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_data1 or - rg_data0 or virt_rg_abstractcs__h706 or virt_rg_command__h770) + rg_data0 or virt_rg_abstractcs__h742 or virt_rg_command__h806) begin case (av_read_dm_addr) 7'h04: av_read = rg_data0; - 7'h16: av_read = virt_rg_abstractcs__h706; - 7'h17: av_read = virt_rg_command__h770; + 7'h16: av_read = virt_rg_abstractcs__h742; + 7'h17: av_read = virt_rg_command__h806; default: av_read = rg_data1; endcase end @@ -416,7 +416,7 @@ module mkDM_Abstract_Commands(CLK, EN_hart0_csr_mem_client_response_put ; // submodule f_hart0_csr_reqs - FIFO1 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_reqs$D_IN), .ENQ(f_hart0_csr_reqs$ENQ), @@ -427,7 +427,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_reqs$EMPTY_N)); // submodule f_hart0_csr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_rsps$D_IN), .ENQ(f_hart0_csr_rsps$ENQ), @@ -438,7 +438,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_rsps$EMPTY_N)); // submodule f_hart0_fpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_reqs$D_IN), .ENQ(f_hart0_fpr_reqs$ENQ), @@ -449,7 +449,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_reqs$EMPTY_N)); // submodule f_hart0_fpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_rsps$D_IN), .ENQ(f_hart0_fpr_rsps$ENQ), @@ -460,7 +460,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_rsps$EMPTY_N)); // submodule f_hart0_gpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_reqs$D_IN), .ENQ(f_hart0_gpr_reqs$ENQ), @@ -471,7 +471,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N)); // submodule f_hart0_gpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_rsps$D_IN), .ENQ(f_hart0_gpr_rsps$ENQ), @@ -611,19 +611,19 @@ module mkDM_Abstract_Commands(CLK, EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h05 ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_1 = - { 1'd1, rg_command_access_reg_regno[11:0], req_data__h860 } ; + { 1'd1, rg_command_access_reg_regno[11:0], req_data__h896 } ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 = { 1'd0, rg_command_access_reg_regno[11:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1746[4:0], req_data__h860 } ; + { 1'd1, x__h1782[4:0], req_data__h896 } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1746[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1782[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1321[4:0], req_data__h860 } ; + { 1'd1, x__h1357[4:0], req_data__h896 } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1321[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1357[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 = f_hart0_fpr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ; always@(write_dm_addr or rg_abstractcs_busy or write_dm_word) @@ -722,10 +722,10 @@ module mkDM_Abstract_Commands(CLK, assign rg_abstractcs_cmderr$EN = EN_write && write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 || - WILL_FIRE_RL_rl_gpr_read_finish || - WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_csr_read_finish || WILL_FIRE_RL_rl_csr_write_finish || + WILL_FIRE_RL_rl_gpr_read_finish || + WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_fpr_read_finish || WILL_FIRE_RL_rl_fpr_write_finish || EN_reset || @@ -897,8 +897,8 @@ module mkDM_Abstract_Commands(CLK, assign f_hart0_gpr_rsps$CLR = EN_reset ; // remaining internal signals - assign regno__h2639 = { 3'd0, rg_command_access_reg_regno } ; - assign req_data__h860 = { rg_data1, rg_data0 } ; + assign regno__h2677 = { 3'd0, rg_command_access_reg_regno } ; + assign req_data__h896 = { rg_data1, rg_data0 } ; assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38 = rg_abstractcs_busy && rg_start_reg_access && rg_command_access_reg_write && @@ -938,10 +938,10 @@ module mkDM_Abstract_Commands(CLK, rg_command_access_reg_regno < 13'h1000 ; assign rg_command_access_reg_regno_ULT_0x1020___d57 = rg_command_access_reg_regno < 13'h1020 ; - assign virt_rg_abstractcs__h706 = - { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd0 } ; - assign virt_rg_command__h770 = - { 15'd17, rg_command_access_reg_write, regno__h2639 } ; + assign virt_rg_abstractcs__h742 = + { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd2 } ; + assign virt_rg_command__h806 = + { 15'd17, rg_command_access_reg_write, regno__h2677 } ; assign write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 = write_dm_addr == 7'h16 && (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) || @@ -975,8 +975,8 @@ module mkDM_Abstract_Commands(CLK, write_dm_word[22:20] != 3'd4 && write_dm_word[22:20] != 3'd5 && write_dm_word[22:20] != 3'd6 ; - assign x__h1321 = rg_command_access_reg_regno - 13'h1000 ; - assign x__h1746 = rg_command_access_reg_regno - 13'h1020 ; + assign x__h1357 = rg_command_access_reg_regno - 13'h1000 ; + assign x__h1782 = rg_command_access_reg_regno - 13'h1020 ; // handling of inlined registers @@ -1031,14 +1031,14 @@ module mkDM_Abstract_Commands(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) begin - v__h2815 = $stime; + v__h2853 = $stime; #0; end - v__h2809 = v__h2815 / 32'd10; + v__h2847 = v__h2853 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR", - v__h2809, + v__h2847, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) @@ -1048,16 +1048,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr == 7'h17 && rg_abstractcs_busy) begin - v__h3054 = $stime; + v__h3092 = $stime; #0; end - v__h3048 = v__h3054 / 32'd10; + v__h3086 = v__h3092 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3048, + v__h3086, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1068,15 +1068,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) begin - v__h3179 = $stime; + v__h3217 = $stime; #0; end - v__h3173 = v__h3179 / 32'd10; + v__h3211 = v__h3217 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3173, + v__h3211, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1094,15 +1094,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) begin - v__h3506 = $stime; + v__h3544 = $stime; #0; end - v__h3500 = v__h3506 / 32'd10; + v__h3538 = v__h3544 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3500, + v__h3538, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1112,15 +1112,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) begin - v__h3623 = $stime; + v__h3661 = $stime; #0; end - v__h3617 = v__h3623 / 32'd10; + v__h3655 = v__h3661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3617, + v__h3655, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1130,15 +1130,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) begin - v__h3336 = $stime; + v__h3374 = $stime; #0; end - v__h3330 = v__h3336 / 32'd10; + v__h3368 = v__h3374 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3330, + v__h3368, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1201,17 +1201,17 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr != 7'h04 && write_dm_addr != 7'h05) begin - v__h4114 = $stime; + v__h4152 = $stime; #0; end - v__h4108 = v__h4114 / 32'd10; + v__h4146 = v__h4152 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 && write_dm_addr != 7'h17 && write_dm_addr != 7'h04 && write_dm_addr != 7'h05) - $write("%0d: DM_Abstract_Commands.write: [", v__h4108); + $write("%0d: DM_Abstract_Commands.write: [", v__h4146); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol"); diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v b/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v index ddcbcb2..c048133 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v @@ -29,7 +29,6 @@ // master_awqos O 4 reg // master_awregion O 4 reg // master_wvalid O 1 reg -// master_wid O 4 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg @@ -62,7 +61,6 @@ // slave_awqos I 4 reg // slave_awregion I 4 reg // slave_wvalid I 1 -// slave_wid I 4 reg // slave_wdata I 64 reg // slave_wstrb I 8 reg // slave_wlast I 1 reg @@ -127,7 +125,6 @@ module mkDM_Mem_Tap(CLK, slave_awready, slave_wvalid, - slave_wid, slave_wdata, slave_wstrb, slave_wlast, @@ -194,8 +191,6 @@ module mkDM_Mem_Tap(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -266,7 +261,6 @@ module mkDM_Mem_Tap(CLK, // action method slave_m_wvalid input slave_wvalid; - input [3 : 0] slave_wid; input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; @@ -365,9 +359,6 @@ module mkDM_Mem_Tap(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -455,7 +446,6 @@ module mkDM_Mem_Tap(CLK, master_awid, master_awqos, master_awregion, - master_wid, slave_bid, slave_rid; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; @@ -509,7 +499,7 @@ module mkDM_Mem_Tap(CLK, master_xactor_f_wr_addr$FULL_N; // ports of submodule master_xactor_f_wr_data - wire [76 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; + wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; wire master_xactor_f_wr_data$CLR, master_xactor_f_wr_data$DEQ, master_xactor_f_wr_data$EMPTY_N, @@ -549,7 +539,7 @@ module mkDM_Mem_Tap(CLK, slave_xactor_f_wr_addr$FULL_N; // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; wire slave_xactor_f_wr_data$CLR, slave_xactor_f_wr_data$DEQ, slave_xactor_f_wr_data$EMPTY_N, @@ -597,7 +587,7 @@ module mkDM_Mem_Tap(CLK, WILL_FIRE_trace_data_out_get; // remaining internal signals - wire [63 : 0] stval___1__h1532, x__h1527, y_avValue_fst__h1438; + wire [63 : 0] stval___1__h1524, x__h1519, y_avValue_fst__h1430; // action method slave_m_awvalid assign CAN_FIRE_slave_m_awvalid = 1'd1 ; @@ -692,9 +682,6 @@ module mkDM_Mem_Tap(CLK, // value method master_m_wvalid assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; - // value method master_m_wid - assign master_wid = master_xactor_f_wr_data$D_OUT[76:73] ; - // value method master_m_wdata assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; @@ -813,7 +800,7 @@ module mkDM_Mem_Tap(CLK, .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); // submodule master_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(master_xactor_f_wr_data$D_IN), @@ -869,7 +856,7 @@ module mkDM_Mem_Tap(CLK, .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), + FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(slave_xactor_f_wr_data$D_IN), .ENQ(slave_xactor_f_wr_data$ENQ), @@ -920,7 +907,7 @@ module mkDM_Mem_Tap(CLK, // submodule f_trace_data assign f_trace_data$D_IN = { 171'h12AAAAAAAAAAAAAAA955555554A0000000000000002, - x__h1527, + x__h1519, slave_xactor_f_wr_addr$D_OUT[92:29], 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign f_trace_data$ENQ = CAN_FIRE_RL_write_reqs ; @@ -1006,7 +993,7 @@ module mkDM_Mem_Tap(CLK, // submodule slave_xactor_f_wr_data assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; + { slave_wdata, slave_wstrb, slave_wlast } ; assign slave_xactor_f_wr_data$ENQ = slave_wvalid && slave_xactor_f_wr_data$FULL_N ; assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_write_reqs ; @@ -1020,12 +1007,12 @@ module mkDM_Mem_Tap(CLK, assign slave_xactor_f_wr_resp$CLR = 1'b0 ; // remaining internal signals - assign stval___1__h1532 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; - assign x__h1527 = + assign stval___1__h1524 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; + assign x__h1519 = (slave_xactor_f_wr_data$D_OUT[8:1] == 8'h0F) ? - stval___1__h1532 : - y_avValue_fst__h1438 ; - assign y_avValue_fst__h1438 = + stval___1__h1524 : + y_avValue_fst__h1430 ; + assign y_avValue_fst__h1430 = { 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ; endmodule // mkDM_Mem_Tap diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 2c47720..4ba0a0f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -12,27 +12,35 @@ // av_read O 32 // RDY_av_read O 1 const // RDY_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg // hart0_get_other_req_get O 4 reg // RDY_hart0_get_other_req_get O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 // write_dm_addr I 7 // write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg +// ndm_reset_client_response_put I 1 reg // EN_reset I 1 // EN_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_av_read I 1 unused +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: // av_read_dm_addr -> av_read @@ -71,8 +79,13 @@ module mkDM_Run_Control(CLK, EN_write, RDY_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -86,8 +99,13 @@ module mkDM_Run_Control(CLK, hart0_get_other_req_get, RDY_hart0_get_other_req_get, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get); + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put); input CLK; input RST_N; @@ -111,9 +129,15 @@ module mkDM_Run_Control(CLK, input EN_write; output RDY_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -130,24 +154,34 @@ module mkDM_Run_Control(CLK, output [3 : 0] hart0_get_other_req_get; output RDY_hart0_get_other_req_get; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // signals for module outputs reg [31 : 0] av_read; wire [3 : 0] hart0_get_other_req_get; wire RDY_av_read, RDY_dmactive, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_reset, RDY_write, dmactive, - hart0_client_run_halt_request_get; + hart0_client_run_halt_request_get, + hart0_reset_client_request_get, + ndm_reset_client_request_get; // register rg_dmcontrol_dmactive reg rg_dmcontrol_dmactive; @@ -170,6 +204,14 @@ module mkDM_Run_Control(CLK, reg rg_dmstatus_allresumeack$D_IN; wire rg_dmstatus_allresumeack$EN; + // register rg_dmstatus_allunavail + reg rg_dmstatus_allunavail; + wire rg_dmstatus_allunavail$D_IN, rg_dmstatus_allunavail$EN; + + // register rg_hart0_hasreset + reg rg_hart0_hasreset; + wire rg_hart0_hasreset$D_IN, rg_hart0_hasreset$EN; + // register rg_hart0_running reg rg_hart0_running; reg rg_hart0_running$D_IN; @@ -191,10 +233,21 @@ module mkDM_Run_Control(CLK, // ports of submodule f_hart0_reset_reqs wire f_hart0_reset_reqs$CLR, f_hart0_reset_reqs$DEQ, + f_hart0_reset_reqs$D_IN, + f_hart0_reset_reqs$D_OUT, f_hart0_reset_reqs$EMPTY_N, f_hart0_reset_reqs$ENQ, f_hart0_reset_reqs$FULL_N; + // ports of submodule f_hart0_reset_rsps + wire f_hart0_reset_rsps$CLR, + f_hart0_reset_rsps$DEQ, + f_hart0_reset_rsps$D_IN, + f_hart0_reset_rsps$D_OUT, + f_hart0_reset_rsps$EMPTY_N, + f_hart0_reset_rsps$ENQ, + f_hart0_reset_rsps$FULL_N; + // ports of submodule f_hart0_run_halt_reqs wire f_hart0_run_halt_reqs$CLR, f_hart0_run_halt_reqs$DEQ, @@ -216,42 +269,89 @@ module mkDM_Run_Control(CLK, // ports of submodule f_ndm_reset_reqs wire f_ndm_reset_reqs$CLR, f_ndm_reset_reqs$DEQ, + f_ndm_reset_reqs$D_IN, + f_ndm_reset_reqs$D_OUT, f_ndm_reset_reqs$EMPTY_N, f_ndm_reset_reqs$ENQ, f_ndm_reset_reqs$FULL_N; + // ports of submodule f_ndm_reset_rsps + wire f_ndm_reset_rsps$CLR, + f_ndm_reset_rsps$DEQ, + f_ndm_reset_rsps$D_IN, + f_ndm_reset_rsps$D_OUT, + f_ndm_reset_rsps$EMPTY_N, + f_ndm_reset_rsps$ENQ, + f_ndm_reset_rsps$FULL_N; + // rule scheduling signals - wire CAN_FIRE_RL_rl_hart0_run_rsp, + wire CAN_FIRE_RL_rl_hart0_reset_rsp, + CAN_FIRE_RL_rl_hart0_run_rsp, + CAN_FIRE_RL_rl_ndm_reset_rsp, CAN_FIRE_av_read, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, CAN_FIRE_reset, CAN_FIRE_write, + WILL_FIRE_RL_rl_hart0_reset_rsp, WILL_FIRE_RL_rl_hart0_run_rsp, + WILL_FIRE_RL_rl_ndm_reset_rsp, WILL_FIRE_av_read, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, WILL_FIRE_reset, WILL_FIRE_write; // inputs to muxes for submodule ports wire MUX_rg_dmstatus_allresumeack$write_1__SEL_2, MUX_rg_dmstatus_allresumeack$write_1__SEL_3, - MUX_rg_hart0_running$write_1__SEL_3, + MUX_rg_dmstatus_allunavail$write_1__SEL_3, + MUX_rg_hart0_hasreset$write_1__SEL_3, MUX_rg_verbosity$write_1__SEL_2; + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h2225; + reg [31 : 0] v__h2768; + reg [31 : 0] v__h2874; + reg [31 : 0] v__h2989; + reg [31 : 0] v__h3109; + reg [31 : 0] v__h3149; + reg [31 : 0] v__h2186; + reg [31 : 0] v__h1178; + reg [31 : 0] v__h1172; + reg [31 : 0] v__h2180; + reg [31 : 0] v__h2219; + reg [31 : 0] v__h2762; + reg [31 : 0] v__h2868; + reg [31 : 0] v__h2983; + reg [31 : 0] v__h3103; + reg [31 : 0] v__h3143; + // synopsys translate_on + // remaining internal signals - wire [31 : 0] haltsum__h505, - virt_rg_dmcontrol__h670, - virt_rg_dmstatus__h543; - wire write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72, - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77; + wire [31 : 0] haltsum__h699, + virt_rg_dmcontrol__h930, + virt_rg_dmstatus__h805; + wire NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93, + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53, + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57; // value method dmactive assign dmactive = rg_dmcontrol_dmactive ; @@ -265,12 +365,12 @@ module mkDM_Run_Control(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_verbosity or - virt_rg_dmcontrol__h670 or virt_rg_dmstatus__h543 or haltsum__h505) + virt_rg_dmcontrol__h930 or virt_rg_dmstatus__h805 or haltsum__h699) begin case (av_read_dm_addr) - 7'h10: av_read = virt_rg_dmcontrol__h670; - 7'h11: av_read = virt_rg_dmstatus__h543; - 7'h13, 7'h40: av_read = haltsum__h505; + 7'h10: av_read = virt_rg_dmcontrol__h930; + 7'h11: av_read = virt_rg_dmstatus__h805; + 7'h13, 7'h40: av_read = haltsum__h699; default: av_read = { 28'd0, rg_verbosity }; endcase end @@ -280,19 +380,27 @@ module mkDM_Run_Control(CLK, // action method write assign RDY_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && - f_hart0_other_reqs$FULL_N ; - assign CAN_FIRE_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && + (rg_dmstatus_allunavail || + f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && + f_hart0_run_halt_reqs$FULL_N) && f_hart0_other_reqs$FULL_N ; + assign CAN_FIRE_write = RDY_write ; assign WILL_FIRE_write = EN_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign CAN_FIRE_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = f_hart0_reset_reqs$D_OUT ; + assign RDY_hart0_reset_client_request_get = f_hart0_reset_reqs$EMPTY_N ; + assign CAN_FIRE_hart0_reset_client_request_get = + f_hart0_reset_reqs$EMPTY_N ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = f_hart0_reset_rsps$FULL_N ; + assign CAN_FIRE_hart0_reset_client_response_put = + f_hart0_reset_rsps$FULL_N ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = f_hart0_run_halt_reqs$D_OUT ; @@ -317,10 +425,18 @@ module mkDM_Run_Control(CLK, assign CAN_FIRE_hart0_get_other_req_get = f_hart0_other_reqs$EMPTY_N ; assign WILL_FIRE_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign CAN_FIRE_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = f_ndm_reset_reqs$D_OUT ; + assign RDY_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign CAN_FIRE_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign CAN_FIRE_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule f_hart0_other_reqs FIFO2 #(.width(32'd4), .guarded(32'd1)) f_hart0_other_reqs(.RST(RST_N), @@ -334,13 +450,26 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_other_reqs$EMPTY_N)); // submodule f_hart0_reset_reqs - FIFO20 #(.guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_hart0_reset_reqs$ENQ), - .DEQ(f_hart0_reset_reqs$DEQ), - .CLR(f_hart0_reset_reqs$CLR), - .FULL_N(f_hart0_reset_reqs$FULL_N), - .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_reqs$D_IN), + .ENQ(f_hart0_reset_reqs$ENQ), + .DEQ(f_hart0_reset_reqs$DEQ), + .CLR(f_hart0_reset_reqs$CLR), + .D_OUT(f_hart0_reset_reqs$D_OUT), + .FULL_N(f_hart0_reset_reqs$FULL_N), + .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + + // submodule f_hart0_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_rsps$D_IN), + .ENQ(f_hart0_reset_rsps$ENQ), + .DEQ(f_hart0_reset_rsps$DEQ), + .CLR(f_hart0_reset_rsps$CLR), + .D_OUT(f_hart0_reset_rsps$D_OUT), + .FULL_N(f_hart0_reset_rsps$FULL_N), + .EMPTY_N(f_hart0_reset_rsps$EMPTY_N)); // submodule f_hart0_run_halt_reqs FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_run_halt_reqs(.RST(RST_N), @@ -365,27 +494,52 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_run_halt_rsps$EMPTY_N)); // submodule f_ndm_reset_reqs - FIFO20 #(.guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_ndm_reset_reqs$ENQ), - .DEQ(f_ndm_reset_reqs$DEQ), - .CLR(f_ndm_reset_reqs$CLR), - .FULL_N(f_ndm_reset_reqs$FULL_N), - .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_reqs$D_IN), + .ENQ(f_ndm_reset_reqs$ENQ), + .DEQ(f_ndm_reset_reqs$DEQ), + .CLR(f_ndm_reset_reqs$CLR), + .D_OUT(f_ndm_reset_reqs$D_OUT), + .FULL_N(f_ndm_reset_reqs$FULL_N), + .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + + // submodule f_ndm_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_rsps$D_IN), + .ENQ(f_ndm_reset_rsps$ENQ), + .DEQ(f_ndm_reset_rsps$DEQ), + .CLR(f_ndm_reset_rsps$CLR), + .D_OUT(f_ndm_reset_rsps$D_OUT), + .FULL_N(f_ndm_reset_rsps$FULL_N), + .EMPTY_N(f_ndm_reset_rsps$EMPTY_N)); + + // rule RL_rl_hart0_reset_rsp + assign CAN_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + + // rule RL_rl_ndm_reset_rsp + assign CAN_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; // rule RL_rl_hart0_run_rsp - assign CAN_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; - assign WILL_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; + assign CAN_FIRE_RL_rl_hart0_run_rsp = + f_hart0_run_halt_rsps$EMPTY_N && !f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_run_rsp = CAN_FIRE_RL_rl_hart0_run_rsp ; // inputs to muxes for submodule ports assign MUX_rg_dmstatus_allresumeack$write_1__SEL_2 = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT ; + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT ; assign MUX_rg_dmstatus_allresumeack$write_1__SEL_3 = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 ; - assign MUX_rg_hart0_running$write_1__SEL_3 = EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) ; + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 ; + assign MUX_rg_dmstatus_allunavail$write_1__SEL_3 = + EN_write && + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 ; + assign MUX_rg_hart0_hasreset$write_1__SEL_3 = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 ; assign MUX_rg_verbosity$write_1__SEL_2 = EN_write && write_dm_addr == 7'h60 ; @@ -422,26 +576,47 @@ module mkDM_Run_Control(CLK, default: rg_dmstatus_allresumeack$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_dmstatus_allresumeack$EN = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT || + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT || + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 || + EN_reset ; + + // register rg_dmstatus_allunavail + assign rg_dmstatus_allunavail$D_IN = + !EN_reset && !f_ndm_reset_rsps$EMPTY_N ; + assign rg_dmstatus_allunavail$EN = EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 || + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 || + f_ndm_reset_rsps$EMPTY_N || + EN_reset ; + + // register rg_hart0_hasreset + assign rg_hart0_hasreset$D_IN = !EN_reset && !f_hart0_reset_rsps$EMPTY_N ; + assign rg_hart0_hasreset$EN = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_hart0_running always@(EN_reset or - f_hart0_run_halt_rsps$EMPTY_N or - f_hart0_run_halt_rsps$D_OUT or MUX_rg_hart0_running$write_1__SEL_3) + WILL_FIRE_RL_rl_hart0_run_rsp or + f_hart0_run_halt_rsps$D_OUT or + f_ndm_reset_rsps$EMPTY_N or + f_ndm_reset_rsps$D_OUT or + f_hart0_reset_rsps$EMPTY_N or f_hart0_reset_rsps$D_OUT) case (1'b1) EN_reset: rg_hart0_running$D_IN = 1'd1; - f_hart0_run_halt_rsps$EMPTY_N: + WILL_FIRE_RL_rl_hart0_run_rsp: rg_hart0_running$D_IN = f_hart0_run_halt_rsps$D_OUT; - MUX_rg_hart0_running$write_1__SEL_3: rg_hart0_running$D_IN = 1'd1; + f_ndm_reset_rsps$EMPTY_N: rg_hart0_running$D_IN = f_ndm_reset_rsps$D_OUT; + f_hart0_reset_rsps$EMPTY_N: + rg_hart0_running$D_IN = f_hart0_reset_rsps$D_OUT; default: rg_hart0_running$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_hart0_running$EN = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) || - f_hart0_run_halt_rsps$EMPTY_N || + f_ndm_reset_rsps$EMPTY_N || WILL_FIRE_RL_rl_hart0_run_rsp || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_verbosity @@ -455,66 +630,123 @@ module mkDM_Run_Control(CLK, assign f_hart0_other_reqs$CLR = 1'b0 ; // submodule f_hart0_reset_reqs - assign f_hart0_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - write_dm_word[29] ; - assign f_hart0_reset_reqs$DEQ = EN_hart0_get_reset_req_get ; + assign f_hart0_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_hart0_reset_reqs$ENQ = MUX_rg_hart0_hasreset$write_1__SEL_3 ; + assign f_hart0_reset_reqs$DEQ = EN_hart0_reset_client_request_get ; assign f_hart0_reset_reqs$CLR = EN_reset ; + // submodule f_hart0_reset_rsps + assign f_hart0_reset_rsps$D_IN = hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$ENQ = EN_hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$DEQ = f_hart0_reset_rsps$EMPTY_N ; + assign f_hart0_reset_rsps$CLR = EN_reset ; + // submodule f_hart0_run_halt_reqs assign f_hart0_run_halt_reqs$D_IN = write_dm_word[30] && !rg_hart0_running ; assign f_hart0_run_halt_reqs$ENQ = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 ; + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 ; assign f_hart0_run_halt_reqs$DEQ = EN_hart0_client_run_halt_request_get ; assign f_hart0_run_halt_reqs$CLR = EN_reset ; // submodule f_hart0_run_halt_rsps assign f_hart0_run_halt_rsps$D_IN = hart0_client_run_halt_response_put ; assign f_hart0_run_halt_rsps$ENQ = EN_hart0_client_run_halt_response_put ; - assign f_hart0_run_halt_rsps$DEQ = f_hart0_run_halt_rsps$EMPTY_N ; + assign f_hart0_run_halt_rsps$DEQ = CAN_FIRE_RL_rl_hart0_run_rsp ; assign f_hart0_run_halt_rsps$CLR = EN_reset ; // submodule f_ndm_reset_reqs - assign f_ndm_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] ; - assign f_ndm_reset_reqs$DEQ = EN_get_ndm_reset_req_get ; + assign f_ndm_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_ndm_reset_reqs$ENQ = MUX_rg_dmstatus_allunavail$write_1__SEL_3 ; + assign f_ndm_reset_reqs$DEQ = EN_ndm_reset_client_request_get ; assign f_ndm_reset_reqs$CLR = EN_reset ; + // submodule f_ndm_reset_rsps + assign f_ndm_reset_rsps$D_IN = ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$ENQ = EN_ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$DEQ = f_ndm_reset_rsps$EMPTY_N ; + assign f_ndm_reset_rsps$CLR = EN_reset ; + // remaining internal signals - assign haltsum__h505 = { 31'h0, !rg_hart0_running } ; - assign virt_rg_dmcontrol__h670 = + assign NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 = + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + (!write_dm_word[31] || !write_dm_word[30]) && + (write_dm_word[30] && !rg_hart0_running || + write_dm_word[31] && rg_hart0_running) ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[31] && + write_dm_word[30] && + !rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[30] && + write_dm_word[31] && + rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + write_dm_word[29] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[26] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[25:16] != 10'd0 ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[31] && + write_dm_word[30] ; + assign haltsum__h699 = { 31'h0, !rg_hart0_running } ; + assign virt_rg_dmcontrol__h930 = { 2'b0, rg_dmcontrol_hartreset, 27'd0, rg_dmcontrol_ndmreset, rg_dmcontrol_dmactive } ; - assign virt_rg_dmstatus__h543 = - { 14'b0, + assign virt_rg_dmstatus__h805 = + { 12'd0, + rg_hart0_hasreset, + rg_hart0_hasreset, rg_dmstatus_allresumeack, rg_dmstatus_allresumeack, - 4'd0, + 2'd0, + rg_dmstatus_allunavail, + rg_dmstatus_allunavail, rg_hart0_running, rg_hart0_running, !rg_hart0_running, !rg_hart0_running, 8'd130 } ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 = + assign write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 = write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && + !write_dm_word[1] ; + assign write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57 = + write_dm_word[0] && !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && !write_dm_word[1] && - !write_dm_word[29] && - (!write_dm_word[31] || !write_dm_word[30]) && - (write_dm_word[30] && !rg_hart0_running || - write_dm_word[31] && rg_hart0_running) ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 = - write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[31] && - write_dm_word[30] && - !rg_hart0_running ; + write_dm_word[29] ; // handling of inlined registers @@ -523,12 +755,16 @@ module mkDM_Run_Control(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (rg_dmcontrol_dmactive$EN) rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_dmactive$D_IN; + if (rg_dmstatus_allunavail$EN) + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY + rg_dmstatus_allunavail$D_IN; end if (rg_dmcontrol_haltreq$EN) rg_dmcontrol_haltreq <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_haltreq$D_IN; @@ -541,6 +777,8 @@ module mkDM_Run_Control(CLK, if (rg_dmstatus_allresumeack$EN) rg_dmstatus_allresumeack <= `BSV_ASSIGNMENT_DELAY rg_dmstatus_allresumeack$D_IN; + if (rg_hart0_hasreset$EN) + rg_hart0_hasreset <= `BSV_ASSIGNMENT_DELAY rg_hart0_hasreset$D_IN; if (rg_hart0_running$EN) rg_hart0_running <= `BSV_ASSIGNMENT_DELAY rg_hart0_running$D_IN; if (rg_verbosity$EN) @@ -557,6 +795,8 @@ module mkDM_Run_Control(CLK, rg_dmcontrol_hartreset = 1'h0; rg_dmcontrol_ndmreset = 1'h0; rg_dmstatus_allresumeack = 1'h0; + rg_dmstatus_allunavail = 1'h0; + rg_hart0_hasreset = 1'h0; rg_hart0_running = 1'h0; rg_verbosity = 4'hA; end @@ -571,75 +811,117 @@ module mkDM_Run_Control(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1]) - $display("DM_Run_Control.write: dmcontrol 0x%08h: ndmreset=1: resetting platform", + rg_dmstatus_allunavail) + begin + v__h2225 = $stime; + #0; + end + v__h2219 = v__h2225 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + rg_dmstatus_allunavail) + $display("%0d: %m.dmcontrol_write 0x%0h: ndm reset in progress; ignoring this write", + v__h2219, write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - write_dm_word); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" WARNING: %m.dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display(" Both ndmreset (bit 1) and hartreset (bit 29) are asserted"); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" Both ndmreset [1] and hartreset [29] are asserted"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) $display(" ndmreset has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[26]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: 'hasel' is not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + begin + v__h2768 = $stime; + #0; + end + v__h2762 = v__h2768 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hasel is not supported", + v__h2762, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[25:16] != 10'd0) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: hartsel 0x%0h not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + begin + v__h2874 = $stime; + #0; + end + v__h2868 = v__h2874 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hartsel 0x%0h not supported", + v__h2868, write_dm_word, write_dm_word[25:16]); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: haltreq=1 and resumereq=1", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + begin + v__h2989 = $stime; + #0; + end + v__h2983 = v__h2989 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: haltreq=1 and resumereq=1", + v__h2983, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) $display(" This behavior is 'undefined' in the spec; ignoring"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77) - $display("DM_Run_Control.write: hart0 resume request"); + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + begin + v__h3109 = $stime; + #0; + end + v__h3103 = v__h3109 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[30] && - write_dm_word[31] && - rg_hart0_running) - $display("DM_Run_Control.write: hart0 halt request"); + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + $display("%0d: %m.dmcontrol_write: hart0 resume request", v__h3103); + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + begin + v__h3149 = $stime; + #0; + end + v__h3143 = v__h3149 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + $display("%0d: %m.dmcontrol_write: hart0 halt request", v__h3143); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) - $display("DM_Run_Control.write: dmcontrol 0x%08h (dmactive=0): resetting Debug Module", + begin + v__h2186 = $stime; + #0; + end + v__h2180 = v__h2186 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) + $display("%0d: %m.dmcontrol_write 0x%08h (dmactive=0): resetting Debug Module", + v__h2180, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[1]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -652,7 +934,7 @@ module mkDM_Run_Control(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -663,11 +945,21 @@ module mkDM_Run_Control(CLK, write_dm_word[29]) $display(" dmactive has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 running"); + if (f_ndm_reset_rsps$EMPTY_N) + begin + v__h1178 = $stime; + #0; + end + v__h1172 = v__h1178 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && !f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 halted"); + if (f_ndm_reset_rsps$EMPTY_N) + $write("%0d: %m.rl_ndm_reset_rsp: hart running = ", v__h1172); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && f_ndm_reset_rsps$D_OUT) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && !f_ndm_reset_rsps$D_OUT) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) if (f_ndm_reset_rsps$EMPTY_N) $write("\n"); end // synopsys translate_on endmodule // mkDM_Run_Control diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v index 8a04bd0..6b4f0c3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v @@ -10,7 +10,7 @@ // av_read O 32 // RDY_av_read O 1 // RDY_write O 1 -// master_awvalid O 1 +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -21,13 +21,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -38,7 +37,7 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 @@ -60,9 +59,7 @@ // EN_av_read I 1 // // Combinational paths from inputs to outputs: -// (master_awready, master_wready, master_arready) -> RDY_write -// master_arready -> RDY_av_read -// (master_arready, av_read_dm_addr) -> av_read +// av_read_dm_addr -> av_read // // @@ -121,8 +118,6 @@ module mkDM_System_Bus(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -228,9 +223,6 @@ module mkDM_System_Bus(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -312,8 +304,7 @@ module mkDM_System_Bus(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_av_read, @@ -328,66 +319,6 @@ module mkDM_System_Bus(CLK, master_wlast, master_wvalid; - // inlined wires - wire master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - wire [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - wire [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - // register rg_sb_state reg [1 : 0] rg_sb_state; wire [1 : 0] rg_sb_state$D_IN; @@ -440,6 +371,46 @@ module mkDM_System_Bus(CLK, reg [31 : 0] rg_sbdata0$D_IN; wire rg_sbdata0$EN; + // ports of submodule master_xactor_f_rd_addr + wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT; + wire master_xactor_f_rd_addr$CLR, + master_xactor_f_rd_addr$DEQ, + master_xactor_f_rd_addr$EMPTY_N, + master_xactor_f_rd_addr$ENQ, + master_xactor_f_rd_addr$FULL_N; + + // ports of submodule master_xactor_f_rd_data + wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT; + wire master_xactor_f_rd_data$CLR, + master_xactor_f_rd_data$DEQ, + master_xactor_f_rd_data$EMPTY_N, + master_xactor_f_rd_data$ENQ, + master_xactor_f_rd_data$FULL_N; + + // ports of submodule master_xactor_f_wr_addr + wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT; + wire master_xactor_f_wr_addr$CLR, + master_xactor_f_wr_addr$DEQ, + master_xactor_f_wr_addr$EMPTY_N, + master_xactor_f_wr_addr$ENQ, + master_xactor_f_wr_addr$FULL_N; + + // ports of submodule master_xactor_f_wr_data + wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; + wire master_xactor_f_wr_data$CLR, + master_xactor_f_wr_data$DEQ, + master_xactor_f_wr_data$EMPTY_N, + master_xactor_f_wr_data$ENQ, + master_xactor_f_wr_data$FULL_N; + + // ports of submodule master_xactor_f_wr_resp + wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT; + wire master_xactor_f_wr_resp$CLR, + master_xactor_f_wr_resp$DEQ, + master_xactor_f_wr_resp$EMPTY_N, + master_xactor_f_wr_resp$ENQ, + master_xactor_f_wr_resp$FULL_N; + // rule scheduling signals wire CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, @@ -466,9 +437,9 @@ module mkDM_System_Bus(CLK, reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2, MUX_rg_sbaddress1$write_1__VAL_2; reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4; - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, + wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1, + MUX_master_xactor_f_rd_addr$enq_1__VAL_2; + wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1, MUX_rg_sbaddress0$write_1__SEL_2, MUX_rg_sbaddress0$write_1__SEL_3, MUX_rg_sbaddress1$write_1__SEL_2, @@ -485,45 +456,45 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79, - wrd_wdata__h5118; - reg [7 : 0] wrd_wstrb__h5119; - reg [2 : 0] x__h3284, x__h4989; - wire [63 : 0] _theResult___fst__h5027, - addr64__h4331, - result__h1836, - result__h1866, - result__h1893, - result__h1920, - result__h1947, - result__h1974, - result__h2001, - result__h2028, - result__h2073, - result__h2100, - result__h2127, - result__h2154, - result__h2195, - result__h2222, + wrd_wdata__h4397; + reg [7 : 0] wrd_wstrb__h4398; + reg [2 : 0] x__h2654, x__h4302; + wire [63 : 0] _theResult___fst__h4340, + addr64__h3701, + result__h1250, + result__h1280, + result__h1307, + result__h1334, + result__h1361, + result__h1388, + result__h1415, + result__h1442, + result__h1487, + result__h1514, + result__h1541, + result__h1568, + result__h1609, + result__h1636, rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104, - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300, - sbaddress__h1228, - word64__h4971; - wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311, - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302, - v__h2728, - v__h2862; - wire [7 : 0] strobe64__h5026, strobe64__h5029, strobe64__h5032; - wire [5 : 0] shift_bits__h4974; + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299, + sbaddress__h638, + word64__h4284; + wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310, + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301, + v__h2132, + v__h2266; + wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345; + wire [5 : 0] shift_bits__h4287; wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317, + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316, rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95, - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279, - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327; + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278, + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326; // action method reset assign RDY_reset = 1'd1 ; @@ -532,13 +503,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h2728 or rg_sbaddress0 or rg_sbaddress1 or v__h2862) + v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266) begin case (av_read_dm_addr) - 7'h38: av_read = v__h2728; + 7'h38: av_read = v__h2132; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h2862; + 7'h3C: av_read = v__h2266; default: av_read = 32'd0; endcase end @@ -546,7 +517,7 @@ module mkDM_System_Bus(CLK, rg_sb_state == 2'd0 && (rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadondata || - !master_xactor_crg_rd_addr_full$port2__read) ; + master_xactor_f_rd_addr$FULL_N) ; assign CAN_FIRE_av_read = RDY_av_read ; assign WILL_FIRE_av_read = EN_av_read ; @@ -556,64 +527,61 @@ module mkDM_System_Bus(CLK, (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadonaddr || - !master_xactor_crg_rd_addr_full$port2__read) && + master_xactor_f_rd_addr$FULL_N) && (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; + master_xactor_f_wr_addr$FULL_N && + master_xactor_f_wr_data$FULL_N) ; assign WILL_FIRE_write = EN_write ; // value method master_m_awvalid - assign master_awvalid = master_xactor_crg_wr_addr_full ; + assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ; // value method master_m_awid - assign master_awid = master_xactor_rg_wr_addr[96:93] ; + assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ; // value method master_m_awaddr - assign master_awaddr = master_xactor_rg_wr_addr[92:29] ; + assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ; // value method master_m_awlen - assign master_awlen = master_xactor_rg_wr_addr[28:21] ; + assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ; // value method master_m_awsize - assign master_awsize = master_xactor_rg_wr_addr[20:18] ; + assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ; // value method master_m_awburst - assign master_awburst = master_xactor_rg_wr_addr[17:16] ; + assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ; // value method master_m_awlock - assign master_awlock = master_xactor_rg_wr_addr[15] ; + assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ; // value method master_m_awcache - assign master_awcache = master_xactor_rg_wr_addr[14:11] ; + assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ; // value method master_m_awprot - assign master_awprot = master_xactor_rg_wr_addr[10:8] ; + assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ; // value method master_m_awqos - assign master_awqos = master_xactor_rg_wr_addr[7:4] ; + assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ; // value method master_m_awregion - assign master_awregion = master_xactor_rg_wr_addr[3:0] ; + assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ; // action method master_m_awready assign CAN_FIRE_master_m_awready = 1'd1 ; assign WILL_FIRE_master_m_awready = 1'd1 ; // value method master_m_wvalid - assign master_wvalid = master_xactor_crg_wr_data_full ; - - // value method master_m_wid - assign master_wid = master_xactor_rg_wr_data[76:73] ; + assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; // value method master_m_wdata - assign master_wdata = master_xactor_rg_wr_data[72:9] ; + assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; // value method master_m_wstrb - assign master_wstrb = master_xactor_rg_wr_data[8:1] ; + assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ; // value method master_m_wlast - assign master_wlast = master_xactor_rg_wr_data[0] ; + assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ; // action method master_m_wready assign CAN_FIRE_master_m_wready = 1'd1 ; @@ -624,40 +592,40 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_bvalid = 1'd1 ; // value method master_m_bready - assign master_bready = 1'b1 ; + assign master_bready = master_xactor_f_wr_resp$FULL_N ; // value method master_m_arvalid - assign master_arvalid = master_xactor_crg_rd_addr_full ; + assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ; // value method master_m_arid - assign master_arid = master_xactor_rg_rd_addr[96:93] ; + assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ; // value method master_m_araddr - assign master_araddr = master_xactor_rg_rd_addr[92:29] ; + assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ; // value method master_m_arlen - assign master_arlen = master_xactor_rg_rd_addr[28:21] ; + assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ; // value method master_m_arsize - assign master_arsize = master_xactor_rg_rd_addr[20:18] ; + assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ; // value method master_m_arburst - assign master_arburst = master_xactor_rg_rd_addr[17:16] ; + assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ; // value method master_m_arlock - assign master_arlock = master_xactor_rg_rd_addr[15] ; + assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ; // value method master_m_arcache - assign master_arcache = master_xactor_rg_rd_addr[14:11] ; + assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ; // value method master_m_arprot - assign master_arprot = master_xactor_rg_rd_addr[10:8] ; + assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ; // value method master_m_arqos - assign master_arqos = master_xactor_rg_rd_addr[7:4] ; + assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ; // value method master_m_arregion - assign master_arregion = master_xactor_rg_rd_addr[3:0] ; + assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ; // action method master_m_arready assign CAN_FIRE_master_m_arready = 1'd1 ; @@ -668,20 +636,79 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_rvalid = 1'd1 ; // value method master_m_rready - assign master_rready = !master_xactor_crg_rd_data_full$port2__read ; + assign master_rready = master_xactor_f_rd_data$FULL_N ; + + // submodule master_xactor_f_rd_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_addr$D_IN), + .ENQ(master_xactor_f_rd_addr$ENQ), + .DEQ(master_xactor_f_rd_addr$DEQ), + .CLR(master_xactor_f_rd_addr$CLR), + .D_OUT(master_xactor_f_rd_addr$D_OUT), + .FULL_N(master_xactor_f_rd_addr$FULL_N), + .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N)); + + // submodule master_xactor_f_rd_data + FIFO2 #(.width(32'd71), + .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_data$D_IN), + .ENQ(master_xactor_f_rd_data$ENQ), + .DEQ(master_xactor_f_rd_data$DEQ), + .CLR(master_xactor_f_rd_data$CLR), + .D_OUT(master_xactor_f_rd_data$D_OUT), + .FULL_N(master_xactor_f_rd_data$FULL_N), + .EMPTY_N(master_xactor_f_rd_data$EMPTY_N)); + + // submodule master_xactor_f_wr_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_addr$D_IN), + .ENQ(master_xactor_f_wr_addr$ENQ), + .DEQ(master_xactor_f_wr_addr$DEQ), + .CLR(master_xactor_f_wr_addr$CLR), + .D_OUT(master_xactor_f_wr_addr$D_OUT), + .FULL_N(master_xactor_f_wr_addr$FULL_N), + .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); + + // submodule master_xactor_f_wr_data + FIFO2 #(.width(32'd73), + .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_data$D_IN), + .ENQ(master_xactor_f_wr_data$ENQ), + .DEQ(master_xactor_f_wr_data$DEQ), + .CLR(master_xactor_f_wr_data$CLR), + .D_OUT(master_xactor_f_wr_data$D_OUT), + .FULL_N(master_xactor_f_wr_data$FULL_N), + .EMPTY_N(master_xactor_f_wr_data$EMPTY_N)); + + // submodule master_xactor_f_wr_resp + FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_resp$D_IN), + .ENQ(master_xactor_f_wr_resp$ENQ), + .DEQ(master_xactor_f_wr_resp$DEQ), + .CLR(master_xactor_f_wr_resp$CLR), + .D_OUT(master_xactor_f_wr_resp$D_OUT), + .FULL_N(master_xactor_f_wr_resp$FULL_N), + .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N)); // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = - master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 && + master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 && rg_sbcs_sberror == 3'd0 ; assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ; // rule RL_rl_sb_write_response - assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; - assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; + assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; + assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; // inputs to muxes for submodule ports - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = + assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ; assign MUX_rg_sbaddress0$write_1__SEL_2 = @@ -699,50 +726,50 @@ module mkDM_System_Bus(CLK, ((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 || + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 || write_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_1 = - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 ; + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_3 = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 ; + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_4 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ; assign MUX_rg_sbdata0$write_1__SEL_3 = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, sbaddress__h1228, 8'd0, x__h3284, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, addr64__h4331, 8'd0, x__h3284, 18'd65536 } ; + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 = + { 4'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 = + { 4'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311) + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress0$write_1__VAL_2 = - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311; + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310; default: MUX_rg_sbaddress0$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0]; endcase end always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302) + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress1$write_1__VAL_2 = - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302; + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301; default: MUX_rg_sbaddress1$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32]; endcase @@ -755,100 +782,6 @@ module mkDM_System_Bus(CLK, endcase end - // inlined wires - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full && master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full && master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full && master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_rl_sb_read_finish && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - master_rvalid && !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - assign master_xactor_rg_wr_addr$D_IN = - { 4'd0, sbaddress__h1228, 8'd0, x__h4989, 18'd65536 } ; - assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_data - assign master_xactor_rg_wr_data$D_IN = - { 4'd0, wrd_wdata__h5118, wrd_wstrb__h5119, 1'd1 } ; - assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_rg_wr_resp$EN = master_bvalid ; - // register rg_sb_state assign rg_sb_state$D_IN = (EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ; @@ -856,7 +789,7 @@ module mkDM_System_Bus(CLK, EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 || + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; @@ -904,27 +837,27 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - sbaddress__h1228 : - addr64__h4331 ; + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + sbaddress__h638 : + addr64__h3701 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; // register rg_sbcs_sbaccess assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ; assign rg_sbcs_sbaccess$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbautoincrement assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ; assign rg_sbcs_sbautoincrement$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbbusyerror @@ -941,7 +874,7 @@ module mkDM_System_Bus(CLK, assign rg_sbcs_sbbusyerror$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 || EN_reset ; // register rg_sbcs_sberror @@ -960,25 +893,25 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbcs_sberror$EN = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 || - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 || + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 || + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 || EN_reset ; // register rg_sbcs_sbreadonaddr assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ; assign rg_sbcs_sbreadonaddr$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbreadondata assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ; assign rg_sbcs_sbreadondata$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbdata0 @@ -996,42 +929,93 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbdata0$EN = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 || + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; + // submodule master_xactor_f_rd_addr + assign master_xactor_f_rd_addr$D_IN = + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + MUX_master_xactor_f_rd_addr$enq_1__VAL_1 : + MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ; + assign master_xactor_f_rd_addr$ENQ = + EN_av_read && av_read_dm_addr == 7'h3C && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || + EN_write && write_dm_addr == 7'h39 && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; + assign master_xactor_f_rd_addr$DEQ = + master_xactor_f_rd_addr$EMPTY_N && master_arready ; + assign master_xactor_f_rd_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_rd_data + assign master_xactor_f_rd_data$D_IN = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_f_rd_data$ENQ = + master_rvalid && master_xactor_f_rd_data$FULL_N ; + assign master_xactor_f_rd_data$DEQ = + master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 && + rg_sbcs_sberror == 3'd0 ; + assign master_xactor_f_rd_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_addr + assign master_xactor_f_wr_addr$D_IN = + { 4'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ; + assign master_xactor_f_wr_addr$ENQ = + EN_write && + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign master_xactor_f_wr_addr$DEQ = + master_xactor_f_wr_addr$EMPTY_N && master_awready ; + assign master_xactor_f_wr_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_data + assign master_xactor_f_wr_data$D_IN = + { wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ; + assign master_xactor_f_wr_data$ENQ = + EN_write && + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign master_xactor_f_wr_data$DEQ = + master_xactor_f_wr_data$EMPTY_N && master_wready ; + assign master_xactor_f_wr_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_resp + assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ; + assign master_xactor_f_wr_resp$ENQ = + master_bvalid && master_xactor_f_wr_resp$FULL_N ; + assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ; + assign master_xactor_f_wr_resp$CLR = 1'b0 ; + // remaining internal signals - assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311 = + assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 = rg_sbcs_sbreadonaddr ? (rg_sbcs_sbautoincrement ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[31:0] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] : write_dm_word) : write_dm_word ; - assign IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302 = + assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 = (write_dm_addr == 7'h39) ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[63:32] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] : write_dm_word ; - assign _theResult___fst__h5027 = word64__h4971 << shift_bits__h4974 ; - assign addr64__h4331 = { rg_sbaddress1, write_dm_word } ; - assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; + assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ; + assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ; + assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ; + assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ; + assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ; + assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ; + assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ; + assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ; + assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ; + assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ; + assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ; + assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ; + assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ; + assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ; + assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ; + assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ; assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadondata ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 = + assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; @@ -1040,21 +1024,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbautoincrement ; assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 = - sbaddress__h1228 + + sbaddress__h638 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300 = - addr64__h4331 + + assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 = + addr64__h3701 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 = + assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h4974 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h5026 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h5029 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h5032 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h2728 = + assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h2132 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1064,71 +1048,71 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h2862 = + assign v__h2266 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h4971 = { 32'd0, write_dm_word } ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 = + assign word64__h4284 = { 32'd0, write_dm_word } ; + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && write_dm_word[19:17] != 3'd4 && write_dm_word[19:17] != 3'd3 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 = - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 = + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || (write_dm_addr == 7'h39 || write_dm_addr == 7'h3A || write_dm_addr == 7'h3C) && rg_sb_state != 2'd0 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && rg_sbcs_sbbusyerror && !write_dm_word[22] ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && (write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ; - assign write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 = + assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 = write_dm_addr == 7'h3C && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 ; always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: x__h3284 = rg_sbcs_sbaccess; - default: x__h3284 = 3'b011; + 3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess; + default: x__h2654 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2, 3'd3: x__h4989 = rg_sbcs_sbaccess; - default: x__h4989 = 3'b111; + 3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess; + default: x__h4302 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h5026 or strobe64__h5029 or strobe64__h5032) + strobe64__h4339 or strobe64__h4342 or strobe64__h4345) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h5119 = strobe64__h5026; - 3'd1: wrd_wstrb__h5119 = strobe64__h5029; - 3'd2: wrd_wstrb__h5119 = strobe64__h5032; - 3'd3: wrd_wstrb__h5119 = 8'b11111111; - default: wrd_wstrb__h5119 = 8'd0; + 3'd0: wrd_wstrb__h4398 = strobe64__h4339; + 3'd1: wrd_wstrb__h4398 = strobe64__h4342; + 3'd2: wrd_wstrb__h4398 = strobe64__h4345; + 3'd3: wrd_wstrb__h4398 = 8'b11111111; + default: wrd_wstrb__h4398 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h4971 or _theResult___fst__h5027) + always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h5118 = _theResult___fst__h5027; - default: wrd_wdata__h5118 = word64__h4971; + 3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340; + default: wrd_wdata__h4397 = word64__h4284; endcase end always@(rg_sbcs_sbaccess) @@ -1143,68 +1127,68 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h1836 or - result__h1866 or - result__h1893 or - result__h1920 or - result__h1947 or result__h1974 or result__h2001 or result__h2028) + result__h1250 or + result__h1280 or + result__h1307 or + result__h1334 or + result__h1361 or result__h1388 or result__h1415 or result__h1442) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1836; + result__h1250; 3'h1: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1866; + result__h1280; 3'h2: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1893; + result__h1307; 3'h3: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1920; + result__h1334; 3'h4: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1947; + result__h1361; 3'h5: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1974; + result__h1388; 3'h6: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2001; + result__h1415; 3'h7: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2028; + result__h1442; endcase end always@(rg_sbaddress_reading or - result__h2073 or result__h2100 or result__h2127 or result__h2154) + result__h1487 or result__h1514 or result__h1541 or result__h1568) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2073; + result__h1487; 3'h2: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2100; + result__h1514; 3'h4: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2127; + result__h1541; 3'h6: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2154; + result__h1568; default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h2195 or result__h2222) + always@(rg_sbaddress_reading or result__h1609 or result__h1636) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2195; + result__h1609; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2222; + result__h1636; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0; endcase end @@ -1212,7 +1196,7 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or - rg_sbaddress_reading or master_xactor_rg_rd_data) + rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT) begin case (rg_sbcs_sbaccess) 3'd0: @@ -1227,7 +1211,7 @@ module mkDM_System_Bus(CLK, 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = (rg_sbaddress_reading[2:0] == 3'h0) ? - master_xactor_rg_rd_data[66:3] : + master_xactor_f_rd_data$D_OUT[66:3] : 64'd0; default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = 64'd0; @@ -1240,51 +1224,16 @@ module mkDM_System_Bus(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0; end else begin - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_sbaddress0$EN) + if (rg_sbaddress0$EN) rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN; if (rg_sbaddress1$EN) rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN; end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN; if (rg_sbaddress_reading$EN) rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN; @@ -1309,16 +1258,6 @@ module mkDM_System_Bus(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; rg_sb_state = 2'h2; rg_sbaddress0 = 32'hAAAAAAAA; rg_sbaddress1 = 32'hAAAAAAAA; @@ -1484,24 +1423,24 @@ module mkDM_System_Bus(CLK, $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" ERROR: existing sbbusyerror (%0d) is not being cleared.", rg_sbcs_sbbusyerror); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" ERROR: sbaccess "); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && @@ -1517,7 +1456,7 @@ module mkDM_System_Bus(CLK, $write("DM_SBACCESS_128_BIT"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h38 && @@ -1658,61 +1597,61 @@ module mkDM_System_Bus(CLK, $write("] <= 0x%08h; addr not supported", write_dm_word, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(" rdr = "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[70:67]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[66:3]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[2:1]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + master_xactor_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + !master_xactor_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index bcb67ff..66dbc3c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -10,7 +10,9 @@ // dmi_read_data O 32 // RDY_dmi_read_data O 1 // RDY_dmi_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg @@ -25,8 +27,10 @@ // hart0_csr_mem_client_request_get O 77 reg // RDY_hart0_csr_mem_client_request_get O 1 reg // RDY_hart0_csr_mem_client_response_put O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg -// master_awvalid O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -37,13 +41,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -54,16 +57,18 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // dmi_read_addr_dm_addr I 7 // dmi_write_dm_addr I 7 // dmi_write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg // hart0_gpr_mem_client_response_put I 65 reg // hart0_fpr_mem_client_response_put I 65 reg // hart0_csr_mem_client_response_put I 65 reg +// ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 // master_bvalid I 1 @@ -77,28 +82,24 @@ // master_rlast I 1 reg // EN_dmi_read_addr I 1 // EN_dmi_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 // EN_hart0_gpr_mem_client_response_put I 1 // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_dmi_read_data I 1 +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 // EN_hart0_gpr_mem_client_request_get I 1 // EN_hart0_fpr_mem_client_request_get I 1 // EN_hart0_csr_mem_client_request_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr) -> RDY_dmi_read_data -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr, -// EN_dmi_read_data) -> dmi_read_data -// (master_awready, master_wready, master_arready) -> RDY_dmi_write +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -131,8 +132,13 @@ module mkDebug_Module(CLK, EN_dmi_write, RDY_dmi_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -170,8 +176,13 @@ module mkDebug_Module(CLK, EN_hart0_csr_mem_client_response_put, RDY_hart0_csr_mem_client_response_put, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put, master_awvalid, @@ -199,8 +210,6 @@ module mkDebug_Module(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -265,9 +274,15 @@ module mkDebug_Module(CLK, input EN_dmi_write; output RDY_dmi_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -314,9 +329,15 @@ module mkDebug_Module(CLK, input EN_hart0_csr_mem_client_response_put; output RDY_hart0_csr_mem_client_response_put; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // value method master_m_awvalid output master_awvalid; @@ -359,9 +380,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -447,14 +465,12 @@ module mkDebug_Module(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_dmi_read_addr, RDY_dmi_read_data, RDY_dmi_write, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_csr_mem_client_request_get, @@ -462,10 +478,14 @@ module mkDebug_Module(CLK, RDY_hart0_fpr_mem_client_request_get, RDY_hart0_fpr_mem_client_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, RDY_hart0_gpr_mem_client_request_get, RDY_hart0_gpr_mem_client_response_put, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, hart0_client_run_halt_request_get, + hart0_reset_client_request_get, master_arlock, master_arvalid, master_awlock, @@ -473,7 +493,8 @@ module mkDebug_Module(CLK, master_bready, master_rready, master_wlast, - master_wvalid; + master_wvalid, + ndm_reset_client_request_get; // inlined wires wire [7 : 0] f_read_addr_rv$port0__write_1, @@ -517,22 +538,30 @@ module mkDebug_Module(CLK, wire [6 : 0] dm_run_control$av_read_dm_addr, dm_run_control$write_dm_addr; wire [3 : 0] dm_run_control$hart0_get_other_req_get; wire dm_run_control$EN_av_read, - dm_run_control$EN_get_ndm_reset_req_get, dm_run_control$EN_hart0_client_run_halt_request_get, dm_run_control$EN_hart0_client_run_halt_response_put, dm_run_control$EN_hart0_get_other_req_get, - dm_run_control$EN_hart0_get_reset_req_get, + dm_run_control$EN_hart0_reset_client_request_get, + dm_run_control$EN_hart0_reset_client_response_put, + dm_run_control$EN_ndm_reset_client_request_get, + dm_run_control$EN_ndm_reset_client_response_put, dm_run_control$EN_reset, dm_run_control$EN_write, - dm_run_control$RDY_get_ndm_reset_req_get, dm_run_control$RDY_hart0_client_run_halt_request_get, dm_run_control$RDY_hart0_client_run_halt_response_put, dm_run_control$RDY_hart0_get_other_req_get, - dm_run_control$RDY_hart0_get_reset_req_get, + dm_run_control$RDY_hart0_reset_client_request_get, + dm_run_control$RDY_hart0_reset_client_response_put, + dm_run_control$RDY_ndm_reset_client_request_get, + dm_run_control$RDY_ndm_reset_client_response_put, dm_run_control$RDY_write, dm_run_control$dmactive, dm_run_control$hart0_client_run_halt_request_get, - dm_run_control$hart0_client_run_halt_response_put; + dm_run_control$hart0_client_run_halt_response_put, + dm_run_control$hart0_reset_client_request_get, + dm_run_control$hart0_reset_client_response_put, + dm_run_control$ndm_reset_client_request_get, + dm_run_control$ndm_reset_client_response_put; // ports of submodule dm_system_bus wire [63 : 0] dm_system_bus$master_araddr, @@ -553,8 +582,7 @@ module mkDebug_Module(CLK, dm_system_bus$master_awqos, dm_system_bus$master_awregion, dm_system_bus$master_bid, - dm_system_bus$master_rid, - dm_system_bus$master_wid; + dm_system_bus$master_rid; wire [2 : 0] dm_system_bus$master_arprot, dm_system_bus$master_arsize, dm_system_bus$master_awprot, @@ -588,7 +616,6 @@ module mkDebug_Module(CLK, CAN_FIRE_dmi_read_addr, CAN_FIRE_dmi_read_data, CAN_FIRE_dmi_write, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_csr_mem_client_request_get, @@ -596,19 +623,21 @@ module mkDebug_Module(CLK, CAN_FIRE_hart0_fpr_mem_client_request_get, CAN_FIRE_hart0_fpr_mem_client_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, CAN_FIRE_hart0_gpr_mem_client_request_get, CAN_FIRE_hart0_gpr_mem_client_response_put, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, CAN_FIRE_master_m_arready, CAN_FIRE_master_m_awready, CAN_FIRE_master_m_bvalid, CAN_FIRE_master_m_rvalid, CAN_FIRE_master_m_wready, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, WILL_FIRE_RL_rl_reset, WILL_FIRE_dmi_read_addr, WILL_FIRE_dmi_read_data, WILL_FIRE_dmi_write, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_csr_mem_client_request_get, @@ -616,19 +645,22 @@ module mkDebug_Module(CLK, WILL_FIRE_hart0_fpr_mem_client_request_get, WILL_FIRE_hart0_fpr_mem_client_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, WILL_FIRE_hart0_gpr_mem_client_request_get, WILL_FIRE_hart0_gpr_mem_client_response_put, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, WILL_FIRE_master_m_arready, WILL_FIRE_master_m_awready, WILL_FIRE_master_m_bvalid, WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready; + WILL_FIRE_master_m_wready, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h887; - reg [31 : 0] v__h881; + reg [31 : 0] v__h911; + reg [31 : 0] v__h905; // synopsys translate_on // action method dmi_read_addr @@ -705,12 +737,23 @@ module mkDebug_Module(CLK, dm_run_control$RDY_write && dm_system_bus$RDY_write ; assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign CAN_FIRE_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = + dm_run_control$hart0_reset_client_request_get ; + assign RDY_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign CAN_FIRE_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign CAN_FIRE_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = @@ -792,12 +835,23 @@ module mkDebug_Module(CLK, assign WILL_FIRE_hart0_csr_mem_client_response_put = EN_hart0_csr_mem_client_response_put ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + dm_run_control$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // value method master_m_awvalid assign master_awvalid = dm_system_bus$master_awvalid ; @@ -839,9 +893,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid assign master_wvalid = dm_system_bus$master_wvalid ; - // value method master_m_wid - assign master_wid = dm_system_bus$master_wid ; - // value method master_m_wdata assign master_wdata = dm_system_bus$master_wdata ; @@ -943,29 +994,37 @@ module mkDebug_Module(CLK, .RST_N(RST_N), .av_read_dm_addr(dm_run_control$av_read_dm_addr), .hart0_client_run_halt_response_put(dm_run_control$hart0_client_run_halt_response_put), + .hart0_reset_client_response_put(dm_run_control$hart0_reset_client_response_put), + .ndm_reset_client_response_put(dm_run_control$ndm_reset_client_response_put), .write_dm_addr(dm_run_control$write_dm_addr), .write_dm_word(dm_run_control$write_dm_word), .EN_reset(dm_run_control$EN_reset), .EN_av_read(dm_run_control$EN_av_read), .EN_write(dm_run_control$EN_write), - .EN_hart0_get_reset_req_get(dm_run_control$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(dm_run_control$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(dm_run_control$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(dm_run_control$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(dm_run_control$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(dm_run_control$EN_hart0_get_other_req_get), - .EN_get_ndm_reset_req_get(dm_run_control$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(dm_run_control$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(dm_run_control$EN_ndm_reset_client_response_put), .dmactive(dm_run_control$dmactive), .RDY_dmactive(), .RDY_reset(), .av_read(dm_run_control$av_read), .RDY_av_read(), .RDY_write(dm_run_control$RDY_write), - .RDY_hart0_get_reset_req_get(dm_run_control$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(dm_run_control$hart0_reset_client_request_get), + .RDY_hart0_reset_client_request_get(dm_run_control$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(dm_run_control$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(dm_run_control$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(dm_run_control$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(dm_run_control$RDY_hart0_client_run_halt_response_put), .hart0_get_other_req_get(dm_run_control$hart0_get_other_req_get), .RDY_hart0_get_other_req_get(dm_run_control$RDY_hart0_get_other_req_get), - .RDY_get_ndm_reset_req_get(dm_run_control$RDY_get_ndm_reset_req_get)); + .ndm_reset_client_request_get(dm_run_control$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(dm_run_control$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(dm_run_control$RDY_ndm_reset_client_response_put)); // submodule dm_system_bus mkDM_System_Bus dm_system_bus(.CLK(CLK), @@ -1003,7 +1062,6 @@ module mkDebug_Module(CLK, .master_awqos(dm_system_bus$master_awqos), .master_awregion(dm_system_bus$master_awregion), .master_wvalid(dm_system_bus$master_wvalid), - .master_wid(dm_system_bus$master_wid), .master_wdata(dm_system_bus$master_wdata), .master_wstrb(dm_system_bus$master_wstrb), .master_wlast(dm_system_bus$master_wlast), @@ -1100,6 +1158,10 @@ module mkDebug_Module(CLK, assign dm_run_control$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; assign dm_run_control$hart0_client_run_halt_response_put = hart0_client_run_halt_response_put ; + assign dm_run_control$hart0_reset_client_response_put = + hart0_reset_client_response_put ; + assign dm_run_control$ndm_reset_client_response_put = + ndm_reset_client_response_put ; assign dm_run_control$write_dm_addr = dmi_write_dm_addr ; assign dm_run_control$write_dm_word = dmi_write_dm_word ; assign dm_run_control$EN_reset = WILL_FIRE_RL_rl_reset ; @@ -1128,15 +1190,20 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h40 || dmi_write_dm_addr == 7'h5F || dmi_write_dm_addr == 7'h60) ; - assign dm_run_control$EN_hart0_get_reset_req_get = - EN_hart0_get_reset_req_get ; + assign dm_run_control$EN_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + assign dm_run_control$EN_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; assign dm_run_control$EN_hart0_client_run_halt_request_get = EN_hart0_client_run_halt_request_get ; assign dm_run_control$EN_hart0_client_run_halt_response_put = EN_hart0_client_run_halt_response_put ; assign dm_run_control$EN_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - assign dm_run_control$EN_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + assign dm_run_control$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign dm_run_control$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule dm_system_bus assign dm_system_bus$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; @@ -1208,12 +1275,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h887 = $stime; + v__h911 = $stime; #0; end - v__h881 = v__h887 / 32'd10; + v__h905 = v__h911 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h881); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h905); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v index fdb8f0f..8a1a6a7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v +++ b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric_2x3(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric_2x3(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric_2x3(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric_2x3(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,34 +1175,57 @@ module mkFabric_2x3(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1237,7 +1233,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1245,7 +1241,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1270,52 +1266,61 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1366,7 +1371,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1411,7 +1416,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1456,7 +1461,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1501,7 +1506,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1546,7 +1551,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1602,6 +1607,8 @@ module mkFabric_2x3(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_reset, CAN_FIRE_set_verbosity, CAN_FIRE_v_from_masters_0_m_arvalid, @@ -1658,6 +1665,8 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_reset, WILL_FIRE_set_verbosity, WILL_FIRE_v_from_masters_0_m_arvalid, @@ -1687,91 +1696,152 @@ module mkFabric_2x3(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8376; - reg [31 : 0] v__h8854; - reg [31 : 0] v__h9332; - reg [31 : 0] v__h9903; - reg [31 : 0] v__h10365; - reg [31 : 0] v__h10827; - reg [31 : 0] v__h12052; - reg [31 : 0] v__h12404; - reg [31 : 0] v__h12756; - reg [31 : 0] v__h13171; - reg [31 : 0] v__h13499; - reg [31 : 0] v__h13827; - reg [31 : 0] v__h14823; - reg [31 : 0] v__h15116; - reg [31 : 0] v__h15409; - reg [31 : 0] v__h15715; - reg [31 : 0] v__h15982; - reg [31 : 0] v__h16249; - reg [31 : 0] v__h16556; - reg [31 : 0] v__h16823; - reg [31 : 0] v__h17170; - reg [31 : 0] v__h17493; - reg [31 : 0] v__h17816; - reg [31 : 0] v__h18143; - reg [31 : 0] v__h18429; - reg [31 : 0] v__h18715; - reg [31 : 0] v__h19040; - reg [31 : 0] v__h19314; - reg [31 : 0] v__h5509; - reg [31 : 0] v__h5503; - reg [31 : 0] v__h8370; - reg [31 : 0] v__h8848; - reg [31 : 0] v__h9326; - reg [31 : 0] v__h9897; - reg [31 : 0] v__h10359; - reg [31 : 0] v__h10821; - reg [31 : 0] v__h12046; - reg [31 : 0] v__h12398; - reg [31 : 0] v__h12750; - reg [31 : 0] v__h13165; - reg [31 : 0] v__h13493; - reg [31 : 0] v__h13821; - reg [31 : 0] v__h14817; - reg [31 : 0] v__h15110; - reg [31 : 0] v__h15403; - reg [31 : 0] v__h15709; - reg [31 : 0] v__h15976; - reg [31 : 0] v__h16243; - reg [31 : 0] v__h16550; - reg [31 : 0] v__h16817; - reg [31 : 0] v__h17164; - reg [31 : 0] v__h17487; - reg [31 : 0] v__h17810; - reg [31 : 0] v__h18137; - reg [31 : 0] v__h18423; - reg [31 : 0] v__h18709; - reg [31 : 0] v__h19034; - reg [31 : 0] v__h19308; + reg [31 : 0] v__h8785; + reg [31 : 0] v__h9160; + reg [31 : 0] v__h9535; + reg [31 : 0] v__h9980; + reg [31 : 0] v__h10349; + reg [31 : 0] v__h10718; + reg [31 : 0] v__h11990; + reg [31 : 0] v__h12433; + reg [31 : 0] v__h12808; + reg [31 : 0] v__h13100; + reg [31 : 0] v__h13392; + reg [31 : 0] v__h13695; + reg [31 : 0] v__h13961; + reg [31 : 0] v__h14227; + reg [31 : 0] v__h14491; + reg [31 : 0] v__h14717; + reg [31 : 0] v__h15146; + reg [31 : 0] v__h15502; + reg [31 : 0] v__h15858; + reg [31 : 0] v__h16275; + reg [31 : 0] v__h16607; + reg [31 : 0] v__h16939; + reg [31 : 0] v__h17955; + reg [31 : 0] v__h18206; + reg [31 : 0] v__h18581; + reg [31 : 0] v__h18822; + reg [31 : 0] v__h19197; + reg [31 : 0] v__h19438; + reg [31 : 0] v__h19800; + reg [31 : 0] v__h20051; + reg [31 : 0] v__h20381; + reg [31 : 0] v__h20622; + reg [31 : 0] v__h20952; + reg [31 : 0] v__h21193; + reg [31 : 0] v__h21706; + reg [31 : 0] v__h22107; + reg [31 : 0] v__h5833; + reg [31 : 0] v__h5827; + reg [31 : 0] v__h8779; + reg [31 : 0] v__h9154; + reg [31 : 0] v__h9529; + reg [31 : 0] v__h9974; + reg [31 : 0] v__h10343; + reg [31 : 0] v__h10712; + reg [31 : 0] v__h11984; + reg [31 : 0] v__h12427; + reg [31 : 0] v__h12802; + reg [31 : 0] v__h13094; + reg [31 : 0] v__h13386; + reg [31 : 0] v__h13689; + reg [31 : 0] v__h13955; + reg [31 : 0] v__h14221; + reg [31 : 0] v__h14485; + reg [31 : 0] v__h14711; + reg [31 : 0] v__h15140; + reg [31 : 0] v__h15496; + reg [31 : 0] v__h15852; + reg [31 : 0] v__h16269; + reg [31 : 0] v__h16601; + reg [31 : 0] v__h16933; + reg [31 : 0] v__h17949; + reg [31 : 0] v__h18200; + reg [31 : 0] v__h18575; + reg [31 : 0] v__h18816; + reg [31 : 0] v__h19191; + reg [31 : 0] v__h19432; + reg [31 : 0] v__h19794; + reg [31 : 0] v__h20045; + reg [31 : 0] v__h20375; + reg [31 : 0] v__h20616; + reg [31 : 0] v__h20946; + reg [31 : 0] v__h21187; + reg [31 : 0] v__h21700; + reg [31 : 0] v__h22101; // synopsys translate_on // remaining internal signals - wire NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11895, + x__h12338, + x__h18092, + x__h18718, + x__h19334, + x__h21638, + x__h22039; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + x1_avValue_rresp__h18070, + x1_avValue_rresp__h18696, + x1_avValue_rresp__h19312; + wire _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538, + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -1962,10 +2032,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2094,10 +2160,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2226,10 +2288,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2307,58 +2365,36 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2372,7 +2408,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2386,7 +2422,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2427,58 +2463,58 @@ module mkFabric_2x3(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2492,7 +2528,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2506,7 +2542,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2584,7 +2620,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2644,7 +2680,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2704,7 +2740,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2764,7 +2800,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2824,7 +2860,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2896,58 +2932,54 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2955,15 +2987,14 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2971,100 +3002,37 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; @@ -3075,7 +3043,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; @@ -3086,7 +3054,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; @@ -3097,7 +3065,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && + fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; @@ -3108,7 +3076,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && + fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; @@ -3119,7 +3087,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && + fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; @@ -3128,8 +3096,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && + fabric_v_f_wr_err_info_0$EMPTY_N && fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; @@ -3138,40 +3105,123 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && + fabric_v_f_wr_err_info_1$EMPTY_N && fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_v_f_rd_sjs_0$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_1 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_2 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_3 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_4 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_5 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3180,9 +3230,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3191,9 +3241,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3202,9 +3252,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3213,8 +3263,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3223,8 +3272,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3234,14 +3282,75 @@ module mkFabric_2x3(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + 8'd0 : + x__h18092 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + 8'd0 : + x__h18718 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + 8'd0 : + x__h19334 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? + 8'd0 : + x__h11895 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ? + 8'd0 : + x__h12338 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3251,67 +3360,156 @@ module mkFabric_2x3(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ? + 8'd0 : + x__h21638 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ? + 8'd0 : + x__h22039 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3334,10 +3532,14 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3360,41 +3562,89 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_0$DEQ = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_1$DEQ = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3405,9 +3655,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3418,9 +3666,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3504,24 +3750,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3562,17 +3808,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3635,24 +3878,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3693,17 +3936,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3785,12 +4025,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3849,12 +4091,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -3913,12 +4157,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -3941,56 +4187,155 @@ module mkFabric_2x3(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 = - fabric_cfg_verbosity > 4'd1 ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 = + assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + x1_avValue_rresp__h18070 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + x1_avValue_rresp__h18696 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + x1_avValue_rresp__h19312 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < + soc_map$m_plic_addr_lim ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 = + soc_map$m_mem0_controller_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h18070 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18696 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19312 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11895 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12338 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h18092 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18718 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19334 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21638 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h22039 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -4000,6 +4345,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -4008,6 +4360,27 @@ module mkFabric_2x3(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4018,6 +4391,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4030,2581 +4410,3009 @@ module mkFabric_2x3(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8376 = $stime; + v__h8785 = $stime; #0; end - v__h8370 = v__h8376 / 32'd10; + v__h8779 = v__h8785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8370, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8779, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8854 = $stime; + v__h9160 = $stime; #0; end - v__h8848 = v__h8854 / 32'd10; + v__h9154 = v__h9160 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8848, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9154, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h9332 = $stime; + v__h9535 = $stime; #0; end - v__h9326 = v__h9332 / 32'd10; + v__h9529 = v__h9535 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9326, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9529, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9980 = $stime; + #0; + end + v__h9974 = v__h9980 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9974, + $signed(32'd1), + $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10349 = $stime; + #0; + end + v__h10343 = v__h10349 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10343, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10718 = $stime; + #0; + end + v__h10712 = v__h10718 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10712, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h11990 = $stime; + #0; + end + v__h11984 = v__h11990 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h11984, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9903 = $stime; + v__h12433 = $stime; #0; end - v__h9897 = v__h9903 / 32'd10; + v__h12427 = v__h12433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9897, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12427, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10365 = $stime; - #0; - end - v__h10359 = v__h10365 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10359, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10827 = $stime; - #0; - end - v__h10821 = v__h10827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12052 = $stime; - #0; - end - v__h12046 = v__h12052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12046, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12404 = $stime; - #0; - end - v__h12398 = v__h12404 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12398, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12756 = $stime; - #0; - end - v__h12750 = v__h12756 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12750, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13171 = $stime; - #0; - end - v__h13165 = v__h13171 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13165, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13499 = $stime; - #0; - end - v__h13493 = v__h13499 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13493, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13827 = $stime; - #0; - end - v__h13821 = v__h13827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h14823 = $stime; + v__h12808 = $stime; #0; end - v__h14817 = v__h14823 / 32'd10; + v__h12802 = v__h12808 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h14817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12802, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15116 = $stime; + v__h13100 = $stime; #0; end - v__h15110 = v__h15116 / 32'd10; + v__h13094 = v__h13100 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15110, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13094, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15409 = $stime; + v__h13392 = $stime; #0; end - v__h15403 = v__h15409 / 32'd10; + v__h13386 = v__h13392 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15403, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13386, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15715 = $stime; + v__h13695 = $stime; #0; end - v__h15709 = v__h15715 / 32'd10; + v__h13689 = v__h13695 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15709, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13689, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15982 = $stime; + v__h13961 = $stime; #0; end - v__h15976 = v__h15982 / 32'd10; + v__h13955 = v__h13961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15976, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13955, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16249 = $stime; + v__h14227 = $stime; #0; end - v__h16243 = v__h16249 / 32'd10; + v__h14221 = v__h14227 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16243, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14221, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16556 = $stime; + v__h14491 = $stime; #0; end - v__h16550 = v__h16556 / 32'd10; + v__h14485 = v__h14491 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16550, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14485, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16823 = $stime; + v__h14717 = $stime; #0; end - v__h16817 = v__h16823 / 32'd10; + v__h14711 = v__h14717 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14711, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15146 = $stime; + #0; + end + v__h15140 = v__h15146 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15140, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15502 = $stime; + #0; + end + v__h15496 = v__h15502 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15496, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15858 = $stime; + #0; + end + v__h15852 = v__h15858 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15852, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16275 = $stime; + #0; + end + v__h16269 = v__h16275 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16269, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16607 = $stime; + #0; + end + v__h16601 = v__h16607 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16601, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16939 = $stime; + #0; + end + v__h16933 = v__h16939 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16933, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17170 = $stime; + v__h17955 = $stime; #0; end - v__h17164 = v__h17170 / 32'd10; + v__h17949 = v__h17955 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17164, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h17949, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18206 = $stime; + #0; + end + v__h18200 = v__h18206 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18200, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17493 = $stime; + v__h18581 = $stime; #0; end - v__h17487 = v__h17493 / 32'd10; + v__h18575 = v__h18581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17487, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18575, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h18822 = $stime; + #0; + end + v__h18816 = v__h18822 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18816, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h17816 = $stime; + v__h19197 = $stime; #0; end - v__h17810 = v__h17816 / 32'd10; + v__h19191 = v__h19197 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17810, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19191, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19438 = $stime; + #0; + end + v__h19432 = v__h19438 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19432, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18143 = $stime; + v__h19800 = $stime; #0; end - v__h18137 = v__h18143 / 32'd10; + v__h19794 = v__h19800 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18137, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19794, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20051 = $stime; + #0; + end + v__h20045 = v__h20051 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20045, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18429 = $stime; + v__h20381 = $stime; #0; end - v__h18423 = v__h18429 / 32'd10; + v__h20375 = v__h20381 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18423, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20375, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20622 = $stime; + #0; + end + v__h20616 = v__h20622 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20616, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18715 = $stime; + v__h20952 = $stime; #0; end - v__h18709 = v__h18715 / 32'd10; + v__h20946 = v__h20952 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18709, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20946, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21193 = $stime; + #0; + end + v__h21187 = v__h21193 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21187, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19040 = $stime; + v__h21706 = $stime; #0; end - v__h19034 = v__h19040 / 32'd10; + v__h21700 = v__h21706 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19034, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21700, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19314 = $stime; + v__h22107 = $stime; #0; end - v__h19308 = v__h19314 / 32'd10; + v__h22101 = v__h22107 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19308, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h22101, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5509 = $stime; + v__h5833 = $stime; #0; end - v__h5503 = v__h5509 / 32'd10; + v__h5827 = v__h5833 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5503); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5827); end // synopsys translate_on endmodule // mkFabric_2x3 diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index 1de88dc..4f4586d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1611,23 +1611,23 @@ module mkLLCache(CLK, MUX_cache_toMInfoQ$enq_1__SEL_1; // remaining internal signals - reg [63 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247, + reg [63 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q74, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q75, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q76, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q77, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q79, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q82, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q83, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q84, @@ -1650,7 +1650,7 @@ module mkLLCache(CLK, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q103, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q104, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q105, - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248, + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q259, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q226, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q227, @@ -1677,7 +1677,7 @@ module mkLLCache(CLK, CASE_cache_pipelinefirst_BIT_577_0_cache_cRqM_ETC__q97, CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q237, CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q273, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q258, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q260, IF_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2505, @@ -1738,7 +1738,6 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62, @@ -1749,9 +1748,10 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q112, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q113, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q116, @@ -1817,14 +1817,14 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q94, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q95, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q96, - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251, + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249, CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q271, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q270, CASE_cache_rsLdToDmaQ_deqP_0_NOT_cache_rsLdToD_ETC__q267, CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q268, CASE_cache_rsStToDmaQ_deqP_0_NOT_cache_rsStToD_ETC__q3, CASE_cache_rsStToDmaQ_deqP_0_cache_rsStToDmaQ__ETC__q4, - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252, + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250, CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q272, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q262, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q106, @@ -1889,8 +1889,8 @@ module mkLLCache(CLK, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q219, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q222, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q223, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254, SEL_ARR_NOT_cache_toCQ_data_0_534_BIT_583_535__ETC___d3541, SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706, x__h231129, @@ -3772,7 +3772,7 @@ module mkLLCache(CLK, SEL_ARR_cache_rqFromDmaQ_data_0_367_BIT_580_81_ETC___d2044, _1_CONCAT_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_ETC___d2062 } ; assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2 = - { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882, SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2164 } ; assign MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1 = @@ -5778,7 +5778,7 @@ module mkLLCache(CLK, cache_cRqMshr$pipelineResp_getAddrSucc, 1'd0 } ; assign IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_ETC___d1884 = - (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882) ? 2'd3 : 2'd1 ; @@ -6680,131 +6680,131 @@ module mkLLCache(CLK, perfReqQ_enqReq_lat_0$wget[4] : perfReqQ_enqReq_rl[4] ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 || + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 || + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 ; assign NOT_SEL_ARR_NOT_cache_rsFromCQ_data_0_171_BIT__ETC___d2229 = - { !CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251, + { !CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249, SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2223, x__h255367 } ; assign NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3038 = @@ -7010,8 +7010,8 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81 } ; assign SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2164 = { SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2155, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 } ; + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 } ; assign SEL_ARR_cache_rqFromDmaQ_data_0_367_BIT_580_81_ETC___d1894 = { CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q94, @@ -7138,21 +7138,21 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205 = - { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 } ; + { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2214 = { SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q79 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2223 = { SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2214, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 } ; + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_579_TO__ETC___d2230 = - { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254, + { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252, NOT_SEL_ARR_NOT_cache_rsFromCQ_data_0_171_BIT__ETC___d2229 } ; assign SEL_ARR_cache_rsFromMQ_data_0_234_BITS_516_TO__ETC___d2267 = { CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q82, @@ -7190,7 +7190,7 @@ module mkLLCache(CLK, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q105 } ; assign SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3607 = { SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3602, - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248, + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246, SEL_ARR_cache_toCQ_data_0_534_BITS_66_TO_3_543_ETC___d3546 } ; assign SEL_ARR_cache_toCQ_data_0_534_BITS_582_TO_519__ETC___d3615 = { CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q259, @@ -7198,7 +7198,7 @@ module mkLLCache(CLK, SEL_ARR_cache_toCQ_data_0_534_BIT_516_565_cach_ETC___d3614 } ; assign SEL_ARR_cache_toCQ_data_0_534_BIT_516_565_cach_ETC___d3614 = { x__h384525, - !CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252, + !CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250, SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3607, x__h386046 } ; assign SEL_ARR_cache_toMQ_data_0_699_BITS_511_TO_448__ETC___d4031 = @@ -7341,8 +7341,8 @@ module mkLLCache(CLK, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q223 } ; assign SEL_ARR_cache_toMQ_data_0_699_BIT_575_726_cach_ETC___d4013 = { SEL_ARR_cache_toMQ_data_0_699_BIT_575_726_cach_ETC___d4004, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 } ; + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 } ; assign _0_CONCAT_IF_cache_pipeline_first__533_BITS_521_ETC___d2993 = { 1'd0, cache_pipeline_first__533_BITS_521_TO_520_551__ETC___d2552 ? @@ -7756,6 +7756,14 @@ module mkLLCache(CLK, cache_rsStToDmaQ_data_1[2:0]; endcase end + always@(cache_rqFromCQ_deqP or + cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) + begin + case (cache_rqFromCQ_deqP) + 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; + 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; + endcase + end always@(cache_cRqRetryIndexQ_deqP or cache_cRqRetryIndexQ_data_0 or cache_cRqRetryIndexQ_data_1 or @@ -7792,14 +7800,6 @@ module mkLLCache(CLK, 4'd15: x__h230768 = cache_cRqRetryIndexQ_data_15; endcase end - always@(cache_rqFromCQ_deqP or - cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) - begin - case (cache_rqFromCQ_deqP) - 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; - 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; - endcase - end always@(cache_rqFromCQ_deqP or cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) begin @@ -7860,783 +7860,15 @@ module mkLLCache(CLK, 1'd1: x__h255367 = cache_rsFromCQ_data_1[0]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = - !cache_rqFromDmaQ_data_0[578]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = - !cache_rqFromDmaQ_data_1[578]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = - !cache_rqFromDmaQ_data_0[579]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = - !cache_rqFromDmaQ_data_1[579]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = - !cache_rqFromDmaQ_data_0[580]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = - !cache_rqFromDmaQ_data_1[580]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = - !cache_rqFromDmaQ_data_0[576]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = - !cache_rqFromDmaQ_data_1[576]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = - !cache_rqFromDmaQ_data_0[577]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = - !cache_rqFromDmaQ_data_1[577]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = - !cache_rqFromDmaQ_data_0[574]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = - !cache_rqFromDmaQ_data_1[574]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = - !cache_rqFromDmaQ_data_0[575]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = - !cache_rqFromDmaQ_data_1[575]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = - !cache_rqFromDmaQ_data_0[572]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = - !cache_rqFromDmaQ_data_1[572]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = - !cache_rqFromDmaQ_data_0[573]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = - !cache_rqFromDmaQ_data_1[573]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = - !cache_rqFromDmaQ_data_0[570]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = - !cache_rqFromDmaQ_data_1[570]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = - !cache_rqFromDmaQ_data_0[571]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = - !cache_rqFromDmaQ_data_1[571]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = - !cache_rqFromDmaQ_data_0[568]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = - !cache_rqFromDmaQ_data_1[568]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = - !cache_rqFromDmaQ_data_0[569]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = - !cache_rqFromDmaQ_data_1[569]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = - !cache_rqFromDmaQ_data_0[566]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = - !cache_rqFromDmaQ_data_1[566]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = - !cache_rqFromDmaQ_data_0[567]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = - !cache_rqFromDmaQ_data_1[567]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = - !cache_rqFromDmaQ_data_0[564]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = - !cache_rqFromDmaQ_data_1[564]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = - !cache_rqFromDmaQ_data_0[565]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = - !cache_rqFromDmaQ_data_1[565]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = - !cache_rqFromDmaQ_data_0[562]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = - !cache_rqFromDmaQ_data_1[562]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = - !cache_rqFromDmaQ_data_0[563]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = - !cache_rqFromDmaQ_data_1[563]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = - !cache_rqFromDmaQ_data_0[560]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = - !cache_rqFromDmaQ_data_1[560]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = - !cache_rqFromDmaQ_data_0[561]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = - !cache_rqFromDmaQ_data_1[561]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = - !cache_rqFromDmaQ_data_0[558]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = - !cache_rqFromDmaQ_data_1[558]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = - !cache_rqFromDmaQ_data_0[559]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = - !cache_rqFromDmaQ_data_1[559]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = - !cache_rqFromDmaQ_data_0[556]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = - !cache_rqFromDmaQ_data_1[556]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = - !cache_rqFromDmaQ_data_0[557]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = - !cache_rqFromDmaQ_data_1[557]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = - !cache_rqFromDmaQ_data_0[554]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = - !cache_rqFromDmaQ_data_1[554]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = - !cache_rqFromDmaQ_data_0[555]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = - !cache_rqFromDmaQ_data_1[555]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = - !cache_rqFromDmaQ_data_0[552]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = - !cache_rqFromDmaQ_data_1[552]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = - !cache_rqFromDmaQ_data_0[553]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = - !cache_rqFromDmaQ_data_1[553]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = - !cache_rqFromDmaQ_data_0[550]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = - !cache_rqFromDmaQ_data_1[550]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = - !cache_rqFromDmaQ_data_0[551]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = - !cache_rqFromDmaQ_data_1[551]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = - !cache_rqFromDmaQ_data_0[548]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = - !cache_rqFromDmaQ_data_1[548]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = - !cache_rqFromDmaQ_data_0[549]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = - !cache_rqFromDmaQ_data_1[549]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = - !cache_rqFromDmaQ_data_0[546]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = - !cache_rqFromDmaQ_data_1[546]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = - !cache_rqFromDmaQ_data_0[547]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = - !cache_rqFromDmaQ_data_1[547]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = - !cache_rqFromDmaQ_data_0[544]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = - !cache_rqFromDmaQ_data_1[544]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = - !cache_rqFromDmaQ_data_0[545]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = - !cache_rqFromDmaQ_data_1[545]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = - !cache_rqFromDmaQ_data_0[542]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = - !cache_rqFromDmaQ_data_1[542]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = - !cache_rqFromDmaQ_data_0[543]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = - !cache_rqFromDmaQ_data_1[543]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = - !cache_rqFromDmaQ_data_0[540]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = - !cache_rqFromDmaQ_data_1[540]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = - !cache_rqFromDmaQ_data_0[541]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = - !cache_rqFromDmaQ_data_1[541]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = - !cache_rqFromDmaQ_data_0[538]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = - !cache_rqFromDmaQ_data_1[538]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = - !cache_rqFromDmaQ_data_0[539]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = - !cache_rqFromDmaQ_data_1[539]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = - !cache_rqFromDmaQ_data_0[536]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = - !cache_rqFromDmaQ_data_1[536]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = - !cache_rqFromDmaQ_data_0[537]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = - !cache_rqFromDmaQ_data_1[537]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = - !cache_rqFromDmaQ_data_0[534]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = - !cache_rqFromDmaQ_data_1[534]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = - !cache_rqFromDmaQ_data_0[535]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = - !cache_rqFromDmaQ_data_1[535]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = - !cache_rqFromDmaQ_data_0[532]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = - !cache_rqFromDmaQ_data_1[532]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = - !cache_rqFromDmaQ_data_0[533]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = - !cache_rqFromDmaQ_data_1[533]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = - !cache_rqFromDmaQ_data_0[530]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = - !cache_rqFromDmaQ_data_1[530]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = - !cache_rqFromDmaQ_data_0[531]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = - !cache_rqFromDmaQ_data_1[531]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = - !cache_rqFromDmaQ_data_0[528]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = - !cache_rqFromDmaQ_data_1[528]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = - !cache_rqFromDmaQ_data_0[529]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = - !cache_rqFromDmaQ_data_1[529]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = - !cache_rqFromDmaQ_data_0[526]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = - !cache_rqFromDmaQ_data_1[526]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = - !cache_rqFromDmaQ_data_0[527]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = - !cache_rqFromDmaQ_data_1[527]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = - !cache_rqFromDmaQ_data_0[524]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = - !cache_rqFromDmaQ_data_1[524]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = - !cache_rqFromDmaQ_data_0[525]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = - !cache_rqFromDmaQ_data_1[525]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = - !cache_rqFromDmaQ_data_0[522]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = - !cache_rqFromDmaQ_data_1[522]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = - !cache_rqFromDmaQ_data_0[523]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = - !cache_rqFromDmaQ_data_1[523]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = - !cache_rqFromDmaQ_data_0[520]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = - !cache_rqFromDmaQ_data_1[520]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = - !cache_rqFromDmaQ_data_0[521]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = - !cache_rqFromDmaQ_data_1[521]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = - !cache_rqFromDmaQ_data_0[518]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = - !cache_rqFromDmaQ_data_1[518]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = - !cache_rqFromDmaQ_data_0[519]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = - !cache_rqFromDmaQ_data_1[519]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = - !cache_rqFromDmaQ_data_0[517]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = - !cache_rqFromDmaQ_data_1[517]; - endcase - end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = cache_rsFromCQ_data_0[512:449]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = cache_rsFromCQ_data_1[512:449]; endcase end @@ -8645,10 +7877,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = cache_rsFromCQ_data_0[448:385]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = cache_rsFromCQ_data_1[448:385]; endcase end @@ -8657,10 +7889,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = cache_rsFromCQ_data_0[384:321]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = cache_rsFromCQ_data_1[384:321]; endcase end @@ -8669,13 +7901,781 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = cache_rsFromCQ_data_0[320:257]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = cache_rsFromCQ_data_1[320:257]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + !cache_rqFromDmaQ_data_0[578]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + !cache_rqFromDmaQ_data_1[578]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + !cache_rqFromDmaQ_data_0[579]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + !cache_rqFromDmaQ_data_1[579]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + !cache_rqFromDmaQ_data_0[580]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + !cache_rqFromDmaQ_data_1[580]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + !cache_rqFromDmaQ_data_0[576]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + !cache_rqFromDmaQ_data_1[576]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + !cache_rqFromDmaQ_data_0[577]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + !cache_rqFromDmaQ_data_1[577]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + !cache_rqFromDmaQ_data_0[574]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + !cache_rqFromDmaQ_data_1[574]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + !cache_rqFromDmaQ_data_0[575]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + !cache_rqFromDmaQ_data_1[575]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + !cache_rqFromDmaQ_data_0[572]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + !cache_rqFromDmaQ_data_1[572]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + !cache_rqFromDmaQ_data_0[573]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + !cache_rqFromDmaQ_data_1[573]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + !cache_rqFromDmaQ_data_0[570]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + !cache_rqFromDmaQ_data_1[570]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + !cache_rqFromDmaQ_data_0[571]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + !cache_rqFromDmaQ_data_1[571]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + !cache_rqFromDmaQ_data_0[568]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + !cache_rqFromDmaQ_data_1[568]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + !cache_rqFromDmaQ_data_0[569]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + !cache_rqFromDmaQ_data_1[569]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + !cache_rqFromDmaQ_data_0[566]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + !cache_rqFromDmaQ_data_1[566]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + !cache_rqFromDmaQ_data_0[567]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + !cache_rqFromDmaQ_data_1[567]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + !cache_rqFromDmaQ_data_0[564]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + !cache_rqFromDmaQ_data_1[564]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + !cache_rqFromDmaQ_data_0[565]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + !cache_rqFromDmaQ_data_1[565]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + !cache_rqFromDmaQ_data_0[562]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + !cache_rqFromDmaQ_data_1[562]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + !cache_rqFromDmaQ_data_0[563]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + !cache_rqFromDmaQ_data_1[563]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + !cache_rqFromDmaQ_data_0[560]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + !cache_rqFromDmaQ_data_1[560]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + !cache_rqFromDmaQ_data_0[561]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + !cache_rqFromDmaQ_data_1[561]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + !cache_rqFromDmaQ_data_0[558]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + !cache_rqFromDmaQ_data_1[558]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + !cache_rqFromDmaQ_data_0[559]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + !cache_rqFromDmaQ_data_1[559]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + !cache_rqFromDmaQ_data_0[556]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + !cache_rqFromDmaQ_data_1[556]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + !cache_rqFromDmaQ_data_0[557]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + !cache_rqFromDmaQ_data_1[557]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + !cache_rqFromDmaQ_data_0[554]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + !cache_rqFromDmaQ_data_1[554]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + !cache_rqFromDmaQ_data_0[555]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + !cache_rqFromDmaQ_data_1[555]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + !cache_rqFromDmaQ_data_0[552]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + !cache_rqFromDmaQ_data_1[552]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + !cache_rqFromDmaQ_data_0[553]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + !cache_rqFromDmaQ_data_1[553]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + !cache_rqFromDmaQ_data_0[550]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + !cache_rqFromDmaQ_data_1[550]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + !cache_rqFromDmaQ_data_0[551]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + !cache_rqFromDmaQ_data_1[551]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + !cache_rqFromDmaQ_data_0[548]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + !cache_rqFromDmaQ_data_1[548]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + !cache_rqFromDmaQ_data_0[549]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + !cache_rqFromDmaQ_data_1[549]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + !cache_rqFromDmaQ_data_0[546]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + !cache_rqFromDmaQ_data_1[546]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + !cache_rqFromDmaQ_data_0[547]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + !cache_rqFromDmaQ_data_1[547]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + !cache_rqFromDmaQ_data_0[544]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + !cache_rqFromDmaQ_data_1[544]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + !cache_rqFromDmaQ_data_0[545]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + !cache_rqFromDmaQ_data_1[545]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + !cache_rqFromDmaQ_data_0[542]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + !cache_rqFromDmaQ_data_1[542]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + !cache_rqFromDmaQ_data_0[543]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + !cache_rqFromDmaQ_data_1[543]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + !cache_rqFromDmaQ_data_0[540]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + !cache_rqFromDmaQ_data_1[540]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + !cache_rqFromDmaQ_data_0[541]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + !cache_rqFromDmaQ_data_1[541]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + !cache_rqFromDmaQ_data_0[538]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + !cache_rqFromDmaQ_data_1[538]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + !cache_rqFromDmaQ_data_0[539]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + !cache_rqFromDmaQ_data_1[539]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + !cache_rqFromDmaQ_data_0[536]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + !cache_rqFromDmaQ_data_1[536]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + !cache_rqFromDmaQ_data_0[537]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + !cache_rqFromDmaQ_data_1[537]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + !cache_rqFromDmaQ_data_0[534]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + !cache_rqFromDmaQ_data_1[534]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + !cache_rqFromDmaQ_data_0[535]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + !cache_rqFromDmaQ_data_1[535]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + !cache_rqFromDmaQ_data_0[532]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + !cache_rqFromDmaQ_data_1[532]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + !cache_rqFromDmaQ_data_0[533]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + !cache_rqFromDmaQ_data_1[533]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + !cache_rqFromDmaQ_data_0[530]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + !cache_rqFromDmaQ_data_1[530]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + !cache_rqFromDmaQ_data_0[531]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + !cache_rqFromDmaQ_data_1[531]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + !cache_rqFromDmaQ_data_0[528]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + !cache_rqFromDmaQ_data_1[528]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + !cache_rqFromDmaQ_data_0[529]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + !cache_rqFromDmaQ_data_1[529]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + !cache_rqFromDmaQ_data_0[526]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + !cache_rqFromDmaQ_data_1[526]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + !cache_rqFromDmaQ_data_0[527]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + !cache_rqFromDmaQ_data_1[527]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + !cache_rqFromDmaQ_data_0[524]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + !cache_rqFromDmaQ_data_1[524]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + !cache_rqFromDmaQ_data_0[525]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + !cache_rqFromDmaQ_data_1[525]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + !cache_rqFromDmaQ_data_0[522]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + !cache_rqFromDmaQ_data_1[522]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + !cache_rqFromDmaQ_data_0[523]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + !cache_rqFromDmaQ_data_1[523]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + !cache_rqFromDmaQ_data_0[520]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + !cache_rqFromDmaQ_data_1[520]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + !cache_rqFromDmaQ_data_0[521]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + !cache_rqFromDmaQ_data_1[521]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + !cache_rqFromDmaQ_data_0[518]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + !cache_rqFromDmaQ_data_1[518]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + !cache_rqFromDmaQ_data_0[519]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + !cache_rqFromDmaQ_data_1[519]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + !cache_rqFromDmaQ_data_0[517]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + !cache_rqFromDmaQ_data_1[517]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -9003,6 +9003,17 @@ module mkLLCache(CLK, !cache_toCQ_data_1[583]; endcase end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = + !cache_toMQ_data_0[640]; + 1'd1: + SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = + !cache_toMQ_data_1[640]; + endcase + end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) @@ -9070,17 +9081,6 @@ module mkLLCache(CLK, endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = - !cache_toMQ_data_0[640]; - 1'd1: - SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = - !cache_toMQ_data_1[640]; - endcase - end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) 1'd0: @@ -10679,37 +10679,15 @@ module mkLLCache(CLK, cache_rsLdToDmaQ_data_1[260:197]; endcase end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244 = - cache_toMQ_data_0[513]; - 1'd1: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244 = - cache_toMQ_data_1[513]; - endcase - end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 = - cache_toMQ_data_0[512]; - 1'd1: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 = - cache_toMQ_data_1[512]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244 = cache_rqFromDmaQ_data_0[132:69]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244 = cache_rqFromDmaQ_data_1[132:69]; endcase end @@ -10718,10 +10696,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 = cache_rqFromDmaQ_data_0[68:5]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 = cache_rqFromDmaQ_data_1[68:5]; endcase end @@ -10729,10 +10707,10 @@ module mkLLCache(CLK, begin case (cache_toCQ_deqP) 1'd0: - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 = + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246 = cache_toCQ_data_0[130:67]; 1'd1: - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 = + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246 = cache_toCQ_data_1[130:67]; endcase end @@ -10741,10 +10719,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247 = cache_rsFromCQ_data_0[128:65]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247 = cache_rsFromCQ_data_1[128:65]; endcase end @@ -10753,10 +10731,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 = cache_rsFromCQ_data_0[64:1]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 = cache_rsFromCQ_data_1[64:1]; endcase end @@ -10833,10 +10811,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251 = + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249 = !cache_rsFromCQ_data_0[513]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251 = + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249 = !cache_rsFromCQ_data_1[513]; endcase end @@ -10844,10 +10822,10 @@ module mkLLCache(CLK, begin case (cache_toCQ_deqP) 1'd0: - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252 = + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250 = !cache_toCQ_data_0[515]; 1'd1: - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252 = + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250 = !cache_toCQ_data_1[515]; endcase end @@ -10856,10 +10834,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251 = cache_rsFromCQ_data_0[579:516]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251 = cache_rsFromCQ_data_1[579:516]; endcase end @@ -10868,14 +10846,36 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252 = cache_rsFromCQ_data_0[515:514]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252 = cache_rsFromCQ_data_1[515:514]; endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253 = + cache_toMQ_data_0[513]; + 1'd1: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253 = + cache_toMQ_data_1[513]; + endcase + end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 = + cache_toMQ_data_0[512]; + 1'd1: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 = + cache_toMQ_data_1[512]; + endcase + end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) 1'd0: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index a3e2152..2bc3b30 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1376,12 +1376,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_511_EQ_0_512_THEN_m__ETC___d3768; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5; reg [47 : 0] y_avValue_info_tag__h195314; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_IF_m_pipe_enq2Mat_lat_0_whas__77_TH_ETC___d3401; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3212, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310; @@ -3943,11 +3943,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5, IF_send_r_BITS_583_TO_582_511_EQ_0_512_THEN_m__ETC___d3789 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5911,7 +5911,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -9970,38 +9970,25 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10516,75 +10503,6 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3399; endcase end - always@(way__h173542 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308) - begin - case (way__h173542) - 4'd0: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218; - 4'd1: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224; - 4'd2: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230; - 4'd3: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236; - 4'd4: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242; - 4'd5: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248; - 4'd6: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254; - 4'd7: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260; - 4'd8: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266; - 4'd9: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272; - 4'd10: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278; - 4'd11: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284; - 4'd12: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290; - 4'd13: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296; - 4'd14: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302; - 4'd15: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; - endcase - end always@(way__h173542 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or @@ -10654,6 +10572,75 @@ module mkLLPipeline(CLK, IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; endcase end + always@(way__h173542 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308) + begin + case (way__h173542) + 4'd0: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218; + 4'd1: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224; + 4'd2: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230; + 4'd3: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236; + 4'd4: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242; + 4'd5: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248; + 4'd6: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254; + 4'd7: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260; + 4'd8: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266; + 4'd9: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272; + 4'd10: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278; + 4'd11: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284; + 4'd12: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290; + 4'd13: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296; + 4'd14: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302; + 4'd15: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; + endcase + end always@(way__h173542 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3406 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3411 or @@ -10723,6 +10710,19 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3481; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end // handling of inlined registers diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index 1344419..dc42889 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -25072,75 +25072,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or @@ -25210,6 +25141,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25376,6 +25376,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -25528,75 +25597,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[65]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25680,6 +25680,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11114 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11115 or @@ -25832,75 +25901,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[63]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25984,75 +25984,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[62]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or @@ -26122,6 +26053,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26288,75 +26288,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[60]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -26426,6 +26357,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26592,75 +26592,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[58]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or @@ -26730,6 +26661,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26896,75 +26896,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[56]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263 or @@ -27034,6 +26965,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27200,75 +27200,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[54]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300 or @@ -27338,6 +27269,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27808,75 +27808,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[50]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or @@ -27946,6 +27877,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -28112,75 +28112,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[48]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411 or @@ -28250,6 +28181,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -29024,75 +29024,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[42]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522 or @@ -29162,6 +29093,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34535,6 +34535,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34671,73 +34738,6 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end - always@(transfer_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getSlot_n or m_slotVec_0_dummy2_0_read__2303_AND_m_slotVec__ETC___d12503 or m_slotVec_1_dummy2_0_read__2308_AND_m_slotVec__ETC___d12504 or @@ -35083,6 +35083,75 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2378_AND_m_slotVec_ETC___d12418; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; + endcase + end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2568_AND_m_dat_ETC___d12573 or m_dataValidVec_1_dummy2_0_read__2574_AND_m_dat_ETC___d12579 or @@ -35221,75 +35290,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or @@ -35360,72 +35360,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; endcase end always@(sendRsToDmaC_getRq_n or @@ -35842,75 +35842,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -35980,6 +35911,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or @@ -36257,72 +36257,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; endcase end always@(sendRsToDmaC_getRq_n or @@ -36394,75 +36394,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or @@ -36532,6 +36463,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or @@ -36739,6 +36739,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or @@ -36877,75 +36946,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or @@ -37222,75 +37222,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or @@ -37360,6 +37291,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11595 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11596 or @@ -37843,75 +37843,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or @@ -37981,6 +37912,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11761 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11762 or @@ -38257,6 +38257,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11832; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11835 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11836 or @@ -38326,6 +38395,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or @@ -38395,75 +38533,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -38740,6 +38809,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11961; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11965 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11966 or @@ -38878,75 +39016,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or @@ -39223,144 +39292,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109; - endcase - end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or @@ -39430,6 +39361,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109; + endcase + end always@(sendRsToDmaC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -39702,6 +39702,75 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; + endcase + end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or @@ -39840,75 +39909,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12811; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; - endcase - end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12781 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12783 or @@ -40185,7 +40185,7 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12846; endcase end - always@(sendToM_getData_n or + always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or @@ -40203,54 +40203,54 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) begin - case (sendToM_getData_n) + case (sendRsToDmaC_getData_n) 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; endcase end @@ -40323,75 +40323,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12880; endcase end - always@(sendRsToDmaC_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) - begin - case (sendRsToDmaC_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40461,6 +40392,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12949; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40668,6 +40668,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or @@ -40806,75 +40875,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -41151,75 +41151,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or @@ -41289,6 +41220,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -41772,75 +41772,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or @@ -41910,6 +41841,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or @@ -42187,72 +42187,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; endcase end always@(sendRqToC_getRq_n or @@ -42324,75 +42324,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11465 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11466 or @@ -42462,6 +42393,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11502 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11503 or @@ -42669,6 +42669,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or @@ -42807,75 +42876,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11610; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11613 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11614 or @@ -43152,75 +43152,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11684; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707 or @@ -43290,6 +43221,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or @@ -43773,75 +43773,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or @@ -43911,6 +43842,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -44188,72 +44188,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; endcase end always@(sendRqToC_getRq_n or @@ -44325,75 +44325,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11980; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12002 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12003 or @@ -44463,6 +44394,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12039 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12040 or @@ -44670,6 +44670,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or @@ -44808,75 +44877,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; - endcase - end always@(sendRqToC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -46328,122 +46328,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[62]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[62]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[62]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[62]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[62]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[62]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[62]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[62]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[62]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[62]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[62]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[62]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[62]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[62]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[62]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[62]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46560,6 +46444,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[63]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[62]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[62]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[62]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[62]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[62]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[62]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[62]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[62]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[62]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[62]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[62]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[62]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[62]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[62]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[62]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[62]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47024,6 +47024,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[58]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[56]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[56]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[56]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[56]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[56]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[56]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[56]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[56]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[56]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[56]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[56]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[56]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[56]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[56]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[56]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[56]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47256,122 +47372,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[55]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[56]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[56]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[56]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[56]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[56]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[56]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[56]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[56]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[56]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[56]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[56]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[56]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[56]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[56]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[56]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[56]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47836,6 +47836,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[51]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[49]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[49]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[49]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[49]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[49]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[49]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[49]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[49]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[49]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[49]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[49]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[49]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[49]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[49]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[49]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[49]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48068,122 +48184,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[48]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[49]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[49]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[49]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[49]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[49]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[49]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[49]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[49]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[49]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[49]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[49]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[49]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[49]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[49]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[49]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[49]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48648,122 +48648,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[44]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[43]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[43]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[43]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[43]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[43]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[43]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[43]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[43]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[43]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[43]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[43]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[43]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[43]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[43]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[43]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[43]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48880,6 +48764,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[42]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[43]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[43]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[43]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[43]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[43]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[43]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[43]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[43]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[43]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[43]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[43]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[43]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[43]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[43]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[43]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[43]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49692,122 +49692,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[33]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[33]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[33]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[33]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[33]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[33]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[33]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[33]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[33]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[33]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[33]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[33]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[33]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[33]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[33]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[33]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49924,6 +49808,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[34]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[33]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[33]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[33]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[33]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[33]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[33]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[33]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[33]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[33]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[33]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[33]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[33]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[33]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[33]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[33]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[33]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50388,6 +50388,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[29]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[27]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[27]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[27]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[27]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[27]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[27]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[27]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[27]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[27]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[27]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[27]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[27]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[27]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[27]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[27]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[27]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50620,122 +50736,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[26]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[27]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[27]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[27]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[27]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[27]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[27]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[27]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[27]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[27]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[27]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[27]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[27]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[27]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[27]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[27]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[27]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51200,6 +51200,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[22]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[20]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[20]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[20]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[20]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[20]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[20]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[20]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[20]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[20]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[20]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[20]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[20]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[20]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[20]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[20]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[20]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51432,122 +51548,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[19]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[20]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[20]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[20]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[20]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[20]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[20]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[20]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[20]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[20]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[20]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[20]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[20]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[20]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[20]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[20]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[20]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52012,122 +52012,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[15]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[14]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[14]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[14]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[14]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[14]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[14]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[14]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[14]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[14]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[14]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[14]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[14]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[14]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[14]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[14]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[14]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52244,6 +52128,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[13]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[14]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[14]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[14]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[14]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[14]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[14]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[14]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[14]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[14]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[14]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[14]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[14]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[14]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[14]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[14]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[14]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53007,6 +53007,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53139,73 +53206,6 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getAddrSucc_n or m_addrSuccValidVec_0_dummy2_1$Q_OUT or m_addrSuccValidVec_0_dummy2_2$Q_OUT or @@ -53872,6 +53872,73 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end + always@(sendRqToC_getSlot_n or + m_slotVec_0_rl or + m_slotVec_1_rl or + m_slotVec_2_rl or + m_slotVec_3_rl or + m_slotVec_4_rl or + m_slotVec_5_rl or + m_slotVec_6_rl or + m_slotVec_7_rl or + m_slotVec_8_rl or + m_slotVec_9_rl or + m_slotVec_10_rl or + m_slotVec_11_rl or + m_slotVec_12_rl or + m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) + begin + case (sendRqToC_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_0_rl[1:0]; + 4'd1: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_1_rl[1:0]; + 4'd2: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_2_rl[1:0]; + 4'd3: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_3_rl[1:0]; + 4'd4: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_4_rl[1:0]; + 4'd5: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_5_rl[1:0]; + 4'd6: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_6_rl[1:0]; + 4'd7: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_7_rl[1:0]; + 4'd8: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_8_rl[1:0]; + 4'd9: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_9_rl[1:0]; + 4'd10: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_10_rl[1:0]; + 4'd11: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_11_rl[1:0]; + 4'd12: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_12_rl[1:0]; + 4'd13: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_13_rl[1:0]; + 4'd14: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_14_rl[1:0]; + 4'd15: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_15_rl[1:0]; + endcase + end always@(sendToM_getSlot_n or m_slotVec_0_rl or m_slotVec_1_rl or @@ -54006,73 +54073,6 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end - always@(sendRqToC_getSlot_n or - m_slotVec_0_rl or - m_slotVec_1_rl or - m_slotVec_2_rl or - m_slotVec_3_rl or - m_slotVec_4_rl or - m_slotVec_5_rl or - m_slotVec_6_rl or - m_slotVec_7_rl or - m_slotVec_8_rl or - m_slotVec_9_rl or - m_slotVec_10_rl or - m_slotVec_11_rl or - m_slotVec_12_rl or - m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) - begin - case (sendRqToC_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_0_rl[1:0]; - 4'd1: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_1_rl[1:0]; - 4'd2: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_2_rl[1:0]; - 4'd3: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_3_rl[1:0]; - 4'd4: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_4_rl[1:0]; - 4'd5: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_5_rl[1:0]; - 4'd6: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_6_rl[1:0]; - 4'd7: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_7_rl[1:0]; - 4'd8: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_8_rl[1:0]; - 4'd9: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_9_rl[1:0]; - 4'd10: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_10_rl[1:0]; - 4'd11: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_11_rl[1:0]; - 4'd12: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_12_rl[1:0]; - 4'd13: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_13_rl[1:0]; - 4'd14: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_14_rl[1:0]; - 4'd15: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_15_rl[1:0]; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or @@ -54515,75 +54515,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169 or @@ -54653,6 +54584,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -55786,74 +55786,6 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899271; endcase end - always@(sendRsToDmaC_getRq_n or - n__read_addr__h897906 or - n__read_addr__h897997 or - n__read_addr__h898088 or - n__read_addr__h898179 or - n__read_addr__h898270 or - n__read_addr__h898361 or - n__read_addr__h898452 or - n__read_addr__h898543 or - n__read_addr__h898634 or - n__read_addr__h898725 or - n__read_addr__h898816 or - n__read_addr__h898907 or - n__read_addr__h898998 or - n__read_addr__h899089 or - n__read_addr__h899180 or n__read_addr__h899271) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897906; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897997; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898088; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898179; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898270; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898361; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898452; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898543; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898634; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898725; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898816; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898907; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898998; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899089; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899180; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899271; - endcase - end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -55923,6 +55855,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end + always@(sendRsToDmaC_getRq_n or + n__read_addr__h897906 or + n__read_addr__h897997 or + n__read_addr__h898088 or + n__read_addr__h898179 or + n__read_addr__h898270 or + n__read_addr__h898361 or + n__read_addr__h898452 or + n__read_addr__h898543 or + n__read_addr__h898634 or + n__read_addr__h898725 or + n__read_addr__h898816 or + n__read_addr__h898907 or + n__read_addr__h898998 or + n__read_addr__h899089 or + n__read_addr__h899180 or n__read_addr__h899271) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897906; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897997; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898088; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898179; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898270; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898361; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898452; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898543; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898634; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898725; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898816; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898907; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898998; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899089; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899180; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899271; + endcase + end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -56129,6 +56129,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995883 or + n__read_addr__h995985 or + n__read_addr__h996087 or + n__read_addr__h996189 or + n__read_addr__h996291 or + n__read_addr__h996393 or + n__read_addr__h996495 or + n__read_addr__h996597 or + n__read_addr__h996699 or + n__read_addr__h996801 or + n__read_addr__h996903 or + n__read_addr__h997005 or + n__read_addr__h997107 or + n__read_addr__h997209 or + n__read_addr__h997311 or n__read_addr__h997413) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995883; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995985; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996087; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996189; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996291; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996393; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996495; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996597; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996699; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996801; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996903; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997005; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997107; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997209; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997311; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997413; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -56261,74 +56329,6 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995883 or - n__read_addr__h995985 or - n__read_addr__h996087 or - n__read_addr__h996189 or - n__read_addr__h996291 or - n__read_addr__h996393 or - n__read_addr__h996495 or - n__read_addr__h996597 or - n__read_addr__h996699 or - n__read_addr__h996801 or - n__read_addr__h996903 or - n__read_addr__h997005 or - n__read_addr__h997107 or - n__read_addr__h997209 or - n__read_addr__h997311 or n__read_addr__h997413) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995883; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995985; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996087; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996189; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996291; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996393; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996495; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996597; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996699; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996801; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996903; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997005; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997107; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997209; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997311; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997413; - endcase - end always@(sendRqToC_setSlot_s) begin case (sendRqToC_setSlot_s[7:6]) @@ -56770,123 +56770,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3267; endcase end - always@(pipelineResp_getSlot_n or - m_slotVec_0_dummy2_1$Q_OUT or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930 or - m_slotVec_1_dummy2_1$Q_OUT or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017 or - m_slotVec_2_dummy2_1$Q_OUT or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103 or - m_slotVec_3_dummy2_1$Q_OUT or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189 or - m_slotVec_4_dummy2_1$Q_OUT or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275 or - m_slotVec_5_dummy2_1$Q_OUT or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361 or - m_slotVec_6_dummy2_1$Q_OUT or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447 or - m_slotVec_7_dummy2_1$Q_OUT or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533 or - m_slotVec_8_dummy2_1$Q_OUT or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619 or - m_slotVec_9_dummy2_1$Q_OUT or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705 or - m_slotVec_10_dummy2_1$Q_OUT or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791 or - m_slotVec_11_dummy2_1$Q_OUT or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877 or - m_slotVec_12_dummy2_1$Q_OUT or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963 or - m_slotVec_13_dummy2_1$Q_OUT or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049 or - m_slotVec_14_dummy2_1$Q_OUT or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135 or - m_slotVec_15_dummy2_1$Q_OUT or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221) - begin - case (pipelineResp_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_0_dummy2_1$Q_OUT && m_slotVec_0_dummy2_2$Q_OUT && - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930; - 4'd1: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_1_dummy2_1$Q_OUT && m_slotVec_1_dummy2_2$Q_OUT && - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017; - 4'd2: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_2_dummy2_1$Q_OUT && m_slotVec_2_dummy2_2$Q_OUT && - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103; - 4'd3: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_3_dummy2_1$Q_OUT && m_slotVec_3_dummy2_2$Q_OUT && - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189; - 4'd4: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_4_dummy2_1$Q_OUT && m_slotVec_4_dummy2_2$Q_OUT && - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275; - 4'd5: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_5_dummy2_1$Q_OUT && m_slotVec_5_dummy2_2$Q_OUT && - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361; - 4'd6: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_6_dummy2_1$Q_OUT && m_slotVec_6_dummy2_2$Q_OUT && - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447; - 4'd7: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_7_dummy2_1$Q_OUT && m_slotVec_7_dummy2_2$Q_OUT && - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533; - 4'd8: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_8_dummy2_1$Q_OUT && m_slotVec_8_dummy2_2$Q_OUT && - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619; - 4'd9: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_9_dummy2_1$Q_OUT && m_slotVec_9_dummy2_2$Q_OUT && - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705; - 4'd10: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_10_dummy2_1$Q_OUT && m_slotVec_10_dummy2_2$Q_OUT && - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791; - 4'd11: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_11_dummy2_1$Q_OUT && m_slotVec_11_dummy2_2$Q_OUT && - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877; - 4'd12: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_12_dummy2_1$Q_OUT && m_slotVec_12_dummy2_2$Q_OUT && - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963; - 4'd13: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_13_dummy2_1$Q_OUT && m_slotVec_13_dummy2_2$Q_OUT && - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049; - 4'd14: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_14_dummy2_1$Q_OUT && m_slotVec_14_dummy2_2$Q_OUT && - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135; - 4'd15: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_15_dummy2_1$Q_OUT && m_slotVec_15_dummy2_2$Q_OUT && - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221; - endcase - end always@(pipelineResp_getSlot_n or m_slotVec_0_dummy2_1$Q_OUT or m_slotVec_0_dummy2_2$Q_OUT or @@ -57004,6 +56887,123 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260; endcase end + always@(pipelineResp_getSlot_n or + m_slotVec_0_dummy2_1$Q_OUT or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930 or + m_slotVec_1_dummy2_1$Q_OUT or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017 or + m_slotVec_2_dummy2_1$Q_OUT or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103 or + m_slotVec_3_dummy2_1$Q_OUT or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189 or + m_slotVec_4_dummy2_1$Q_OUT or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275 or + m_slotVec_5_dummy2_1$Q_OUT or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361 or + m_slotVec_6_dummy2_1$Q_OUT or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447 or + m_slotVec_7_dummy2_1$Q_OUT or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533 or + m_slotVec_8_dummy2_1$Q_OUT or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619 or + m_slotVec_9_dummy2_1$Q_OUT or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705 or + m_slotVec_10_dummy2_1$Q_OUT or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791 or + m_slotVec_11_dummy2_1$Q_OUT or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877 or + m_slotVec_12_dummy2_1$Q_OUT or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963 or + m_slotVec_13_dummy2_1$Q_OUT or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049 or + m_slotVec_14_dummy2_1$Q_OUT or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135 or + m_slotVec_15_dummy2_1$Q_OUT or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221) + begin + case (pipelineResp_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_0_dummy2_1$Q_OUT && m_slotVec_0_dummy2_2$Q_OUT && + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930; + 4'd1: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_1_dummy2_1$Q_OUT && m_slotVec_1_dummy2_2$Q_OUT && + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017; + 4'd2: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_2_dummy2_1$Q_OUT && m_slotVec_2_dummy2_2$Q_OUT && + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103; + 4'd3: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_3_dummy2_1$Q_OUT && m_slotVec_3_dummy2_2$Q_OUT && + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189; + 4'd4: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_4_dummy2_1$Q_OUT && m_slotVec_4_dummy2_2$Q_OUT && + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275; + 4'd5: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_5_dummy2_1$Q_OUT && m_slotVec_5_dummy2_2$Q_OUT && + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361; + 4'd6: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_6_dummy2_1$Q_OUT && m_slotVec_6_dummy2_2$Q_OUT && + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447; + 4'd7: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_7_dummy2_1$Q_OUT && m_slotVec_7_dummy2_2$Q_OUT && + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533; + 4'd8: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_8_dummy2_1$Q_OUT && m_slotVec_8_dummy2_2$Q_OUT && + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619; + 4'd9: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_9_dummy2_1$Q_OUT && m_slotVec_9_dummy2_2$Q_OUT && + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705; + 4'd10: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_10_dummy2_1$Q_OUT && m_slotVec_10_dummy2_2$Q_OUT && + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791; + 4'd11: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_11_dummy2_1$Q_OUT && m_slotVec_11_dummy2_2$Q_OUT && + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877; + 4'd12: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_12_dummy2_1$Q_OUT && m_slotVec_12_dummy2_2$Q_OUT && + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963; + 4'd13: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_13_dummy2_1$Q_OUT && m_slotVec_13_dummy2_2$Q_OUT && + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049; + 4'd14: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_14_dummy2_1$Q_OUT && m_slotVec_14_dummy2_2$Q_OUT && + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135; + 4'd15: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_15_dummy2_1$Q_OUT && m_slotVec_15_dummy2_2$Q_OUT && + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221; + endcase + end always@(pipelineResp_getSlot_n or IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1957 or IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2043 or diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index b7af2b7..e58a869 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -18,7 +18,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -47,7 +46,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 reg -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -64,12 +62,12 @@ // master1_arqos O 4 reg // master1_arregion O 4 reg // master1_rready O 1 reg +// jtag_tdo O 1 // tv_verifier_info_tx_tvalid O 1 reg // tv_verifier_info_tx_tdata O 608 reg // tv_verifier_info_tx_tstrb O 76 reg // tv_verifier_info_tx_tkeep O 76 reg // tv_verifier_info_tx_tlast O 1 reg -// jtag_tdo O 1 // CLK_jtag_tclk_out O 1 clock // CLK_GATE_jtag_tclk_out O 1 const // CLK I 1 clock @@ -97,11 +95,11 @@ // master1_rresp I 2 reg // master1_rlast I 1 reg // cpu_external_interrupt_req I 16 -// debug_external_interrupt_req_set_not_clear I 1 -// tv_verifier_info_tx_tready I 1 +// debug_external_interrupt_req_set_not_clear I 1 unused // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 +// tv_verifier_info_tx_tready I 1 // // Combinational paths from inputs to outputs: // (master0_awready, master0_wready) -> master0_bready @@ -150,8 +148,6 @@ module mkP3_Core(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -224,8 +220,6 @@ module mkP3_Core(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -276,6 +270,14 @@ module mkP3_Core(CLK, debug_external_interrupt_req_set_not_clear, + jtag_tdi, + + jtag_tms, + + jtag_tclk, + + jtag_tdo, + tv_verifier_info_tx_tvalid, tv_verifier_info_tx_tdata, @@ -288,14 +290,6 @@ module mkP3_Core(CLK, tv_verifier_info_tx_tready, - jtag_tdi, - - jtag_tms, - - jtag_tclk, - - jtag_tdo, - CLK_jtag_tclk_out, CLK_GATE_jtag_tclk_out); input CLK; @@ -342,9 +336,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -456,9 +447,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -535,6 +523,18 @@ module mkP3_Core(CLK, // action method debug_external_interrupt_req input debug_external_interrupt_req_set_not_clear; + // action method jtag_tdi + input jtag_tdi; + + // action method jtag_tms + input jtag_tms; + + // action method jtag_tclk + input jtag_tclk; + + // value method jtag_tdo + output jtag_tdo; + // value method tv_verifier_info_tx_m_tvalid output tv_verifier_info_tx_tvalid; @@ -559,18 +559,6 @@ module mkP3_Core(CLK, // action method tv_verifier_info_tx_m_tready input tv_verifier_info_tx_tready; - // action method jtag_tdi - input jtag_tdi; - - // action method jtag_tms - input jtag_tms; - - // action method jtag_tclk - input jtag_tclk; - - // value method jtag_tdo - output jtag_tdo; - // oscillator and gates for output clock CLK_jtag_tclk_out output CLK_jtag_tclk_out; output CLK_GATE_jtag_tclk_out; @@ -598,7 +586,6 @@ module mkP3_Core(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -606,8 +593,7 @@ module mkP3_Core(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -661,9 +647,10 @@ module mkP3_Core(CLK, reg [33 : 0] bus_dmi_rsp_fifof_q_1$D_IN; wire bus_dmi_rsp_fifof_q_1$EN; - // register rg_once - reg rg_once; - wire rg_once$D_IN, rg_once$EN; + // register rg_ndm_reset_delay + reg [7 : 0] rg_ndm_reset_delay; + wire [7 : 0] rg_ndm_reset_delay$D_IN; + wire rg_ndm_reset_delay$EN; // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; @@ -683,17 +670,17 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, - corew$set_htif_addrs_fromhost_addr, - corew$set_htif_addrs_tohost_addr, - corew$set_verbosity_logdelay; - wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; + corew$set_verbosity_logdelay, + corew$start_fromhost_addr, + corew$start_tohost_addr; + wire [31 : 0] corew$dmi_read_data, corew$dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, corew$cpu_dmem_master_wstrb, corew$cpu_imem_master_arlen, corew$cpu_imem_master_awlen, corew$cpu_imem_master_wstrb; - wire [6 : 0] corew$dm_dmi_read_addr_dm_addr, corew$dm_dmi_write_dm_addr; + wire [6 : 0] corew$dmi_read_addr_dm_addr, corew$dmi_write_dm_addr; wire [3 : 0] corew$cpu_dmem_master_arcache, corew$cpu_dmem_master_arid, corew$cpu_dmem_master_arqos, @@ -704,7 +691,6 @@ module mkP3_Core(CLK, corew$cpu_dmem_master_awregion, corew$cpu_dmem_master_bid, corew$cpu_dmem_master_rid, - corew$cpu_dmem_master_wid, corew$cpu_imem_master_arcache, corew$cpu_imem_master_arid, corew$cpu_imem_master_arqos, @@ -715,7 +701,6 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awregion, corew$cpu_imem_master_bid, corew$cpu_imem_master_rid, - corew$cpu_imem_master_wid, corew$set_verbosity_verbosity; wire [2 : 0] corew$cpu_dmem_master_arprot, corew$cpu_dmem_master_arsize, @@ -733,21 +718,19 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awburst, corew$cpu_imem_master_bresp, corew$cpu_imem_master_rresp; - wire corew$EN_cpu_reset_server_request_put, - corew$EN_cpu_reset_server_response_get, - corew$EN_dm_dmi_read_addr, - corew$EN_dm_dmi_read_data, - corew$EN_dm_dmi_write, - corew$EN_dm_ndm_reset_req_get_get, - corew$EN_set_htif_addrs, + wire corew$EN_dmi_read_addr, + corew$EN_dmi_read_data, + corew$EN_dmi_write, + corew$EN_ndm_reset_client_request_get, + corew$EN_ndm_reset_client_response_put, corew$EN_set_verbosity, + corew$EN_start, corew$EN_tv_verifier_info_get_get, - corew$RDY_cpu_reset_server_request_put, - corew$RDY_cpu_reset_server_response_get, - corew$RDY_dm_dmi_read_addr, - corew$RDY_dm_dmi_read_data, - corew$RDY_dm_dmi_write, - corew$RDY_dm_ndm_reset_req_get_get, + corew$RDY_dmi_read_addr, + corew$RDY_dmi_read_data, + corew$RDY_dmi_write, + corew$RDY_ndm_reset_client_request_get, + corew$RDY_ndm_reset_client_response_put, corew$RDY_tv_verifier_info_get_get, corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, @@ -793,7 +776,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$debug_external_interrupt_req_set_not_clear; + corew$ndm_reset_client_response_put, + corew$nmi_req_set_not_clear; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -809,6 +793,12 @@ module mkP3_Core(CLK, jtagtap$jtag_tdo, jtagtap$jtag_tms; + // ports of submodule ndm_reset + wire ndm_reset$RST_OUT; + + // ports of submodule ndm_reset_controller + wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -834,13 +824,13 @@ module mkP3_Core(CLK, CAN_FIRE_RL_mkConnectionVtoAf_6, CAN_FIRE_RL_mkConnectionVtoAf_7, CAN_FIRE_RL_mkConnectionVtoAf_8, + CAN_FIRE_RL_rl_always, CAN_FIRE_RL_rl_dmi_req, CAN_FIRE_RL_rl_dmi_req_cpu, CAN_FIRE_RL_rl_dmi_rsp, CAN_FIRE_RL_rl_dmi_rsp_cpu, - CAN_FIRE_RL_rl_ndmreset, - CAN_FIRE_RL_rl_once, - CAN_FIRE_RL_rl_reset_response, + CAN_FIRE_RL_rl_ndm_reset, + CAN_FIRE_RL_rl_ndm_reset_wait, CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_interrupt_reqs, CAN_FIRE_jtag_tclk, @@ -872,13 +862,13 @@ module mkP3_Core(CLK, WILL_FIRE_RL_mkConnectionVtoAf_6, WILL_FIRE_RL_mkConnectionVtoAf_7, WILL_FIRE_RL_mkConnectionVtoAf_8, + WILL_FIRE_RL_rl_always, WILL_FIRE_RL_rl_dmi_req, WILL_FIRE_RL_rl_dmi_req_cpu, WILL_FIRE_RL_rl_dmi_rsp, WILL_FIRE_RL_rl_dmi_rsp_cpu, - WILL_FIRE_RL_rl_ndmreset, - WILL_FIRE_RL_rl_once, - WILL_FIRE_RL_rl_reset_response, + WILL_FIRE_RL_rl_ndm_reset, + WILL_FIRE_RL_rl_ndm_reset_wait, WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_interrupt_reqs, WILL_FIRE_jtag_tclk, @@ -899,9 +889,10 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2, - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; + wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2; wire MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2, @@ -909,9 +900,17 @@ module mkP3_Core(CLK, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1; + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h1278; + reg [31 : 0] v__h1389; + reg [31 : 0] v__h1272; + reg [31 : 0] v__h1383; + // synopsys translate_on + // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28; - wire IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37; + wire IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87, _dfoo1, _dfoo3; @@ -959,9 +958,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid assign master0_wvalid = corew$cpu_imem_master_wvalid ; - // value method master0_m_wid - assign master0_wid = corew$cpu_imem_master_wid ; - // value method master0_m_wdata assign master0_wdata = corew$cpu_imem_master_wdata ; @@ -1066,9 +1062,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid assign master1_wvalid = corew$cpu_dmem_master_wvalid ; - // value method master1_m_wid - assign master1_wid = corew$cpu_dmem_master_wid ; - // value method master1_m_wdata assign master1_wdata = corew$cpu_dmem_master_wdata ; @@ -1141,6 +1134,21 @@ module mkP3_Core(CLK, assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method jtag_tdi + assign CAN_FIRE_jtag_tdi = 1'd1 ; + assign WILL_FIRE_jtag_tdi = 1'd1 ; + + // action method jtag_tms + assign CAN_FIRE_jtag_tms = 1'd1 ; + assign WILL_FIRE_jtag_tms = 1'd1 ; + + // action method jtag_tclk + assign CAN_FIRE_jtag_tclk = 1'd1 ; + assign WILL_FIRE_jtag_tclk = 1'd1 ; + + // value method jtag_tdo + assign jtag_tdo = jtagtap$jtag_tdo ; + // value method tv_verifier_info_tx_m_tvalid assign tv_verifier_info_tx_tvalid = tv_xactor$axi_out_tvalid ; @@ -1160,21 +1168,6 @@ module mkP3_Core(CLK, assign CAN_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; assign WILL_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - // action method jtag_tdi - assign CAN_FIRE_jtag_tdi = 1'd1 ; - assign WILL_FIRE_jtag_tdi = 1'd1 ; - - // action method jtag_tms - assign CAN_FIRE_jtag_tms = 1'd1 ; - assign WILL_FIRE_jtag_tms = 1'd1 ; - - // action method jtag_tclk - assign CAN_FIRE_jtag_tclk = 1'd1 ; - assign WILL_FIRE_jtag_tclk = 1'd1 ; - - // value method jtag_tdo - assign jtag_tdo = jtagtap$jtag_tdo ; - // submodule bus_dmi_req_fifof FIFO2 #(.width(32'd41), .guarded(32'd1)) bus_dmi_req_fifof(.RST(RST_N), .CLK(CLK), @@ -1187,8 +1180,9 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.CLK(CLK), - .RST_N(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + .CLK(CLK), + .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), @@ -1227,27 +1221,25 @@ module mkP3_Core(CLK, .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), - .debug_external_interrupt_req_set_not_clear(corew$debug_external_interrupt_req_set_not_clear), - .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), - .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), - .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), - .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), - .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), + .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), + .dmi_write_dm_addr(corew$dmi_write_dm_addr), + .dmi_write_dm_word(corew$dmi_write_dm_word), + .ndm_reset_client_response_put(corew$ndm_reset_client_response_put), + .nmi_req_set_not_clear(corew$nmi_req_set_not_clear), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), + .start_fromhost_addr(corew$start_fromhost_addr), + .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), - .EN_set_htif_addrs(corew$EN_set_htif_addrs), - .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), - .EN_dm_dmi_read_addr(corew$EN_dm_dmi_read_addr), - .EN_dm_dmi_read_data(corew$EN_dm_dmi_read_data), - .EN_dm_dmi_write(corew$EN_dm_dmi_write), - .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), + .EN_start(corew$EN_start), + .EN_dmi_read_addr(corew$EN_dmi_read_addr), + .EN_dmi_read_data(corew$EN_dmi_read_data), + .EN_dmi_write(corew$EN_dmi_write), + .EN_ndm_reset_client_request_get(corew$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(corew$EN_ndm_reset_client_response_put), .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), .RDY_set_verbosity(), - .RDY_set_htif_addrs(), - .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), - .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), + .RDY_start(), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), .cpu_imem_master_awid(corew$cpu_imem_master_awid), .cpu_imem_master_awaddr(corew$cpu_imem_master_awaddr), @@ -1260,7 +1252,6 @@ module mkP3_Core(CLK, .cpu_imem_master_awqos(corew$cpu_imem_master_awqos), .cpu_imem_master_awregion(corew$cpu_imem_master_awregion), .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), - .cpu_imem_master_wid(corew$cpu_imem_master_wid), .cpu_imem_master_wdata(corew$cpu_imem_master_wdata), .cpu_imem_master_wstrb(corew$cpu_imem_master_wstrb), .cpu_imem_master_wlast(corew$cpu_imem_master_wlast), @@ -1289,7 +1280,6 @@ module mkP3_Core(CLK, .cpu_dmem_master_awqos(corew$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(corew$cpu_dmem_master_awregion), .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(corew$cpu_dmem_master_wid), .cpu_dmem_master_wdata(corew$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(corew$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(corew$cpu_dmem_master_wlast), @@ -1306,11 +1296,13 @@ module mkP3_Core(CLK, .cpu_dmem_master_arqos(corew$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(corew$cpu_dmem_master_arregion), .cpu_dmem_master_rready(corew$cpu_dmem_master_rready), - .RDY_dm_dmi_read_addr(corew$RDY_dm_dmi_read_addr), - .dm_dmi_read_data(corew$dm_dmi_read_data), - .RDY_dm_dmi_read_data(corew$RDY_dm_dmi_read_data), - .RDY_dm_dmi_write(corew$RDY_dm_dmi_write), - .RDY_dm_ndm_reset_req_get_get(corew$RDY_dm_ndm_reset_req_get_get), + .RDY_dmi_read_addr(corew$RDY_dmi_read_addr), + .dmi_read_data(corew$dmi_read_data), + .RDY_dmi_read_data(corew$RDY_dmi_read_data), + .RDY_dmi_write(corew$RDY_dmi_write), + .ndm_reset_client_request_get(), + .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), .RDY_tv_verifier_info_get_get(corew$RDY_tv_verifier_info_get_get)); @@ -1333,6 +1325,19 @@ module mkP3_Core(CLK, .CLK_jtag_tclk_out(jtagtap$CLK_jtag_tclk_out), .CLK_GATE_jtag_tclk_out()); + // submodule ndm_reset + ResetEither ndm_reset(.A_RST(RST_N), + .B_RST(ndm_reset_controller$OUT_RST), + .RST_OUT(ndm_reset$RST_OUT)); + + // submodule ndm_reset_controller + MakeResetA #(.RSTDELAY(32'd10), .init(1'd1)) ndm_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(ndm_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1346,21 +1351,15 @@ module mkP3_Core(CLK, .axi_out_tkeep(tv_xactor$axi_out_tkeep), .axi_out_tlast(tv_xactor$axi_out_tlast)); - // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = - corew$RDY_cpu_reset_server_request_put && !rg_once ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; + // rule RL_rl_always + assign CAN_FIRE_RL_rl_always = 1'd1 ; + assign WILL_FIRE_RL_rl_always = 1'd1 ; - // rule RL_rl_reset_response - assign CAN_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - assign WILL_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - - // rule RL_rl_ndmreset - assign CAN_FIRE_RL_rl_ndmreset = - corew$RDY_dm_ndm_reset_req_get_get && rg_once ; - assign WILL_FIRE_RL_rl_ndmreset = CAN_FIRE_RL_rl_ndmreset ; + // rule RL_rl_ndm_reset + assign CAN_FIRE_RL_rl_ndm_reset = + corew$RDY_ndm_reset_client_request_get && + rg_ndm_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset = CAN_FIRE_RL_rl_ndm_reset ; // rule RL_mkConnectionVtoAf assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; @@ -1409,15 +1408,22 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 ; + IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu assign CAN_FIRE_RL_rl_dmi_rsp_cpu = - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_read_data ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_read_data ; assign WILL_FIRE_RL_rl_dmi_rsp_cpu = CAN_FIRE_RL_rl_dmi_rsp_cpu && !WILL_FIRE_RL_rl_dmi_req_cpu ; + // rule RL_rl_ndm_reset_wait + assign CAN_FIRE_RL_rl_ndm_reset_wait = + (rg_ndm_reset_delay != 8'd1 || + corew$RDY_ndm_reset_client_response_put) && + rg_ndm_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; + // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = corew$RDY_tv_verifier_info_get_get && tv_xactor$RDY_tv_in_put ; @@ -1458,37 +1464,38 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = - (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : - bus_dmi_rsp_fifof_q_1 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ? MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 : MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 = + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = + (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : + bus_dmi_rsp_fifof_q_1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 = (bus_dmi_rsp_fifof_cntr_r == 2'd2) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : 34'd0 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 = { 32'hAAAAAAAA, (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2) ? 2'd0 : 2'd2 } ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 = - { corew$dm_dmi_read_data, 2'd0 } ; + { corew$dmi_read_data, 2'd0 } ; + assign MUX_rg_ndm_reset_delay$write_1__VAL_1 = rg_ndm_reset_delay - 8'd1 ; // inlined wires assign bus_dmi_rsp_fifof_enqueueing$whas = @@ -1503,7 +1510,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 : + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1530,25 +1537,25 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_0$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register bus_dmi_rsp_fifof_q_1 always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr) begin case (1'b1) // synopsys parallel_case MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1; + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1; MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2; + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2; WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr: bus_dmi_rsp_fifof_q_1$D_IN = 34'd0; default: bus_dmi_rsp_fifof_q_1$D_IN = @@ -1556,14 +1563,18 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_1$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; - // register rg_once - assign rg_once$D_IN = !WILL_FIRE_RL_rl_ndmreset ; - assign rg_once$EN = WILL_FIRE_RL_rl_ndmreset || WILL_FIRE_RL_rl_once ; + // register rg_ndm_reset_delay + assign rg_ndm_reset_delay$D_IN = + WILL_FIRE_RL_rl_ndm_reset_wait ? + MUX_rg_ndm_reset_delay$write_1__VAL_1 : + 8'd110 ; + assign rg_ndm_reset_delay$EN = + WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; @@ -1626,28 +1637,27 @@ module mkP3_Core(CLK, assign corew$cpu_imem_master_rresp = master0_rresp ; assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; - assign corew$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; - assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; - assign corew$set_htif_addrs_tohost_addr = 64'h0 ; + assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; + assign corew$start_fromhost_addr = 64'h0 ; + assign corew$start_tohost_addr = 64'h0 ; assign corew$EN_set_verbosity = 1'b0 ; - assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; - assign corew$EN_cpu_reset_server_response_get = - corew$RDY_cpu_reset_server_response_get ; - assign corew$EN_dm_dmi_read_addr = + assign corew$EN_start = 1'b0 ; + assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; - assign corew$EN_dm_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; - assign corew$EN_dm_dmi_write = + assign corew$EN_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; + assign corew$EN_dmi_write = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ; - assign corew$EN_dm_ndm_reset_req_get_get = CAN_FIRE_RL_rl_ndmreset ; + assign corew$EN_ndm_reset_client_request_get = CAN_FIRE_RL_rl_ndm_reset ; + assign corew$EN_ndm_reset_client_response_put = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; // submodule jtagtap @@ -1659,26 +1669,29 @@ module mkP3_Core(CLK, assign jtagtap$jtag_tdi = jtag_tdi ; assign jtagtap$jtag_tms = jtag_tms ; + // submodule ndm_reset_controller + assign ndm_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule tv_xactor assign tv_xactor$axi_out_tready = tv_verifier_info_tx_tready ; assign tv_xactor$tv_in_put = corew$tv_verifier_info_get_get ; assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 = + assign IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? - corew$RDY_dm_dmi_read_addr : + corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || bus_dmi_rsp_fifof_cntr_r != 2'd2) && (bus_dmi_req_fifof$D_OUT[1:0] != 2'd2 || - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_write) ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 = + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1690,7 +1703,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_once <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -1703,7 +1716,8 @@ module mkP3_Core(CLK, if (bus_dmi_rsp_fifof_q_1$EN) bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY bus_dmi_rsp_fifof_q_1$D_IN; - if (rg_once$EN) rg_once <= `BSV_ASSIGNMENT_DELAY rg_once$D_IN; + if (rg_ndm_reset_delay$EN) + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end end @@ -1715,9 +1729,41 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_once = 1'h0; + rg_ndm_reset_delay = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + begin + v__h1278 = $stime; + #0; + end + v__h1272 = v__h1278 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1272, + $signed(32'd10)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1389 = $stime; + #0; + end + v__h1383 = v__h1389 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1383); + end + // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index a4e336f..0e742fc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -41,7 +41,6 @@ // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg // axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg @@ -133,7 +132,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awready, axi4_slave_wvalid, - axi4_slave_wid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, @@ -253,7 +251,6 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_m_wvalid input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; @@ -814,7 +811,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_wr_addr$FULL_N; // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; wire m_slave_xactor_f_wr_data$CLR, m_slave_xactor_f_wr_data$DEQ, m_slave_xactor_f_wr_data$EMPTY_N, @@ -1015,22 +1012,22 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75671; - reg [31 : 0] v__h75866; - reg [31 : 0] v__h76061; - reg [31 : 0] v__h76256; - reg [31 : 0] v__h76451; - reg [31 : 0] v__h76646; - reg [31 : 0] v__h76841; - reg [31 : 0] v__h77036; - reg [31 : 0] v__h77231; - reg [31 : 0] v__h77426; - reg [31 : 0] v__h77621; - reg [31 : 0] v__h77816; - reg [31 : 0] v__h78011; - reg [31 : 0] v__h78206; - reg [31 : 0] v__h78401; - reg [31 : 0] v__h78596; + reg [31 : 0] v__h75656; + reg [31 : 0] v__h75851; + reg [31 : 0] v__h76046; + reg [31 : 0] v__h76241; + reg [31 : 0] v__h76436; + reg [31 : 0] v__h76631; + reg [31 : 0] v__h76826; + reg [31 : 0] v__h77021; + reg [31 : 0] v__h77216; + reg [31 : 0] v__h77411; + reg [31 : 0] v__h77606; + reg [31 : 0] v__h77801; + reg [31 : 0] v__h77996; + reg [31 : 0] v__h78191; + reg [31 : 0] v__h78386; + reg [31 : 0] v__h78581; reg [31 : 0] v__h6142; reg [31 : 0] v__h13078; reg [31 : 0] v__h13263; @@ -1042,19 +1039,19 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h24054; reg [31 : 0] v__h26248; reg [31 : 0] v__h26461; - reg [31 : 0] v__h26738; - reg [31 : 0] v__h26966; - reg [31 : 0] v__h27863; - reg [31 : 0] v__h28046; - reg [31 : 0] v__h67028; - reg [31 : 0] v__h67316; - reg [31 : 0] v__h67845; - reg [31 : 0] v__h67931; - reg [31 : 0] v__h68130; - reg [31 : 0] v__h68351; - reg [31 : 0] v__h74688; - reg [31 : 0] v__h74798; - reg [31 : 0] v__h74911; + reg [31 : 0] v__h26735; + reg [31 : 0] v__h26959; + reg [31 : 0] v__h27854; + reg [31 : 0] v__h28037; + reg [31 : 0] v__h67019; + reg [31 : 0] v__h67307; + reg [31 : 0] v__h67836; + reg [31 : 0] v__h67922; + reg [31 : 0] v__h68121; + reg [31 : 0] v__h68340; + reg [31 : 0] v__h74675; + reg [31 : 0] v__h74785; + reg [31 : 0] v__h74898; reg [31 : 0] v__h6136; reg [31 : 0] v__h13072; reg [31 : 0] v__h13257; @@ -1066,42 +1063,42 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h25967; reg [31 : 0] v__h26242; reg [31 : 0] v__h26455; - reg [31 : 0] v__h26732; - reg [31 : 0] v__h26960; - reg [31 : 0] v__h27857; - reg [31 : 0] v__h28040; - reg [31 : 0] v__h67022; - reg [31 : 0] v__h67310; - reg [31 : 0] v__h67839; - reg [31 : 0] v__h67925; - reg [31 : 0] v__h68124; - reg [31 : 0] v__h68345; - reg [31 : 0] v__h74682; - reg [31 : 0] v__h74792; - reg [31 : 0] v__h74905; - reg [31 : 0] v__h75665; - reg [31 : 0] v__h75860; - reg [31 : 0] v__h76055; - reg [31 : 0] v__h76250; - reg [31 : 0] v__h76445; - reg [31 : 0] v__h76640; - reg [31 : 0] v__h76835; - reg [31 : 0] v__h77030; - reg [31 : 0] v__h77225; - reg [31 : 0] v__h77420; - reg [31 : 0] v__h77615; - reg [31 : 0] v__h77810; - reg [31 : 0] v__h78005; - reg [31 : 0] v__h78200; - reg [31 : 0] v__h78395; - reg [31 : 0] v__h78590; + reg [31 : 0] v__h26729; + reg [31 : 0] v__h26953; + reg [31 : 0] v__h27848; + reg [31 : 0] v__h28031; + reg [31 : 0] v__h67013; + reg [31 : 0] v__h67301; + reg [31 : 0] v__h67830; + reg [31 : 0] v__h67916; + reg [31 : 0] v__h68115; + reg [31 : 0] v__h68334; + reg [31 : 0] v__h74669; + reg [31 : 0] v__h74779; + reg [31 : 0] v__h74892; + reg [31 : 0] v__h75650; + reg [31 : 0] v__h75845; + reg [31 : 0] v__h76040; + reg [31 : 0] v__h76235; + reg [31 : 0] v__h76430; + reg [31 : 0] v__h76625; + reg [31 : 0] v__h76820; + reg [31 : 0] v__h77015; + reg [31 : 0] v__h77210; + reg [31 : 0] v__h77405; + reg [31 : 0] v__h77600; + reg [31 : 0] v__h77795; + reg [31 : 0] v__h77990; + reg [31 : 0] v__h78185; + reg [31 : 0] v__h78380; + reg [31 : 0] v__h78575; // synopsys translate_on // remaining internal signals reg [63 : 0] y_avValue_fst__h26146; - reg [4 : 0] x__h24009, x__h67485; + reg [4 : 0] x__h24009, x__h67476; reg [2 : 0] x__h13491, x__h23830; - reg [1 : 0] v__h67105, y_avValue_snd__h26147; + reg [1 : 0] v__h67096, y_avValue_snd__h26147; reg CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, @@ -1150,7 +1147,7 @@ module mkPLIC_16_2_7(CLK, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, @@ -1248,7 +1245,7 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; wire [63 : 0] addr_offset__h13214, - addr_offset__h26927, + addr_offset__h26920, rdata___1__h26402, rdata__h26200, v__h13420, @@ -1269,9 +1266,9 @@ module mkPLIC_16_2_7(CLK, y_avValue_fst__h26192; wire [31 : 0] v_ie__h18145, v_ip__h13672, - wdata32__h26928, + wdata32__h26921, x__h23671, - x__h67108; + x__h67099; wire [9 : 0] source_id__h15663, source_id__h15770, source_id__h15843, @@ -1334,121 +1331,121 @@ module mkPLIC_16_2_7(CLK, source_id__h23227, source_id__h23335, source_id__h23443, - source_id__h29473, - source_id__h30683, - source_id__h31893, - source_id__h33103, - source_id__h34313, - source_id__h35523, - source_id__h36733, - source_id__h37943, - source_id__h39153, - source_id__h40363, - source_id__h41573, - source_id__h42783, - source_id__h43993, - source_id__h45203, - source_id__h46413, - source_id__h47623, - source_id__h48833, - source_id__h50043, - source_id__h51253, - source_id__h52463, - source_id__h53673, - source_id__h54883, - source_id__h56093, - source_id__h57303, - source_id__h58513, - source_id__h59723, - source_id__h60933, - source_id__h62143, - source_id__h63353, - source_id__h64563, - source_id__h65773, - source_id__h67434, + source_id__h29464, + source_id__h30674, + source_id__h31884, + source_id__h33094, + source_id__h34304, + source_id__h35514, + source_id__h36724, + source_id__h37934, + source_id__h39144, + source_id__h40354, + source_id__h41564, + source_id__h42774, + source_id__h43984, + source_id__h45194, + source_id__h46404, + source_id__h47614, + source_id__h48824, + source_id__h50034, + source_id__h51244, + source_id__h52454, + source_id__h53664, + source_id__h54874, + source_id__h56084, + source_id__h57294, + source_id__h58504, + source_id__h59714, + source_id__h60924, + source_id__h62134, + source_id__h63344, + source_id__h64554, + source_id__h65764, + source_id__h67425, source_id_base__h13628, - source_id_base__h28146; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, + source_id_base__h28137; + wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71311, - b__h73316, + b__h71298, + b__h73303, max_id__h23957; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, + wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71310, - a__h73315; + a__h71297, + a__h73302; wire [1 : 0] rresp__h26201, - v__h26932, - v__h27092, - v__h27105, - v__h27940, - v__h27959, - v__h28123, - v__h28142, - v__h67142, - v__h67430, - v__h67474, + v__h26925, + v__h27083, + v__h27096, + v__h27931, + v__h27950, + v__h28114, + v__h28133, + v__h67133, + v__h67421, + v__h67465, y_avValue_snd__h26093, y_avValue_snd__h26114, y_avValue_snd__h26126, @@ -1460,8 +1457,8 @@ module mkPLIC_16_2_7(CLK, y_avValue_snd__h26193; wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, NOT_m_cfg_verbosity_read_ULE_1_5___d16, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, @@ -1469,62 +1466,62 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320, - NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328, - NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336, - NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344, - NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352, - NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360, - NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256, - NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264, - NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272, - NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280, - NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288, - NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296, - NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304, - NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, + NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240, + NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318, + NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326, + NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334, + NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342, + NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350, + NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358, + NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247, + NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254, + NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262, + NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270, + NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278, + NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286, + NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294, + NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302, + NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310, _dfoo1, _dfoo10, _dfoo100, @@ -3098,83 +3095,83 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; @@ -3321,10 +3318,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71310 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h71297 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73315 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h73302 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3381,7 +3378,7 @@ module mkPLIC_16_2_7(CLK, .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(m_slave_xactor_f_wr_data$D_IN), @@ -3442,181 +3439,181 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3686,174 +3683,174 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1988 ; // register m_cfg_verbosity @@ -3879,8 +3876,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 @@ -3894,8 +3891,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3906,8 +3903,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3918,8 +3915,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3931,8 +3928,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3944,8 +3941,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3957,8 +3954,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3970,8 +3967,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3983,8 +3980,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3996,8 +3993,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4009,8 +4006,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4021,8 +4018,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4033,8 +4030,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4045,8 +4042,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4057,8 +4054,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4069,8 +4066,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4081,8 +4078,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4093,8 +4090,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4105,8 +4102,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 @@ -4312,192 +4309,192 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4829,10 +4826,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_data assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; assign m_slave_xactor_f_wr_data$ENQ = axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; @@ -4840,7 +4834,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_resp assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26932 } ; + { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26925 } ; assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_f_wr_resp$DEQ = axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; @@ -4863,54 +4857,54 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67108 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67108 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26927[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : + ((x__h67099 == 32'h00200000) ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : + x__h67099 != 32'h00200004 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + addr_offset__h26920[11:2] == 10'd0 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? m_vrg_source_prio_10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? m_vrg_source_prio_11 : @@ -4921,38 +4915,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? 5'd10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? m_vrg_source_prio_12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? m_vrg_source_prio_13 : @@ -4963,50 +4957,50 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? 5'd12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? m_vrg_source_prio_14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? 5'd15 : (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? 5'd14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : @@ -5015,39 +5009,39 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? m_vrg_source_prio_2 : IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? @@ -5065,38 +5059,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? m_vrg_source_prio_4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? m_vrg_source_prio_5 : @@ -5107,38 +5101,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? 5'd4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? m_vrg_source_prio_6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? m_vrg_source_prio_7 : @@ -5149,38 +5143,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? 5'd6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? m_vrg_source_prio_8 : IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? m_vrg_source_prio_9 : @@ -5237,10792 +5231,10792 @@ module mkPLIC_16_2_7(CLK, x__h23671 == 32'h00200004 && m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && x__h24009 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30683 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h30674 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31893 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h31884 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33103 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h33094 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34313 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h34304 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35523 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h35514 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36733 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h36724 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37943 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h37934 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39153 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h39144 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40363 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h40354 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41573 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h41564 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42783 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h42774 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43993 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h43984 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45203 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h45194 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46413 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h46404 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47623 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h47614 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48833 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h48824 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50043 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h50034 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51253 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h51244 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52463 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h52454 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53673 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h53664 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54883 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h54874 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56093 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h56084 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57303 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h57294 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58513 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h58504 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59723 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h59714 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60933 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h60924 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62143 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h62134 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63353 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h63344 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64563 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h64554 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65773 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h65764 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29473 <= 10'd16 ; - assign NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242 = + source_id__h29464 <= 10'd16 ; + assign NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240 = !m_vrg_source_busy_0 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_0 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320 = + assign NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328 = + assign NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336 = + assign NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344 = + assign NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352 = + assign NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360 = + assign NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249 = + assign NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256 = + assign NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264 = + assign NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272 = + assign NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280 = + assign NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288 = + assign NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296 = + assign NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304 = + assign NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_8_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312 = + assign NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_9_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo10 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo100 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo883 ; assign _dfoo102 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo963 ; assign _dfoo11 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo110 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo983 ; assign _dfoo112 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo120 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo130 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1233 ; assign _dfoo137 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1253 ; assign _dfoo139 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo140 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1273 ; assign _dfoo141 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1363 ; assign _dfoo15 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo150 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1373 ; assign _dfoo151 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1393 ; assign _dfoo153 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1413 ; assign _dfoo155 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo160 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1513 ; assign _dfoo165 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1533 ; assign _dfoo167 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1553 ; assign _dfoo169 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1563 ; assign _dfoo17 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo170 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1633 ; assign _dfoo177 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1653 ; assign _dfoo179 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo180 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1673 ; assign _dfoo181 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1693 ; assign _dfoo183 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo190 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1773 ; assign _dfoo191 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1793 ; assign _dfoo193 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1813 ; assign _dfoo195 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1833 ; assign _dfoo197 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo20 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo200 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1963 ; assign _dfoo21 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo210 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo220 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo230 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo240 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo250 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo260 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo270 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo137 ; assign _dfoo274 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo139 ; assign _dfoo276 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo141 ; assign _dfoo278 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo143 ; assign _dfoo28 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo280 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo145 ; assign _dfoo282 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo147 ; assign _dfoo284 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo149 ; assign _dfoo286 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo151 ; assign _dfoo288 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo153 ; assign _dfoo29 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo290 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo155 ; assign _dfoo292 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo157 ; assign _dfoo294 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo159 ; assign _dfoo296 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo161 ; assign _dfoo298 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo163 ; assign _dfoo3 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo30 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo300 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo165 ; assign _dfoo302 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo167 ; assign _dfoo304 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo169 ; assign _dfoo306 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo171 ; assign _dfoo308 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo173 ; assign _dfoo31 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo310 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo175 ; assign _dfoo312 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo177 ; assign _dfoo314 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo179 ; assign _dfoo316 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo181 ; assign _dfoo318 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo183 ; assign _dfoo32 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo320 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo185 ; assign _dfoo322 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo187 ; assign _dfoo324 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo189 ; assign _dfoo326 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo191 ; assign _dfoo328 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo193 ; assign _dfoo33 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo330 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo195 ; assign _dfoo332 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo197 ; assign _dfoo334 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo199 ; assign _dfoo336 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo201 ; assign _dfoo338 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo203 ; assign _dfoo34 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo340 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo350 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo360 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo370 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo380 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo390 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo40 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo400 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo273 ; assign _dfoo41 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo410 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo275 ; assign _dfoo412 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo277 ; assign _dfoo414 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo279 ; assign _dfoo416 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo281 ; assign _dfoo418 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo283 ; assign _dfoo42 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo420 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo285 ; assign _dfoo422 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo287 ; assign _dfoo424 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo289 ; assign _dfoo426 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo291 ; assign _dfoo428 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo293 ; assign _dfoo43 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo430 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo295 ; assign _dfoo432 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo297 ; assign _dfoo434 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo299 ; assign _dfoo436 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo301 ; assign _dfoo438 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo303 ; assign _dfoo44 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo440 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo305 ; assign _dfoo442 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo307 ; assign _dfoo444 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo309 ; assign _dfoo446 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo311 ; assign _dfoo448 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo313 ; assign _dfoo45 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo450 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo315 ; assign _dfoo452 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo317 ; assign _dfoo454 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo319 ; assign _dfoo456 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo321 ; assign _dfoo458 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo323 ; assign _dfoo46 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo460 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo325 ; assign _dfoo462 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo327 ; assign _dfoo464 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo329 ; assign _dfoo466 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo331 ; assign _dfoo468 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo333 ; assign _dfoo47 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo470 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo335 ; assign _dfoo472 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo337 ; assign _dfoo474 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo339 ; assign _dfoo476 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo480 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo490 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo50 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo500 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo510 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo520 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo530 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo540 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo409 ; assign _dfoo546 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo411 ; assign _dfoo548 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo413 ; assign _dfoo55 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo550 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo415 ; assign _dfoo552 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo417 ; assign _dfoo554 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo419 ; assign _dfoo556 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo421 ; assign _dfoo558 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo423 ; assign _dfoo56 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo560 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo425 ; assign _dfoo562 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo427 ; assign _dfoo564 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo429 ; assign _dfoo566 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo431 ; assign _dfoo568 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo433 ; assign _dfoo57 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo570 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo435 ; assign _dfoo572 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo437 ; assign _dfoo574 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo439 ; assign _dfoo576 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo441 ; assign _dfoo578 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo443 ; assign _dfoo58 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo580 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo445 ; assign _dfoo582 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo447 ; assign _dfoo584 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo449 ; assign _dfoo586 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo451 ; assign _dfoo588 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo453 ; assign _dfoo59 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo590 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo455 ; assign _dfoo592 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo457 ; assign _dfoo594 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo459 ; assign _dfoo596 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo461 ; assign _dfoo598 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo463 ; assign _dfoo6 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo60 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo600 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo465 ; assign _dfoo602 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo467 ; assign _dfoo604 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo469 ; assign _dfoo606 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo471 ; assign _dfoo608 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo473 ; assign _dfoo61 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo610 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo475 ; assign _dfoo612 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo620 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo630 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo640 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo650 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo660 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo670 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo680 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo545 ; assign _dfoo682 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo547 ; assign _dfoo684 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo549 ; assign _dfoo686 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo551 ; assign _dfoo688 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo553 ; assign _dfoo690 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo555 ; assign _dfoo692 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo557 ; assign _dfoo694 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo559 ; assign _dfoo696 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo561 ; assign _dfoo698 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo563 ; assign _dfoo7 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo70 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo565 ; assign _dfoo702 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo567 ; assign _dfoo704 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo569 ; assign _dfoo706 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo571 ; assign _dfoo708 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo573 ; assign _dfoo710 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo575 ; assign _dfoo712 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo577 ; assign _dfoo714 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo579 ; assign _dfoo716 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo581 ; assign _dfoo718 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo583 ; assign _dfoo72 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo585 ; assign _dfoo722 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo587 ; assign _dfoo724 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo589 ; assign _dfoo726 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo591 ; assign _dfoo728 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo593 ; assign _dfoo730 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo595 ; assign _dfoo732 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo597 ; assign _dfoo734 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo599 ; assign _dfoo736 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo601 ; assign _dfoo738 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo603 ; assign _dfoo74 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo605 ; assign _dfoo742 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo607 ; assign _dfoo744 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo609 ; assign _dfoo746 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo611 ; assign _dfoo748 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo80 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo681 ; assign _dfoo818 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo683 ; assign _dfoo82 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo685 ; assign _dfoo822 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo687 ; assign _dfoo824 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo689 ; assign _dfoo826 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo691 ; assign _dfoo828 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo693 ; assign _dfoo830 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo695 ; assign _dfoo832 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo697 ; assign _dfoo834 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo699 ; assign _dfoo836 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo701 ; assign _dfoo838 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo703 ; assign _dfoo84 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo705 ; assign _dfoo842 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo707 ; assign _dfoo844 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo709 ; assign _dfoo846 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo711 ; assign _dfoo848 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo713 ; assign _dfoo850 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo715 ; assign _dfoo852 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo717 ; assign _dfoo854 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo719 ; assign _dfoo856 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo721 ; assign _dfoo858 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo723 ; assign _dfoo86 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo725 ; assign _dfoo862 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo727 ; assign _dfoo864 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo729 ; assign _dfoo866 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo731 ; assign _dfoo868 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo733 ; assign _dfoo870 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo735 ; assign _dfoo872 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo737 ; assign _dfoo874 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo739 ; assign _dfoo876 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo741 ; assign _dfoo878 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo743 ; assign _dfoo88 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo745 ; assign _dfoo882 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo747 ; assign _dfoo884 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo90 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo817 ; assign _dfoo954 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo819 ; assign _dfoo956 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo821 ; assign _dfoo958 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo823 ; assign _dfoo96 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo825 ; assign _dfoo962 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo827 ; assign _dfoo964 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo829 ; assign _dfoo966 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo831 ; assign _dfoo968 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo833 ; assign _dfoo970 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo835 ; assign _dfoo972 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo837 ; assign _dfoo974 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo839 ; assign _dfoo976 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo841 ; assign _dfoo978 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo843 ; assign _dfoo98 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo845 ; assign _dfoo982 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo847 ; assign _dfoo984 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo849 ; assign _dfoo986 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo851 ; assign _dfoo988 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo853 ; assign _dfoo990 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo855 ; assign _dfoo992 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo857 ; assign _dfoo994 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo859 ; assign _dfoo996 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo861 ; assign _dfoo998 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo863 ; - assign a__h71310 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign a__h71297 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73315 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; + assign a__h73302 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; assign addr_offset__h13214 = m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26927 = + assign addr_offset__h26920 = m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71311 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign b__h71298 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73316 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; + assign b__h73303 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = addr_offset__h13214 < 64'h0000000000003000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = @@ -16044,181 +16038,181 @@ module mkPLIC_16_2_7(CLK, addr_offset__h13214 < 64'h0000000000002000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = source_id_base__h13628 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26927[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26927[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26927[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = + addr_offset__h26920[16:12] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = + addr_offset__h26920[16:12] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = + addr_offset__h26920[16:12] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26927 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26927[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26927[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26927[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26927[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26927[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26927[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26927[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26927[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26927[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26927[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26927[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26927[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26927[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26927[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26927[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26927[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26927[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = + addr_offset__h26920 < 64'h0000000000001000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = + addr_offset__h26920[11:2] <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = + addr_offset__h26920[11:2] == 10'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = + addr_offset__h26920[11:2] == 10'd2 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = + addr_offset__h26920[11:2] == 10'd3 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = + addr_offset__h26920[11:2] == 10'd4 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = + addr_offset__h26920[11:2] == 10'd5 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = + addr_offset__h26920[11:2] == 10'd6 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = + addr_offset__h26920[11:2] == 10'd7 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = + addr_offset__h26920[11:2] == 10'd8 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = + addr_offset__h26920[11:2] == 10'd9 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = + addr_offset__h26920[11:2] == 10'd10 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = + addr_offset__h26920[11:2] == 10'd11 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = + addr_offset__h26920[11:2] == 10'd12 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = + addr_offset__h26920[11:2] == 10'd13 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = + addr_offset__h26920[11:2] == 10'd14 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = + addr_offset__h26920[11:2] == 10'd15 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = + addr_offset__h26920[11:2] == 10'd16 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26927 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28146 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = + addr_offset__h26920 < 64'h0000000000002000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = + source_id_base__h28137 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = + addr_offset__h26920 < 64'h0000000000003000 ; assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26927 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26927[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26927[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26927[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = + addr_offset__h26920[11:7] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = + addr_offset__h26920[11:7] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = + addr_offset__h26920[11:7] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && m_vvrg_ie_1_10 ; assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && m_vvrg_ie_1_11 ; assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && m_vvrg_ie_1_12 ; assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && m_vvrg_ie_1_13 ; assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = m_vrg_source_ip_13 && @@ -16233,45 +16227,45 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && m_vvrg_ie_1_14 ; assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && m_vvrg_ie_1_15 ; assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && m_vvrg_ie_1_16 ; assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = m_vrg_source_ip_16 && @@ -16285,90 +16279,90 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && m_vvrg_ie_1_2 ; assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && m_vvrg_ie_1_3 ; assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && m_vvrg_ie_1_4 ; assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && m_vvrg_ie_1_5 ; assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && m_vvrg_ie_1_6 ; assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && m_vvrg_ie_1_7 ; assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = m_vrg_source_ip_7 && @@ -16383,30 +16377,30 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && m_vvrg_ie_1_8 ; assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && m_vvrg_ie_1_9 ; assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = m_vrg_source_ip_9 && @@ -16493,40 +16487,40 @@ module mkPLIC_16_2_7(CLK, assign source_id__h23227 = 10'd3 + source_id_base__h13628 ; assign source_id__h23335 = 10'd2 + source_id_base__h13628 ; assign source_id__h23443 = 10'd1 + source_id_base__h13628 ; - assign source_id__h29473 = { addr_offset__h26927[4:0], 5'd1 } ; - assign source_id__h30683 = { addr_offset__h26927[4:0], 5'd2 } ; - assign source_id__h31893 = { addr_offset__h26927[4:0], 5'd3 } ; - assign source_id__h33103 = { addr_offset__h26927[4:0], 5'd4 } ; - assign source_id__h34313 = { addr_offset__h26927[4:0], 5'd5 } ; - assign source_id__h35523 = { addr_offset__h26927[4:0], 5'd6 } ; - assign source_id__h36733 = { addr_offset__h26927[4:0], 5'd7 } ; - assign source_id__h37943 = { addr_offset__h26927[4:0], 5'd8 } ; - assign source_id__h39153 = { addr_offset__h26927[4:0], 5'd9 } ; - assign source_id__h40363 = { addr_offset__h26927[4:0], 5'd10 } ; - assign source_id__h41573 = { addr_offset__h26927[4:0], 5'd11 } ; - assign source_id__h42783 = { addr_offset__h26927[4:0], 5'd12 } ; - assign source_id__h43993 = { addr_offset__h26927[4:0], 5'd13 } ; - assign source_id__h45203 = { addr_offset__h26927[4:0], 5'd14 } ; - assign source_id__h46413 = { addr_offset__h26927[4:0], 5'd15 } ; - assign source_id__h47623 = { addr_offset__h26927[4:0], 5'd16 } ; - assign source_id__h48833 = { addr_offset__h26927[4:0], 5'd17 } ; - assign source_id__h50043 = { addr_offset__h26927[4:0], 5'd18 } ; - assign source_id__h51253 = { addr_offset__h26927[4:0], 5'd19 } ; - assign source_id__h52463 = { addr_offset__h26927[4:0], 5'd20 } ; - assign source_id__h53673 = { addr_offset__h26927[4:0], 5'd21 } ; - assign source_id__h54883 = { addr_offset__h26927[4:0], 5'd22 } ; - assign source_id__h56093 = { addr_offset__h26927[4:0], 5'd23 } ; - assign source_id__h57303 = { addr_offset__h26927[4:0], 5'd24 } ; - assign source_id__h58513 = { addr_offset__h26927[4:0], 5'd25 } ; - assign source_id__h59723 = { addr_offset__h26927[4:0], 5'd26 } ; - assign source_id__h60933 = { addr_offset__h26927[4:0], 5'd27 } ; - assign source_id__h62143 = { addr_offset__h26927[4:0], 5'd28 } ; - assign source_id__h63353 = { addr_offset__h26927[4:0], 5'd29 } ; - assign source_id__h64563 = { addr_offset__h26927[4:0], 5'd30 } ; - assign source_id__h65773 = { addr_offset__h26927[4:0], 5'd31 } ; - assign source_id__h67434 = { 5'd0, x__h67485 } ; + assign source_id__h29464 = { addr_offset__h26920[4:0], 5'd1 } ; + assign source_id__h30674 = { addr_offset__h26920[4:0], 5'd2 } ; + assign source_id__h31884 = { addr_offset__h26920[4:0], 5'd3 } ; + assign source_id__h33094 = { addr_offset__h26920[4:0], 5'd4 } ; + assign source_id__h34304 = { addr_offset__h26920[4:0], 5'd5 } ; + assign source_id__h35514 = { addr_offset__h26920[4:0], 5'd6 } ; + assign source_id__h36724 = { addr_offset__h26920[4:0], 5'd7 } ; + assign source_id__h37934 = { addr_offset__h26920[4:0], 5'd8 } ; + assign source_id__h39144 = { addr_offset__h26920[4:0], 5'd9 } ; + assign source_id__h40354 = { addr_offset__h26920[4:0], 5'd10 } ; + assign source_id__h41564 = { addr_offset__h26920[4:0], 5'd11 } ; + assign source_id__h42774 = { addr_offset__h26920[4:0], 5'd12 } ; + assign source_id__h43984 = { addr_offset__h26920[4:0], 5'd13 } ; + assign source_id__h45194 = { addr_offset__h26920[4:0], 5'd14 } ; + assign source_id__h46404 = { addr_offset__h26920[4:0], 5'd15 } ; + assign source_id__h47614 = { addr_offset__h26920[4:0], 5'd16 } ; + assign source_id__h48824 = { addr_offset__h26920[4:0], 5'd17 } ; + assign source_id__h50034 = { addr_offset__h26920[4:0], 5'd18 } ; + assign source_id__h51244 = { addr_offset__h26920[4:0], 5'd19 } ; + assign source_id__h52454 = { addr_offset__h26920[4:0], 5'd20 } ; + assign source_id__h53664 = { addr_offset__h26920[4:0], 5'd21 } ; + assign source_id__h54874 = { addr_offset__h26920[4:0], 5'd22 } ; + assign source_id__h56084 = { addr_offset__h26920[4:0], 5'd23 } ; + assign source_id__h57294 = { addr_offset__h26920[4:0], 5'd24 } ; + assign source_id__h58504 = { addr_offset__h26920[4:0], 5'd25 } ; + assign source_id__h59714 = { addr_offset__h26920[4:0], 5'd26 } ; + assign source_id__h60924 = { addr_offset__h26920[4:0], 5'd27 } ; + assign source_id__h62134 = { addr_offset__h26920[4:0], 5'd28 } ; + assign source_id__h63344 = { addr_offset__h26920[4:0], 5'd29 } ; + assign source_id__h64554 = { addr_offset__h26920[4:0], 5'd30 } ; + assign source_id__h65764 = { addr_offset__h26920[4:0], 5'd31 } ; + assign source_id__h67425 = { 5'd0, x__h67476 } ; assign source_id_base__h13628 = { addr_offset__h13214[4:0], 5'h0 } ; - assign source_id_base__h28146 = { addr_offset__h26927[4:0], 5'h0 } ; + assign source_id_base__h28137 = { addr_offset__h26920[4:0], 5'h0 } ; assign v__h13420 = { 61'd0, x__h13491 } ; assign v__h13669 = { 32'd0, v_ip__h13672 } ; assign v__h18142 = { 32'd0, v_ie__h18145 } ; @@ -16536,48 +16530,48 @@ module mkPLIC_16_2_7(CLK, v__h25472 : 64'd0 ; assign v__h25472 = { 59'd0, max_id__h23957 } ; - assign v__h26932 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? + assign v__h26925 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? 2'b11 : - v__h27092 ; - assign v__h27092 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27105 : - v__h27940 ; - assign v__h27105 = - (addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? + v__h27083 ; + assign v__h27083 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + v__h27096 : + v__h27931 ; + assign v__h27096 = + (addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? 2'b0 : 2'b10 ; - assign v__h27940 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27959 : - v__h28123 ; - assign v__h27959 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? + assign v__h27931 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? + v__h27950 : + v__h28114 ; + assign v__h27950 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? 2'b0 : 2'b10 ; - assign v__h28123 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign v__h28114 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? + v__h28133 : + v__h67096 ; + assign v__h28133 = + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28142 : - v__h67105 ; - assign v__h28142 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? 2'b0 : 2'b10 ; - assign v__h67142 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? + assign v__h67133 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? 2'b0 : 2'b10 ; - assign v__h67430 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67474 : + assign v__h67421 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? + v__h67465 : 2'b10 ; - assign v__h67474 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? + assign v__h67465 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? 2'b0 : 2'b10 ; assign v_ie__h18145 = @@ -16710,8 +16704,8 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26928 = - (addr_offset__h26927[2:0] == 3'd4) ? + assign wdata32__h26921 = + (addr_offset__h26920[2:0] == 3'd4) ? m_slave_xactor_f_wr_data$D_OUT[72:41] : m_slave_xactor_f_wr_data$D_OUT[40:9] ; assign x__h23671 = @@ -16720,8 +16714,8 @@ module mkPLIC_16_2_7(CLK, (addr_offset__h13214[2:0] == 3'd4) ? rdata___1__h26402 : rdata__h26200 ; - assign x__h67108 = - { addr_offset__h26927[31:16], 4'd0, addr_offset__h26927[11:0] } ; + assign x__h67099 = + { addr_offset__h26920[31:16], 4'd0, addr_offset__h26920[11:0] } ; assign y_avValue_fst__h26092 = (x__h24009 == 5'd0) ? v__h25453 : 64'd0 ; assign y_avValue_fst__h26113 = m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? @@ -16853,13 +16847,13 @@ module mkPLIC_16_2_7(CLK, default: x__h24009 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h26927 or + always@(addr_offset__h26920 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26927[16:12]) - 5'd0: x__h67485 = m_vrg_servicing_source_0; - 5'd1: x__h67485 = m_vrg_servicing_source_1; - default: x__h67485 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h26920[16:12]) + 5'd0: x__h67476 = m_vrg_servicing_source_0; + 5'd1: x__h67476 = m_vrg_servicing_source_1; + default: x__h67476 = 5'b01010 /* unspecified value */ ; endcase end always@(source_id__h16208 or @@ -24574,7 +24568,7 @@ module mkPLIC_16_2_7(CLK, default: y_avValue_fst__h26146 = 64'd0; endcase end - always@(source_id__h67434 or + always@(source_id__h67425 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24592,68 +24586,68 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h67434) + case (source_id__h67425) 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_0; 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_1; 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_2; 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_3; 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_4; 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_5; 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_6; 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_7; 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_8; 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_9; 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_10; 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_11; 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_12; 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_13; 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_14; 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_15; 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h67108 or v__h67142 or v__h67430) + always@(x__h67099 or v__h67133 or v__h67421) begin - case (x__h67108) - 32'h00200000: v__h67105 = v__h67142; - 32'h00200004: v__h67105 = v__h67430; - default: v__h67105 = 2'b10; + case (x__h67099) + 32'h00200000: v__h67096 = v__h67133; + 32'h00200004: v__h67096 = v__h67421; + default: v__h67096 = 2'b10; endcase end @@ -25240,9 +25234,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71310, + a__h71297, m_vrg_target_threshold_0, - b__h71311, + b__h71298, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25283,216 +25277,216 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73315, + a__h73302, m_vrg_target_threshold_1, - b__h73316, + b__h73303, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) begin - v__h75671 = $stime; + v__h75656 = $stime; #0; end - v__h75665 = v__h75671 / 32'd10; + v__h75650 = v__h75656 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75665, + v__h75650, $signed(32'd0), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) begin - v__h75866 = $stime; + v__h75851 = $stime; #0; end - v__h75860 = v__h75866 / 32'd10; + v__h75845 = v__h75851 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75860, + v__h75845, $signed(32'd1), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) begin - v__h76061 = $stime; + v__h76046 = $stime; #0; end - v__h76055 = v__h76061 / 32'd10; + v__h76040 = v__h76046 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76055, + v__h76040, $signed(32'd2), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) begin - v__h76256 = $stime; + v__h76241 = $stime; #0; end - v__h76250 = v__h76256 / 32'd10; + v__h76235 = v__h76241 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76250, + v__h76235, $signed(32'd3), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) begin - v__h76451 = $stime; + v__h76436 = $stime; #0; end - v__h76445 = v__h76451 / 32'd10; + v__h76430 = v__h76436 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76445, + v__h76430, $signed(32'd4), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) begin - v__h76646 = $stime; + v__h76631 = $stime; #0; end - v__h76640 = v__h76646 / 32'd10; + v__h76625 = v__h76631 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76640, + v__h76625, $signed(32'd5), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) begin - v__h76841 = $stime; + v__h76826 = $stime; #0; end - v__h76835 = v__h76841 / 32'd10; + v__h76820 = v__h76826 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76835, + v__h76820, $signed(32'd6), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) begin - v__h77036 = $stime; + v__h77021 = $stime; #0; end - v__h77030 = v__h77036 / 32'd10; + v__h77015 = v__h77021 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77030, + v__h77015, $signed(32'd7), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) begin - v__h77231 = $stime; + v__h77216 = $stime; #0; end - v__h77225 = v__h77231 / 32'd10; + v__h77210 = v__h77216 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77225, + v__h77210, $signed(32'd8), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) begin - v__h77426 = $stime; + v__h77411 = $stime; #0; end - v__h77420 = v__h77426 / 32'd10; + v__h77405 = v__h77411 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77420, + v__h77405, $signed(32'd9), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) begin - v__h77621 = $stime; + v__h77606 = $stime; #0; end - v__h77615 = v__h77621 / 32'd10; + v__h77600 = v__h77606 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77615, + v__h77600, $signed(32'd10), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) begin - v__h77816 = $stime; + v__h77801 = $stime; #0; end - v__h77810 = v__h77816 / 32'd10; + v__h77795 = v__h77801 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77810, + v__h77795, $signed(32'd11), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) begin - v__h78011 = $stime; + v__h77996 = $stime; #0; end - v__h78005 = v__h78011 / 32'd10; + v__h77990 = v__h77996 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78005, + v__h77990, $signed(32'd12), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) begin - v__h78206 = $stime; + v__h78191 = $stime; #0; end - v__h78200 = v__h78206 / 32'd10; + v__h78185 = v__h78191 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78200, + v__h78185, $signed(32'd13), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) begin - v__h78401 = $stime; + v__h78386 = $stime; #0; end - v__h78395 = v__h78401 / 32'd10; + v__h78380 = v__h78386 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78395, + v__h78380, $signed(32'd14), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) begin - v__h78596 = $stime; + v__h78581 = $stime; #0; end - v__h78590 = v__h78596 / 32'd10; + v__h78575 = v__h78581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78590, + v__h78575, $signed(32'd15), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) @@ -26127,14 +26121,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h26738 = $stime; + v__h26735 = $stime; #0; end - v__h26732 = v__h26738 / 32'd10; + v__h26729 = v__h26735 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26732); + $display("%0d: PLIC.rl_process_wr_req", v__h26729); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26238,15 +26232,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26287,485 +26273,467 @@ module mkPLIC_16_2_7(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) begin - v__h26966 = $stime; + v__h26959 = $stime; #0; end - v__h26960 = v__h26966 / 32'd10; + v__h26953 = v__h26959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26960); + v__h26953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) begin - v__h27863 = $stime; + v__h27854 = $stime; #0; end - v__h27857 = v__h27863 / 32'd10; + v__h27848 = v__h27854 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27857, - addr_offset__h26927[11:2], - wdata32__h26928); + v__h27848, + addr_offset__h26920[11:2], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) begin - v__h28046 = $stime; + v__h28037 = $stime; #0; end - v__h28040 = v__h28046 / 32'd10; + v__h28031 = v__h28037 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28040, - source_id_base__h28146); + v__h28031, + source_id_base__h28137); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) begin - v__h67028 = $stime; + v__h67019 = $stime; #0; end - v__h67022 = v__h67028 / 32'd10; + v__h67013 = v__h67019 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67022, - addr_offset__h26927[11:7], - source_id_base__h28146, - wdata32__h26928); + v__h67013, + addr_offset__h26920[11:7], + source_id_base__h28137, + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) begin - v__h67316 = $stime; + v__h67307 = $stime; #0; end - v__h67310 = v__h67316 / 32'd10; + v__h67301 = v__h67307 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67310, - addr_offset__h26927[16:12], - wdata32__h26928); + v__h67301, + addr_offset__h26920[16:12], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) begin - v__h67845 = $stime; + v__h67836 = $stime; #0; end - v__h67839 = v__h67845 / 32'd10; + v__h67830 = v__h67836 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67839, - addr_offset__h26927[16:12], - source_id__h67434); + v__h67830, + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) begin - v__h67931 = $stime; + v__h67922 = $stime; #0; end - v__h67925 = v__h67931 / 32'd10; + v__h67916 = v__h67922 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67925); + v__h67916); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Completion message from target %0d to source %0d", - addr_offset__h26927[16:12], - source_id__h67434); + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) begin - v__h68130 = $stime; + v__h68121 = $stime; #0; end - v__h68124 = v__h68130 / 32'd10; + v__h68115 = v__h68121 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68124); + v__h68115); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h68351 = $stime; + v__h68340 = $stime; #0; end - v__h68345 = v__h68351 / 32'd10; + v__h68334 = v__h68340 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68345); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68334); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26869,15 +26837,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26935,7 +26895,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26932); + $write("'h%h", v__h26925); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26951,38 +26911,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74688 = $stime; + v__h74675 = $stime; #0; end - v__h74682 = v__h74688 / 32'd10; + v__h74669 = v__h74675 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74682, + v__h74669, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74798 = $stime; + v__h74785 = $stime; #0; end - v__h74792 = v__h74798 / 32'd10; + v__h74779 = v__h74785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74792, + v__h74779, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74911 = $stime; + v__h74898 = $stime; #0; end - v__h74905 = v__h74911 / 32'd10; + v__h74892 = v__h74898 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74905, + v__h74892, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 6809f3b..5b384c7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -6,8 +6,6 @@ // // Ports: // Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg // RDY_start O 1 // master0_awvalid O 1 // master0_awid O 4 reg @@ -21,7 +19,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -50,7 +47,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -125,7 +121,6 @@ // master1_rlast I 1 reg // m_external_interrupt_req_set_not_clear I 1 // s_external_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 // debug_module_mem_server_awvalid I 1 @@ -140,7 +135,6 @@ // debug_module_mem_server_awqos I 4 reg // debug_module_mem_server_awregion I 4 reg // debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_wid I 4 reg // debug_module_mem_server_wdata I 64 reg // debug_module_mem_server_wstrb I 8 reg // debug_module_mem_server_wlast I 1 reg @@ -162,8 +156,6 @@ // hart0_fpr_mem_server_request_put I 70 reg // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 -// EN_hart0_server_reset_request_put I 1 -// EN_hart0_server_reset_response_get I 1 // EN_start I 1 // EN_set_verbosity I 1 // EN_hart0_run_halt_server_request_put I 1 @@ -200,12 +192,6 @@ module mkProc(CLK, RST_N, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - start_startpc, start_tohostAddr, start_fromhostAddr, @@ -238,8 +224,6 @@ module mkProc(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -312,8 +296,6 @@ module mkProc(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -364,8 +346,6 @@ module mkProc(CLK, s_external_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, - non_maskable_interrupt_req_set_not_clear, set_verbosity_verbosity, @@ -387,7 +367,6 @@ module mkProc(CLK, debug_module_mem_server_awready, debug_module_mem_server_wvalid, - debug_module_mem_server_wid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, @@ -474,14 +453,6 @@ module mkProc(CLK, input CLK; input RST_N; - // action method hart0_server_reset_request_put - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // action method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - // action method start input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; @@ -530,9 +501,6 @@ module mkProc(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -644,9 +612,6 @@ module mkProc(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -723,9 +688,6 @@ module mkProc(CLK, // action method s_external_interrupt_req input s_external_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; - // action method non_maskable_interrupt_req input non_maskable_interrupt_req_set_not_clear; @@ -752,7 +714,6 @@ module mkProc(CLK, // action method debug_module_mem_server_m_wvalid input debug_module_mem_server_wvalid; - input [3 : 0] debug_module_mem_server_wid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; @@ -893,7 +854,6 @@ module mkProc(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -901,8 +861,7 @@ module mkProc(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -926,8 +885,6 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, - RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, RDY_set_verbosity, RDY_start, RDY_v_to_TV_0_get, @@ -966,11 +923,9 @@ module mkProc(CLK, wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read; wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, @@ -1074,8 +1029,8 @@ module mkProc(CLK, wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN; // register llc_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire llc_axi4_adapter_master_xactor_rg_wr_data$EN; // register llc_axi4_adapter_master_xactor_rg_wr_resp @@ -1122,6 +1077,26 @@ module mkProc(CLK, reg llc_mem_server_propDstIdx_0_rl; wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN; + // register llc_mem_server_rg_cacheline_cache_addr + reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr; + wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN; + wire llc_mem_server_rg_cacheline_cache_addr$EN; + + // register llc_mem_server_rg_cacheline_cache_data + reg [511 : 0] llc_mem_server_rg_cacheline_cache_data; + wire [511 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN; + wire llc_mem_server_rg_cacheline_cache_data$EN; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay; + wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN; + + // register llc_mem_server_rg_cacheline_cache_state + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state; + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN; + wire llc_mem_server_rg_cacheline_cache_state$EN; + // register mmioPlatform_amoResp reg [63 : 0] mmioPlatform_amoResp; wire [63 : 0] mmioPlatform_amoResp$D_IN; @@ -1322,8 +1297,8 @@ module mkProc(CLK, wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_resp @@ -1435,7 +1410,6 @@ module mkProc(CLK, core_0$EN_recvDoStats, core_0$EN_renameDebug_renameErr_get, core_0$EN_sendDoStats, - core_0$EN_setDEIP, core_0$EN_setMEIP, core_0$EN_setSEIP, core_0$EN_tlbToMem_memReq_deq, @@ -1489,7 +1463,6 @@ module mkProc(CLK, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, core_0$sendDoStats, - core_0$setDEIP_v, core_0$setMEIP_v, core_0$setSEIP_v; @@ -1509,20 +1482,6 @@ module mkProc(CLK, enqDst_1_0_dummy2_1$EN, enqDst_1_0_dummy2_1$Q_OUT; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule llc reg [644 : 0] llc$dma_memReq_enq_x; wire [640 : 0] llc$to_mem_toM_first; @@ -1603,7 +1562,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N; // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_data - wire [76 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, + wire [72 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT; wire llc_mem_server_axi4_slave_xactor_f_wr_data$CLR, llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ, @@ -1631,13 +1590,10 @@ module mkProc(CLK, llc_mem_server_enqDst_0_dummy2_1$Q_OUT; // ports of submodule llc_mem_server_f_dword_in_line - wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN, - llc_mem_server_f_dword_in_line$D_OUT; + wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN; wire llc_mem_server_f_dword_in_line$CLR, llc_mem_server_f_dword_in_line$DEQ, - llc_mem_server_f_dword_in_line$EMPTY_N, - llc_mem_server_f_dword_in_line$ENQ, - llc_mem_server_f_dword_in_line$FULL_N; + llc_mem_server_f_dword_in_line$ENQ; // ports of submodule llc_mem_server_propDstData_0_dummy2_0 wire llc_mem_server_propDstData_0_dummy2_0$D_IN, @@ -1843,11 +1799,17 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, CAN_FIRE_RL_llc_mem_server_propDstData_0_canon, CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader, CAN_FIRE_RL_llc_mem_server_sendStRespToTlb, CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC, CAN_FIRE_RL_llc_mem_server_srcPropose, @@ -1901,7 +1863,6 @@ module mkProc(CLK, CAN_FIRE_RL_rl_dummy7, CAN_FIRE_RL_rl_dummy8, CAN_FIRE_RL_rl_dummy9, - CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_terminate, CAN_FIRE_RL_rl_tohost, CAN_FIRE_RL_sendPRq, @@ -1912,7 +1873,6 @@ module mkProc(CLK, CAN_FIRE_RL_srcPropose_1, CAN_FIRE_RL_srcPropose_2, CAN_FIRE_RL_srcPropose_3, - CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_debug_module_mem_server_m_arvalid, CAN_FIRE_debug_module_mem_server_m_awvalid, CAN_FIRE_debug_module_mem_server_m_bready, @@ -1927,8 +1887,6 @@ module mkProc(CLK, CAN_FIRE_hart0_put_other_req_put, CAN_FIRE_hart0_run_halt_server_request_put, CAN_FIRE_hart0_run_halt_server_response_get, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_master0_m_arready, CAN_FIRE_master0_m_awready, @@ -1962,11 +1920,17 @@ module mkProc(CLK, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, WILL_FIRE_RL_llc_mem_server_propDstData_0_canon, WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader, WILL_FIRE_RL_llc_mem_server_sendStRespToTlb, WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC, WILL_FIRE_RL_llc_mem_server_srcPropose, @@ -2020,7 +1984,6 @@ module mkProc(CLK, WILL_FIRE_RL_rl_dummy7, WILL_FIRE_RL_rl_dummy8, WILL_FIRE_RL_rl_dummy9, - WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_terminate, WILL_FIRE_RL_rl_tohost, WILL_FIRE_RL_sendPRq, @@ -2031,7 +1994,6 @@ module mkProc(CLK, WILL_FIRE_RL_srcPropose_1, WILL_FIRE_RL_srcPropose_2, WILL_FIRE_RL_srcPropose_3, - WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_debug_module_mem_server_m_arvalid, WILL_FIRE_debug_module_mem_server_m_awvalid, WILL_FIRE_debug_module_mem_server_m_bready, @@ -2046,8 +2008,6 @@ module mkProc(CLK, WILL_FIRE_hart0_put_other_req_put, WILL_FIRE_hart0_run_halt_server_request_put, WILL_FIRE_hart0_run_halt_server_response_get, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_master0_m_arready, WILL_FIRE_master0_m_awready, @@ -2071,9 +2031,11 @@ module mkProc(CLK, MUX_mmioPlatform_state$write_1__VAL_4; wire [644 : 0] MUX_llc$dma_memReq_enq_1__VAL_1, MUX_llc$dma_memReq_enq_1__VAL_2, - MUX_llc$dma_memReq_enq_1__VAL_3; + MUX_llc$dma_memReq_enq_1__VAL_3, + MUX_llc$dma_memReq_enq_1__VAL_4; wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + wire [511 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3, @@ -2097,6 +2059,7 @@ module mkProc(CLK, wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4; + wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2; wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1; wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1, MUX_mmioPlatform_state$write_1__VAL_2, @@ -2111,7 +2074,8 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, MUX_llc$dma_memReq_enq_1__SEL_1, - MUX_llc$dma_memReq_enq_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, MUX_mmioPlatform_amoResp$write_1__SEL_1, MUX_mmioPlatform_amoResp$write_1__SEL_2, MUX_mmioPlatform_curReq$write_1__SEL_1, @@ -2127,318 +2091,312 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h151720; - reg [31 : 0] v__h4189; - reg [31 : 0] v__h4362; - reg [31 : 0] v__h4626; - reg [31 : 0] v__h6665; - reg [31 : 0] v__h2465; - reg [31 : 0] v__h6966; - reg [31 : 0] v__h7459; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h93935; - reg [31 : 0] v__h93980; - reg [31 : 0] v__h93890; - reg [31 : 0] v__h104972; - reg [31 : 0] v__h104927; - reg [31 : 0] v__h123524; - reg [31 : 0] v__h123691; - reg [31 : 0] v__h125794; - reg [31 : 0] v__h143140; - reg [31 : 0] v__h122905; - reg [31 : 0] v__h149835; - reg [31 : 0] v__h150343; - reg [31 : 0] v__h2459; - reg [31 : 0] v__h4183; - reg [31 : 0] v__h4356; - reg [31 : 0] v__h4620; - reg [31 : 0] v__h6659; - reg [31 : 0] v__h6960; - reg [31 : 0] v__h7453; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h93884; - reg [31 : 0] v__h93929; - reg [31 : 0] v__h93974; - reg [31 : 0] v__h104921; - reg [31 : 0] v__h104966; - reg [31 : 0] v__h122899; - reg [31 : 0] v__h123518; - reg [31 : 0] v__h123685; - reg [31 : 0] v__h125788; - reg [31 : 0] v__h143134; - reg [31 : 0] v__h149829; - reg [31 : 0] v__h150337; - reg [31 : 0] v__h151714; + reg [31 : 0] v__h160987; + reg [31 : 0] v__h160523; + reg [31 : 0] v__h4001; + reg [31 : 0] v__h4174; + reg [31 : 0] v__h4438; + reg [31 : 0] v__h6475; + reg [31 : 0] v__h2277; + reg [31 : 0] v__h6775; + reg [31 : 0] v__h7268; + reg [31 : 0] v__h7431; + reg [31 : 0] v__h99152; + reg [31 : 0] v__h99950; + reg [31 : 0] v__h100099; + reg [31 : 0] v__h132480; + reg [31 : 0] v__h132647; + reg [31 : 0] v__h134750; + reg [31 : 0] v__h152094; + reg [31 : 0] v__h131861; + reg [31 : 0] v__h158788; + reg [31 : 0] v__h159296; + reg [31 : 0] v__h2271; + reg [31 : 0] v__h3995; + reg [31 : 0] v__h4168; + reg [31 : 0] v__h4432; + reg [31 : 0] v__h6469; + reg [31 : 0] v__h6769; + reg [31 : 0] v__h7262; + reg [31 : 0] v__h7425; + reg [31 : 0] v__h99146; + reg [31 : 0] v__h99944; + reg [31 : 0] v__h100093; + reg [31 : 0] v__h131855; + reg [31 : 0] v__h132474; + reg [31 : 0] v__h132641; + reg [31 : 0] v__h134744; + reg [31 : 0] v__h152088; + reg [31 : 0] v__h158782; + reg [31 : 0] v__h159290; + reg [31 : 0] v__h160517; + reg [31 : 0] v__h160981; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34, - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909, - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846, - data64__h136964, - ld_data__h121022, - rd_data_rdata__h119471, - w1__h45347, - w1__h45352, - w2__h45348, - w2__h45354, - x__h45343; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944; - reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5, - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1; - reg [7 : 0] strb8__h136965; - reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6, - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3; - reg [2 : 0] x__h59061; - reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22; + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34, + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908, + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875, + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843, + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845, + data64__h145920, + dword__h91077, + ld_data__h130082, + old_dword__h86767, + w1__h45156, + w1__h45161, + w2__h45157, + w2__h45163, + x__h45152; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943; + reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1, + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5; + reg [7 : 0] strb8__h145921; + reg [5 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441; + reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2, + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3, + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6, + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7; + reg [2 : 0] x__h58870; + reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4, + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8, + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20, - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319, - x__h59068, - x__h79786; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - new_cline__h123827; - wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394; - wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645; - wire [64 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - data__h29436, - failed_testnum__h151763, - line_addr__h104901, - mem_req_rd_addr_araddr__h123125, - mem_req_wr_addr_awaddr__h137049, - mmioPlatform_fromHostQ_data_0__h40137, - mmioPlatform_mtime__h34750, - mmioPlatform_reqData__h45939, - n__read_addr__h58929, - n__read_addr__h59014, - n__read_addr__h77548, - n__read_addr__h77627, - n__read_snd_addr__h92309, - newData__h29517, - newData__h32447, - op_result__h45955, - op_result__h46485, - op_result__h46490, - op_result__h46495, - op_result__h46500, - op_result__h46506, - op_result__h46513, - op_result__h46519, - req_addr__h94041, - result__h45398, - result__h45522, - result__h45550, - result__h45578, - result__h45606, - result__h45634, - result__h45662, - result__h45690, - result__h45718, - result__h45763, - result__h45791, - result__h45819, - result__h45847, - result__h45888, - result__h45916, - result__h46042, - result__h46069, - result__h46096, - result__h46123, - result__h46150, - result__h46177, - result__h46204, - result__h46231, - result__h46275, - result__h46302, - result__h46329, - result__h46356, - result__h46396, - result__h46423, - result__h46540, - result__h46606, - result__h46672, - result__h46738, - result__h46804, - result__h46870, - result__h46936, - result__h46998, - result__h47043, - result__h47109, - result__h47175, - result__h47233, - result__h47278, - w1___1__h45457, - w2___1__h45458, - x1_avValue_data__h37809, - x1_avValue_data__h42276, - x__h29628, - x__h32538, - x__h34898, - x__h38327, - x__h38338, - x__h40347, - x__h40358, - x__h47455; - wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671; - wire [31 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952, + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20, + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318, + x__h58877, + x__h79595; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410, + new_cline__h132783; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644; + wire [64 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192, + data__h29245, + failed_testnum__h160566, + line_addr__h100012, + line_addr__h99863, + mask__h86764, + mem_req_rd_addr_araddr__h132081, + mem_req_wr_addr_awaddr__h146005, + mmioPlatform_fromHostQ_data_0__h39946, + mmioPlatform_mtime__h34559, + mmioPlatform_reqData__h45748, + n__read_addr__h58738, + n__read_addr__h58823, + n__read_addr__h77357, + n__read_addr__h77436, + n__read_snd_addr__h121516, + newData__h29326, + newData__h32256, + new_dword__h86768, + op_result__h45764, + op_result__h46294, + op_result__h46299, + op_result__h46304, + op_result__h46309, + op_result__h46315, + op_result__h46322, + op_result__h46328, + result__h45207, + result__h45331, + result__h45359, + result__h45387, + result__h45415, + result__h45443, + result__h45471, + result__h45499, + result__h45527, + result__h45572, + result__h45600, + result__h45628, + result__h45656, + result__h45697, + result__h45725, + result__h45851, + result__h45878, + result__h45905, + result__h45932, + result__h45959, + result__h45986, + result__h46013, + result__h46040, + result__h46084, + result__h46111, + result__h46138, + result__h46165, + result__h46205, + result__h46232, + result__h46349, + result__h46415, + result__h46481, + result__h46547, + result__h46613, + result__h46679, + result__h46745, + result__h46807, + result__h46852, + result__h46918, + result__h46984, + result__h47042, + result__h47087, + w1___1__h45266, + w2___1__h45267, + x1_avValue_data__h37618, + x1_avValue_data__h42085, + x__h29437, + x__h32347, + x__h34707, + x__h38136, + x__h38147, + x__h40156, + x__h40167, + x__h47264, + x__h87930, + y__h87931, + y__h87932; + wire [47 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670; + wire [31 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665, + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h29229, - v__h29266, - w15347_BITS_31_TO_0__q15, - w25348_BITS_31_TO_0__q16, - x_data__h28019; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121; - wire [5 : 0] x__h123160, x__h137074; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120; - wire [3 : 0] b__h122832, b__h2359; - wire [2 : 0] n__read_id__h58933, n__read_id__h59018; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; - wire IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515, - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054, - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423, - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267, - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470, - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165, - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219, - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969, - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138, - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145, - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976, - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056, - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325, - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934, - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283, - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304, - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609, - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205, - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226, - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338, - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340, - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053, - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623, - mmioPlatform_cycle_12_ULT_99___d313, - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936, - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27644, - mmioPlatform_reqBE_BIT_4___h27604, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58934, - n__read_child__h59019, - n__read_child__h77551, - n__read_child__h77630, - n__read_snd_id__h92310, - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093, - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097, - x__h58747, - x__h72299, - x__h77370; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // action method hart0_server_reset_response_get - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; + v__h29038, + v__h29075, + w15156_BITS_31_TO_0__q15, + w25157_BITS_31_TO_0__q16, + x_data__h27828; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120; + wire [5 : 0] x__h132116, x__h146030; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119; + wire [3 : 0] b__h131788, b__h2171; + wire [2 : 0] n__read_id__h58742, n__read_id__h58827; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072, + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197, + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076, + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086; + wire IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514, + IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053, + IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422, + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266, + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617, + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164, + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460, + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218, + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968, + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137, + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144, + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975, + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055, + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324, + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933, + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282, + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303, + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608, + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204, + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225, + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337, + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339, + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052, + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477, + mmioPlatform_cycle_11_ULT_99___d312, + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935, + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295, + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576, + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321, + mmioPlatform_reqBE_BIT_0___h27453, + mmioPlatform_reqBE_BIT_4___h27413, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596, + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217, + n__read_child__h58743, + n__read_child__h58828, + n__read_child__h77360, + n__read_child__h77439, + n__read_snd_id__h121517, + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092, + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096, + x__h58556, + x__h72108, + x__h77179; // action method start - assign RDY_start = CAN_FIRE_start ; + assign RDY_start = mmioPlatform_state == 2'd0 ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -2482,9 +2440,6 @@ module mkProc(CLK, // value method master0_m_wvalid assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master0_m_wid - assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master0_m_wdata assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2591,9 +2546,6 @@ module mkProc(CLK, // value method master1_m_wvalid assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master1_m_wid - assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master1_m_wdata assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2668,10 +2620,6 @@ module mkProc(CLK, assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // action method non_maskable_interrupt_req assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ; assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ; @@ -2826,17 +2774,17 @@ module mkProc(CLK, assign v_to_TV_0_get = { core_0$v_to_TV_0_get[319:154], core_0$v_to_TV_0_get[154] ? - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 : + CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 : 12'hAAA, core_0$v_to_TV_0_get[141], core_0$v_to_TV_0_get[141] ? { core_0$v_to_TV_0_get[140], core_0$v_to_TV_0_get[140] ? - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 : - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 } : + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 : + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 } : 5'h0A, core_0$v_to_TV_0_get[135:72], - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, + CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4, core_0$v_to_TV_0_get[69:0] } ; assign RDY_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; assign CAN_FIRE_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; @@ -2846,17 +2794,17 @@ module mkProc(CLK, assign v_to_TV_1_get = { core_0$v_to_TV_1_get[319:154], core_0$v_to_TV_1_get[154] ? - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 : + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 : 12'hAAA, core_0$v_to_TV_1_get[141], core_0$v_to_TV_1_get[141] ? { core_0$v_to_TV_1_get[140], core_0$v_to_TV_1_get[140] ? - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 : - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 } : + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 : + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 } : 5'h0A, core_0$v_to_TV_1_get[135:72], - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8, core_0$v_to_TV_1_get[69:0] } ; assign RDY_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; assign CAN_FIRE_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; @@ -2880,7 +2828,6 @@ module mkProc(CLK, .mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x), .mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t), .recvDoStats_x(core_0$recvDoStats_x), - .setDEIP_v(core_0$setDEIP_v), .setMEIP_v(core_0$setMEIP_v), .setSEIP_v(core_0$setSEIP_v), .tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x), @@ -2915,7 +2862,6 @@ module mkProc(CLK, .EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get), .EN_setMEIP(core_0$EN_setMEIP), .EN_setSEIP(core_0$EN_setSEIP), - .EN_setDEIP(core_0$EN_setDEIP), .EN_hart0_run_halt_server_request_put(core_0$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(core_0$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(core_0$EN_hart0_gpr_mem_server_request_put), @@ -3006,7 +2952,6 @@ module mkProc(CLK, .RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get), .RDY_setMEIP(), .RDY_setSEIP(), - .RDY_setDEIP(), .RDY_hart0_run_halt_server_request_put(core_0$RDY_hart0_run_halt_server_request_put), .hart0_run_halt_server_response_get(core_0$hart0_run_halt_server_response_get), .RDY_hart0_run_halt_server_response_get(core_0$RDY_hart0_run_halt_server_response_get), @@ -3048,24 +2993,6 @@ module mkProc(CLK, .EN(enqDst_1_0_dummy2_1$EN), .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - // submodule llc mkLLCache llc(.CLK(CLK), .RST_N(RST_N), @@ -3189,7 +3116,7 @@ module mkProc(CLK, .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N)); // submodule llc_mem_server_axi4_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN), @@ -3234,9 +3161,9 @@ module mkProc(CLK, .ENQ(llc_mem_server_f_dword_in_line$ENQ), .DEQ(llc_mem_server_f_dword_in_line$DEQ), .CLR(llc_mem_server_f_dword_in_line$CLR), - .D_OUT(llc_mem_server_f_dword_in_line$D_OUT), - .FULL_N(llc_mem_server_f_dword_in_line$FULL_N), - .EMPTY_N(llc_mem_server_f_dword_in_line$EMPTY_N)); + .D_OUT(), + .FULL_N(), + .EMPTY_N()); // submodule llc_mem_server_propDstData_0_dummy2_0 RevertReg #(.width(32'd1), @@ -3511,16 +3438,16 @@ module mkProc(CLK, // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = - core_0$RDY_dCacheToParent_rqToP_first && core_0$RDY_dCacheToParent_rqToP_deq && + core_0$RDY_dCacheToParent_rqToP_first && (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || !propDstIdx_0_rl) ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = - core_0$RDY_iCacheToParent_rqToP_first && core_0$RDY_iCacheToParent_rqToP_deq && + core_0$RDY_iCacheToParent_rqToP_first && (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || !propDstIdx_1_rl) ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; @@ -3532,13 +3459,13 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 ; + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = - core_0$RDY_dCacheToParent_rsToP_first && core_0$RDY_dCacheToParent_rsToP_deq && + core_0$RDY_dCacheToParent_rsToP_first && (!propDstIdx_1_0_dummy2_0$Q_OUT || !propDstIdx_1_0_dummy2_1$Q_OUT || !propDstIdx_1_0_rl) ; @@ -3546,8 +3473,8 @@ module mkProc(CLK, // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = - core_0$RDY_iCacheToParent_rsToP_first && core_0$RDY_iCacheToParent_rsToP_deq && + core_0$RDY_iCacheToParent_rsToP_first && (!propDstIdx_1_1_dummy2_0$Q_OUT || !propDstIdx_1_1_dummy2_1$Q_OUT || !propDstIdx_1_1_rl) ; @@ -3560,7 +3487,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 ; + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3671,13 +3598,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2359 == 4'd0 ; + b__h2171 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2359 != 4'd0 && + b__h2171 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3701,23 +3628,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_12_ULT_99___d313 ; + mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_12_ULT_99___d313 ; + !mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 && + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3734,7 +3661,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 && + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3743,7 +3670,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 && + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3759,8 +3686,8 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMTimeCmpDone assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone = - core_0$RDY_mmioToPlatform_cRs_deq && core_0$RDY_mmioToPlatform_pRs_enq && + core_0$RDY_mmioToPlatform_cRs_deq && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone = @@ -3789,7 +3716,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40347 == 64'd0 || + x__h40156 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3807,7 +3734,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3815,14 +3742,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3832,22 +3759,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930 && + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3923,10 +3850,105 @@ module mkProc(CLK, assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ; assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ; + // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_st_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + !llc$dma_respSt_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd1 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + !llc$dma_respLd_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd2 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + // rule RL_llc_mem_server_srcPropose assign CAN_FIRE_RL_llc_mem_server_srcPropose = - core_0$RDY_tlbToMem_memReq_first && core_0$RDY_tlbToMem_memReq_deq && + core_0$RDY_tlbToMem_memReq_first && (!llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT || !llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT || !llc_mem_server_propDstIdx_0_rl) ; @@ -3941,64 +3963,20 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_wr - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b011 || - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] || - llc$RDY_dma_memReq_enq) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_rd - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b011 || - llc$RDY_dma_memReq_enq && - llc_mem_server_f_dword_in_line$FULL_N) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - // rule RL_llc_mem_server_sendTlbReqToLLC assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC = llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ; assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC = CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendLdRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - llc_mem_server_f_dword_in_line$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && - !llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = @@ -4008,14 +3986,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; - // rule RL_llc_mem_server_sendStRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && - llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && - !llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; - // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && @@ -4066,27 +4036,23 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h122832 == 4'd0 ; + b__h131788 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h122832 != 4'd0 && + b__h131788 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 ; + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4094,41 +4060,36 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || + (!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 ; - assign MUX_llc$dma_memReq_enq_1__SEL_2 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign MUX_mmioPlatform_amoResp$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,12 +4101,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || @@ -4175,20 +4136,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28019 } ; + x_data__h27828 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4202,35 +4163,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29436 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29245 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4239,91 +4200,44 @@ module mkProc(CLK, { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } : mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = - { req_addr__h94041, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, + { llc_mem_server_rg_cacheline_cache_addr, + 64'hFFFFFFFFFFFFFFFF, + llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h104901, + { line_addr__h99863, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = + { line_addr__h100012, + 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], 577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd1) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[127:64], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd0) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[63:0] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = + llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4248,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366))) ; + IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4261,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4276,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 or + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 or + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,75 +4309,75 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ? + (mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45343 } ; + x__h45152 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47455, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47264, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40347 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40156 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40347 != 64'd0 ; + x__h40156 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38327 == 64'd0 ; + x__h38136 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - x__h58747 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 && + x__h58556 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 } ; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - x__h77370 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 && + x__h77179 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 } ; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h92309, n__read_snd_id__h92310 } ; + { 1'd1, n__read_snd_addr__h121516, n__read_snd_id__h121517 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4512,15 +4426,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2359 - 4'd1 ; + b__h2171 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2359 ; - assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h2171 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4569,30 +4479,26 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h122832 - 4'd1 ; + b__h131788 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h122832 ; - assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h131788 ; // register cfg_verbosity assign cfg_verbosity$D_IN = EN_hart0_put_other_req_put ? hart0_put_other_req_put : set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ; + assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + (NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4600,8 +4506,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 } ; + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230, + IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4610,7 +4516,7 @@ module mkProc(CLK, // register llc_axi4_adapter_ctr_wr_rsps_pending_crg assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register llc_axi4_adapter_master_xactor_crg_rd_addr_full @@ -4640,7 +4546,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h123125, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h132081, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4651,13 +4557,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h137049, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h146005, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h136964, strb8__h136965, 1'd1 } ; + { data64__h145920, strb8__h145921, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4669,7 +4575,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h123827 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h132783 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4700,10 +4606,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487, + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4717,10 +4623,66 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; + // register llc_mem_server_rg_cacheline_cache_addr + assign llc_mem_server_rg_cacheline_cache_addr$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? + line_addr__h99863 : + line_addr__h100012 ; + assign llc_mem_server_rg_cacheline_cache_addr$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; + + // register llc_mem_server_rg_cacheline_cache_data + assign llc_mem_server_rg_cacheline_cache_data$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 : + llc$dma_respLd_first[516:5] ; + assign llc_mem_server_rg_cacheline_cache_data$EN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 10'd1023 : + MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ; + assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // register llc_mem_server_rg_cacheline_cache_state + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3; + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4; + default: llc_mem_server_rg_cacheline_cache_state$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign llc_mem_server_rg_cacheline_cache_state$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + // register mmioPlatform_amoResp assign mmioPlatform_amoResp$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ? @@ -4743,7 +4705,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4756,11 +4718,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 && + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4770,11 +4732,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4788,7 +4750,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_data_0$D_IN = mmioPlatform_fromHostQ_enqReq_rl[63:0] ; assign mmioPlatform_fromHostQ_data_0$EN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] ; @@ -4800,7 +4762,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_empty$D_IN = mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_fromHostQ_clearReq_rl || - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 ; + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 ; assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ; // register mmioPlatform_fromHostQ_enqReq_rl @@ -4809,8 +4771,8 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_full assign mmioPlatform_fromHostQ_full$D_IN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 ; + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 ; assign mmioPlatform_fromHostQ_full$EN = 1'd1 ; // register mmioPlatform_instSel @@ -4821,16 +4783,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32447 : + newData__h32256 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4839,7 +4801,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29517 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29326 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4849,9 +4811,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4953,9 +4915,9 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] : mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4965,7 +4927,7 @@ module mkProc(CLK, assign mmioPlatform_toHostQ_empty$D_IN = mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_toHostQ_clearReq_rl || - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 ; + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 ; assign mmioPlatform_toHostQ_empty$EN = 1'd1 ; // register mmioPlatform_toHostQ_enqReq_rl @@ -4974,8 +4936,8 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 ; + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 ; assign mmioPlatform_toHostQ_full$EN = 1'd1 ; // register mmioPlatform_waitLowerMSIPCRs @@ -4985,7 +4947,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4993,15 +4955,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5009,7 +4971,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full @@ -5060,8 +5022,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_master_xactor_rg_wr_data assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], + { mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64], 1'd1 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN = @@ -5083,28 +5044,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, + { IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 } ; + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, + { IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 } ; + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5117,36 +5078,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 ; + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5252,11 +5213,10 @@ module mkProc(CLK, end assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ; assign core_0$recvDoStats_x = core_0$sendDoStats ; - assign core_0$setDEIP_v = debug_external_interrupt_req_set_not_clear ; assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h121022, llc$dma_respLd_first[3] } ; + { ld_data__h130082, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5277,13 +5237,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || + (!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5294,15 +5254,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 || + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5337,7 +5297,6 @@ module mkProc(CLK, core_0$RDY_renameDebug_renameErr_get ; assign core_0$EN_setMEIP = 1'd1 ; assign core_0$EN_setSEIP = 1'd1 ; - assign core_0$EN_setDEIP = 1'd1 ; assign core_0$EN_hart0_run_halt_server_request_put = EN_hart0_run_halt_server_request_put ; assign core_0$EN_hart0_run_halt_server_response_get = @@ -5360,7 +5319,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5369,37 +5328,31 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule llc always@(MUX_llc$dma_memReq_enq_1__SEL_1 or MUX_llc$dma_memReq_enq_1__VAL_1 or - MUX_llc$dma_memReq_enq_1__SEL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or MUX_llc$dma_memReq_enq_1__VAL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or + MUX_llc$dma_memReq_enq_1__VAL_3 or WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or - MUX_llc$dma_memReq_enq_1__VAL_3) + MUX_llc$dma_memReq_enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case MUX_llc$dma_memReq_enq_1__SEL_1: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1; - MUX_llc$dma_memReq_enq_1__SEL_2: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2; - WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3; + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4; default: llc$dma_memReq_enq_x = 645'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5407,17 +5360,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 } ; + { IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h123827, + { new_cline__h132783, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5426,26 +5379,18 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign llc$EN_dma_memReq_enq = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 || - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; assign llc$EN_dma_respLd_deq = WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; assign llc$EN_dma_respSt_deq = WILL_FIRE_RL_llc_mem_server_sendStRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign llc$EN_to_mem_toM_deq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_rg_rd_req_beat == 3'd7 || @@ -5496,14 +5441,14 @@ module mkProc(CLK, debug_module_mem_server_arvalid && llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, rd_data_rdata__h119471, 3'd1 } ; + { 4'd0, dword__h91077, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = debug_module_mem_server_rready && llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ; @@ -5525,26 +5470,25 @@ module mkProc(CLK, debug_module_mem_server_awvalid && llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_data assign llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN = - { debug_module_mem_server_wid, - debug_module_mem_server_wdata, + { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast } ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ = debug_module_mem_server_wvalid && llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp assign llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN = 6'd0 ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ = debug_module_mem_server_bready && llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ; @@ -5553,7 +5497,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5561,12 +5505,9 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_doEnq ; // submodule llc_mem_server_f_dword_in_line - assign llc_mem_server_f_dword_in_line$D_IN = - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32] ; - assign llc_mem_server_f_dword_in_line$ENQ = - MUX_llc$dma_memReq_enq_1__SEL_2 ; - assign llc_mem_server_f_dword_in_line$DEQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ; + assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ; assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ; // submodule llc_mem_server_propDstData_0_dummy2_0 @@ -5586,11 +5527,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5784,86 +5725,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), - .amoExec_current_data(x__h34898), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h29628)); + .amoExec_current_data(x__h34707), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h29437)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34750), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h32538)); + .amoExec_current_data(mmioPlatform_mtime__h34559), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h32347)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, + 2'd0 }), + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h39946), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h38147)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h40358)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, - 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40137), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h38338)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h40167)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37809 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + x1_avValue_data__h37618 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 = + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 = + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29517 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054 = - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ? + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 = + newData__h29326 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053 = + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 : + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323 = - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ? + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322 = + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 : + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366 = + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; + assign IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5871,89 +5812,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + assign IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999 = + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 = + assign IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - x__h72299 } ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 = + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + x__h72108 } ; + assign IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538 = + { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd7) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[511:448], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd6) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[447:384], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd5) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[383:320], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd4) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[319:256] } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd3) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[255:192], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd2) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[191:128] } ; + assign IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 = - ((mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + assign IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 = + ((mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5966,23 +5934,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5995,23 +5963,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6024,144 +5992,144 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 = + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 = + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40347 == 64'd0 : - x__h38327 == 64'd0, + x__h40156 == 64'd0 : + x__h38136 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42276 } ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = + x1_avValue_data__h42085 } ; + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = + assign IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 = mmioPlatform_waitLowerMSIPCRs ? - core_0$RDY_mmioToPlatform_cRs_first && - core_0$RDY_mmioToPlatform_cRs_deq : + core_0$RDY_mmioToPlatform_cRs_deq && + core_0$RDY_mmioToPlatform_cRs_first : (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_first) && + core_0$RDY_mmioToPlatform_cRs_deq) && (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 = + core_0$RDY_mmioToPlatform_cRs_first) ; + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943) : mmioPlatform_fetchedInsts_0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 = + assign IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 = + assign IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077 = + assign IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087 = + assign IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 = + assign IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 = + assign IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 = + assign IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 = + assign IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 = + assign NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 || - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054) ; - assign NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 || + IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053) ; + assign NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 ; + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6172,7 +6140,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6183,7 +6151,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6195,7 +6163,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6207,7 +6175,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6217,7 +6185,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6227,44 +6195,44 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 = + assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 = !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_fromHostQ_clearReq_rl ; - assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 = + assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 = (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT || !mmioPlatform_fromHostQ_enqReq_rl[64]) && (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT && (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 = + assign NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || !core_0$mmioToPlatform_cRq_notEmpty || - core_0$RDY_mmioToPlatform_cRq_first && - core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = + core_0$RDY_mmioToPlatform_cRq_deq && + core_0$RDY_mmioToPlatform_cRq_first ; + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 = + assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_toHostQ_clearReq_rl ; - assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 = + assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 = (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT || (mmioPlatform_toHostQ_enqReq_lat_0$whas ? !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6273,101 +6241,109 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 = + assign NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340 = + assign NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 = + assign NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 = + assign NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 = - { CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 = - { CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - x__h79786 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360 = - { CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 = - { CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20, - x__h59061, - x__h59068 } ; - assign b__h122832 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120 = + { CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417 = + { CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410, + x__h79595 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359 = + { CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119 = + { CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20, + x__h58870, + x__h58877 } ; + assign b__h131788 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2359 = + assign b__h2171 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29436 = + assign data__h29245 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29229, 32'd0 } ; - assign failed_testnum__h151763 = + { v__h29038, 32'd0 } ; + assign failed_testnum__h160566 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h104901 = + assign line_addr__h100012 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign mem_req_rd_addr_araddr__h123125 = - { llc$to_mem_toM_first[68:11], x__h123160 } ; - assign mem_req_wr_addr_awaddr__h137049 = - { llc$to_mem_toM_first[639:582], x__h137074 } ; - assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 = + assign line_addr__h99863 = + { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], + 6'b0 } ; + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 = + line_addr__h100012 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 = + line_addr__h99863 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h86764 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'hFF : + 8'h0 } ; + assign mem_req_rd_addr_araddr__h132081 = + { llc$to_mem_toM_first[68:11], x__h132116 } ; + assign mem_req_wr_addr_awaddr__h146005 = + { llc$to_mem_toM_first[639:582], x__h146030 } ; + assign mmioPlatform_cycle_11_ULT_99___d312 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40137 = + assign mmioPlatform_fromHostQ_data_0__h39946 = mmioPlatform_fromHostQ_data_0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = + assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] || (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT || @@ -6376,275 +6352,273 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34750 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32447 ; - assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = + assign mmioPlatform_mtime__h34559 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 = + mmioPlatform_mtimecmp_0 <= newData__h32256 ; + assign mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27644 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27604 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h45939 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = + assign mmioPlatform_reqBE_BIT_0___h27453 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27413 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h45748 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (!IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (!mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 = + assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 || + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 || (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h58929 = + assign n__read_addr__h58738 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59014 = + assign n__read_addr__h58823 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77548 = + assign n__read_addr__h77357 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 : + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154 : 64'd0 ; - assign n__read_addr__h77627 = + assign n__read_addr__h77436 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 : + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192 : 64'd0 ; - assign n__read_child__h58934 = + assign n__read_child__h58743 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59019 = + assign n__read_child__h58828 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77551 = + assign n__read_child__h77360 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 ; - assign n__read_child__h77630 = + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 ; + assign n__read_child__h77439 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 ; - assign n__read_id__h58933 = + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 ; + assign n__read_id__h58742 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59018 = + assign n__read_id__h58827 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h92309 = + assign n__read_snd_addr__h121516 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h92310 = + assign n__read_snd_id__h121517 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h29517 = + assign newData__h29326 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29628 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32447 = + x__h29437 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 ; + assign newData__h32256 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32538 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h123827 = + x__h32347 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 ; + assign new_cline__h132783 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h45955 = - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 + - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ; - assign op_result__h46485 = w1__h45352 ^ w2__h45354 ; - assign op_result__h46490 = w1__h45352 & w2__h45354 ; - assign op_result__h46495 = w1__h45352 | w2__h45354 ; - assign op_result__h46500 = - (w1__h45352 < w2__h45354) ? w1__h45352 : w2__h45354 ; - assign op_result__h46506 = - (w1__h45352 <= w2__h45354) ? w2__h45354 : w1__h45352 ; - assign op_result__h46513 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + assign new_dword__h86768 = x__h87930 | y__h87931 ; + assign op_result__h45764 = + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 + + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ; + assign op_result__h46294 = w1__h45161 ^ w2__h45163 ; + assign op_result__h46299 = w1__h45161 & w2__h45163 ; + assign op_result__h46304 = w1__h45161 | w2__h45163 ; + assign op_result__h46309 = + (w1__h45161 < w2__h45163) ? w1__h45161 : w2__h45163 ; + assign op_result__h46315 = + (w1__h45161 <= w2__h45163) ? w2__h45163 : w1__h45161 ; + assign op_result__h46322 = + ((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^ 64'h8000000000000000)) ? - w1__h45352 : - w2__h45354 ; - assign op_result__h46519 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + w1__h45161 : + w2__h45163 ; + assign op_result__h46328 = + ((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^ 64'h8000000000000000)) ? - w2__h45354 : - w1__h45352 ; - assign propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 = + w2__h45163 : + w1__h45161 ; + assign propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097 = + assign propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign req_addr__h94041 = - { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], - 6'b0 } ; - assign result__h45398 = + assign result__h45207 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0] } ; - assign result__h45522 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45550 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45578 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45606 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45634 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45662 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45690 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45718 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45763 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h45791 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h45819 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h45847 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h45888 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h45916 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46042 = + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0] } ; + assign result__h45331 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45359 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45387 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45415 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45443 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45471 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45499 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45527 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45572 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45600 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45628 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45656 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45697 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h45725 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h45851 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46069 = + assign result__h45878 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46096 = + assign result__h45905 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46123 = + assign result__h45932 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46150 = + assign result__h45959 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46177 = + assign result__h45986 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46204 = + assign result__h46013 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46231 = + assign result__h46040 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46275 = + assign result__h46084 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46302 = + assign result__h46111 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46329 = + assign result__h46138 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46356 = + assign result__h46165 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46396 = + assign result__h46205 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46423 = + assign result__h46232 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46540 = + assign result__h46349 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46606 = + assign result__h46415 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46672 = + assign result__h46481 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46738 = + assign result__h46547 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h46804 = + assign result__h46613 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h46870 = + assign result__h46679 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h46936 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + assign result__h46745 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h46998 = + assign result__h46807 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0] } ; - assign result__h47043 = + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0] } ; + assign result__h46852 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47109 = + assign result__h46918 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47175 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + assign result__h46984 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47233 = + assign result__h47042 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0] } ; - assign result__h47278 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0] } ; + assign result__h47087 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29229 = mmioPlatform_waitUpperMSIPCRs ? v__h29266 : 32'd0 ; - assign v__h29266 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15347_BITS_31_TO_0__q15 = w1__h45347[31:0] ; - assign w1___1__h45457 = { 32'd0, w1__h45347[31:0] } ; - assign w25348_BITS_31_TO_0__q16 = w2__h45348[31:0] ; - assign w2___1__h45458 = { 32'd0, w2__h45348[31:0] } ; - assign x1_avValue_data__h37809 = + assign v__h29038 = mmioPlatform_waitUpperMSIPCRs ? v__h29075 : 32'd0 ; + assign v__h29075 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15156_BITS_31_TO_0__q15 = w1__h45156[31:0] ; + assign w1___1__h45266 = { 32'd0, w1__h45156[31:0] } ; + assign w25157_BITS_31_TO_0__q16 = w2__h45157[31:0] ; + assign w2___1__h45267 = { 32'd0, w2__h45157[31:0] } ; + assign x1_avValue_data__h37618 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42276 = + assign x1_avValue_data__h42085 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h123160 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h137074 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34898 = mmioPlatform_mtimecmp_0 ; - assign x__h38327 = + assign x__h132116 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h146030 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34707 = mmioPlatform_mtimecmp_0 ; + assign x__h38136 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38338 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 ; - assign x__h40347 = + x__h38147 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675 ; + assign x__h40156 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40358 : + x__h40167 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6653,107 +6627,48 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47455 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58747 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? + assign x__h47264 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58556 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ; - assign x__h72299 = + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 ; + assign x__h72108 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 ; - assign x__h77370 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 ; + assign x__h77179 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ; - assign x_data__h28019 = { 31'd0, mmioPlatform_reqData[0] } ; - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - core_0$v_to_TV_1_get[153:142]; - default: CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - 12'd2303; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[71:70]) - 2'd0, 2'd1: - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = - core_0$v_to_TV_1_get[71:70]; - default: CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = 2'd2; - endcase - end + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 ; + assign x__h87930 = old_dword__h86767 & y__h87932 ; + assign x_data__h27828 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h87931 = + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & + mask__h86764 ; + assign y__h87932 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'd0 : + 8'd255 } ; always@(core_0$v_to_TV_0_get) begin case (core_0$v_to_TV_0_get[153:142]) @@ -6797,9 +6712,9 @@ module mkProc(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = + CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 = core_0$v_to_TV_0_get[153:142]; - default: CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = + default: CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 = 12'd2303; endcase end @@ -6807,9 +6722,9 @@ module mkProc(CLK, begin case (core_0$v_to_TV_0_get[139:136]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 = core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = 4'd15; + default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 = 4'd15; endcase end always@(core_0$v_to_TV_0_get) @@ -6828,469 +6743,579 @@ module mkProc(CLK, 4'd11, 4'd12, 4'd13: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 = core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = 4'd15; + default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 = 4'd15; endcase end always@(core_0$v_to_TV_0_get) begin case (core_0$v_to_TV_0_get[71:70]) 2'd0, 2'd1: - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = + CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4 = core_0$v_to_TV_0_get[71:70]; - default: CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = 2'd2; + default: CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4 = 2'd2; endcase end - always@(llc_mem_server_f_dword_in_line$D_OUT or llc$dma_respLd_first) + always@(core_0$v_to_TV_1_get) begin - case (llc_mem_server_f_dword_in_line$D_OUT) - 3'd0: rd_data_rdata__h119471 = llc$dma_respLd_first[68:5]; - 3'd1: rd_data_rdata__h119471 = llc$dma_respLd_first[132:69]; - 3'd2: rd_data_rdata__h119471 = llc$dma_respLd_first[196:133]; - 3'd3: rd_data_rdata__h119471 = llc$dma_respLd_first[260:197]; - 3'd4: rd_data_rdata__h119471 = llc$dma_respLd_first[324:261]; - 3'd5: rd_data_rdata__h119471 = llc$dma_respLd_first[388:325]; - 3'd6: rd_data_rdata__h119471 = llc$dma_respLd_first[452:389]; - 3'd7: rd_data_rdata__h119471 = llc$dma_respLd_first[516:453]; + case (core_0$v_to_TV_1_get[153:142]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 = + core_0$v_to_TV_1_get[153:142]; + default: CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 = + 12'd2303; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[139:136]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 = + core_0$v_to_TV_1_get[139:136]; + default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 = 4'd15; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[139:136]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 = + core_0$v_to_TV_1_get[139:136]; + default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 = 4'd15; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[71:70]) + 2'd0, 2'd1: + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8 = + core_0$v_to_TV_1_get[71:70]; + default: CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8 = 2'd2; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) + 3'd0: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h121022 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h121022 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h121022 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h121022 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h121022 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h121022 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h121022 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h121022 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h130082 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h130082 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h130082 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h130082 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h130082 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h130082 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h130082 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h130082 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h136964 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h136964 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h136964 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h136964 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h136964 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h136964 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h136964 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h136964 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h145920 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h145920 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h145920 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h145920 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h145920 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h145920 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h145920 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h145920 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h136965 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h136965 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h136965 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h136965 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h136965 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h136965 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h136965 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h136965 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h145921 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h145921 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h145921 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h145921 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h145921 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h145921 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h145921 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h145921 = llc$to_mem_toM_first[575:568]; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) + 3'd0: old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h45763 or - result__h45791 or result__h45819 or result__h45847) + result__h45331 or + result__h45359 or + result__h45387 or + result__h45415 or + result__h45443 or + result__h45471 or result__h45499 or result__h45527) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45763; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45331; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45359; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45791; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45387; + 3'h3: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45415; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45819; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45443; + 3'h5: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45471; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45847; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45499; + 3'h7: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45527; + endcase + end + always@(mmioPlatform_curReq or + result__h45572 or + result__h45600 or result__h45628 or result__h45656) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45572; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45600; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45628; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45656; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h45522 or - result__h45550 or - result__h45578 or - result__h45606 or - result__h45634 or - result__h45662 or result__h45690 or result__h45718) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45522; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45550; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45578; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45606; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45634; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45662; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45690; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45718; - endcase - end - always@(mmioPlatform_curReq or result__h45888 or result__h45916) + always@(mmioPlatform_curReq or result__h45697 or result__h45725) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h45888; + result__h45697; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h45916; + result__h45725; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; 2'b10: - w2__h45348 = + w2__h45157 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w2___1__h45458 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or + w2___1__h45267 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: w2__h45354 = w2___1__h45458; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; + 2'b10: w2__h45163 = w2___1__h45267; 2'b11: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_curReq or - result__h46275 or - result__h46302 or result__h46329 or result__h46356) + result__h45851 or + result__h45878 or + result__h45905 or + result__h45932 or + result__h45959 or + result__h45986 or result__h46013 or result__h46040) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46275; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45851; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45878; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46302; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45905; + 3'h3: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45932; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46329; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45959; + 3'h5: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45986; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46356; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h46013; + 3'h7: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h46040; + endcase + end + always@(mmioPlatform_curReq or + result__h46084 or + result__h46111 or result__h46138 or result__h46165) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46084; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46111; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46138; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46165; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h46042 or - result__h46069 or - result__h46096 or - result__h46123 or - result__h46150 or - result__h46177 or result__h46204 or result__h46231) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46042; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46069; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46096; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46123; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46150; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46177; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46204; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46231; - endcase - end - always@(mmioPlatform_curReq or result__h46396 or result__h46423) + always@(mmioPlatform_curReq or result__h46205 or result__h46232) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46396; + result__h46205; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46423; + result__h46232; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; 2'b10: - w1__h45347 = + w1__h45156 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w1___1__h45457 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or + w1___1__h45266 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: w1__h45352 = w1___1__h45457; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; + 2'b10: w1__h45161 = w1___1__h45266; 2'b11: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w15347_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or + w15156_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - { {32{w15347_BITS_31_TO_0__q15[31]}}, - w15347_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + { {32{w15156_BITS_31_TO_0__q15[31]}}, + w15156_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w25348_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or + w25157_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - { {32{w25348_BITS_31_TO_0__q16[31]}}, - w25348_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + { {32{w25157_BITS_31_TO_0__q16[31]}}, + w25157_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46519 or - w2__h45354 or - op_result__h45955 or - op_result__h46485 or - op_result__h46490 or - op_result__h46495 or - op_result__h46513 or op_result__h46500 or op_result__h46506) + op_result__h46328 or + w2__h45163 or + op_result__h45764 or + op_result__h46294 or + op_result__h46299 or + op_result__h46304 or + op_result__h46322 or op_result__h46309 or op_result__h46315) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - w2__h45354; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + w2__h45163; 4'd1: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h45955; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h45764; 4'd2: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46485; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46294; 4'd3: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46490; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46299; 4'd4: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46495; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46304; 4'd5: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46513; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46322; 4'd7: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46500; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46309; 4'd8: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46506; - default: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46519; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46315; + default: IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46328; endcase end always@(mmioPlatform_curReq or - result__h46998 or - result__h47043 or result__h47109 or result__h47175) + result__h46807 or + result__h46852 or result__h46918 or result__h46984) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h46998; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46807; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47043; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46852; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47109; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46918; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47175; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46984; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45398 or - result__h46540 or - result__h46606 or - result__h46672 or - result__h46738 or - result__h46804 or result__h46870 or result__h46936) + result__h45207 or + result__h46349 or + result__h46415 or + result__h46481 or + result__h46547 or + result__h46613 or result__h46679 or result__h46745) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h45398; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h45207; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46540; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46349; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46606; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46415; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46672; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46481; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46738; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46547; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46804; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46613; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46870; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46679; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46936; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46745; endcase end - always@(mmioPlatform_curReq or result__h47233 or result__h47278) + always@(mmioPlatform_curReq or result__h47042 or result__h47087) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47233; + result__h47042; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47278; + result__h47087; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899; 2'b01: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908; 2'b10: - x__h45343 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h45152 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7298,15 +7323,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 or + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7314,11 +7339,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520; + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 or + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7326,315 +7351,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586; + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 or + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976) + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969; + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976; + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 or + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145) + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138; + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145; + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144; endcase end - always@(x__h58747 or n__read_id__h58933 or n__read_id__h59018) + always@(x__h58556 or n__read_id__h58742 or n__read_id__h58827) begin - case (x__h58747) - 1'd0: x__h59061 = n__read_id__h58933; - 1'd1: x__h59061 = n__read_id__h59018; + case (x__h58556) + 1'd0: x__h58870 = n__read_id__h58742; + 1'd1: x__h58870 = n__read_id__h58827; endcase end - always@(x__h58747 or n__read_child__h58934 or n__read_child__h59019) + always@(x__h58556 or n__read_child__h58743 or n__read_child__h58828) begin - case (x__h58747) - 1'd0: x__h59068 = n__read_child__h58934; - 1'd1: x__h59068 = n__read_child__h59019; + case (x__h58556) + 1'd0: x__h58877 = n__read_child__h58743; + 1'd1: x__h58877 = n__read_child__h58828; endcase end - always@(x__h58747 or - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 or - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097) + always@(x__h58556 or + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092 or + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20 = - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093; + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20 = + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092; 1'd1: - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20 = - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097; + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20 = + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096; endcase end - always@(x__h58747 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077) + always@(x__h58556 or + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072 or + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072; 1'd1: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076; endcase end - always@(x__h58747 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087) + always@(x__h58556 or + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082 or + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082; 1'd1: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086; endcase end - always@(x__h58747 or n__read_addr__h58929 or n__read_addr__h59014) + always@(x__h58556 or n__read_addr__h58738 or n__read_addr__h58823) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23 = - n__read_addr__h58929; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23 = + n__read_addr__h58738; 1'd1: - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23 = - n__read_addr__h59014; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23 = + n__read_addr__h58823; endcase end - always@(x__h77370 or n__read_child__h77551 or n__read_child__h77630) + always@(x__h77179 or n__read_child__h77360 or n__read_child__h77439) begin - case (x__h77370) - 1'd0: x__h79786 = n__read_child__h77551; - 1'd1: x__h79786 = n__read_child__h77630; + case (x__h77179) + 1'd0: x__h79595 = n__read_child__h77360; + 1'd1: x__h79595 = n__read_child__h77439; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77370 or + always@(x__h77179 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 or + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198) + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 : + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 : 2'd0; 1'd1: - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 : + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197 : 2'd0; endcase end - always@(x__h77370 or - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 or - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340) + always@(x__h77179 or + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337 or + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338; + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337; 1'd1: - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340; + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339; endcase end - always@(x__h77370 or n__read_addr__h77548 or n__read_addr__h77627) + always@(x__h77179 or n__read_addr__h77357 or n__read_addr__h77436) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34 = - n__read_addr__h77548; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34 = + n__read_addr__h77357; 1'd1: - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34 = - n__read_addr__h77627; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34 = + n__read_addr__h77436; endcase end @@ -7670,6 +7695,10 @@ module mkProc(CLK, llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1; + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + 10'd0; + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3; mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0; mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7767,6 +7796,15 @@ module mkProc(CLK, if (llc_mem_server_propDstIdx_0_rl$EN) llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY llc_mem_server_propDstIdx_0_rl$D_IN; + if (llc_mem_server_rg_cacheline_cache_addr$EN) + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_addr$D_IN; + if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN) + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + if (llc_mem_server_rg_cacheline_cache_state$EN) + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_state$D_IN; if (mmioPlatform_cycle$EN) mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN; if (mmioPlatform_fromHostAddr$EN) @@ -7879,6 +7917,9 @@ module mkProc(CLK, if (llc_axi4_adapter_rg_cline$EN) llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_cline$D_IN; + if (llc_mem_server_rg_cacheline_cache_data$EN) + llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_data$D_IN; if (mmioPlatform_amoResp$EN) mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN; if (mmioPlatform_curReq$EN) @@ -7947,7 +7988,7 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; llc_axi4_adapter_rg_cline = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7958,6 +7999,11 @@ module mkProc(CLK, llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA; llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl = 1'h0; + llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_data = + 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA; + llc_mem_server_rg_cacheline_cache_state = 3'h2; mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA; mmioPlatform_cycle = 7'h2A; @@ -8002,7 +8048,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = @@ -8028,7 +8074,15 @@ module mkProc(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", + begin + v__h160987 = $stime; + #0; + end + v__h160981 = v__h160987 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h160981, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8038,14 +8092,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h151720 = $stime; + v__h160523 = $stime; #0; end - v__h151714 = v__h151720 / 32'd10; + v__h160517 = v__h160523 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h151714, + v__h160517, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8055,7 +8109,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h151763); + $display("FAIL %0d", failed_testnum__h160566); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8063,14 +8117,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4189 = $stime; + v__h4001 = $stime; #0; end - v__h4183 = v__h4189 / 32'd10; + v__h3995 = v__h4001 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4183); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h3995); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8130,16 +8184,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4362 = $stime; + v__h4174 = $stime; #0; end - v__h4356 = v__h4362 / 32'd10; + v__h4168 = v__h4174 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4356); + v__h4168); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8243,15 +8297,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4626 = $stime; + v__h4438 = $stime; #0; end - v__h4620 = v__h4626 / 32'd10; + v__h4432 = v__h4438 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4620); + v__h4432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8420,14 +8474,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6665 = $stime; + v__h6475 = $stime; #0; end - v__h6659 = v__h6665 / 32'd10; + v__h6469 = v__h6475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6659); + $display("%0d: ERROR: CreditCounter: overflow", v__h6469); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8535,15 +8589,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8580,15 +8626,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2465 = $stime; + v__h2277 = $stime; #0; end - v__h2459 = v__h2465 / 32'd10; + v__h2271 = v__h2277 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2459); + v__h2271); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8853,14 +8899,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6966 = $stime; + v__h6775 = $stime; #0; end - v__h6960 = v__h6966 / 32'd10; + v__h6769 = v__h6775 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6960); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6769); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8897,15 +8943,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7459 = $stime; + v__h7268 = $stime; #0; end - v__h7453 = v__h7459 / 32'd10; + v__h7262 = v__h7268 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7453); + v__h7262); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -8945,14 +8991,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7622 = $stime; + v__h7431 = $stime; #0; end - v__h7616 = v__h7622 / 32'd10; + v__h7425 = v__h7431 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7616); + v__h7425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9136,1088 +9182,131 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) begin - v__h93935 = $stime; + v__h99152 = $stime; #0; end - v__h93929 = v__h93935 / 32'd10; + v__h99146 = v__h99152 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awsize is not code for 1,2,4,8", - v__h93929); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display("%0d: %m.fa_writeback line at %0h", + v__h99146, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) begin - v__h93980 = $stime; + v__h99950 = $stime; #0; end - v__h93974 = v__h93980 / 32'd10; + v__h99944 = v__h99950 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: wlast is 1", - v__h93974); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h99944, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(" "); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) begin - v__h93890 = $stime; + v__h100099 = $stime; #0; end - v__h93884 = v__h93890 / 32'd10; + v__h100093 = v__h100099 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awlen is not 0 (burst length is not 1)", - v__h93884); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h100093, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - begin - v__h104972 = $stime; - #0; - end - v__h104966 = v__h104972 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arsize is not code for 1,2,4,8", - v__h104966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - begin - v__h104927 = $stime; - #0; - end - v__h104921 = v__h104927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arlen is not 0 (burst length is not 1)", - v__h104921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("\n"); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) begin - v__h123524 = $stime; + v__h132480 = $stime; #0; end - v__h123518 = v__h123524 / 32'd10; + v__h132474 = v__h132480 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h123518, + v__h132474, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h123691 = $stime; + v__h132647 = $stime; #0; end - v__h123685 = v__h123691 / 32'd10; + v__h132641 = v__h132647 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h123685); + v__h132641); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10279,135 +9368,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h125794 = $stime; + v__h134750 = $stime; #0; end - v__h125788 = v__h125794 / 32'd10; + v__h134744 = v__h134750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h125788); + v__h134744); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11605,177 +10694,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h143140 = $stime; + v__h152094 = $stime; #0; end - v__h143134 = v__h143140 / 32'd10; + v__h152088 = v__h152094 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h143134); + $display("%0d: ERROR: CreditCounter: overflow", v__h152088); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", mem_req_wr_addr_awaddr__h137049); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", mem_req_wr_addr_awaddr__h146005); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("AXI4_Wr_Data { ", "wid: "); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", 4'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", data64__h145920); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", data64__h136964); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", strb8__h136965); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", strb8__h145921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h122905 = $stime; + v__h131861 = $stime; #0; end - v__h122899 = v__h122905 / 32'd10; + v__h131855 = v__h131861 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h122899, + v__h131855, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11846,159 +10927,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", mem_req_rd_addr_araddr__h123125); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", mem_req_rd_addr_araddr__h132081); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) begin - v__h149835 = $stime; + v__h158788 = $stime; #0; end - v__h149829 = v__h149835 / 32'd10; + v__h158782 = v__h158788 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h149829, + v__h158782, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h150343 = $stime; + v__h159296 = $stime; #0; end - v__h150337 = v__h150343 / 32'd10; + v__h159290 = v__h159296 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h150337); + v__h159290); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index 17acf2a..ec9efa4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -3633,9 +3633,9 @@ module mkReorderBufferSynth(CLK, MUX_m_valid_1_23_dummy2_1$write_1__SEL_1, MUX_m_valid_1_23_dummy2_1$write_1__SEL_2, MUX_m_valid_1_23_dummy_1_0$wset_1__VAL_1, + MUX_m_valid_1_24_dummy2_1$write_1__SEL_1, MUX_m_valid_1_24_dummy2_1$write_1__SEL_2, MUX_m_valid_1_24_dummy_1_0$wset_1__VAL_1, - MUX_m_valid_1_24_lat_1$wset_1__SEL_1, MUX_m_valid_1_25_dummy2_1$write_1__SEL_1, MUX_m_valid_1_25_dummy2_1$write_1__SEL_2, MUX_m_valid_1_25_dummy_1_0$wset_1__VAL_1, @@ -9238,12 +9238,12 @@ module mkReorderBufferSynth(CLK, assign MUX_m_valid_1_23_dummy2_1$write_1__SEL_2 = WILL_FIRE_RL_m_canon_enq && m_enqP_1 == 5'd23 && SEL_ARR_m_enqEn_0_whas__20_m_enqEn_1_whas__21__ETC___d1420 ; + assign MUX_m_valid_1_24_dummy2_1$write_1__SEL_1 = + EN_specUpdate_incorrectSpeculation && + (m_wrongSpecEn$wget[16] || m_row_1_24$dependsOn_wrongSpec) ; assign MUX_m_valid_1_24_dummy2_1$write_1__SEL_2 = WILL_FIRE_RL_m_canon_enq && m_enqP_1 == 5'd24 && SEL_ARR_m_enqEn_0_whas__20_m_enqEn_1_whas__21__ETC___d1420 ; - assign MUX_m_valid_1_24_lat_1$wset_1__SEL_1 = - EN_specUpdate_incorrectSpeculation && - (m_wrongSpecEn$wget[16] || m_row_1_24$dependsOn_wrongSpec) ; assign MUX_m_valid_1_25_dummy2_1$write_1__SEL_1 = EN_specUpdate_incorrectSpeculation && (m_wrongSpecEn$wget[16] || m_row_1_25$dependsOn_wrongSpec) ; @@ -10302,7 +10302,7 @@ module mkReorderBufferSynth(CLK, // register m_valid_1_24_rl assign m_valid_1_24_rl$D_IN = m_valid_1_24_lat_1$whas ? - !MUX_m_valid_1_24_lat_1$wset_1__SEL_1 : + !MUX_m_valid_1_24_dummy2_1$write_1__SEL_1 : !MUX_m_valid_1_24_dummy_1_0$wset_1__VAL_1 && m_valid_1_24_rl ; assign m_valid_1_24_rl$EN = 1'd1 ; diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 3f30a9b..7717c76 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved. package P3_Core; @@ -24,12 +24,14 @@ import GetPut :: *; import ClientServer :: *; import Connectable :: *; import Bus :: *; +import Clocks :: *; // ---------------- // BSV additional libs import GetPut_Aux :: *; import Semi_FIFOF :: *; +import Cur_Cycle :: *; // ================================================================ // Project imports @@ -75,7 +77,8 @@ interface P3_Core_IFC; // External interrupt sources (* always_ready, always_enabled, prefix="" *) - method Action interrupt_reqs ((* port="cpu_external_interrupt_req" *) Bit #(N_External_Interrupt_Sources) reqs); + method Action interrupt_reqs ((* port="cpu_external_interrupt_req" *) + Bit #(N_External_Interrupt_Sources) reqs); // ---------------- // External interrupt [14] to go into Debug Mode @@ -83,15 +86,6 @@ interface P3_Core_IFC; (* always_ready, always_enabled *) method Action debug_external_interrupt_req (Bool set_not_clear); -`ifdef INCLUDE_TANDEM_VERIF - // ---------------------------------------------------------------- - // Optional Tandem Verifier interface. The data signal is - // packed output tuples (n,vb),/ where 'vb' is a vector of - // bytes with relevant bytes in locations [0]..[n-1] - - interface AXI4_Stream_Master_IFC #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser) tv_verifier_info_tx; -`endif - `ifdef INCLUDE_GDB_CONTROL // ---------------- // JTAG interface @@ -100,6 +94,17 @@ interface P3_Core_IFC; interface JTAG_IFC jtag; `endif `endif + +`ifdef INCLUDE_TANDEM_VERIF + // ---------------------------------------------------------------- + // Optional Tandem Verifier interface. The data signal is + // packed output tuples (n,vb),/ where 'vb' is a vector of + // bytes with relevant bytes in locations [0]..[n-1] + + interface AXI4_Stream_Master_IFC #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser) + tv_verifier_info_tx; +`endif + endinterface // ================================================================ @@ -107,8 +112,39 @@ endinterface (* synthesize *) module mkP3_Core (P3_Core_IFC); - // CoreW: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) - CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW; + // ================================================================ + // The RISC-V Debug Module is at the following point in the module hierarchy: + // p3_core.corew.debug_module + // (instances of mkP3_Core, mkCoreW, mkDebug_Module) + + // The Debug Module is reset only once, on power-up, hence we pass + // its reset down from here. + + // (power-on reset) and the Debug Module's 'hart_reset' control. + + let power_on_reset <- exposeCurrentReset; + let dm_power_on_reset = power_on_reset; + + // The rest of the system (corew minus the Debug Module) are reset: + // - on power-on, and + // - when the Debug Module requests an NDM reset (for non-DebugModule). + +`ifdef INCLUDE_GDB_CONTROL + let clk <- exposeCurrentClock; + Bool initial_reset_val = False; + Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM + let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); + + let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); +`else + let ndm_reset = power_on_reset; +`endif + + // ================================================================ + // CoreW + // CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) + CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW (dm_power_on_reset, + reset_by ndm_reset); // ================================================================ // Tie-offs (not used in SSITH GFE) @@ -118,31 +154,43 @@ module mkP3_Core (P3_Core_IFC); corew.set_verbosity (?, ?); endrule - // ================================================================ - // Reset on startup, and also on NDM reset from Debug Module - // (NDM reset from Debug Module = reset all except Debug Module) - - Reg #(Bool) rg_once <- mkReg (False); - - rule rl_once (! rg_once); - corew.cpu_reset_server.request.put (?); - rg_once <= True; + // Tie-offs + rule rl_always (True); + // Non-maskable interrupt request. + corew.nmi_req (False); endrule - rule rl_reset_response; - let tmp <- corew.cpu_reset_server.response.get; - endrule - - rule rl_ndmreset (rg_once); - let tmp <- corew.dm_ndm_reset_req_get.get; - rg_once <= False; - endrule - - // ================================================================ `ifdef INCLUDE_GDB_CONTROL + // ================================================================ + // NDM reset (reset for non-DebugModule) + Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); + + // Get an NDM-reset request from the Debug Module, assert ndm-reset, + // and then wait for a suitable delay. + rule rl_ndm_reset (rg_ndm_reset_delay == 0); + let x <- corew.ndm_reset_client.request.get; + ndm_reset_controller.assertReset; + rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 100); // NOTE: heuristic + + $display ("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + cur_cycle, ndm_reset_duration); + endrule + + // Wait for suitable delay, then send ack response to Debug Module for NDM-reset request + rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); + if (rg_ndm_reset_delay == 1) begin + Bool is_running = True; + corew.ndm_reset_client.response.put (is_running); + $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + cur_cycle); + end + rg_ndm_reset_delay <= rg_ndm_reset_delay - 1; + endrule + + // ================================================================ // Instantiate JTAG TAP controller, - // connect to corew.dm_dmi; + // connect to corew.dmi; // and export its JTAG interface Wire#(Bit#(7)) w_dmi_req_addr <- mkDWire(0); @@ -184,9 +232,9 @@ module mkP3_Core (P3_Core_IFC); match {.addr, .data, .op} = bus_dmi_req.out.first; bus_dmi_req.out.deq; case (op) - 1: corew.dm_dmi.read_addr(addr); + 1: corew.dmi.read_addr(addr); 2: begin - corew.dm_dmi.write(addr, data); + corew.dmi.write(addr, data); bus_dmi_rsp.in.enq(tuple2(?, 0)); end default: bus_dmi_rsp.in.enq(tuple2(?, 2)); @@ -194,15 +242,19 @@ module mkP3_Core (P3_Core_IFC); endrule rule rl_dmi_rsp_cpu; - let data <- corew.dm_dmi.read_data; + let data <- corew.dmi.read_data; bus_dmi_rsp.in.enq(tuple2(data, 0)); endrule + // ================================================================ `endif `ifdef INCLUDE_TANDEM_VERIF + // ================================================================ let tv_xactor <- mkTV_Xactor; + mkConnection (corew.tv_verifier_info_get, tv_xactor.tv_in); + // ================================================================ `endif // ================================================================ @@ -225,12 +277,14 @@ module mkP3_Core (P3_Core_IFC); end endmethod - // ---------------- - // External interrupt [14] to go into Debug Mode +`ifdef INCLUDE_GDB_CONTROL + // ---------------------------------------------------------------- + // Optional Debug Module interfaces - method Action debug_external_interrupt_req (Bool set_not_clear); - corew.debug_external_interrupt_req (set_not_clear); - endmethod +`ifdef JTAG_TAP + interface JTAG_IFC jtag = jtagtap.jtag; +`endif +`endif `ifdef INCLUDE_TANDEM_VERIF // ---------------------------------------------------------------- @@ -241,15 +295,6 @@ module mkP3_Core (P3_Core_IFC); interface tv_verifier_info_tx = tv_xactor.axi_out; `endif -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional Debug Module interfaces - -`ifdef JTAG_TAP - interface JTAG_IFC jtag = jtagtap.jtag; -`endif - -`endif endmodule // ================================================================ diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 5224c90..e96531a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -86,7 +86,6 @@ // RDY_renameDebug_renameErr_get O 1 const // RDY_setMEIP O 1 const // RDY_setSEIP O 1 const -// RDY_setDEIP O 1 const // RDY_hart0_run_halt_server_request_put O 1 reg // hart0_run_halt_server_response_get O 1 reg // RDY_hart0_run_halt_server_response_get O 1 reg @@ -119,7 +118,6 @@ // recvDoStats_x I 1 reg // setMEIP_v I 1 // setSEIP_v I 1 -// setDEIP_v I 1 // hart0_run_halt_server_request_put I 1 reg // hart0_gpr_mem_server_request_put I 70 reg // hart0_fpr_mem_server_request_put I 70 reg @@ -144,7 +142,6 @@ // EN_deadlock_checkStarted_get I 1 unused // EN_setMEIP I 1 // EN_setSEIP I 1 -// EN_setDEIP I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -362,10 +359,6 @@ module mkCore(CLK, EN_setSEIP, RDY_setSEIP, - setDEIP_v, - EN_setDEIP, - RDY_setDEIP, - hart0_run_halt_server_request_put, EN_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_request_put, @@ -633,11 +626,6 @@ module mkCore(CLK, input EN_setSEIP; output RDY_setSEIP; - // action method setDEIP - input setDEIP_v; - input EN_setDEIP; - output RDY_setDEIP; - // action method hart0_run_halt_server_request_put input hart0_run_halt_server_request_put; input EN_hart0_run_halt_server_request_put; @@ -757,7 +745,6 @@ module mkCore(CLK, RDY_recvDoStats, RDY_renameDebug_renameErr_get, RDY_sendDoStats, - RDY_setDEIP, RDY_setMEIP, RDY_setSEIP, RDY_tlbToMem_memReq_deq, @@ -1319,11 +1306,6 @@ module mkCore(CLK, reg csrInstOrInterruptInflight_rl; wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN; - // register csrf_debug_int_pend - reg csrf_debug_int_pend; - reg csrf_debug_int_pend$D_IN; - wire csrf_debug_int_pend$EN; - // register csrf_external_int_en_vec_0 reg csrf_external_int_en_vec_0; wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN; @@ -1502,7 +1484,7 @@ module mkCore(CLK, // register csrf_prv_reg reg [1 : 0] csrf_prv_reg; - wire [1 : 0] csrf_prv_reg$D_IN; + reg [1 : 0] csrf_prv_reg$D_IN; wire csrf_prv_reg$EN; // register csrf_rg_dcsr @@ -3965,7 +3947,6 @@ module mkCore(CLK, CAN_FIRE_recvDoStats, CAN_FIRE_renameDebug_renameErr_get, CAN_FIRE_sendDoStats, - CAN_FIRE_setDEIP, CAN_FIRE_setMEIP, CAN_FIRE_setSEIP, CAN_FIRE_tlbToMem_memReq_deq, @@ -4201,7 +4182,6 @@ module mkCore(CLK, WILL_FIRE_recvDoStats, WILL_FIRE_renameDebug_renameErr_get, WILL_FIRE_sendDoStats, - WILL_FIRE_setDEIP, WILL_FIRE_setMEIP, WILL_FIRE_setSEIP, WILL_FIRE_tlbToMem_memReq_deq, @@ -4279,6 +4259,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2; wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; + wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4340,6 +4322,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2, + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2, MUX_coreFix_memExe_lsq$getHit_1__SEL_1, @@ -4355,12 +4338,12 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, - MUX_csrf_debug_int_pend$write_1__SEL_1, - MUX_csrf_debug_int_pend$write_1__SEL_2, MUX_csrf_external_int_en_vec_0$write_1__SEL_1, MUX_csrf_external_int_en_vec_3$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_2, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fflags_reg$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_3, @@ -4398,8 +4381,9 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_3$write_1__SEL_1, MUX_csrf_prev_ie_vec_3$write_1__VAL_1, MUX_csrf_prv_reg$write_1__SEL_1, + MUX_csrf_prv_reg$write_1__SEL_2, + MUX_csrf_prv_reg$write_1__SEL_3, MUX_csrf_rg_dcsr$write_1__SEL_1, - MUX_csrf_rg_dcsr$write_1__SEL_3, MUX_csrf_rg_dpc$write_1__SEL_1, MUX_csrf_rg_dpc$write_1__SEL_3, MUX_csrf_rg_dscratch0$write_1__SEL_1, @@ -4443,7 +4427,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, MUX_started$write_1__SEL_1, - MUX_update_vm_info$write_1__SEL_2, MUX_v_f_to_TV_0$enq_1__SEL_1; // remaining internal signals @@ -4470,34 +4453,34 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287946, - curData__h190796, - data_out__h718266, - rVal1__h606894, - rVal1__h631060, - trap_val__h699161, - x__h195006; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, + addr__h287914, + curData__h190763, + data_out__h718171, + rVal1__h606861, + rVal1__h631001, + trap_val__h699101, + x__h194973; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217, - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218, - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219, - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220, - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205, - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206, - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207, - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208, - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209, - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210, - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221, - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222, - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223, - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224, - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225, - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226, - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215, - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216, + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217, + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218, + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219, + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220, + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205, + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206, + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207, + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208, + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209, + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210, + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221, + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222, + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223, + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224, + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225, + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226, + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215, + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641, @@ -4509,45 +4492,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86, - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87, - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88, - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89, - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119, - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120, - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49, - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50, - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117, - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118, - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47, - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48, - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121, - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122, - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51, - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52, - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123, - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124, - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53, - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54, - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82, - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83, - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84, - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85, - _theResult___fst_sfd__h343945, - _theResult___fst_sfd__h352668, - _theResult___fst_sfd__h361250, - _theResult___fst_sfd__h370434, - _theResult___fst_sfd__h379070, - _theResult___fst_sfd__h389644, - _theResult___fst_sfd__h398365, - _theResult___fst_sfd__h406947, - _theResult___fst_sfd__h416131, - _theResult___fst_sfd__h424767, - _theResult___fst_sfd__h435339, - _theResult___fst_sfd__h444060, - _theResult___fst_sfd__h452642, - _theResult___fst_sfd__h461826, - _theResult___fst_sfd__h470462; + reg [22 : 0] CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86, + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87, + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88, + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89, + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119, + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120, + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49, + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50, + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117, + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118, + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47, + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48, + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121, + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122, + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51, + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52, + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123, + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124, + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54, + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55, + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84, + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85, + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82, + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83, + _theResult___fst_sfd__h343912, + _theResult___fst_sfd__h352635, + _theResult___fst_sfd__h361217, + _theResult___fst_sfd__h370401, + _theResult___fst_sfd__h379037, + _theResult___fst_sfd__h389611, + _theResult___fst_sfd__h398332, + _theResult___fst_sfd__h406914, + _theResult___fst_sfd__h416098, + _theResult___fst_sfd__h424734, + _theResult___fst_sfd__h435306, + _theResult___fst_sfd__h444027, + _theResult___fst_sfd__h452609, + _theResult___fst_sfd__h461793, + _theResult___fst_sfd__h470429; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278, @@ -4556,8 +4539,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282, @@ -4571,28 +4554,28 @@ module mkCore(CLK, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296, CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1, - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912; + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211, - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212, - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213, - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214, - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183, - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184, - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185, - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186, - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187, - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188, - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160, - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161, - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189, - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190, - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191, - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192, - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143, - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211, + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212, + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213, + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214, + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183, + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184, + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185, + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186, + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187, + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188, + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160, + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161, + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191, + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192, + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189, + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190, + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143, + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570, @@ -4602,54 +4585,54 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800; - reg [7 : 0] CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75, - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76, - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80, - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81, - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104, - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105, - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34, - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35, - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102, - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103, - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32, - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33, - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110, - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111, - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40, - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41, - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115, - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116, - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45, - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46, - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69, - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70, - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67, - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68, + reg [7 : 0] CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75, + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76, + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80, + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81, + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104, + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105, + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34, + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35, + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102, + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103, + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32, + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33, + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110, + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111, + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40, + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41, + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115, + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116, + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45, + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46, + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69, + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70, + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67, + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343944, - _theResult___fst_exp__h352667, - _theResult___fst_exp__h361249, - _theResult___fst_exp__h370433, - _theResult___fst_exp__h379069, - _theResult___fst_exp__h389643, - _theResult___fst_exp__h398364, - _theResult___fst_exp__h406946, - _theResult___fst_exp__h416130, - _theResult___fst_exp__h424766, - _theResult___fst_exp__h435338, - _theResult___fst_exp__h444059, - _theResult___fst_exp__h452641, - _theResult___fst_exp__h461825, - _theResult___fst_exp__h470461; + _theResult___fst_exp__h343911, + _theResult___fst_exp__h352634, + _theResult___fst_exp__h361216, + _theResult___fst_exp__h370400, + _theResult___fst_exp__h379036, + _theResult___fst_exp__h389610, + _theResult___fst_exp__h398331, + _theResult___fst_exp__h406913, + _theResult___fst_exp__h416097, + _theResult___fst_exp__h424733, + _theResult___fst_exp__h435305, + _theResult___fst_exp__h444026, + _theResult___fst_exp__h452608, + _theResult___fst_exp__h461792, + _theResult___fst_exp__h470428; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271, - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180; - reg [3 : 0] CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234, + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176; + reg [3 : 0] CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273, @@ -4660,11 +4643,11 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2, CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052, - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181, - i__h698137, - i__h698297; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048, + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177, + i__h698077, + i__h698237; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277, @@ -4678,8 +4661,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714, - x__h283725, - x__h289495; + x__h283692, + x__h289463; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263, @@ -4711,51 +4694,51 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239, + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240, + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4794,31 +4777,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378, - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374, + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517, @@ -4827,29 +4810,29 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573; - wire [321 : 0] basicExec___d11914, basicExec___d12560; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569; + wire [321 : 0] basicExec___d11911, basicExec___d12557; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994; wire [68 : 0] execFpuSimple___d11053; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344, @@ -4871,156 +4854,156 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - _theResult___fst__h601247, - _theResult___snd__h601248, - a___1__h600966, - a___1__h601252, - a__h600825, + _theResult___fst__h601214, + _theResult___snd__h601215, + a___1__h600933, + a___1__h601219, + a__h600792, amoExec___d880, - b___1__h600967, - b___1__h601297, - b__h600826, - base__h700740, - base__h700943, - data___1__h472885, - data___1__h473693, - data__h473159, - fcsr_csr__read__h607196, - fflags_csr__read__h607171, - frm_csr__read__h607182, - mcause_csr__read__h608843, - mcounteren_csr__read__h608588, - medeleg_csr__read__h608188, - mideleg_csr__read__h608283, - mie_csr__read__h608414, - mip_csr__read__h609083, - mstatus_csr__read__h608040, - mtvec_csr__read__h608496, - n___1__h196409, - n__h192334, - n__read__h609187, - n__read__h609378, - n__read__h6636, - n__read__h710013, - next_pc__h709359, - q___1__h473758, - rVal1__h479638, - rVal2__h479639, - r___1__h473784, - res_data__h335746, - res_data__h335751, - res_data__h381448, - res_data__h381453, - res_data__h427143, - res_data__h427148, - resp_addr__h289850, + b___1__h600934, + b___1__h601264, + b__h600793, + base__h700680, + base__h700883, + data___1__h472852, + data___1__h473660, + data__h473126, + fcsr_csr__read__h607163, + fflags_csr__read__h607138, + frm_csr__read__h607149, + mcause_csr__read__h608803, + mcounteren_csr__read__h608548, + medeleg_csr__read__h608155, + mideleg_csr__read__h608250, + mie_csr__read__h608374, + mip_csr__read__h609036, + mstatus_csr__read__h608007, + mtvec_csr__read__h608456, + n___1__h196376, + n__h192301, + n__read__h609140, + n__read__h609331, + n__read__h6604, + n__read__h709918, + next_pc__h709264, + q___1__h473725, + rVal1__h479605, + rVal2__h479606, + r___1__h473751, + res_data__h335713, + res_data__h335718, + res_data__h381415, + res_data__h381420, + res_data__h427110, + res_data__h427115, + resp_addr__h289818, robdeqPort_0_deq_data_BITS_95_TO_32__q270, - satp_csr__read__h607897, - scause_csr__read__h607695, - scounteren_csr__read__h607557, - shiftData__h181173, - sie_csr__read__h607461, - sip_csr__read__h607834, - sstatus_csr__read__h607392, - stvec_csr__read__h607504, - upd__h4024, - upd__h5341, - upd__h6750, - upd__h710124, - v__h605779, - v__h630099, - vaddr__h181168, - x__h153484, - x__h157031, - x__h159845, - x__h161693, - x__h181082, - x__h181083, - x__h18203, - x__h20741, - x__h285170, - x__h287024, - x__h46110, - x__h479547, - x__h479548, - x__h479549, - x__h48646, - x__h614583, - x__h614584, - x__h636445, - x__h636446, - x__h692296, - x__h712792, - x_addr__h311953, - x_quotient__h473073, - x_reg_ifc__read__h607301, - x_remainder__h473074, - y__h712818, - y__h714209, - y_avValue__h180170, - y_avValue__h180776, - y_avValue__h476683, - y_avValue__h477291, - y_avValue__h477893, - y_avValue__h606684, - y_avValue__h612440, - y_avValue__h630852, - y_avValue__h634312, - y_avValue__h699008, - y_avValue__h700777, - y_avValue_snd_snd_snd_snd_snd__h712833, - y_avValue_snd_snd_snd_snd_snd__h714258, - y_avValue_snd_snd_snd_snd_snd__h714287; + satp_csr__read__h607864, + scause_csr__read__h607662, + scounteren_csr__read__h607524, + shiftData__h181140, + sie_csr__read__h607428, + sip_csr__read__h607801, + sstatus_csr__read__h607359, + stvec_csr__read__h607471, + upd__h3992, + upd__h5309, + upd__h6718, + upd__h710029, + v__h605746, + v__h630040, + vaddr__h181135, + x__h153450, + x__h156997, + x__h159811, + x__h161659, + x__h181049, + x__h181050, + x__h18170, + x__h20708, + x__h285138, + x__h286992, + x__h46077, + x__h479514, + x__h479515, + x__h479516, + x__h48613, + x__h614524, + x__h614525, + x__h636385, + x__h636386, + x__h692236, + x__h712697, + x_addr__h311921, + x_quotient__h473040, + x_reg_ifc__read__h607268, + x_remainder__h473041, + y__h712723, + y__h714114, + y_avValue__h180137, + y_avValue__h180743, + y_avValue__h476650, + y_avValue__h477258, + y_avValue__h477860, + y_avValue__h606651, + y_avValue__h612381, + y_avValue__h630793, + y_avValue__h634252, + y_avValue__h698948, + y_avValue__h700717, + y_avValue_snd_snd_snd_snd_snd__h712738, + y_avValue_snd_snd_snd_snd_snd__h714163, + y_avValue_snd_snd_snd_snd_snd__h714192; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879, - r1__read__h610355, - r1__read__h610759, - r1__read__h611289, - r1__read__h611294, - r1__read__h611313, - r1__read__h611566, - r1__read__h611732, - r1__read__h611850, - r1__read__h611855, - r1__read__h611874; - wire [61 : 0] r1__read__h610357, - r1__read__h610761, - r1__read__h611296, - r1__read__h611315, - r1__read__h611568, - r1__read__h611708, - r1__read__h611734, - r1__read__h611857, - r1__read__h611876; - wire [60 : 0] r1__read__h611570, - r1__read__h611710, - r1__read__h611736, - r1__read__h611878; - wire [59 : 0] r1__read__h610359, - r1__read__h610763, - r1__read__h611307, - r1__read__h611317, - r1__read__h611572, - r1__read__h611738, - r1__read__h611868, - r1__read__h611880; - wire [58 : 0] r1__read__h610361, - r1__read__h610765, - r1__read__h611319, - r1__read__h611574, - r1__read__h611740, - r1__read__h611882; + r1__read__h610308, + r1__read__h610712, + r1__read__h611242, + r1__read__h611247, + r1__read__h611266, + r1__read__h611519, + r1__read__h611685, + r1__read__h611796, + r1__read__h611801, + r1__read__h611820; + wire [61 : 0] r1__read__h610310, + r1__read__h610714, + r1__read__h611249, + r1__read__h611268, + r1__read__h611521, + r1__read__h611661, + r1__read__h611687, + r1__read__h611803, + r1__read__h611822; + wire [60 : 0] r1__read__h611523, + r1__read__h611663, + r1__read__h611689, + r1__read__h611824; + wire [59 : 0] r1__read__h610312, + r1__read__h610716, + r1__read__h611260, + r1__read__h611270, + r1__read__h611525, + r1__read__h611691, + r1__read__h611814, + r1__read__h611826; + wire [58 : 0] r1__read__h610314, + r1__read__h610718, + r1__read__h611272, + r1__read__h611527, + r1__read__h611693, + r1__read__h611828; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h610363, - r1__read__h610767, - r1__read__h611321, - r1__read__h611576, - r1__read__h611712, - r1__read__h611742, - r1__read__h611884, - y__h252683; + r1__read__h610316, + r1__read__h610720, + r1__read__h611274, + r1__read__h611529, + r1__read__h611665, + r1__read__h611695, + r1__read__h611830, + y__h252650; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5048,187 +5031,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338, - _theResult____h343962, - _theResult____h361601, - _theResult____h389661, - _theResult____h407298, - _theResult____h435356, - _theResult____h452993, - _theResult____h500746, - _theResult____h539599, - _theResult____h578903, - _theResult___snd__h352084, - _theResult___snd__h352095, - _theResult___snd__h352097, - _theResult___snd__h352107, - _theResult___snd__h352113, - _theResult___snd__h352136, - _theResult___snd__h360680, - _theResult___snd__h360682, - _theResult___snd__h360689, - _theResult___snd__h360695, - _theResult___snd__h360718, - _theResult___snd__h369850, - _theResult___snd__h369861, - _theResult___snd__h369863, - _theResult___snd__h369873, - _theResult___snd__h369879, - _theResult___snd__h369902, - _theResult___snd__h378470, - _theResult___snd__h378484, - _theResult___snd__h378490, - _theResult___snd__h378508, - _theResult___snd__h397781, - _theResult___snd__h397792, - _theResult___snd__h397794, - _theResult___snd__h397804, - _theResult___snd__h397810, - _theResult___snd__h397833, - _theResult___snd__h406377, - _theResult___snd__h406379, - _theResult___snd__h406386, - _theResult___snd__h406392, - _theResult___snd__h406415, - _theResult___snd__h415547, - _theResult___snd__h415558, - _theResult___snd__h415560, - _theResult___snd__h415570, - _theResult___snd__h415576, - _theResult___snd__h415599, - _theResult___snd__h424167, - _theResult___snd__h424181, - _theResult___snd__h424187, - _theResult___snd__h424205, - _theResult___snd__h443476, - _theResult___snd__h443487, - _theResult___snd__h443489, - _theResult___snd__h443499, - _theResult___snd__h443505, - _theResult___snd__h443528, - _theResult___snd__h452072, - _theResult___snd__h452074, - _theResult___snd__h452081, - _theResult___snd__h452087, - _theResult___snd__h452110, - _theResult___snd__h461242, - _theResult___snd__h461253, - _theResult___snd__h461255, - _theResult___snd__h461265, - _theResult___snd__h461271, - _theResult___snd__h461294, - _theResult___snd__h469862, - _theResult___snd__h469876, - _theResult___snd__h469882, - _theResult___snd__h469900, - _theResult___snd__h499356, - _theResult___snd__h499358, - _theResult___snd__h499365, - _theResult___snd__h499371, - _theResult___snd__h499394, - _theResult___snd__h508993, - _theResult___snd__h509004, - _theResult___snd__h509006, - _theResult___snd__h509016, - _theResult___snd__h509022, - _theResult___snd__h509045, - _theResult___snd__h517761, - _theResult___snd__h517775, - _theResult___snd__h517781, - _theResult___snd__h517799, - _theResult___snd__h538209, - _theResult___snd__h538211, - _theResult___snd__h538218, - _theResult___snd__h538224, - _theResult___snd__h538247, - _theResult___snd__h547846, - _theResult___snd__h547857, - _theResult___snd__h547859, - _theResult___snd__h547869, - _theResult___snd__h547875, - _theResult___snd__h547898, - _theResult___snd__h556614, - _theResult___snd__h556628, - _theResult___snd__h556634, - _theResult___snd__h556652, - _theResult___snd__h577513, - _theResult___snd__h577515, - _theResult___snd__h577522, - _theResult___snd__h577528, - _theResult___snd__h577551, - _theResult___snd__h587150, - _theResult___snd__h587161, - _theResult___snd__h587163, - _theResult___snd__h587173, - _theResult___snd__h587179, - _theResult___snd__h587202, - _theResult___snd__h595918, - _theResult___snd__h595932, - _theResult___snd__h595938, - _theResult___snd__h595956, - r1__read__h611578, - r1__read__h611714, - r1__read__h611744, - r1__read__h611886, - result__h362214, - result__h407911, - result__h453606, - result__h501359, - result__h540212, - result__h579516, - sfd__h336357, - sfd__h382059, - sfd__h427754, - sfd__h480379, - sfd__h519373, - sfd__h558677, - sfdin__h352067, - sfdin__h369833, - sfdin__h397764, - sfdin__h415530, - sfdin__h443459, - sfdin__h461225, - sfdin__h508976, - sfdin__h547829, - sfdin__h587133, - x__h362311, - x__h408008, - x__h453703, - x__h501454, - x__h540307, - x__h579611; - wire [55 : 0] r1__read__h610365, - r1__read__h610769, - r1__read__h611323, - r1__read__h611580, - r1__read__h611746, - r1__read__h611888; - wire [54 : 0] r1__read__h610367, - r1__read__h610771, - r1__read__h611325, - r1__read__h611582, - r1__read__h611748, - r1__read__h611890; - wire [53 : 0] r1__read__h611691, - r1__read__h611716, - r1__read__h611750, - r1__read__h611892, - sfd__h499423, - sfd__h509074, - sfd__h517834, - sfd__h538276, - sfd__h547927, - sfd__h556687, - sfd__h577580, - sfd__h587231, - sfd__h595991, - value__h344584, - value__h390281, - value__h435976; - wire [52 : 0] r1__read__h611584, - r1__read__h611693, - r1__read__h611718, - r1__read__h611752, - r1__read__h611894; + _theResult____h343929, + _theResult____h361568, + _theResult____h389628, + _theResult____h407265, + _theResult____h435323, + _theResult____h452960, + _theResult____h500713, + _theResult____h539566, + _theResult____h578870, + _theResult___snd__h352051, + _theResult___snd__h352062, + _theResult___snd__h352064, + _theResult___snd__h352074, + _theResult___snd__h352080, + _theResult___snd__h352103, + _theResult___snd__h360647, + _theResult___snd__h360649, + _theResult___snd__h360656, + _theResult___snd__h360662, + _theResult___snd__h360685, + _theResult___snd__h369817, + _theResult___snd__h369828, + _theResult___snd__h369830, + _theResult___snd__h369840, + _theResult___snd__h369846, + _theResult___snd__h369869, + _theResult___snd__h378437, + _theResult___snd__h378451, + _theResult___snd__h378457, + _theResult___snd__h378475, + _theResult___snd__h397748, + _theResult___snd__h397759, + _theResult___snd__h397761, + _theResult___snd__h397771, + _theResult___snd__h397777, + _theResult___snd__h397800, + _theResult___snd__h406344, + _theResult___snd__h406346, + _theResult___snd__h406353, + _theResult___snd__h406359, + _theResult___snd__h406382, + _theResult___snd__h415514, + _theResult___snd__h415525, + _theResult___snd__h415527, + _theResult___snd__h415537, + _theResult___snd__h415543, + _theResult___snd__h415566, + _theResult___snd__h424134, + _theResult___snd__h424148, + _theResult___snd__h424154, + _theResult___snd__h424172, + _theResult___snd__h443443, + _theResult___snd__h443454, + _theResult___snd__h443456, + _theResult___snd__h443466, + _theResult___snd__h443472, + _theResult___snd__h443495, + _theResult___snd__h452039, + _theResult___snd__h452041, + _theResult___snd__h452048, + _theResult___snd__h452054, + _theResult___snd__h452077, + _theResult___snd__h461209, + _theResult___snd__h461220, + _theResult___snd__h461222, + _theResult___snd__h461232, + _theResult___snd__h461238, + _theResult___snd__h461261, + _theResult___snd__h469829, + _theResult___snd__h469843, + _theResult___snd__h469849, + _theResult___snd__h469867, + _theResult___snd__h499323, + _theResult___snd__h499325, + _theResult___snd__h499332, + _theResult___snd__h499338, + _theResult___snd__h499361, + _theResult___snd__h508960, + _theResult___snd__h508971, + _theResult___snd__h508973, + _theResult___snd__h508983, + _theResult___snd__h508989, + _theResult___snd__h509012, + _theResult___snd__h517728, + _theResult___snd__h517742, + _theResult___snd__h517748, + _theResult___snd__h517766, + _theResult___snd__h538176, + _theResult___snd__h538178, + _theResult___snd__h538185, + _theResult___snd__h538191, + _theResult___snd__h538214, + _theResult___snd__h547813, + _theResult___snd__h547824, + _theResult___snd__h547826, + _theResult___snd__h547836, + _theResult___snd__h547842, + _theResult___snd__h547865, + _theResult___snd__h556581, + _theResult___snd__h556595, + _theResult___snd__h556601, + _theResult___snd__h556619, + _theResult___snd__h577480, + _theResult___snd__h577482, + _theResult___snd__h577489, + _theResult___snd__h577495, + _theResult___snd__h577518, + _theResult___snd__h587117, + _theResult___snd__h587128, + _theResult___snd__h587130, + _theResult___snd__h587140, + _theResult___snd__h587146, + _theResult___snd__h587169, + _theResult___snd__h595885, + _theResult___snd__h595899, + _theResult___snd__h595905, + _theResult___snd__h595923, + r1__read__h611531, + r1__read__h611667, + r1__read__h611697, + r1__read__h611832, + result__h362181, + result__h407878, + result__h453573, + result__h501326, + result__h540179, + result__h579483, + sfd__h336324, + sfd__h382026, + sfd__h427721, + sfd__h480346, + sfd__h519340, + sfd__h558644, + sfdin__h352034, + sfdin__h369800, + sfdin__h397731, + sfdin__h415497, + sfdin__h443426, + sfdin__h461192, + sfdin__h508943, + sfdin__h547796, + sfdin__h587100, + x__h362278, + x__h407975, + x__h453670, + x__h501421, + x__h540274, + x__h579578; + wire [55 : 0] r1__read__h610318, + r1__read__h610722, + r1__read__h611276, + r1__read__h611533, + r1__read__h611699, + r1__read__h611834; + wire [54 : 0] r1__read__h610320, + r1__read__h610724, + r1__read__h611278, + r1__read__h611535, + r1__read__h611701, + r1__read__h611836; + wire [53 : 0] r1__read__h611644, + r1__read__h611669, + r1__read__h611703, + r1__read__h611838, + sfd__h499390, + sfd__h509041, + sfd__h517801, + sfd__h538243, + sfd__h547894, + sfd__h556654, + sfd__h577547, + sfd__h587198, + sfd__h595958, + value__h344551, + value__h390248, + value__h435943; + wire [52 : 0] r1__read__h611537, + r1__read__h611646, + r1__read__h611671, + r1__read__h611705, + r1__read__h611840; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137, @@ -5250,110 +5233,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878, - _theResult___fst_sfd__h484333, - _theResult___fst_sfd__h500161, - _theResult___fst_sfd__h500164, - _theResult___fst_sfd__h509812, - _theResult___fst_sfd__h509815, - _theResult___fst_sfd__h518596, - _theResult___fst_sfd__h518599, - _theResult___fst_sfd__h518608, - _theResult___fst_sfd__h518614, - _theResult___fst_sfd__h523186, - _theResult___fst_sfd__h539014, - _theResult___fst_sfd__h539017, - _theResult___fst_sfd__h548665, - _theResult___fst_sfd__h548668, - _theResult___fst_sfd__h557449, - _theResult___fst_sfd__h557452, - _theResult___fst_sfd__h557461, - _theResult___fst_sfd__h557467, - _theResult___fst_sfd__h562490, - _theResult___fst_sfd__h578318, - _theResult___fst_sfd__h578321, - _theResult___fst_sfd__h587969, - _theResult___fst_sfd__h587972, - _theResult___fst_sfd__h596753, - _theResult___fst_sfd__h596756, - _theResult___fst_sfd__h596765, - _theResult___fst_sfd__h596771, - _theResult___sfd__h500061, - _theResult___sfd__h509712, - _theResult___sfd__h518496, - _theResult___sfd__h538914, - _theResult___sfd__h548565, - _theResult___sfd__h557349, - _theResult___sfd__h578218, - _theResult___sfd__h587869, - _theResult___sfd__h596653, - _theResult___snd_fst_sfd__h480333, - _theResult___snd_fst_sfd__h500167, - _theResult___snd_fst_sfd__h518602, - _theResult___snd_fst_sfd__h519327, - _theResult___snd_fst_sfd__h539020, - _theResult___snd_fst_sfd__h557455, - _theResult___snd_fst_sfd__h558631, - _theResult___snd_fst_sfd__h578324, - _theResult___snd_fst_sfd__h596759, - out___1_sfd__h480081, - out___1_sfd__h519075, - out___1_sfd__h558379, - out_sfd__h500064, - out_sfd__h509715, - out_sfd__h518499, - out_sfd__h538917, - out_sfd__h548568, - out_sfd__h557352, - out_sfd__h578221, - out_sfd__h587872, - out_sfd__h596656, - r1__read__h611896; - wire [50 : 0] r1__read__h610369, r1__read__h611586; - wire [49 : 0] r1__read__h611695, r1__read__h611898; - wire [48 : 0] r1__read__h610371, r1__read__h611588, r1__read__h611697; - wire [46 : 0] r1__read__h610373, r1__read__h611590; - wire [45 : 0] r1__read__h610375, r1__read__h611592; - wire [44 : 0] r1__read__h610377, r1__read__h611594; - wire [43 : 0] r1__read__h610379, r1__read__h611596; - wire [42 : 0] r1__read__h611598; - wire [41 : 0] r1__read__h611600; - wire [40 : 0] r1__read__h611602; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055, - IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184; + _theResult___fst_sfd__h484300, + _theResult___fst_sfd__h500128, + _theResult___fst_sfd__h500131, + _theResult___fst_sfd__h509779, + _theResult___fst_sfd__h509782, + _theResult___fst_sfd__h518563, + _theResult___fst_sfd__h518566, + _theResult___fst_sfd__h518575, + _theResult___fst_sfd__h518581, + _theResult___fst_sfd__h523153, + _theResult___fst_sfd__h538981, + _theResult___fst_sfd__h538984, + _theResult___fst_sfd__h548632, + _theResult___fst_sfd__h548635, + _theResult___fst_sfd__h557416, + _theResult___fst_sfd__h557419, + _theResult___fst_sfd__h557428, + _theResult___fst_sfd__h557434, + _theResult___fst_sfd__h562457, + _theResult___fst_sfd__h578285, + _theResult___fst_sfd__h578288, + _theResult___fst_sfd__h587936, + _theResult___fst_sfd__h587939, + _theResult___fst_sfd__h596720, + _theResult___fst_sfd__h596723, + _theResult___fst_sfd__h596732, + _theResult___fst_sfd__h596738, + _theResult___sfd__h500028, + _theResult___sfd__h509679, + _theResult___sfd__h518463, + _theResult___sfd__h538881, + _theResult___sfd__h548532, + _theResult___sfd__h557316, + _theResult___sfd__h578185, + _theResult___sfd__h587836, + _theResult___sfd__h596620, + _theResult___snd_fst_sfd__h480300, + _theResult___snd_fst_sfd__h500134, + _theResult___snd_fst_sfd__h518569, + _theResult___snd_fst_sfd__h519294, + _theResult___snd_fst_sfd__h538987, + _theResult___snd_fst_sfd__h557422, + _theResult___snd_fst_sfd__h558598, + _theResult___snd_fst_sfd__h578291, + _theResult___snd_fst_sfd__h596726, + out___1_sfd__h480048, + out___1_sfd__h519042, + out___1_sfd__h558346, + out_sfd__h500031, + out_sfd__h509682, + out_sfd__h518466, + out_sfd__h538884, + out_sfd__h548535, + out_sfd__h557319, + out_sfd__h578188, + out_sfd__h587839, + out_sfd__h596623; + wire [50 : 0] r1__read__h610322, r1__read__h611539; + wire [49 : 0] r1__read__h611648; + wire [48 : 0] r1__read__h610324, r1__read__h611541, r1__read__h611650; + wire [46 : 0] r1__read__h610326, r1__read__h611543; + wire [45 : 0] r1__read__h610328, r1__read__h611545; + wire [44 : 0] r1__read__h610330, r1__read__h611547; + wire [43 : 0] r1__read__h610332, r1__read__h611549; + wire [42 : 0] r1__read__h611551; + wire [41 : 0] r1__read__h611553; + wire [40 : 0] r1__read__h611555; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051, + IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12, - data73159_BITS_31_TO_0__q13, - imm__h651966, - r1__read__h610381, - r1__read__h611604, - x__h191559, - x__h335761, - x__h381463, - x__h427158, - x__h76055, - x_data__h65904, - x_data_imm__h671111, - x_data_imm__h686042; - wire [29 : 0] r1__read__h610383, r1__read__h611606; - wire [27 : 0] r1__read__h611608; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087, - sfd__h352165, - sfd__h360747, - sfd__h369931, - sfd__h378543, - sfd__h397862, - sfd__h406444, - sfd__h415628, - sfd__h424240, - sfd__h443557, - sfd__h452139, - sfd__h461323, - sfd__h469935, - value__h484962, - value__h523815, - value__h563119; + data73126_BITS_31_TO_0__q13, + imm__h651906, + r1__read__h610334, + r1__read__h611557, + x__h191526, + x__h335728, + x__h381430, + x__h427125, + x__h76022, + x_data__h65871, + x_data_imm__h671051, + x_data_imm__h685982; + wire [29 : 0] r1__read__h610336, r1__read__h611559; + wire [27 : 0] r1__read__h611561; + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083, + sfd__h352132, + sfd__h360714, + sfd__h369898, + sfd__h378510, + sfd__h397829, + sfd__h406411, + sfd__h415595, + sfd__h424207, + sfd__h443524, + sfd__h452106, + sfd__h461290, + sfd__h469902, + value__h484929, + value__h523782, + value__h563086; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -5378,80 +5360,80 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352671, - _theResult___fst_sfd__h361253, - _theResult___fst_sfd__h370437, - _theResult___fst_sfd__h379073, - _theResult___fst_sfd__h379082, - _theResult___fst_sfd__h379088, - _theResult___fst_sfd__h398368, - _theResult___fst_sfd__h406950, - _theResult___fst_sfd__h416134, - _theResult___fst_sfd__h424770, - _theResult___fst_sfd__h424779, - _theResult___fst_sfd__h424785, - _theResult___fst_sfd__h444063, - _theResult___fst_sfd__h452645, - _theResult___fst_sfd__h461829, - _theResult___fst_sfd__h470465, - _theResult___fst_sfd__h470474, - _theResult___fst_sfd__h470480, - _theResult___sfd__h352590, - _theResult___sfd__h361172, - _theResult___sfd__h370356, - _theResult___sfd__h378992, - _theResult___sfd__h379094, - _theResult___sfd__h398287, - _theResult___sfd__h406869, - _theResult___sfd__h416053, - _theResult___sfd__h424689, - _theResult___sfd__h424791, - _theResult___sfd__h443982, - _theResult___sfd__h452564, - _theResult___sfd__h461748, - _theResult___sfd__h470384, - _theResult___sfd__h470486, - _theResult___snd_fst_sfd__h336307, - _theResult___snd_fst_sfd__h361256, - _theResult___snd_fst_sfd__h379076, - _theResult___snd_fst_sfd__h382009, - _theResult___snd_fst_sfd__h406953, - _theResult___snd_fst_sfd__h424773, - _theResult___snd_fst_sfd__h427704, - _theResult___snd_fst_sfd__h452648, - _theResult___snd_fst_sfd__h470468, - f1_sfd__h480018, - f2_sfd__h519012, - f3_sfd__h558316, - out_f_sfd__h379371, - out_f_sfd__h425068, - out_f_sfd__h470763, - out_sfd__h352593, - out_sfd__h361175, - out_sfd__h370359, - out_sfd__h378995, - out_sfd__h398290, - out_sfd__h406872, - out_sfd__h416056, - out_sfd__h424692, - out_sfd__h443985, - out_sfd__h452567, - out_sfd__h461751, - out_sfd__h470387; - wire [19 : 0] r1__read__h611543; - wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771, - _theResult____h647786, - enabled_ints___1__h648311, - enabled_ints__h648358, - pend_ints__h647784, - y__h648323; - wire [13 : 0] r1__read_BITS_13_TO_0___h648334; - wire [12 : 0] fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598; + _theResult___fst_sfd__h352638, + _theResult___fst_sfd__h361220, + _theResult___fst_sfd__h370404, + _theResult___fst_sfd__h379040, + _theResult___fst_sfd__h379049, + _theResult___fst_sfd__h379055, + _theResult___fst_sfd__h398335, + _theResult___fst_sfd__h406917, + _theResult___fst_sfd__h416101, + _theResult___fst_sfd__h424737, + _theResult___fst_sfd__h424746, + _theResult___fst_sfd__h424752, + _theResult___fst_sfd__h444030, + _theResult___fst_sfd__h452612, + _theResult___fst_sfd__h461796, + _theResult___fst_sfd__h470432, + _theResult___fst_sfd__h470441, + _theResult___fst_sfd__h470447, + _theResult___sfd__h352557, + _theResult___sfd__h361139, + _theResult___sfd__h370323, + _theResult___sfd__h378959, + _theResult___sfd__h379061, + _theResult___sfd__h398254, + _theResult___sfd__h406836, + _theResult___sfd__h416020, + _theResult___sfd__h424656, + _theResult___sfd__h424758, + _theResult___sfd__h443949, + _theResult___sfd__h452531, + _theResult___sfd__h461715, + _theResult___sfd__h470351, + _theResult___sfd__h470453, + _theResult___snd_fst_sfd__h336274, + _theResult___snd_fst_sfd__h361223, + _theResult___snd_fst_sfd__h379043, + _theResult___snd_fst_sfd__h381976, + _theResult___snd_fst_sfd__h406920, + _theResult___snd_fst_sfd__h424740, + _theResult___snd_fst_sfd__h427671, + _theResult___snd_fst_sfd__h452615, + _theResult___snd_fst_sfd__h470435, + f1_sfd__h479985, + f2_sfd__h518979, + f3_sfd__h558283, + out_f_sfd__h379338, + out_f_sfd__h425035, + out_f_sfd__h470730, + out_sfd__h352560, + out_sfd__h361142, + out_sfd__h370326, + out_sfd__h378962, + out_sfd__h398257, + out_sfd__h406839, + out_sfd__h416023, + out_sfd__h424659, + out_sfd__h443952, + out_sfd__h452534, + out_sfd__h461718, + out_sfd__h470354; + wire [19 : 0] r1__read__h611496; + wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767, + _theResult____h647726, + enabled_ints___1__h648251, + enabled_ints__h648298, + pend_ints__h647724, + y__h648263; + wire [13 : 0] r1__read_BITS_13_TO_0___h648274; + wire [12 : 0] fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658, - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641, - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973, + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638, + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358, @@ -5464,7 +5446,7 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107, - _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744, + _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791, @@ -5477,24 +5459,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h678634, - result__h643363, - result__h643414, - spec_bits__h681761, - w__h643358, - x__h362344, - x__h408041, - x__h453736, - x__h501487, - x__h540340, - x__h579644, - x__h643362, - x__h643413, - y__h643392, - y__h681774, - y_avValue_fst__h675034, - y_avValue_fst__h675063, - y_avValue_fst__h675097; + renaming_spec_bits__h678574, + result__h643303, + result__h643354, + spec_bits__h681701, + w__h643298, + x__h362311, + x__h408008, + x__h453703, + x__h501454, + x__h540307, + x__h579611, + x__h643302, + x__h643353, + y__h643332, + y__h681714, + y_avValue_fst__h674974, + y_avValue_fst__h675003, + y_avValue_fst__h675037; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053, @@ -5516,102 +5498,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h500060, - _theResult___exp__h509711, - _theResult___exp__h518495, - _theResult___exp__h538913, - _theResult___exp__h548564, - _theResult___exp__h557348, - _theResult___exp__h578217, - _theResult___exp__h587868, - _theResult___exp__h596652, - _theResult___fst_exp__h484332, - _theResult___fst_exp__h499396, - _theResult___fst_exp__h499402, - _theResult___fst_exp__h499405, - _theResult___fst_exp__h500160, - _theResult___fst_exp__h500163, - _theResult___fst_exp__h508982, - _theResult___fst_exp__h509047, - _theResult___fst_exp__h509053, - _theResult___fst_exp__h509056, - _theResult___fst_exp__h509811, - _theResult___fst_exp__h509814, - _theResult___fst_exp__h517767, - _theResult___fst_exp__h517806, - _theResult___fst_exp__h517812, - _theResult___fst_exp__h517815, - _theResult___fst_exp__h518595, - _theResult___fst_exp__h518598, - _theResult___fst_exp__h518607, - _theResult___fst_exp__h518610, - _theResult___fst_exp__h523185, - _theResult___fst_exp__h538249, - _theResult___fst_exp__h538255, - _theResult___fst_exp__h538258, - _theResult___fst_exp__h539013, - _theResult___fst_exp__h539016, - _theResult___fst_exp__h547835, - _theResult___fst_exp__h547900, - _theResult___fst_exp__h547906, - _theResult___fst_exp__h547909, - _theResult___fst_exp__h548664, - _theResult___fst_exp__h548667, - _theResult___fst_exp__h556620, - _theResult___fst_exp__h556659, - _theResult___fst_exp__h556665, - _theResult___fst_exp__h556668, - _theResult___fst_exp__h557448, - _theResult___fst_exp__h557451, - _theResult___fst_exp__h557460, - _theResult___fst_exp__h557463, - _theResult___fst_exp__h562489, - _theResult___fst_exp__h577553, - _theResult___fst_exp__h577559, - _theResult___fst_exp__h577562, - _theResult___fst_exp__h578317, - _theResult___fst_exp__h578320, - _theResult___fst_exp__h587139, - _theResult___fst_exp__h587204, - _theResult___fst_exp__h587210, - _theResult___fst_exp__h587213, - _theResult___fst_exp__h587968, - _theResult___fst_exp__h587971, - _theResult___fst_exp__h595924, - _theResult___fst_exp__h595963, - _theResult___fst_exp__h595969, - _theResult___fst_exp__h595972, - _theResult___fst_exp__h596752, - _theResult___fst_exp__h596755, - _theResult___fst_exp__h596764, - _theResult___fst_exp__h596767, - _theResult___snd_fst_exp__h500166, - _theResult___snd_fst_exp__h518601, - _theResult___snd_fst_exp__h539019, - _theResult___snd_fst_exp__h557454, - _theResult___snd_fst_exp__h578323, - _theResult___snd_fst_exp__h596758, + _theResult___exp__h500027, + _theResult___exp__h509678, + _theResult___exp__h518462, + _theResult___exp__h538880, + _theResult___exp__h548531, + _theResult___exp__h557315, + _theResult___exp__h578184, + _theResult___exp__h587835, + _theResult___exp__h596619, + _theResult___fst_exp__h484299, + _theResult___fst_exp__h499363, + _theResult___fst_exp__h499369, + _theResult___fst_exp__h499372, + _theResult___fst_exp__h500127, + _theResult___fst_exp__h500130, + _theResult___fst_exp__h508949, + _theResult___fst_exp__h509014, + _theResult___fst_exp__h509020, + _theResult___fst_exp__h509023, + _theResult___fst_exp__h509778, + _theResult___fst_exp__h509781, + _theResult___fst_exp__h517734, + _theResult___fst_exp__h517773, + _theResult___fst_exp__h517779, + _theResult___fst_exp__h517782, + _theResult___fst_exp__h518562, + _theResult___fst_exp__h518565, + _theResult___fst_exp__h518574, + _theResult___fst_exp__h518577, + _theResult___fst_exp__h523152, + _theResult___fst_exp__h538216, + _theResult___fst_exp__h538222, + _theResult___fst_exp__h538225, + _theResult___fst_exp__h538980, + _theResult___fst_exp__h538983, + _theResult___fst_exp__h547802, + _theResult___fst_exp__h547867, + _theResult___fst_exp__h547873, + _theResult___fst_exp__h547876, + _theResult___fst_exp__h548631, + _theResult___fst_exp__h548634, + _theResult___fst_exp__h556587, + _theResult___fst_exp__h556626, + _theResult___fst_exp__h556632, + _theResult___fst_exp__h556635, + _theResult___fst_exp__h557415, + _theResult___fst_exp__h557418, + _theResult___fst_exp__h557427, + _theResult___fst_exp__h557430, + _theResult___fst_exp__h562456, + _theResult___fst_exp__h577520, + _theResult___fst_exp__h577526, + _theResult___fst_exp__h577529, + _theResult___fst_exp__h578284, + _theResult___fst_exp__h578287, + _theResult___fst_exp__h587106, + _theResult___fst_exp__h587171, + _theResult___fst_exp__h587177, + _theResult___fst_exp__h587180, + _theResult___fst_exp__h587935, + _theResult___fst_exp__h587938, + _theResult___fst_exp__h595891, + _theResult___fst_exp__h595930, + _theResult___fst_exp__h595936, + _theResult___fst_exp__h595939, + _theResult___fst_exp__h596719, + _theResult___fst_exp__h596722, + _theResult___fst_exp__h596731, + _theResult___fst_exp__h596734, + _theResult___snd_fst_exp__h500133, + _theResult___snd_fst_exp__h518568, + _theResult___snd_fst_exp__h538986, + _theResult___snd_fst_exp__h557421, + _theResult___snd_fst_exp__h578290, + _theResult___snd_fst_exp__h596725, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h518655, - din_inc___2_exp__h518690, - din_inc___2_exp__h518716, - din_inc___2_exp__h557508, - din_inc___2_exp__h557543, - din_inc___2_exp__h557569, - din_inc___2_exp__h596812, - din_inc___2_exp__h596847, - din_inc___2_exp__h596873, - out_exp__h500063, - out_exp__h509714, - out_exp__h518498, - out_exp__h538916, - out_exp__h548567, - out_exp__h557351, - out_exp__h578220, - out_exp__h587871, - out_exp__h596655; + din_inc___2_exp__h518622, + din_inc___2_exp__h518657, + din_inc___2_exp__h518683, + din_inc___2_exp__h557475, + din_inc___2_exp__h557510, + din_inc___2_exp__h557536, + din_inc___2_exp__h596779, + din_inc___2_exp__h596814, + din_inc___2_exp__h596840, + out_exp__h500030, + out_exp__h509681, + out_exp__h518465, + out_exp__h538883, + out_exp__h548534, + out_exp__h557318, + out_exp__h578187, + out_exp__h587838, + out_exp__h596622; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5642,125 +5624,125 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739, - _theResult___exp__h352589, - _theResult___exp__h361171, - _theResult___exp__h370355, - _theResult___exp__h378991, - _theResult___exp__h379093, - _theResult___exp__h398286, - _theResult___exp__h406868, - _theResult___exp__h416052, - _theResult___exp__h424688, - _theResult___exp__h424790, - _theResult___exp__h443981, - _theResult___exp__h452563, - _theResult___exp__h461747, - _theResult___exp__h470383, - _theResult___exp__h470485, - _theResult___fst_exp__h352073, - _theResult___fst_exp__h352138, - _theResult___fst_exp__h352144, - _theResult___fst_exp__h352147, - _theResult___fst_exp__h352670, - _theResult___fst_exp__h360720, - _theResult___fst_exp__h360726, - _theResult___fst_exp__h360729, - _theResult___fst_exp__h361252, - _theResult___fst_exp__h369839, - _theResult___fst_exp__h369904, - _theResult___fst_exp__h369910, - _theResult___fst_exp__h369913, - _theResult___fst_exp__h370436, - _theResult___fst_exp__h378476, - _theResult___fst_exp__h378515, - _theResult___fst_exp__h378521, - _theResult___fst_exp__h378524, - _theResult___fst_exp__h379072, - _theResult___fst_exp__h379081, - _theResult___fst_exp__h379084, - _theResult___fst_exp__h397770, - _theResult___fst_exp__h397835, - _theResult___fst_exp__h397841, - _theResult___fst_exp__h397844, - _theResult___fst_exp__h398367, - _theResult___fst_exp__h406417, - _theResult___fst_exp__h406423, - _theResult___fst_exp__h406426, - _theResult___fst_exp__h406949, - _theResult___fst_exp__h415536, - _theResult___fst_exp__h415601, - _theResult___fst_exp__h415607, - _theResult___fst_exp__h415610, - _theResult___fst_exp__h416133, - _theResult___fst_exp__h424173, - _theResult___fst_exp__h424212, - _theResult___fst_exp__h424218, - _theResult___fst_exp__h424221, - _theResult___fst_exp__h424769, - _theResult___fst_exp__h424778, - _theResult___fst_exp__h424781, - _theResult___fst_exp__h443465, - _theResult___fst_exp__h443530, - _theResult___fst_exp__h443536, - _theResult___fst_exp__h443539, - _theResult___fst_exp__h444062, - _theResult___fst_exp__h452112, - _theResult___fst_exp__h452118, - _theResult___fst_exp__h452121, - _theResult___fst_exp__h452644, - _theResult___fst_exp__h461231, - _theResult___fst_exp__h461296, - _theResult___fst_exp__h461302, - _theResult___fst_exp__h461305, - _theResult___fst_exp__h461828, - _theResult___fst_exp__h469868, - _theResult___fst_exp__h469907, - _theResult___fst_exp__h469913, - _theResult___fst_exp__h469916, - _theResult___fst_exp__h470464, - _theResult___fst_exp__h470473, - _theResult___fst_exp__h470476, - _theResult___snd_fst_exp__h361255, - _theResult___snd_fst_exp__h379075, - _theResult___snd_fst_exp__h406952, - _theResult___snd_fst_exp__h424772, - _theResult___snd_fst_exp__h452647, - _theResult___snd_fst_exp__h470467, - din_inc___2_exp__h379106, - din_inc___2_exp__h379130, - din_inc___2_exp__h379160, - din_inc___2_exp__h379184, - din_inc___2_exp__h424803, - din_inc___2_exp__h424827, - din_inc___2_exp__h424857, - din_inc___2_exp__h424881, - din_inc___2_exp__h470498, - din_inc___2_exp__h470522, - din_inc___2_exp__h470552, - din_inc___2_exp__h470576, - f1_exp80017_MINUS_127__q136, - f1_exp__h480017, - f2_exp19011_MINUS_127__q176, - f2_exp__h519011, - f3_exp58315_MINUS_127__q153, - f3_exp__h558315, - out_exp__h352592, - out_exp__h361174, - out_exp__h370358, - out_exp__h378994, - out_exp__h398289, - out_exp__h406871, - out_exp__h416055, - out_exp__h424691, - out_exp__h443984, - out_exp__h452566, - out_exp__h461750, - out_exp__h470386, - out_f_exp__h379370, - out_f_exp__h425067, - out_f_exp__h470762, - x__h610340; + _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735, + _theResult___exp__h352556, + _theResult___exp__h361138, + _theResult___exp__h370322, + _theResult___exp__h378958, + _theResult___exp__h379060, + _theResult___exp__h398253, + _theResult___exp__h406835, + _theResult___exp__h416019, + _theResult___exp__h424655, + _theResult___exp__h424757, + _theResult___exp__h443948, + _theResult___exp__h452530, + _theResult___exp__h461714, + _theResult___exp__h470350, + _theResult___exp__h470452, + _theResult___fst_exp__h352040, + _theResult___fst_exp__h352105, + _theResult___fst_exp__h352111, + _theResult___fst_exp__h352114, + _theResult___fst_exp__h352637, + _theResult___fst_exp__h360687, + _theResult___fst_exp__h360693, + _theResult___fst_exp__h360696, + _theResult___fst_exp__h361219, + _theResult___fst_exp__h369806, + _theResult___fst_exp__h369871, + _theResult___fst_exp__h369877, + _theResult___fst_exp__h369880, + _theResult___fst_exp__h370403, + _theResult___fst_exp__h378443, + _theResult___fst_exp__h378482, + _theResult___fst_exp__h378488, + _theResult___fst_exp__h378491, + _theResult___fst_exp__h379039, + _theResult___fst_exp__h379048, + _theResult___fst_exp__h379051, + _theResult___fst_exp__h397737, + _theResult___fst_exp__h397802, + _theResult___fst_exp__h397808, + _theResult___fst_exp__h397811, + _theResult___fst_exp__h398334, + _theResult___fst_exp__h406384, + _theResult___fst_exp__h406390, + _theResult___fst_exp__h406393, + _theResult___fst_exp__h406916, + _theResult___fst_exp__h415503, + _theResult___fst_exp__h415568, + _theResult___fst_exp__h415574, + _theResult___fst_exp__h415577, + _theResult___fst_exp__h416100, + _theResult___fst_exp__h424140, + _theResult___fst_exp__h424179, + _theResult___fst_exp__h424185, + _theResult___fst_exp__h424188, + _theResult___fst_exp__h424736, + _theResult___fst_exp__h424745, + _theResult___fst_exp__h424748, + _theResult___fst_exp__h443432, + _theResult___fst_exp__h443497, + _theResult___fst_exp__h443503, + _theResult___fst_exp__h443506, + _theResult___fst_exp__h444029, + _theResult___fst_exp__h452079, + _theResult___fst_exp__h452085, + _theResult___fst_exp__h452088, + _theResult___fst_exp__h452611, + _theResult___fst_exp__h461198, + _theResult___fst_exp__h461263, + _theResult___fst_exp__h461269, + _theResult___fst_exp__h461272, + _theResult___fst_exp__h461795, + _theResult___fst_exp__h469835, + _theResult___fst_exp__h469874, + _theResult___fst_exp__h469880, + _theResult___fst_exp__h469883, + _theResult___fst_exp__h470431, + _theResult___fst_exp__h470440, + _theResult___fst_exp__h470443, + _theResult___snd_fst_exp__h361222, + _theResult___snd_fst_exp__h379042, + _theResult___snd_fst_exp__h406919, + _theResult___snd_fst_exp__h424739, + _theResult___snd_fst_exp__h452614, + _theResult___snd_fst_exp__h470434, + din_inc___2_exp__h379073, + din_inc___2_exp__h379097, + din_inc___2_exp__h379127, + din_inc___2_exp__h379151, + din_inc___2_exp__h424770, + din_inc___2_exp__h424794, + din_inc___2_exp__h424824, + din_inc___2_exp__h424848, + din_inc___2_exp__h470465, + din_inc___2_exp__h470489, + din_inc___2_exp__h470519, + din_inc___2_exp__h470543, + f1_exp79984_MINUS_127__q136, + f1_exp__h479984, + f2_exp18978_MINUS_127__q176, + f2_exp__h518978, + f3_exp58282_MINUS_127__q153, + f3_exp__h558282, + out_exp__h352559, + out_exp__h361141, + out_exp__h370325, + out_exp__h378961, + out_exp__h398256, + out_exp__h406838, + out_exp__h416022, + out_exp__h424658, + out_exp__h443951, + out_exp__h452533, + out_exp__h461717, + out_exp__h470353, + out_f_exp__h379337, + out_f_exp__h425034, + out_f_exp__h470729, + x__h610293; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027, @@ -5780,11 +5762,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608, - x__h181305, - x__h700755; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225, - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604, + x__h181272, + x__h700695; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221, + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949, @@ -5800,116 +5782,116 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961, - checkForException___d12946, - checkForException___d13619, - fflags__h714186, - res_fflags__h335747, - res_fflags__h381449, - res_fflags__h427144, - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306, - rs1__h651965, - x__h153478, - x__h157025, - x__h159841, - x__h285158, - y_avValue_fst__h712379, - y_avValue_fst__h714101, - y_avValue_fst__h714129; + checkForException___d12942, + checkForException___d13615, + fflags__h714091, + res_fflags__h335714, + res_fflags__h381416, + res_fflags__h427111, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302, + rs1__h651905, + x__h153444, + x__h156991, + x__h159807, + x__h285126, + y_avValue_fst__h712284, + y_avValue_fst__h714006, + y_avValue_fst__h714034; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145, - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146, - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141, + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142, + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175, IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791, - IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219, - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095, + IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215, + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h698122, - vm_mode_reg__read__h611549; + cause_code__h698062, + vm_mode_reg__read__h611502; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h294400, - dcsr_cause__h697642, - next_deqP___1__h294679, - v__h293820, - v__h294051, - x__h300030, - x_decodeInfo_frm__h651649; + _theResult_____2__h294368, + dcsr_cause__h697582, + next_deqP___1__h294647, + v__h293788, + v__h294019, + x__h299998, + x_decodeInfo_frm__h651589; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206, - IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159, - IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135, - guard__h343972, - guard__h352681, - guard__h361611, - guard__h370447, - guard__h389671, - guard__h398378, - guard__h407308, - guard__h416144, - guard__h435366, - guard__h444073, - guard__h453003, - guard__h461839, - guard__h491444, - guard__h500756, - guard__h509825, - guard__h530297, - guard__h539609, - guard__h548678, - guard__h569601, - guard__h578913, - guard__h587982, - prv__h715821, - prv__h715865, - r1__read_BITS_13_TO_12___h651834, - sbIdx__h156904, - v__h601760, - v__h601770, - v__h602405, - x__h709419, - x__h714428, - y_avValue_snd_snd_snd_fst__h712827, - y_avValue_snd_snd_snd_fst__h714252, - y_avValue_snd_snd_snd_fst__h714281; + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201, + IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159, + IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135, + guard__h343939, + guard__h352648, + guard__h361578, + guard__h370414, + guard__h389638, + guard__h398345, + guard__h407275, + guard__h416111, + guard__h435333, + guard__h444040, + guard__h452970, + guard__h461806, + guard__h491411, + guard__h500723, + guard__h509792, + guard__h530264, + guard__h539576, + guard__h548645, + guard__h569568, + guard__h578880, + guard__h587949, + prv__h715726, + prv__h715770, + r1__read_BITS_13_TO_12___h651774, + sbIdx__h156870, + v__h601727, + v__h601737, + v__h602372, + x__h709324, + x__h714333, + y_avValue_snd_snd_snd_fst__h712732, + y_avValue_snd_snd_snd_fst__h714157, + y_avValue_snd_snd_snd_fst__h714186; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5928,9 +5910,9 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677, - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673, + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704, @@ -5956,12 +5938,12 @@ module mkCore(CLK, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11367, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11368, @@ -5985,11 +5967,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099, - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829, - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837, - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752, - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836, - IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197, + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825, + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833, + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748, + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832, + IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897, @@ -6019,8 +6001,8 @@ module mkCore(CLK, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11342, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376, IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214, @@ -6101,28 +6083,28 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554, - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365, - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754, - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826, - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005, + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361, + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750, + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198, + IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352, - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646, - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348, + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642, + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804, @@ -6136,13 +6118,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510, - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570, - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506, + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566, + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217, NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358, NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230, @@ -6193,37 +6175,37 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585, NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350, - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644, - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172, - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018, - NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407, - NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777, - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124, - NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346, + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640, + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168, + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830, + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014, + NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403, + NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773, + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120, + NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6239,21 +6221,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758, - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103, - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799, - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817, - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935, - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177, - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688, - NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932, - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928, - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754, + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099, + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795, + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813, + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930, + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172, + NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684, + NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927, + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924, + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644, @@ -6287,11 +6269,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653, - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849, - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750, - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573, + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845, + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746, + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180, @@ -6319,7 +6301,8 @@ module mkCore(CLK, _dfoo2, _dfoo20, _dfoo24, - _dfoo30, + _dfoo26, + _dfoo32, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6345,22 +6328,22 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h302396, - _theResult_____2__h308390, - _theResult_____2__h316244, - _theResult_____2__h326588, - _theResult_____2__h329813, - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533, - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534, - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168, - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207, - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181, - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213, - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189, - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217, - coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230, - coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623, - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374, + _theResult_____2__h302364, + _theResult_____2__h308358, + _theResult_____2__h316212, + _theResult_____2__h326556, + _theResult_____2__h329781, + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529, + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530, + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165, + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204, + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178, + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210, + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186, + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214, + coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227, + coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620, + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370, coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334, coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373, coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347, @@ -6368,7 +6351,7 @@ module mkCore(CLK, coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355, coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383, coreFix_aluExe_1_dispToRegQ_first__1311_BIT_13_ETC___d11396, - coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978, + coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244, coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268, @@ -6389,7 +6372,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944, coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570, coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608, coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583, @@ -6451,109 +6434,110 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432, - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712, - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593, - csrf_prv_reg_read__2730_ULE_1___d14571, - csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978, - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815, - f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408, - fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021, - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095, - fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986, - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215, - fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919, - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935, - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439, - fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756, - fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894, - fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906, - guard__h362209, - guard__h407906, - guard__h453601, - guard__h501354, - guard__h540207, - guard__h579511, - idx__h678765, - k__h664143, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428, + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708, + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589, + csrf_prv_reg_read__2727_ULE_1___d14567, + csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974, + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811, + f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403, + fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017, + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091, + fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211, + fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915, + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931, + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435, + fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752, + fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890, + fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902, + guard__h362176, + guard__h407873, + guard__h453568, + guard__h501321, + guard__h540174, + guard__h579478, + idx__h678705, + k__h664083, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153, mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h75940, - next_deqP___1__h302675, - next_deqP___1__h308956, - next_deqP___1__h316810, - next_deqP___1__h326867, - next_deqP___1__h330092, - r1__read_BIT_20___h652494, - r__h610387, - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862, - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067, - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123, - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841, - rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252, - rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693, - rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243, + msip__h75907, + next_deqP___1__h302643, + next_deqP___1__h308924, + next_deqP___1__h316778, + next_deqP___1__h326835, + next_deqP___1__h330060, + r1__read_BIT_20___h652434, + r__h610340, + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858, + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119, + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837, + rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247, + rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689, + rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h297165, - v__h297683, - v__h307679, - v__h307910, - v__h311555, - v__h311786, - v__h326156, - v__h326387, - v__h329381, - v__h329612, - x__h601261; + v__h297133, + v__h297651, + v__h307647, + v__h307878, + v__h311523, + v__h311754, + v__h326124, + v__h326355, + v__h329349, + v__h329580, + value_BIT_52___h399003, + x__h601228; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6594,7 +6578,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6614,7 +6598,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6846,11 +6830,6 @@ module mkCore(CLK, assign CAN_FIRE_setSEIP = 1'd1 ; assign WILL_FIRE_setSEIP = EN_setSEIP ; - // action method setDEIP - assign RDY_setDEIP = 1'd1 ; - assign CAN_FIRE_setDEIP = 1'd1 ; - assign WILL_FIRE_setDEIP = EN_setDEIP ; - // action method hart0_run_halt_server_request_put assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; @@ -9799,7 +9778,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252 && + rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9870,10 +9849,6 @@ module mkCore(CLK, f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ; assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ; - // rule RL_rl_debug_resume - assign CAN_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - // rule RL_rl_debug_run_redundant assign CAN_FIRE_RL_rl_debug_run_redundant = f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && @@ -9900,7 +9875,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408 && + f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10207,7 +10182,7 @@ module mkCore(CLK, (!fetchStage$pipelines_0_canDeq || epochManager$checkEpoch_0_check || fetchStage$RDY_pipelines_0_deq) && - NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715 && + NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 && !epochManager$checkEpoch_0_check ; assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath = CAN_FIRE_RL_renameStage_doRenaming_wrongPath ; @@ -10251,8 +10226,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510 && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534 && + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 && + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 && !commitStage_rg_run_state && commitStage_commitTrap[133] ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = @@ -10302,8 +10277,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693 && - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 && + rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 && + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 && (rob$deqPort_0_deq_data[186:182] == 5'd0 || rob$deqPort_0_deq_data[186:182] == 5'd21 || rob$deqPort_0_deq_data[186:182] == 5'd17 || @@ -10345,8 +10320,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935 && - NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 && + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 && + NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 && rob$deqPort_0_deq_data[186:182] != 5'd0 && rob$deqPort_0_deq_data[186:182] != 5'd21 && rob$deqPort_0_deq_data[186:182] != 5'd17 && @@ -10429,7 +10404,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = !coreFix_aluExe_0_exeToFinQ$first[17] && coreFix_aluExe_0_exeToFinQ$RDY_deq && - coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623 ; + coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10438,7 +10413,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = !coreFix_aluExe_1_exeToFinQ$first[17] && coreFix_aluExe_1_exeToFinQ$RDY_deq && - coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978 ; + coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ; @@ -10484,7 +10459,7 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ$RDY_deq && coreFix_aluExe_0_regToExeQ$RDY_enq && coreFix_aluExe_0_dispToRegQ$RDY_first && - coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230 ; + coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10989,6 +10964,19 @@ module mkCore(CLK, assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; + // rule RL_rl_debug_resume + assign CAN_FIRE_RL_rl_debug_resume = + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && + f_run_halt_reqs$EMPTY_N && + f_run_halt_rsps$FULL_N && + rg_core_run_state == 2'd1 && + f_run_halt_reqs$D_OUT && + !f_gpr_reqs$EMPTY_N && + !f_fpr_reqs$EMPTY_N && + !f_csr_reqs$EMPTY_N ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = coreFix_memExe_dispToRegQ$RDY_deq && @@ -11262,7 +11250,7 @@ module mkCore(CLK, epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 && rob$isEmpty && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = @@ -11274,8 +11262,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297 && + rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -11317,11 +11305,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365) && - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829 && - IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015 ; + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) && + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 && + IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -11360,7 +11348,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 ; + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11482,6 +11470,8 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && @@ -11547,20 +11537,12 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_handle && (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd3) ; - assign MUX_csrf_debug_int_pend$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == - 6'd29 ; - assign MUX_csrf_debug_int_pend$write_1__SEL_2 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd9 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11568,23 +11550,31 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd16 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd324 || f_csr_reqs$D_OUT[75:64] == 12'd836) ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd29 ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11593,22 +11583,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11620,33 +11610,33 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11660,7 +11650,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11668,7 +11658,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11682,17 +11672,17 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11704,24 +11694,26 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd384 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + assign MUX_csrf_prv_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ; + assign MUX_csrf_prv_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd36 ; - assign MUX_csrf_rg_dcsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd37 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11735,7 +11727,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11746,7 +11738,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11756,7 +11748,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd0 && mmio_pRqQ_data_0[37:36] != 2'd1 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd320 ; @@ -11766,7 +11758,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11777,13 +11769,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ; + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = @@ -11796,7 +11788,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -11838,15 +11830,8 @@ module mkCore(CLK, assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_started$write_1__SEL_1 = - commitStage_rg_run_state && f_run_halt_reqs$EMPTY_N && - f_run_halt_rsps$FULL_N && - rg_core_run_state == 2'd1 && - f_run_halt_reqs$D_OUT && - !f_gpr_reqs$EMPTY_N && - !f_fpr_reqs$EMPTY_N && - !f_csr_reqs$EMPTY_N ; - assign MUX_update_vm_info$write_1__SEL_2 = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -11857,19 +11842,19 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h692296, - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306 } ; + x__h692236, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 } ; assign MUX_commitStage_rg_serialnum$write_1__VAL_1 = commitStage_rg_serialnum + 64'd1 ; assign MUX_commitStage_rg_serialnum$write_1__VAL_2 = - commitStage_rg_serialnum + y__h714209 ; + commitStage_rg_serialnum + y__h714114 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h664143 == 1'd0 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021) ? + (k__h664083 == 1'd0 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11879,21 +11864,21 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11988,7 +11973,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -12002,10 +11987,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283725 } ; + x__h283692 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h285170, + x__h285138, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12013,7 +11998,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287946, + addr__h287914, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12026,12 +12011,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153478, x__h153484, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153444, x__h153450, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157025, x__h157031, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h156991, x__h156997, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h159841, - x__h159845, + { x__h159807, + x__h159811, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12042,7 +12027,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161693, + x__h161659, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12055,13 +12040,19 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289850, + resp_addr__h289818, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = + { prv__h715770, + prv__h715770 != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_lsq$getIssueLd[76:72], @@ -12135,7 +12126,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h195006 } ; + x__h194973 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12170,8 +12161,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190796 : - { {32{x__h191559[31]}}, x__h191559 } } ; + curData__h190763 : + { {32{x__h191526[31]}}, x__h191526 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12204,9 +12195,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h714186 ; + csrf_fflags_reg | fflags__h714091 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q270[7:5] ; @@ -12214,10 +12205,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 or + always@(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 or robdeqPort_0_deq_data_BITS_95_TO_32__q270) begin - case (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678) + case (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q270[14:13]; @@ -12232,57 +12223,61 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q270[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h710013 + 64'd1 ; + n__read__h709918 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h710013 + { 62'd0, x__h714428 } ; + n__read__h709918 + { 62'd0, x__h714333 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h699161 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h699101 ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd8 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ? + (rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd36) ? + MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : + ((rob$deqPort_0_deq_data[186:182] == 5'd19) ? + x__h709324 : + csrf_mpp_reg) ; + assign MUX_csrf_prv_reg$write_1__VAL_2 = + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ? 2'd1 : 2'd3 ; - assign MUX_csrf_prv_reg$write_1__VAL_2 = - (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h709419 : - csrf_mpp_reg ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h697642, + dcsr_cause__h697582, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12292,25 +12287,31 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h718266 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h718171 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 ? - y_avValue__h699008 : - y_avValue__h700777 ; + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ? + y_avValue__h698948 : + y_avValue__h700717 ; always@(rob$deqPort_0_deq_data or - next_pc__h709359 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h709264 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h709359; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h709264; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12345,23 +12346,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473693 : - data__h473159 ; + data___1__h473660 : + data__h473126 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335751 : - res_data__h335746 ; + res_data__h335718 : + res_data__h335713 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h381453 : - res_data__h381448 ; + res_data__h381420 : + res_data__h381415 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h427148 : - res_data__h427143 ; + res_data__h427115 : + res_data__h427110 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472885 : + data___1__h472852 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -12376,7 +12377,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12387,16 +12388,16 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087 } ; + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 2'd1, - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004, - IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219, + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000, + IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215, fetchStage$pipelines_0_first[63:0], 2'd0, fetchStage$pipelines_0_first[323:260], @@ -12407,7 +12408,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12425,21 +12426,21 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335747 ; + res_fflags__h335714 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h381449 ; + res_fflags__h381416 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h427144 ; + res_fflags__h427111 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serialnum, rob$deqPort_0_deq_data[282:181], CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306, + rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302, rob$deqPort_0_deq_data[161:98], CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275, rob$deqPort_0_deq_data[95:26] } ; @@ -12461,7 +12462,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[199:195] == 5'd13 || WILL_FIRE_RL_renameStage_doRenaming_Trap && - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233 ; + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 ; assign mmio_dataReqQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ? MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 : @@ -12503,13 +12504,13 @@ module mkCore(CLK, coreFix_aluExe_1_exeToFinQ$first[16] ; assign coreFix_aluExe_0_bypassWire_0$wget = { coreFix_aluExe_0_regToExeQ$first[348:342], - basicExec___d12560[321:258] } ; + basicExec___d12557[321:258] } ; assign coreFix_aluExe_0_bypassWire_0$whas = WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[349] ; assign coreFix_aluExe_0_bypassWire_1$wget = { coreFix_aluExe_1_regToExeQ$first[348:342], - basicExec___d11914[321:258] } ; + basicExec___d11911[321:258] } ; assign coreFix_aluExe_0_bypassWire_1$whas = WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[349] ; @@ -12732,7 +12733,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serialnum @@ -12761,8 +12762,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h602405 : - v__h601760 ; + v__h602372 : + v__h601727 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12869,7 +12870,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h294400 ; + _theResult_____2__h294368 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12891,7 +12892,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293820 ; + v__h293788 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12937,7 +12938,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h302396 ; + _theResult_____2__h302364 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12955,7 +12956,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h297165 ; + v__h297133 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13055,7 +13056,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h308390 ; + _theResult_____2__h308358 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13073,7 +13074,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307679 ; + v__h307647 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13094,7 +13095,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311953, + { x_addr__h311921, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13124,7 +13125,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h316244 ; + _theResult_____2__h316212 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13142,7 +13143,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h311555 ; + v__h311523 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13219,7 +13220,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329813 ; + _theResult_____2__h329781 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13237,7 +13238,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h329381 ; + v__h329349 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13280,7 +13281,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h326588 ; + _theResult_____2__h326556 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13298,7 +13299,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h326156 ; + v__h326124 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13453,28 +13454,6 @@ module mkCore(CLK, csrInstOrInterruptInflight_rl) ; assign csrInstOrInterruptInflight_rl$EN = 1'd1 ; - // register csrf_debug_int_pend - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or - MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or - f_csr_reqs$D_OUT or EN_setDEIP or setDEIP_v) - case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: - csrf_debug_int_pend$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[14]; - MUX_csrf_debug_int_pend$write_1__SEL_2: - csrf_debug_int_pend$D_IN = f_csr_reqs$D_OUT[14]; - EN_setDEIP: csrf_debug_int_pend$D_IN = setDEIP_v; - default: csrf_debug_int_pend$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign csrf_debug_int_pend$EN = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == - 6'd29 || - EN_setDEIP ; - // register csrf_external_int_en_vec_0 assign csrf_external_int_en_vec_0$D_IN = MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ? @@ -13507,7 +13486,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13544,15 +13523,15 @@ module mkCore(CLK, EN_setSEIP ; // register csrf_external_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_external_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[11]; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11]; EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v; default: csrf_external_int_pend_vec_3$D_IN = @@ -13563,7 +13542,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29 || EN_setMEIP ; @@ -13585,12 +13564,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd0 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 || + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13603,9 +13582,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd1 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13627,7 +13606,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 || + NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13660,10 +13639,10 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -13682,24 +13661,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h698122 or + cause_code__h698062 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h698122; + csrf_mcause_code_reg$D_IN = cause_code__h698062; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13708,11 +13687,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13735,11 +13714,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13752,7 +13731,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13765,7 +13744,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13778,11 +13757,11 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd24 ; // register csrf_mcycle_ehr_data_rl - assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5341 ; + assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5309 ; assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ; // register csrf_medeleg_13_11_reg @@ -13795,7 +13774,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_medeleg_15_reg @@ -13808,7 +13787,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -13821,7 +13800,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd20 ; // register csrf_mepc_csr @@ -13844,11 +13823,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd26 ; // register csrf_mideleg_11_reg @@ -13861,7 +13840,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -13874,7 +13853,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -13887,7 +13866,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -13900,13 +13879,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd21 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? - upd__h4024 : + upd__h3992 : IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; @@ -13925,12 +13904,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -13942,7 +13921,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_mscratch_csr @@ -13955,7 +13934,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd25 ; // register csrf_mtval_csr @@ -13978,11 +13957,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -13995,7 +13974,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14008,7 +13987,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd23 ; // register csrf_mxr_reg @@ -14032,7 +14011,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14061,10 +14040,10 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14084,49 +14063,59 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ; // register csrf_prv_reg - assign csrf_prv_reg$D_IN = - MUX_csrf_prv_reg$write_1__SEL_1 ? - MUX_csrf_prv_reg$write_1__VAL_1 : - MUX_csrf_prv_reg$write_1__VAL_2 ; + always@(MUX_csrf_prv_reg$write_1__SEL_1 or + MUX_csrf_prv_reg$write_1__VAL_1 or + MUX_csrf_prv_reg$write_1__SEL_2 or + MUX_csrf_prv_reg$write_1__VAL_2 or + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prv_reg$write_1__SEL_1: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; + MUX_csrf_prv_reg$write_1__SEL_2: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2; + MUX_csrf_prv_reg$write_1__SEL_3: + csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; + default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ; + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_commitStage_rg_run_state$write_1__SEL_1 or MUX_csrf_rg_dcsr$write_1__VAL_2 or - MUX_csrf_rg_dcsr$write_1__SEL_3 or f_csr_reqs$D_OUT) + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_rg_dcsr$write_1__SEL_1: csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32]; MUX_commitStage_rg_run_state$write_1__SEL_1: csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2; - MUX_csrf_rg_dcsr$write_1__SEL_3: + MUX_csrf_prv_reg$write_1__SEL_3: csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_rg_dcsr$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd36 ; // register csrf_rg_dpc @@ -14145,12 +14134,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd37 ; // register csrf_rg_dscratch0 @@ -14163,7 +14152,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd38 ; // register csrf_rg_dscratch1 @@ -14176,20 +14165,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd39 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h698122 or + cause_code__h698062 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h698122; + csrf_scause_code_reg$D_IN = cause_code__h698062; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14198,11 +14187,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14225,11 +14214,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14242,7 +14231,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14255,7 +14244,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14268,7 +14257,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd11 ; // register csrf_sepc_csr @@ -14291,11 +14280,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14330,7 +14319,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14356,19 +14345,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; // register csrf_software_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or f_csr_reqs$D_OUT) + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3]; MUX_csrf_software_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_software_int_pend_vec_3$write_1__VAL_2; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3]; default: csrf_software_int_pend_vec_3$D_IN = 1'b0 /* unspecified value */ ; @@ -14381,7 +14370,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd29 ; // register csrf_spp_reg @@ -14398,10 +14387,10 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14416,7 +14405,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd12 ; // register csrf_stats_module_doStats @@ -14443,11 +14432,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 && - csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 && + csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14460,7 +14449,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14473,7 +14462,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd10 ; // register csrf_sum_reg @@ -14523,7 +14512,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14564,7 +14553,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_tvm_reg @@ -14577,7 +14566,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_tw_reg @@ -14590,7 +14579,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14603,21 +14592,21 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_flushCaches ; // register flush_reservation @@ -14632,11 +14621,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd16 || rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14645,7 +14634,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46110, + { x__h46077, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14657,7 +14646,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48646 } ; + x__h48613 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -14750,7 +14739,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18203, + { x__h18170, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14762,7 +14751,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20741 } ; + x__h20708 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -14846,7 +14835,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65904 } ; + x_data__h65871 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -14936,7 +14925,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -14966,7 +14955,8 @@ module mkCore(CLK, EN_coreReq_start ; // register update_vm_info - assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_2 ; + assign update_vm_info$D_IN = + !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || @@ -14984,7 +14974,7 @@ module mkCore(CLK, coreFix_aluExe_0_rsAlu$dispatchData[8:4], coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -15024,13 +15014,13 @@ module mkCore(CLK, { coreFix_aluExe_0_regToExeQ$first[421:417], coreFix_aluExe_0_regToExeQ$first[349:305], coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11, - basicExec___d12560[321:258], + basicExec___d12557[321:258], coreFix_aluExe_0_regToExeQ$first[395], - basicExec___d12560[257:194], - basicExec___d12560[129:0], + basicExec___d12557[257:194], + basicExec___d12557[129:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15073,14 +15063,14 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h636445, - x__h636446, + x__h636385, + x__h636386, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, coreFix_aluExe_0_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15188,7 +15178,7 @@ module mkCore(CLK, end assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15276,7 +15266,7 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$dispatchData[8:4], coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15315,13 +15305,13 @@ module mkCore(CLK, { coreFix_aluExe_1_regToExeQ$first[421:417], coreFix_aluExe_1_regToExeQ$first[349:305], coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11, - basicExec___d11914[321:258], + basicExec___d11911[321:258], coreFix_aluExe_1_regToExeQ$first[395], - basicExec___d11914[257:194], - basicExec___d11914[129:0], + basicExec___d11911[257:194], + basicExec___d11911[129:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15364,14 +15354,14 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h614583, - x__h614584, + x__h614524, + x__h614525, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, coreFix_aluExe_1_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15407,12 +15397,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h664143 == 1'd1 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021) ? + (k__h664083 == 1'd1 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -15422,13 +15412,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15501,7 +15491,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15580,7 +15570,7 @@ module mkCore(CLK, { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15634,7 +15624,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15722,7 +15712,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15772,7 +15762,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15821,7 +15811,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15865,7 +15855,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15907,19 +15897,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h601247 : - a__h600825 ; + _theResult___fst__h601214 : + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h600826 == 64'd0, - a__h600825, + { b__h600793 == 64'd0, + a__h600792, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h601261, - a__h600825[63], + x__h601228, + a__h600792[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h601248 : - b__h600826 ; + _theResult___snd__h601215 : + b__h600793 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -15940,7 +15930,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15980,20 +15970,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h600825 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h600826 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h600792 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h600825 ; + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h600826 ; + b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h600825 ; + a__h600792 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h600826 ; + b__h600793 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16022,12 +16012,12 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h479547, - x__h479548, - x__h479549, + x__h479514, + x__h479515, + x__h479516, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16065,18 +16055,18 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033) ? - { IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029) ? + { IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, + { IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16149,7 +16139,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16175,9 +16165,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167) ; + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -16230,8 +16220,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h285158, - x__h285170, + { x__h285126, + x__h285138, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -16242,13 +16232,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h287024, + x__h286992, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283725 ; + x__h283692 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16885,16 +16875,16 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h181168[2:0], - vaddr__h181168, + coreFix_memExe_lsq$getOrigBE << vaddr__h181135[2:0], + vaddr__h181135, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h181168[2:0] != 3'd0 : + vaddr__h181135[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h181168[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181168[0]), + vaddr__h181135[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181135[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16921,14 +16911,15 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h715865, - prv__h715865 != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; - assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign coreFix_memExe_dTlb$EN_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_procReq = CAN_FIRE_RL_coreFix_memExe_doExeMem ; assign coreFix_memExe_dTlb$EN_deqProcResp = @@ -16957,7 +16948,7 @@ module mkCore(CLK, coreFix_memExe_rsMem$dispatchData[71:66], coreFix_memExe_rsMem$dispatchData[20:9] } ; assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17030,44 +17021,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ? specTagManager$currentSpecBits : - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ? specTagManager$currentSpecBits : - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17103,7 +17094,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$setAtCommit_1_put = rob$deqPort_1_deq_data[24:19] ; assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17147,7 +17138,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181173 ; + shiftData__h181140 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17247,11 +17238,11 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181082, - x__h181083, + x__h181049, + x__h181050, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17499,9 +17490,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055, + IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17509,10 +17500,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184, + IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h678634, + renaming_spec_bits__h678574, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17585,7 +17576,7 @@ module mkCore(CLK, end assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17740,7 +17731,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -17754,7 +17745,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -17772,7 +17763,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -17783,7 +17774,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17802,8 +17793,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -17811,9 +17802,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -17950,18 +17941,16 @@ module mkCore(CLK, l2Tlb$toChildren_rsToC_first[80:0] ; assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ; assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; - always@(MUX_csrf_prv_reg$write_1__SEL_1 or + always@(MUX_csrf_prv_reg$write_1__SEL_2 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or @@ -17975,7 +17964,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_6) begin case (1'b1) // synopsys parallel_case - MUX_csrf_prv_reg$write_1__SEL_1: + MUX_csrf_prv_reg$write_1__SEL_2: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; @@ -18024,8 +18013,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18033,12 +18022,15 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 ; - assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ; + assign fetchStage$EN_iTlbIfc_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ; assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ; assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ; @@ -18072,14 +18064,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18104,9 +18096,17 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 : MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ; assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ; - assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ; - assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ; - assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_2 ; + assign l2Tlb$updateVMInfo_vmD = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign l2Tlb$updateVMInfo_vmI = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; + assign l2Tlb$EN_updateVMInfo = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign l2Tlb$EN_toChildren_rqFromC_put = WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ; assign l2Tlb$EN_toChildren_rsToC_deq = @@ -18385,11 +18385,11 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h678634 ; + renaming_spec_bits__h678574 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -18415,8 +18415,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -18639,7 +18639,7 @@ module mkCore(CLK, { fetchStage$pipelines_1_first[387:324], fetchStage$pipelines_1_first[127:96], fetchStage$pipelines_1_first[199:195], - fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -18651,11 +18651,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215 || - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225, + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 || + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221, 7'd32, - renaming_spec_bits__h678634 } ; + renaming_spec_bits__h678574 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18798,7 +18798,7 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[102:91] ; assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ; assign rob$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18844,8 +18844,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -18970,8 +18970,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19085,8 +19085,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19123,7 +19123,7 @@ module mkCore(CLK, // submodule specTagManager assign specTagManager$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ; assign specTagManager$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -19148,9 +19148,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202) ; + (fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19173,7 +19173,7 @@ module mkCore(CLK, // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { x__h712792, + { x__h712697, rob$deqPort_1_deq_data[282:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296, 6'd10, @@ -19200,15 +19200,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190796), + .amoExec_current_data(curData__h190763), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h192334)); + .amoExec(n__h192301)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h75940 }), - .amoExec_in_data({ 32'd0, x__h76055 }), + msip__h75907 }), + .amoExec_in_data({ 32'd0, x__h76022 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -19222,7 +19222,7 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), - .basicExec(basicExec___d11914)); + .basicExec(basicExec___d11911)); module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, { coreFix_aluExe_0_regToExeQ$first[395], @@ -19234,13 +19234,13 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12560)); + .basicExec(basicExec___d12557)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830, + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826, { { fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 }, + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 }, fetchStage$pipelines_0_first[160], - x_data_imm__h671111 } }), + x_data_imm__h671051 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19249,12 +19249,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h651649, - r1__read_BITS_13_TO_12___h651834 != + .checkForException_csrState({ x_decodeInfo_frm__h651589, + r1__read_BITS_13_TO_12___h651774 != 2'd0, - { prv__h715821, + { prv__h715726, csrf_tvm_reg, - { r1__read_BIT_20___h652494, + { r1__read_BIT_20___h652434, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19265,12 +19265,12 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d12946)); + .checkForException(checkForException___d12942)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514, - { fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598, + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510, + { fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594, fetchStage$pipelines_1_first[160], - x_data_imm__h686042 } }), + x_data_imm__h685982 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19279,12 +19279,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h651649, - r1__read_BITS_13_TO_12___h651834 != + .checkForException_csrState({ x_decodeInfo_frm__h651589, + r1__read_BITS_13_TO_12___h651774 != 2'd0, - { prv__h715821, + { prv__h715726, csrf_tvm_reg, - { r1__read_BIT_20___h652494, + { r1__read_BIT_20___h652434, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19295,1200 +19295,1200 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13619)); + .checkForException(checkForException___d13615)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h479638), - .execFpuSimple_rVal2(rVal2__h479639), + .execFpuSimple_rVal1(rVal1__h479605), + .execFpuSimple_rVal2(rVal2__h479606), .execFpuSimple(execFpuSimple___d11053)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h352136 : - _theResult____h343962 ; + _theResult___snd__h352103 : + _theResult____h343929 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397833 : - _theResult____h389661 ; + _theResult___snd__h397800 : + _theResult____h389628 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h443528 : - _theResult____h435356 ; + _theResult___snd__h443495 : + _theResult____h435323 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 ? - _theResult___snd__h509045 : - _theResult____h500746 ; + _theResult___snd__h509012 : + _theResult____h500713 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609 ? - _theResult___snd__h587202 : - _theResult____h578903 ; + _theResult___snd__h587169 : + _theResult____h578870 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 ? - _theResult___snd__h547898 : - _theResult____h539599 ; + _theResult___snd__h547865 : + _theResult____h539566 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h461294 : - _theResult____h452993 ; + _theResult___snd__h461261 : + _theResult____h452960 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369902 : - _theResult____h361601 ; + _theResult___snd__h369869 : + _theResult____h361568 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h415599 : - _theResult____h407298 ; + _theResult___snd__h415566 : + _theResult____h407265 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 ? - _theResult___snd__h499394 : + _theResult___snd__h499361 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944 ? - _theResult___snd__h499394 : - _theResult___snd__h517799 ; + _theResult___snd__h499361 : + _theResult___snd__h517766 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312 ? - _theResult___snd__h577551 : + _theResult___snd__h577518 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659 ? - _theResult___snd__h577551 : - _theResult___snd__h595956 ; + _theResult___snd__h577518 : + _theResult___snd__h595923 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 ? - _theResult___snd__h538247 : + _theResult___snd__h538214 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429 ? - _theResult___snd__h538247 : - _theResult___snd__h556652 ; + _theResult___snd__h538214 : + _theResult___snd__h556619 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h452110 : + _theResult___snd__h452077 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h452110 : - _theResult___snd__h469900 ; + _theResult___snd__h452077 : + _theResult___snd__h469867 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360718 : + _theResult___snd__h360685 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360718 : - _theResult___snd__h378508 ; + _theResult___snd__h360685 : + _theResult___snd__h378475 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h406415 : + _theResult___snd__h406382 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h406415 : - _theResult___snd__h424205 ; + _theResult___snd__h406382 : + _theResult___snd__h424172 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h352073 == 8'd255) ? + ((_theResult___fst_exp__h352040 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360729 == 8'd255) ? + ((_theResult___fst_exp__h360696 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h352073 == 8'd255) ? + ((_theResult___fst_exp__h352040 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360729 == 8'd255) ? + ((_theResult___fst_exp__h360696 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397770 == 8'd255) ? + ((_theResult___fst_exp__h397737 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h406426 == 8'd255) ? + ((_theResult___fst_exp__h406393 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397770 == 8'd255) ? + ((_theResult___fst_exp__h397737 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h406426 == 8'd255) ? + ((_theResult___fst_exp__h406393 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h443465 == 8'd255) ? + ((_theResult___fst_exp__h443432 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h452121 == 8'd255) ? + ((_theResult___fst_exp__h452088 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h443465 == 8'd255) ? + ((_theResult___fst_exp__h443432 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h452121 == 8'd255) ? + ((_theResult___fst_exp__h452088 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343962[56] ? + (_theResult____h343929[56] ? 6'd0 : - (_theResult____h343962[55] ? + (_theResult____h343929[55] ? 6'd1 : - (_theResult____h343962[54] ? + (_theResult____h343929[54] ? 6'd2 : - (_theResult____h343962[53] ? + (_theResult____h343929[53] ? 6'd3 : - (_theResult____h343962[52] ? + (_theResult____h343929[52] ? 6'd4 : - (_theResult____h343962[51] ? + (_theResult____h343929[51] ? 6'd5 : - (_theResult____h343962[50] ? + (_theResult____h343929[50] ? 6'd6 : - (_theResult____h343962[49] ? + (_theResult____h343929[49] ? 6'd7 : - (_theResult____h343962[48] ? + (_theResult____h343929[48] ? 6'd8 : - (_theResult____h343962[47] ? + (_theResult____h343929[47] ? 6'd9 : - (_theResult____h343962[46] ? + (_theResult____h343929[46] ? 6'd10 : - (_theResult____h343962[45] ? + (_theResult____h343929[45] ? 6'd11 : - (_theResult____h343962[44] ? + (_theResult____h343929[44] ? 6'd12 : - (_theResult____h343962[43] ? + (_theResult____h343929[43] ? 6'd13 : - (_theResult____h343962[42] ? + (_theResult____h343929[42] ? 6'd14 : - (_theResult____h343962[41] ? + (_theResult____h343929[41] ? 6'd15 : - (_theResult____h343962[40] ? + (_theResult____h343929[40] ? 6'd16 : - (_theResult____h343962[39] ? + (_theResult____h343929[39] ? 6'd17 : - (_theResult____h343962[38] ? + (_theResult____h343929[38] ? 6'd18 : - (_theResult____h343962[37] ? + (_theResult____h343929[37] ? 6'd19 : - (_theResult____h343962[36] ? + (_theResult____h343929[36] ? 6'd20 : - (_theResult____h343962[35] ? + (_theResult____h343929[35] ? 6'd21 : - (_theResult____h343962[34] ? + (_theResult____h343929[34] ? 6'd22 : - (_theResult____h343962[33] ? + (_theResult____h343929[33] ? 6'd23 : - (_theResult____h343962[32] ? + (_theResult____h343929[32] ? 6'd24 : - (_theResult____h343962[31] ? + (_theResult____h343929[31] ? 6'd25 : - (_theResult____h343962[30] ? + (_theResult____h343929[30] ? 6'd26 : - (_theResult____h343962[29] ? + (_theResult____h343929[29] ? 6'd27 : - (_theResult____h343962[28] ? + (_theResult____h343929[28] ? 6'd28 : - (_theResult____h343962[27] ? + (_theResult____h343929[27] ? 6'd29 : - (_theResult____h343962[26] ? + (_theResult____h343929[26] ? 6'd30 : - (_theResult____h343962[25] ? + (_theResult____h343929[25] ? 6'd31 : - (_theResult____h343962[24] ? + (_theResult____h343929[24] ? 6'd32 : - (_theResult____h343962[23] ? + (_theResult____h343929[23] ? 6'd33 : - (_theResult____h343962[22] ? + (_theResult____h343929[22] ? 6'd34 : - (_theResult____h343962[21] ? + (_theResult____h343929[21] ? 6'd35 : - (_theResult____h343962[20] ? + (_theResult____h343929[20] ? 6'd36 : - (_theResult____h343962[19] ? + (_theResult____h343929[19] ? 6'd37 : - (_theResult____h343962[18] ? + (_theResult____h343929[18] ? 6'd38 : - (_theResult____h343962[17] ? + (_theResult____h343929[17] ? 6'd39 : - (_theResult____h343962[16] ? + (_theResult____h343929[16] ? 6'd40 : - (_theResult____h343962[15] ? + (_theResult____h343929[15] ? 6'd41 : - (_theResult____h343962[14] ? + (_theResult____h343929[14] ? 6'd42 : - (_theResult____h343962[13] ? + (_theResult____h343929[13] ? 6'd43 : - (_theResult____h343962[12] ? + (_theResult____h343929[12] ? 6'd44 : - (_theResult____h343962[11] ? + (_theResult____h343929[11] ? 6'd45 : - (_theResult____h343962[10] ? + (_theResult____h343929[10] ? 6'd46 : - (_theResult____h343962[9] ? + (_theResult____h343929[9] ? 6'd47 : - (_theResult____h343962[8] ? + (_theResult____h343929[8] ? 6'd48 : - (_theResult____h343962[7] ? + (_theResult____h343929[7] ? 6'd49 : - (_theResult____h343962[6] ? + (_theResult____h343929[6] ? 6'd50 : - (_theResult____h343962[5] ? + (_theResult____h343929[5] ? 6'd51 : - (_theResult____h343962[4] ? + (_theResult____h343929[4] ? 6'd52 : - (_theResult____h343962[3] ? + (_theResult____h343929[3] ? 6'd53 : - (_theResult____h343962[2] ? + (_theResult____h343929[2] ? 6'd54 : - (_theResult____h343962[1] ? + (_theResult____h343929[1] ? 6'd55 : - (_theResult____h343962[0] ? + (_theResult____h343929[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h389661[56] ? + (_theResult____h389628[56] ? 6'd0 : - (_theResult____h389661[55] ? + (_theResult____h389628[55] ? 6'd1 : - (_theResult____h389661[54] ? + (_theResult____h389628[54] ? 6'd2 : - (_theResult____h389661[53] ? + (_theResult____h389628[53] ? 6'd3 : - (_theResult____h389661[52] ? + (_theResult____h389628[52] ? 6'd4 : - (_theResult____h389661[51] ? + (_theResult____h389628[51] ? 6'd5 : - (_theResult____h389661[50] ? + (_theResult____h389628[50] ? 6'd6 : - (_theResult____h389661[49] ? + (_theResult____h389628[49] ? 6'd7 : - (_theResult____h389661[48] ? + (_theResult____h389628[48] ? 6'd8 : - (_theResult____h389661[47] ? + (_theResult____h389628[47] ? 6'd9 : - (_theResult____h389661[46] ? + (_theResult____h389628[46] ? 6'd10 : - (_theResult____h389661[45] ? + (_theResult____h389628[45] ? 6'd11 : - (_theResult____h389661[44] ? + (_theResult____h389628[44] ? 6'd12 : - (_theResult____h389661[43] ? + (_theResult____h389628[43] ? 6'd13 : - (_theResult____h389661[42] ? + (_theResult____h389628[42] ? 6'd14 : - (_theResult____h389661[41] ? + (_theResult____h389628[41] ? 6'd15 : - (_theResult____h389661[40] ? + (_theResult____h389628[40] ? 6'd16 : - (_theResult____h389661[39] ? + (_theResult____h389628[39] ? 6'd17 : - (_theResult____h389661[38] ? + (_theResult____h389628[38] ? 6'd18 : - (_theResult____h389661[37] ? + (_theResult____h389628[37] ? 6'd19 : - (_theResult____h389661[36] ? + (_theResult____h389628[36] ? 6'd20 : - (_theResult____h389661[35] ? + (_theResult____h389628[35] ? 6'd21 : - (_theResult____h389661[34] ? + (_theResult____h389628[34] ? 6'd22 : - (_theResult____h389661[33] ? + (_theResult____h389628[33] ? 6'd23 : - (_theResult____h389661[32] ? + (_theResult____h389628[32] ? 6'd24 : - (_theResult____h389661[31] ? + (_theResult____h389628[31] ? 6'd25 : - (_theResult____h389661[30] ? + (_theResult____h389628[30] ? 6'd26 : - (_theResult____h389661[29] ? + (_theResult____h389628[29] ? 6'd27 : - (_theResult____h389661[28] ? + (_theResult____h389628[28] ? 6'd28 : - (_theResult____h389661[27] ? + (_theResult____h389628[27] ? 6'd29 : - (_theResult____h389661[26] ? + (_theResult____h389628[26] ? 6'd30 : - (_theResult____h389661[25] ? + (_theResult____h389628[25] ? 6'd31 : - (_theResult____h389661[24] ? + (_theResult____h389628[24] ? 6'd32 : - (_theResult____h389661[23] ? + (_theResult____h389628[23] ? 6'd33 : - (_theResult____h389661[22] ? + (_theResult____h389628[22] ? 6'd34 : - (_theResult____h389661[21] ? + (_theResult____h389628[21] ? 6'd35 : - (_theResult____h389661[20] ? + (_theResult____h389628[20] ? 6'd36 : - (_theResult____h389661[19] ? + (_theResult____h389628[19] ? 6'd37 : - (_theResult____h389661[18] ? + (_theResult____h389628[18] ? 6'd38 : - (_theResult____h389661[17] ? + (_theResult____h389628[17] ? 6'd39 : - (_theResult____h389661[16] ? + (_theResult____h389628[16] ? 6'd40 : - (_theResult____h389661[15] ? + (_theResult____h389628[15] ? 6'd41 : - (_theResult____h389661[14] ? + (_theResult____h389628[14] ? 6'd42 : - (_theResult____h389661[13] ? + (_theResult____h389628[13] ? 6'd43 : - (_theResult____h389661[12] ? + (_theResult____h389628[12] ? 6'd44 : - (_theResult____h389661[11] ? + (_theResult____h389628[11] ? 6'd45 : - (_theResult____h389661[10] ? + (_theResult____h389628[10] ? 6'd46 : - (_theResult____h389661[9] ? + (_theResult____h389628[9] ? 6'd47 : - (_theResult____h389661[8] ? + (_theResult____h389628[8] ? 6'd48 : - (_theResult____h389661[7] ? + (_theResult____h389628[7] ? 6'd49 : - (_theResult____h389661[6] ? + (_theResult____h389628[6] ? 6'd50 : - (_theResult____h389661[5] ? + (_theResult____h389628[5] ? 6'd51 : - (_theResult____h389661[4] ? + (_theResult____h389628[4] ? 6'd52 : - (_theResult____h389661[3] ? + (_theResult____h389628[3] ? 6'd53 : - (_theResult____h389661[2] ? + (_theResult____h389628[2] ? 6'd54 : - (_theResult____h389661[1] ? + (_theResult____h389628[1] ? 6'd55 : - (_theResult____h389661[0] ? + (_theResult____h389628[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h435356[56] ? + (_theResult____h435323[56] ? 6'd0 : - (_theResult____h435356[55] ? + (_theResult____h435323[55] ? 6'd1 : - (_theResult____h435356[54] ? + (_theResult____h435323[54] ? 6'd2 : - (_theResult____h435356[53] ? + (_theResult____h435323[53] ? 6'd3 : - (_theResult____h435356[52] ? + (_theResult____h435323[52] ? 6'd4 : - (_theResult____h435356[51] ? + (_theResult____h435323[51] ? 6'd5 : - (_theResult____h435356[50] ? + (_theResult____h435323[50] ? 6'd6 : - (_theResult____h435356[49] ? + (_theResult____h435323[49] ? 6'd7 : - (_theResult____h435356[48] ? + (_theResult____h435323[48] ? 6'd8 : - (_theResult____h435356[47] ? + (_theResult____h435323[47] ? 6'd9 : - (_theResult____h435356[46] ? + (_theResult____h435323[46] ? 6'd10 : - (_theResult____h435356[45] ? + (_theResult____h435323[45] ? 6'd11 : - (_theResult____h435356[44] ? + (_theResult____h435323[44] ? 6'd12 : - (_theResult____h435356[43] ? + (_theResult____h435323[43] ? 6'd13 : - (_theResult____h435356[42] ? + (_theResult____h435323[42] ? 6'd14 : - (_theResult____h435356[41] ? + (_theResult____h435323[41] ? 6'd15 : - (_theResult____h435356[40] ? + (_theResult____h435323[40] ? 6'd16 : - (_theResult____h435356[39] ? + (_theResult____h435323[39] ? 6'd17 : - (_theResult____h435356[38] ? + (_theResult____h435323[38] ? 6'd18 : - (_theResult____h435356[37] ? + (_theResult____h435323[37] ? 6'd19 : - (_theResult____h435356[36] ? + (_theResult____h435323[36] ? 6'd20 : - (_theResult____h435356[35] ? + (_theResult____h435323[35] ? 6'd21 : - (_theResult____h435356[34] ? + (_theResult____h435323[34] ? 6'd22 : - (_theResult____h435356[33] ? + (_theResult____h435323[33] ? 6'd23 : - (_theResult____h435356[32] ? + (_theResult____h435323[32] ? 6'd24 : - (_theResult____h435356[31] ? + (_theResult____h435323[31] ? 6'd25 : - (_theResult____h435356[30] ? + (_theResult____h435323[30] ? 6'd26 : - (_theResult____h435356[29] ? + (_theResult____h435323[29] ? 6'd27 : - (_theResult____h435356[28] ? + (_theResult____h435323[28] ? 6'd28 : - (_theResult____h435356[27] ? + (_theResult____h435323[27] ? 6'd29 : - (_theResult____h435356[26] ? + (_theResult____h435323[26] ? 6'd30 : - (_theResult____h435356[25] ? + (_theResult____h435323[25] ? 6'd31 : - (_theResult____h435356[24] ? + (_theResult____h435323[24] ? 6'd32 : - (_theResult____h435356[23] ? + (_theResult____h435323[23] ? 6'd33 : - (_theResult____h435356[22] ? + (_theResult____h435323[22] ? 6'd34 : - (_theResult____h435356[21] ? + (_theResult____h435323[21] ? 6'd35 : - (_theResult____h435356[20] ? + (_theResult____h435323[20] ? 6'd36 : - (_theResult____h435356[19] ? + (_theResult____h435323[19] ? 6'd37 : - (_theResult____h435356[18] ? + (_theResult____h435323[18] ? 6'd38 : - (_theResult____h435356[17] ? + (_theResult____h435323[17] ? 6'd39 : - (_theResult____h435356[16] ? + (_theResult____h435323[16] ? 6'd40 : - (_theResult____h435356[15] ? + (_theResult____h435323[15] ? 6'd41 : - (_theResult____h435356[14] ? + (_theResult____h435323[14] ? 6'd42 : - (_theResult____h435356[13] ? + (_theResult____h435323[13] ? 6'd43 : - (_theResult____h435356[12] ? + (_theResult____h435323[12] ? 6'd44 : - (_theResult____h435356[11] ? + (_theResult____h435323[11] ? 6'd45 : - (_theResult____h435356[10] ? + (_theResult____h435323[10] ? 6'd46 : - (_theResult____h435356[9] ? + (_theResult____h435323[9] ? 6'd47 : - (_theResult____h435356[8] ? + (_theResult____h435323[8] ? 6'd48 : - (_theResult____h435356[7] ? + (_theResult____h435323[7] ? 6'd49 : - (_theResult____h435356[6] ? + (_theResult____h435323[6] ? 6'd50 : - (_theResult____h435356[5] ? + (_theResult____h435323[5] ? 6'd51 : - (_theResult____h435356[4] ? + (_theResult____h435323[4] ? 6'd52 : - (_theResult____h435356[3] ? + (_theResult____h435323[3] ? 6'd53 : - (_theResult____h435356[2] ? + (_theResult____h435323[2] ? 6'd54 : - (_theResult____h435356[1] ? + (_theResult____h435323[1] ? 6'd55 : - (_theResult____h435356[0] ? + (_theResult____h435323[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 = - (_theResult____h539599[56] ? + (_theResult____h539566[56] ? 6'd0 : - (_theResult____h539599[55] ? + (_theResult____h539566[55] ? 6'd1 : - (_theResult____h539599[54] ? + (_theResult____h539566[54] ? 6'd2 : - (_theResult____h539599[53] ? + (_theResult____h539566[53] ? 6'd3 : - (_theResult____h539599[52] ? + (_theResult____h539566[52] ? 6'd4 : - (_theResult____h539599[51] ? + (_theResult____h539566[51] ? 6'd5 : - (_theResult____h539599[50] ? + (_theResult____h539566[50] ? 6'd6 : - (_theResult____h539599[49] ? + (_theResult____h539566[49] ? 6'd7 : - (_theResult____h539599[48] ? + (_theResult____h539566[48] ? 6'd8 : - (_theResult____h539599[47] ? + (_theResult____h539566[47] ? 6'd9 : - (_theResult____h539599[46] ? + (_theResult____h539566[46] ? 6'd10 : - (_theResult____h539599[45] ? + (_theResult____h539566[45] ? 6'd11 : - (_theResult____h539599[44] ? + (_theResult____h539566[44] ? 6'd12 : - (_theResult____h539599[43] ? + (_theResult____h539566[43] ? 6'd13 : - (_theResult____h539599[42] ? + (_theResult____h539566[42] ? 6'd14 : - (_theResult____h539599[41] ? + (_theResult____h539566[41] ? 6'd15 : - (_theResult____h539599[40] ? + (_theResult____h539566[40] ? 6'd16 : - (_theResult____h539599[39] ? + (_theResult____h539566[39] ? 6'd17 : - (_theResult____h539599[38] ? + (_theResult____h539566[38] ? 6'd18 : - (_theResult____h539599[37] ? + (_theResult____h539566[37] ? 6'd19 : - (_theResult____h539599[36] ? + (_theResult____h539566[36] ? 6'd20 : - (_theResult____h539599[35] ? + (_theResult____h539566[35] ? 6'd21 : - (_theResult____h539599[34] ? + (_theResult____h539566[34] ? 6'd22 : - (_theResult____h539599[33] ? + (_theResult____h539566[33] ? 6'd23 : - (_theResult____h539599[32] ? + (_theResult____h539566[32] ? 6'd24 : - (_theResult____h539599[31] ? + (_theResult____h539566[31] ? 6'd25 : - (_theResult____h539599[30] ? + (_theResult____h539566[30] ? 6'd26 : - (_theResult____h539599[29] ? + (_theResult____h539566[29] ? 6'd27 : - (_theResult____h539599[28] ? + (_theResult____h539566[28] ? 6'd28 : - (_theResult____h539599[27] ? + (_theResult____h539566[27] ? 6'd29 : - (_theResult____h539599[26] ? + (_theResult____h539566[26] ? 6'd30 : - (_theResult____h539599[25] ? + (_theResult____h539566[25] ? 6'd31 : - (_theResult____h539599[24] ? + (_theResult____h539566[24] ? 6'd32 : - (_theResult____h539599[23] ? + (_theResult____h539566[23] ? 6'd33 : - (_theResult____h539599[22] ? + (_theResult____h539566[22] ? 6'd34 : - (_theResult____h539599[21] ? + (_theResult____h539566[21] ? 6'd35 : - (_theResult____h539599[20] ? + (_theResult____h539566[20] ? 6'd36 : - (_theResult____h539599[19] ? + (_theResult____h539566[19] ? 6'd37 : - (_theResult____h539599[18] ? + (_theResult____h539566[18] ? 6'd38 : - (_theResult____h539599[17] ? + (_theResult____h539566[17] ? 6'd39 : - (_theResult____h539599[16] ? + (_theResult____h539566[16] ? 6'd40 : - (_theResult____h539599[15] ? + (_theResult____h539566[15] ? 6'd41 : - (_theResult____h539599[14] ? + (_theResult____h539566[14] ? 6'd42 : - (_theResult____h539599[13] ? + (_theResult____h539566[13] ? 6'd43 : - (_theResult____h539599[12] ? + (_theResult____h539566[12] ? 6'd44 : - (_theResult____h539599[11] ? + (_theResult____h539566[11] ? 6'd45 : - (_theResult____h539599[10] ? + (_theResult____h539566[10] ? 6'd46 : - (_theResult____h539599[9] ? + (_theResult____h539566[9] ? 6'd47 : - (_theResult____h539599[8] ? + (_theResult____h539566[8] ? 6'd48 : - (_theResult____h539599[7] ? + (_theResult____h539566[7] ? 6'd49 : - (_theResult____h539599[6] ? + (_theResult____h539566[6] ? 6'd50 : - (_theResult____h539599[5] ? + (_theResult____h539566[5] ? 6'd51 : - (_theResult____h539599[4] ? + (_theResult____h539566[4] ? 6'd52 : - (_theResult____h539599[3] ? + (_theResult____h539566[3] ? 6'd53 : - (_theResult____h539599[2] ? + (_theResult____h539566[2] ? 6'd54 : - (_theResult____h539599[1] ? + (_theResult____h539566[1] ? 6'd55 : - (_theResult____h539599[0] ? + (_theResult____h539566[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 = - (_theResult____h500746[56] ? + (_theResult____h500713[56] ? 6'd0 : - (_theResult____h500746[55] ? + (_theResult____h500713[55] ? 6'd1 : - (_theResult____h500746[54] ? + (_theResult____h500713[54] ? 6'd2 : - (_theResult____h500746[53] ? + (_theResult____h500713[53] ? 6'd3 : - (_theResult____h500746[52] ? + (_theResult____h500713[52] ? 6'd4 : - (_theResult____h500746[51] ? + (_theResult____h500713[51] ? 6'd5 : - (_theResult____h500746[50] ? + (_theResult____h500713[50] ? 6'd6 : - (_theResult____h500746[49] ? + (_theResult____h500713[49] ? 6'd7 : - (_theResult____h500746[48] ? + (_theResult____h500713[48] ? 6'd8 : - (_theResult____h500746[47] ? + (_theResult____h500713[47] ? 6'd9 : - (_theResult____h500746[46] ? + (_theResult____h500713[46] ? 6'd10 : - (_theResult____h500746[45] ? + (_theResult____h500713[45] ? 6'd11 : - (_theResult____h500746[44] ? + (_theResult____h500713[44] ? 6'd12 : - (_theResult____h500746[43] ? + (_theResult____h500713[43] ? 6'd13 : - (_theResult____h500746[42] ? + (_theResult____h500713[42] ? 6'd14 : - (_theResult____h500746[41] ? + (_theResult____h500713[41] ? 6'd15 : - (_theResult____h500746[40] ? + (_theResult____h500713[40] ? 6'd16 : - (_theResult____h500746[39] ? + (_theResult____h500713[39] ? 6'd17 : - (_theResult____h500746[38] ? + (_theResult____h500713[38] ? 6'd18 : - (_theResult____h500746[37] ? + (_theResult____h500713[37] ? 6'd19 : - (_theResult____h500746[36] ? + (_theResult____h500713[36] ? 6'd20 : - (_theResult____h500746[35] ? + (_theResult____h500713[35] ? 6'd21 : - (_theResult____h500746[34] ? + (_theResult____h500713[34] ? 6'd22 : - (_theResult____h500746[33] ? + (_theResult____h500713[33] ? 6'd23 : - (_theResult____h500746[32] ? + (_theResult____h500713[32] ? 6'd24 : - (_theResult____h500746[31] ? + (_theResult____h500713[31] ? 6'd25 : - (_theResult____h500746[30] ? + (_theResult____h500713[30] ? 6'd26 : - (_theResult____h500746[29] ? + (_theResult____h500713[29] ? 6'd27 : - (_theResult____h500746[28] ? + (_theResult____h500713[28] ? 6'd28 : - (_theResult____h500746[27] ? + (_theResult____h500713[27] ? 6'd29 : - (_theResult____h500746[26] ? + (_theResult____h500713[26] ? 6'd30 : - (_theResult____h500746[25] ? + (_theResult____h500713[25] ? 6'd31 : - (_theResult____h500746[24] ? + (_theResult____h500713[24] ? 6'd32 : - (_theResult____h500746[23] ? + (_theResult____h500713[23] ? 6'd33 : - (_theResult____h500746[22] ? + (_theResult____h500713[22] ? 6'd34 : - (_theResult____h500746[21] ? + (_theResult____h500713[21] ? 6'd35 : - (_theResult____h500746[20] ? + (_theResult____h500713[20] ? 6'd36 : - (_theResult____h500746[19] ? + (_theResult____h500713[19] ? 6'd37 : - (_theResult____h500746[18] ? + (_theResult____h500713[18] ? 6'd38 : - (_theResult____h500746[17] ? + (_theResult____h500713[17] ? 6'd39 : - (_theResult____h500746[16] ? + (_theResult____h500713[16] ? 6'd40 : - (_theResult____h500746[15] ? + (_theResult____h500713[15] ? 6'd41 : - (_theResult____h500746[14] ? + (_theResult____h500713[14] ? 6'd42 : - (_theResult____h500746[13] ? + (_theResult____h500713[13] ? 6'd43 : - (_theResult____h500746[12] ? + (_theResult____h500713[12] ? 6'd44 : - (_theResult____h500746[11] ? + (_theResult____h500713[11] ? 6'd45 : - (_theResult____h500746[10] ? + (_theResult____h500713[10] ? 6'd46 : - (_theResult____h500746[9] ? + (_theResult____h500713[9] ? 6'd47 : - (_theResult____h500746[8] ? + (_theResult____h500713[8] ? 6'd48 : - (_theResult____h500746[7] ? + (_theResult____h500713[7] ? 6'd49 : - (_theResult____h500746[6] ? + (_theResult____h500713[6] ? 6'd50 : - (_theResult____h500746[5] ? + (_theResult____h500713[5] ? 6'd51 : - (_theResult____h500746[4] ? + (_theResult____h500713[4] ? 6'd52 : - (_theResult____h500746[3] ? + (_theResult____h500713[3] ? 6'd53 : - (_theResult____h500746[2] ? + (_theResult____h500713[2] ? 6'd54 : - (_theResult____h500746[1] ? + (_theResult____h500713[1] ? 6'd55 : - (_theResult____h500746[0] ? + (_theResult____h500713[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 = - (_theResult____h578903[56] ? + (_theResult____h578870[56] ? 6'd0 : - (_theResult____h578903[55] ? + (_theResult____h578870[55] ? 6'd1 : - (_theResult____h578903[54] ? + (_theResult____h578870[54] ? 6'd2 : - (_theResult____h578903[53] ? + (_theResult____h578870[53] ? 6'd3 : - (_theResult____h578903[52] ? + (_theResult____h578870[52] ? 6'd4 : - (_theResult____h578903[51] ? + (_theResult____h578870[51] ? 6'd5 : - (_theResult____h578903[50] ? + (_theResult____h578870[50] ? 6'd6 : - (_theResult____h578903[49] ? + (_theResult____h578870[49] ? 6'd7 : - (_theResult____h578903[48] ? + (_theResult____h578870[48] ? 6'd8 : - (_theResult____h578903[47] ? + (_theResult____h578870[47] ? 6'd9 : - (_theResult____h578903[46] ? + (_theResult____h578870[46] ? 6'd10 : - (_theResult____h578903[45] ? + (_theResult____h578870[45] ? 6'd11 : - (_theResult____h578903[44] ? + (_theResult____h578870[44] ? 6'd12 : - (_theResult____h578903[43] ? + (_theResult____h578870[43] ? 6'd13 : - (_theResult____h578903[42] ? + (_theResult____h578870[42] ? 6'd14 : - (_theResult____h578903[41] ? + (_theResult____h578870[41] ? 6'd15 : - (_theResult____h578903[40] ? + (_theResult____h578870[40] ? 6'd16 : - (_theResult____h578903[39] ? + (_theResult____h578870[39] ? 6'd17 : - (_theResult____h578903[38] ? + (_theResult____h578870[38] ? 6'd18 : - (_theResult____h578903[37] ? + (_theResult____h578870[37] ? 6'd19 : - (_theResult____h578903[36] ? + (_theResult____h578870[36] ? 6'd20 : - (_theResult____h578903[35] ? + (_theResult____h578870[35] ? 6'd21 : - (_theResult____h578903[34] ? + (_theResult____h578870[34] ? 6'd22 : - (_theResult____h578903[33] ? + (_theResult____h578870[33] ? 6'd23 : - (_theResult____h578903[32] ? + (_theResult____h578870[32] ? 6'd24 : - (_theResult____h578903[31] ? + (_theResult____h578870[31] ? 6'd25 : - (_theResult____h578903[30] ? + (_theResult____h578870[30] ? 6'd26 : - (_theResult____h578903[29] ? + (_theResult____h578870[29] ? 6'd27 : - (_theResult____h578903[28] ? + (_theResult____h578870[28] ? 6'd28 : - (_theResult____h578903[27] ? + (_theResult____h578870[27] ? 6'd29 : - (_theResult____h578903[26] ? + (_theResult____h578870[26] ? 6'd30 : - (_theResult____h578903[25] ? + (_theResult____h578870[25] ? 6'd31 : - (_theResult____h578903[24] ? + (_theResult____h578870[24] ? 6'd32 : - (_theResult____h578903[23] ? + (_theResult____h578870[23] ? 6'd33 : - (_theResult____h578903[22] ? + (_theResult____h578870[22] ? 6'd34 : - (_theResult____h578903[21] ? + (_theResult____h578870[21] ? 6'd35 : - (_theResult____h578903[20] ? + (_theResult____h578870[20] ? 6'd36 : - (_theResult____h578903[19] ? + (_theResult____h578870[19] ? 6'd37 : - (_theResult____h578903[18] ? + (_theResult____h578870[18] ? 6'd38 : - (_theResult____h578903[17] ? + (_theResult____h578870[17] ? 6'd39 : - (_theResult____h578903[16] ? + (_theResult____h578870[16] ? 6'd40 : - (_theResult____h578903[15] ? + (_theResult____h578870[15] ? 6'd41 : - (_theResult____h578903[14] ? + (_theResult____h578870[14] ? 6'd42 : - (_theResult____h578903[13] ? + (_theResult____h578870[13] ? 6'd43 : - (_theResult____h578903[12] ? + (_theResult____h578870[12] ? 6'd44 : - (_theResult____h578903[11] ? + (_theResult____h578870[11] ? 6'd45 : - (_theResult____h578903[10] ? + (_theResult____h578870[10] ? 6'd46 : - (_theResult____h578903[9] ? + (_theResult____h578870[9] ? 6'd47 : - (_theResult____h578903[8] ? + (_theResult____h578870[8] ? 6'd48 : - (_theResult____h578903[7] ? + (_theResult____h578870[7] ? 6'd49 : - (_theResult____h578903[6] ? + (_theResult____h578870[6] ? 6'd50 : - (_theResult____h578903[5] ? + (_theResult____h578870[5] ? 6'd51 : - (_theResult____h578903[4] ? + (_theResult____h578870[4] ? 6'd52 : - (_theResult____h578903[3] ? + (_theResult____h578870[3] ? 6'd53 : - (_theResult____h578903[2] ? + (_theResult____h578870[2] ? 6'd54 : - (_theResult____h578903[1] ? + (_theResult____h578870[1] ? 6'd55 : - (_theResult____h578903[0] ? + (_theResult____h578870[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h361601[56] ? + (_theResult____h361568[56] ? 6'd0 : - (_theResult____h361601[55] ? + (_theResult____h361568[55] ? 6'd1 : - (_theResult____h361601[54] ? + (_theResult____h361568[54] ? 6'd2 : - (_theResult____h361601[53] ? + (_theResult____h361568[53] ? 6'd3 : - (_theResult____h361601[52] ? + (_theResult____h361568[52] ? 6'd4 : - (_theResult____h361601[51] ? + (_theResult____h361568[51] ? 6'd5 : - (_theResult____h361601[50] ? + (_theResult____h361568[50] ? 6'd6 : - (_theResult____h361601[49] ? + (_theResult____h361568[49] ? 6'd7 : - (_theResult____h361601[48] ? + (_theResult____h361568[48] ? 6'd8 : - (_theResult____h361601[47] ? + (_theResult____h361568[47] ? 6'd9 : - (_theResult____h361601[46] ? + (_theResult____h361568[46] ? 6'd10 : - (_theResult____h361601[45] ? + (_theResult____h361568[45] ? 6'd11 : - (_theResult____h361601[44] ? + (_theResult____h361568[44] ? 6'd12 : - (_theResult____h361601[43] ? + (_theResult____h361568[43] ? 6'd13 : - (_theResult____h361601[42] ? + (_theResult____h361568[42] ? 6'd14 : - (_theResult____h361601[41] ? + (_theResult____h361568[41] ? 6'd15 : - (_theResult____h361601[40] ? + (_theResult____h361568[40] ? 6'd16 : - (_theResult____h361601[39] ? + (_theResult____h361568[39] ? 6'd17 : - (_theResult____h361601[38] ? + (_theResult____h361568[38] ? 6'd18 : - (_theResult____h361601[37] ? + (_theResult____h361568[37] ? 6'd19 : - (_theResult____h361601[36] ? + (_theResult____h361568[36] ? 6'd20 : - (_theResult____h361601[35] ? + (_theResult____h361568[35] ? 6'd21 : - (_theResult____h361601[34] ? + (_theResult____h361568[34] ? 6'd22 : - (_theResult____h361601[33] ? + (_theResult____h361568[33] ? 6'd23 : - (_theResult____h361601[32] ? + (_theResult____h361568[32] ? 6'd24 : - (_theResult____h361601[31] ? + (_theResult____h361568[31] ? 6'd25 : - (_theResult____h361601[30] ? + (_theResult____h361568[30] ? 6'd26 : - (_theResult____h361601[29] ? + (_theResult____h361568[29] ? 6'd27 : - (_theResult____h361601[28] ? + (_theResult____h361568[28] ? 6'd28 : - (_theResult____h361601[27] ? + (_theResult____h361568[27] ? 6'd29 : - (_theResult____h361601[26] ? + (_theResult____h361568[26] ? 6'd30 : - (_theResult____h361601[25] ? + (_theResult____h361568[25] ? 6'd31 : - (_theResult____h361601[24] ? + (_theResult____h361568[24] ? 6'd32 : - (_theResult____h361601[23] ? + (_theResult____h361568[23] ? 6'd33 : - (_theResult____h361601[22] ? + (_theResult____h361568[22] ? 6'd34 : - (_theResult____h361601[21] ? + (_theResult____h361568[21] ? 6'd35 : - (_theResult____h361601[20] ? + (_theResult____h361568[20] ? 6'd36 : - (_theResult____h361601[19] ? + (_theResult____h361568[19] ? 6'd37 : - (_theResult____h361601[18] ? + (_theResult____h361568[18] ? 6'd38 : - (_theResult____h361601[17] ? + (_theResult____h361568[17] ? 6'd39 : - (_theResult____h361601[16] ? + (_theResult____h361568[16] ? 6'd40 : - (_theResult____h361601[15] ? + (_theResult____h361568[15] ? 6'd41 : - (_theResult____h361601[14] ? + (_theResult____h361568[14] ? 6'd42 : - (_theResult____h361601[13] ? + (_theResult____h361568[13] ? 6'd43 : - (_theResult____h361601[12] ? + (_theResult____h361568[12] ? 6'd44 : - (_theResult____h361601[11] ? + (_theResult____h361568[11] ? 6'd45 : - (_theResult____h361601[10] ? + (_theResult____h361568[10] ? 6'd46 : - (_theResult____h361601[9] ? + (_theResult____h361568[9] ? 6'd47 : - (_theResult____h361601[8] ? + (_theResult____h361568[8] ? 6'd48 : - (_theResult____h361601[7] ? + (_theResult____h361568[7] ? 6'd49 : - (_theResult____h361601[6] ? + (_theResult____h361568[6] ? 6'd50 : - (_theResult____h361601[5] ? + (_theResult____h361568[5] ? 6'd51 : - (_theResult____h361601[4] ? + (_theResult____h361568[4] ? 6'd52 : - (_theResult____h361601[3] ? + (_theResult____h361568[3] ? 6'd53 : - (_theResult____h361601[2] ? + (_theResult____h361568[2] ? 6'd54 : - (_theResult____h361601[1] ? + (_theResult____h361568[1] ? 6'd55 : - (_theResult____h361601[0] ? + (_theResult____h361568[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h407298[56] ? + (_theResult____h407265[56] ? 6'd0 : - (_theResult____h407298[55] ? + (_theResult____h407265[55] ? 6'd1 : - (_theResult____h407298[54] ? + (_theResult____h407265[54] ? 6'd2 : - (_theResult____h407298[53] ? + (_theResult____h407265[53] ? 6'd3 : - (_theResult____h407298[52] ? + (_theResult____h407265[52] ? 6'd4 : - (_theResult____h407298[51] ? + (_theResult____h407265[51] ? 6'd5 : - (_theResult____h407298[50] ? + (_theResult____h407265[50] ? 6'd6 : - (_theResult____h407298[49] ? + (_theResult____h407265[49] ? 6'd7 : - (_theResult____h407298[48] ? + (_theResult____h407265[48] ? 6'd8 : - (_theResult____h407298[47] ? + (_theResult____h407265[47] ? 6'd9 : - (_theResult____h407298[46] ? + (_theResult____h407265[46] ? 6'd10 : - (_theResult____h407298[45] ? + (_theResult____h407265[45] ? 6'd11 : - (_theResult____h407298[44] ? + (_theResult____h407265[44] ? 6'd12 : - (_theResult____h407298[43] ? + (_theResult____h407265[43] ? 6'd13 : - (_theResult____h407298[42] ? + (_theResult____h407265[42] ? 6'd14 : - (_theResult____h407298[41] ? + (_theResult____h407265[41] ? 6'd15 : - (_theResult____h407298[40] ? + (_theResult____h407265[40] ? 6'd16 : - (_theResult____h407298[39] ? + (_theResult____h407265[39] ? 6'd17 : - (_theResult____h407298[38] ? + (_theResult____h407265[38] ? 6'd18 : - (_theResult____h407298[37] ? + (_theResult____h407265[37] ? 6'd19 : - (_theResult____h407298[36] ? + (_theResult____h407265[36] ? 6'd20 : - (_theResult____h407298[35] ? + (_theResult____h407265[35] ? 6'd21 : - (_theResult____h407298[34] ? + (_theResult____h407265[34] ? 6'd22 : - (_theResult____h407298[33] ? + (_theResult____h407265[33] ? 6'd23 : - (_theResult____h407298[32] ? + (_theResult____h407265[32] ? 6'd24 : - (_theResult____h407298[31] ? + (_theResult____h407265[31] ? 6'd25 : - (_theResult____h407298[30] ? + (_theResult____h407265[30] ? 6'd26 : - (_theResult____h407298[29] ? + (_theResult____h407265[29] ? 6'd27 : - (_theResult____h407298[28] ? + (_theResult____h407265[28] ? 6'd28 : - (_theResult____h407298[27] ? + (_theResult____h407265[27] ? 6'd29 : - (_theResult____h407298[26] ? + (_theResult____h407265[26] ? 6'd30 : - (_theResult____h407298[25] ? + (_theResult____h407265[25] ? 6'd31 : - (_theResult____h407298[24] ? + (_theResult____h407265[24] ? 6'd32 : - (_theResult____h407298[23] ? + (_theResult____h407265[23] ? 6'd33 : - (_theResult____h407298[22] ? + (_theResult____h407265[22] ? 6'd34 : - (_theResult____h407298[21] ? + (_theResult____h407265[21] ? 6'd35 : - (_theResult____h407298[20] ? + (_theResult____h407265[20] ? 6'd36 : - (_theResult____h407298[19] ? + (_theResult____h407265[19] ? 6'd37 : - (_theResult____h407298[18] ? + (_theResult____h407265[18] ? 6'd38 : - (_theResult____h407298[17] ? + (_theResult____h407265[17] ? 6'd39 : - (_theResult____h407298[16] ? + (_theResult____h407265[16] ? 6'd40 : - (_theResult____h407298[15] ? + (_theResult____h407265[15] ? 6'd41 : - (_theResult____h407298[14] ? + (_theResult____h407265[14] ? 6'd42 : - (_theResult____h407298[13] ? + (_theResult____h407265[13] ? 6'd43 : - (_theResult____h407298[12] ? + (_theResult____h407265[12] ? 6'd44 : - (_theResult____h407298[11] ? + (_theResult____h407265[11] ? 6'd45 : - (_theResult____h407298[10] ? + (_theResult____h407265[10] ? 6'd46 : - (_theResult____h407298[9] ? + (_theResult____h407265[9] ? 6'd47 : - (_theResult____h407298[8] ? + (_theResult____h407265[8] ? 6'd48 : - (_theResult____h407298[7] ? + (_theResult____h407265[7] ? 6'd49 : - (_theResult____h407298[6] ? + (_theResult____h407265[6] ? 6'd50 : - (_theResult____h407298[5] ? + (_theResult____h407265[5] ? 6'd51 : - (_theResult____h407298[4] ? + (_theResult____h407265[4] ? 6'd52 : - (_theResult____h407298[3] ? + (_theResult____h407265[3] ? 6'd53 : - (_theResult____h407298[2] ? + (_theResult____h407265[2] ? 6'd54 : - (_theResult____h407298[1] ? + (_theResult____h407265[1] ? 6'd55 : - (_theResult____h407298[0] ? + (_theResult____h407265[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452993[56] ? + (_theResult____h452960[56] ? 6'd0 : - (_theResult____h452993[55] ? + (_theResult____h452960[55] ? 6'd1 : - (_theResult____h452993[54] ? + (_theResult____h452960[54] ? 6'd2 : - (_theResult____h452993[53] ? + (_theResult____h452960[53] ? 6'd3 : - (_theResult____h452993[52] ? + (_theResult____h452960[52] ? 6'd4 : - (_theResult____h452993[51] ? + (_theResult____h452960[51] ? 6'd5 : - (_theResult____h452993[50] ? + (_theResult____h452960[50] ? 6'd6 : - (_theResult____h452993[49] ? + (_theResult____h452960[49] ? 6'd7 : - (_theResult____h452993[48] ? + (_theResult____h452960[48] ? 6'd8 : - (_theResult____h452993[47] ? + (_theResult____h452960[47] ? 6'd9 : - (_theResult____h452993[46] ? + (_theResult____h452960[46] ? 6'd10 : - (_theResult____h452993[45] ? + (_theResult____h452960[45] ? 6'd11 : - (_theResult____h452993[44] ? + (_theResult____h452960[44] ? 6'd12 : - (_theResult____h452993[43] ? + (_theResult____h452960[43] ? 6'd13 : - (_theResult____h452993[42] ? + (_theResult____h452960[42] ? 6'd14 : - (_theResult____h452993[41] ? + (_theResult____h452960[41] ? 6'd15 : - (_theResult____h452993[40] ? + (_theResult____h452960[40] ? 6'd16 : - (_theResult____h452993[39] ? + (_theResult____h452960[39] ? 6'd17 : - (_theResult____h452993[38] ? + (_theResult____h452960[38] ? 6'd18 : - (_theResult____h452993[37] ? + (_theResult____h452960[37] ? 6'd19 : - (_theResult____h452993[36] ? + (_theResult____h452960[36] ? 6'd20 : - (_theResult____h452993[35] ? + (_theResult____h452960[35] ? 6'd21 : - (_theResult____h452993[34] ? + (_theResult____h452960[34] ? 6'd22 : - (_theResult____h452993[33] ? + (_theResult____h452960[33] ? 6'd23 : - (_theResult____h452993[32] ? + (_theResult____h452960[32] ? 6'd24 : - (_theResult____h452993[31] ? + (_theResult____h452960[31] ? 6'd25 : - (_theResult____h452993[30] ? + (_theResult____h452960[30] ? 6'd26 : - (_theResult____h452993[29] ? + (_theResult____h452960[29] ? 6'd27 : - (_theResult____h452993[28] ? + (_theResult____h452960[28] ? 6'd28 : - (_theResult____h452993[27] ? + (_theResult____h452960[27] ? 6'd29 : - (_theResult____h452993[26] ? + (_theResult____h452960[26] ? 6'd30 : - (_theResult____h452993[25] ? + (_theResult____h452960[25] ? 6'd31 : - (_theResult____h452993[24] ? + (_theResult____h452960[24] ? 6'd32 : - (_theResult____h452993[23] ? + (_theResult____h452960[23] ? 6'd33 : - (_theResult____h452993[22] ? + (_theResult____h452960[22] ? 6'd34 : - (_theResult____h452993[21] ? + (_theResult____h452960[21] ? 6'd35 : - (_theResult____h452993[20] ? + (_theResult____h452960[20] ? 6'd36 : - (_theResult____h452993[19] ? + (_theResult____h452960[19] ? 6'd37 : - (_theResult____h452993[18] ? + (_theResult____h452960[18] ? 6'd38 : - (_theResult____h452993[17] ? + (_theResult____h452960[17] ? 6'd39 : - (_theResult____h452993[16] ? + (_theResult____h452960[16] ? 6'd40 : - (_theResult____h452993[15] ? + (_theResult____h452960[15] ? 6'd41 : - (_theResult____h452993[14] ? + (_theResult____h452960[14] ? 6'd42 : - (_theResult____h452993[13] ? + (_theResult____h452960[13] ? 6'd43 : - (_theResult____h452993[12] ? + (_theResult____h452960[12] ? 6'd44 : - (_theResult____h452993[11] ? + (_theResult____h452960[11] ? 6'd45 : - (_theResult____h452993[10] ? + (_theResult____h452960[10] ? 6'd46 : - (_theResult____h452993[9] ? + (_theResult____h452960[9] ? 6'd47 : - (_theResult____h452993[8] ? + (_theResult____h452960[8] ? 6'd48 : - (_theResult____h452993[7] ? + (_theResult____h452960[7] ? 6'd49 : - (_theResult____h452993[6] ? + (_theResult____h452960[6] ? 6'd50 : - (_theResult____h452993[5] ? + (_theResult____h452960[5] ? 6'd51 : - (_theResult____h452993[4] ? + (_theResult____h452960[4] ? 6'd52 : - (_theResult____h452993[3] ? + (_theResult____h452960[3] ? 6'd53 : - (_theResult____h452993[2] ? + (_theResult____h452960[2] ? 6'd54 : - (_theResult____h452993[1] ? + (_theResult____h452960[1] ? 6'd55 : - (_theResult____h452993[0] ? + (_theResult____h452960[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10421 = - (_theResult___fst_exp__h547835 == 11'd2047) ? + (_theResult___fst_exp__h547802 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20496,10 +20496,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10688 = - (_theResult___fst_exp__h547835 == 11'd2047) ? + (_theResult___fst_exp__h547802 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20507,10 +20507,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8936 = - (_theResult___fst_exp__h508982 == 11'd2047) ? + (_theResult___fst_exp__h508949 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20518,10 +20518,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9651 = - (_theResult___fst_exp__h587139 == 11'd2047) ? + (_theResult___fst_exp__h587106 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20529,10 +20529,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9919 = - (_theResult___fst_exp__h587139 == 11'd2047) ? + (_theResult___fst_exp__h587106 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20540,538 +20540,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343972 == 2'b0 || + (guard__h343939 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h352073 : - _theResult___exp__h352589 ; + _theResult___fst_exp__h352040 : + _theResult___exp__h352556 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343972 == 2'b0) ? - _theResult___fst_exp__h352073 : + (guard__h343939 == 2'b0) ? + _theResult___fst_exp__h352040 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h352589 : - _theResult___fst_exp__h352073) ; + _theResult___exp__h352556 : + _theResult___fst_exp__h352040) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343972 == 2'b0 || + (guard__h343939 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h352067[56:34] : - _theResult___sfd__h352590 ; + sfdin__h352034[56:34] : + _theResult___sfd__h352557 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343972 == 2'b0) ? - sfdin__h352067[56:34] : + (guard__h343939 == 2'b0) ? + sfdin__h352034[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h352590 : - sfdin__h352067[56:34]) ; + _theResult___sfd__h352557 : + sfdin__h352034[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389671 == 2'b0 || + (guard__h389638 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397770 : - _theResult___exp__h398286 ; + _theResult___fst_exp__h397737 : + _theResult___exp__h398253 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389671 == 2'b0) ? - _theResult___fst_exp__h397770 : + (guard__h389638 == 2'b0) ? + _theResult___fst_exp__h397737 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h398286 : - _theResult___fst_exp__h397770) ; + _theResult___exp__h398253 : + _theResult___fst_exp__h397737) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389671 == 2'b0 || + (guard__h389638 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397764[56:34] : - _theResult___sfd__h398287 ; + sfdin__h397731[56:34] : + _theResult___sfd__h398254 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389671 == 2'b0) ? - sfdin__h397764[56:34] : + (guard__h389638 == 2'b0) ? + sfdin__h397731[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h398287 : - sfdin__h397764[56:34]) ; + _theResult___sfd__h398254 : + sfdin__h397731[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h435366 == 2'b0 || + (guard__h435333 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h443465 : - _theResult___exp__h443981 ; + _theResult___fst_exp__h443432 : + _theResult___exp__h443948 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h435366 == 2'b0) ? - _theResult___fst_exp__h443465 : + (guard__h435333 == 2'b0) ? + _theResult___fst_exp__h443432 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443981 : - _theResult___fst_exp__h443465) ; + _theResult___exp__h443948 : + _theResult___fst_exp__h443432) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h435366 == 2'b0 || + (guard__h435333 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h443459[56:34] : - _theResult___sfd__h443982 ; + sfdin__h443426[56:34] : + _theResult___sfd__h443949 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h435366 == 2'b0) ? - sfdin__h443459[56:34] : + (guard__h435333 == 2'b0) ? + sfdin__h443426[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443982 : - sfdin__h443459[56:34]) ; + _theResult___sfd__h443949 : + sfdin__h443426[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 = - (guard__h539609 == 2'b0 || + (guard__h539576 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547835 : - _theResult___exp__h548564 ; + _theResult___fst_exp__h547802 : + _theResult___exp__h548531 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 = - (guard__h539609 == 2'b0) ? - _theResult___fst_exp__h547835 : + (guard__h539576 == 2'b0) ? + _theResult___fst_exp__h547802 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h548564 : - _theResult___fst_exp__h547835) ; + _theResult___exp__h548531 : + _theResult___fst_exp__h547802) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 = - (guard__h539609 == 2'b0 || + (guard__h539576 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547829[56:5] : - _theResult___sfd__h548565 ; + sfdin__h547796[56:5] : + _theResult___sfd__h548532 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 = - (guard__h539609 == 2'b0) ? - sfdin__h547829[56:5] : + (guard__h539576 == 2'b0) ? + sfdin__h547796[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h548565 : - sfdin__h547829[56:5]) ; + _theResult___sfd__h548532 : + sfdin__h547796[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 = - (guard__h500756 == 2'b0 || + (guard__h500723 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508982 : - _theResult___exp__h509711 ; + _theResult___fst_exp__h508949 : + _theResult___exp__h509678 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 = - (guard__h500756 == 2'b0) ? - _theResult___fst_exp__h508982 : + (guard__h500723 == 2'b0) ? + _theResult___fst_exp__h508949 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h509711 : - _theResult___fst_exp__h508982) ; + _theResult___exp__h509678 : + _theResult___fst_exp__h508949) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 = - (guard__h500756 == 2'b0 || + (guard__h500723 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508976[56:5] : - _theResult___sfd__h509712 ; + sfdin__h508943[56:5] : + _theResult___sfd__h509679 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 = - (guard__h500756 == 2'b0) ? - sfdin__h508976[56:5] : + (guard__h500723 == 2'b0) ? + sfdin__h508943[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h509712 : - sfdin__h508976[56:5]) ; + _theResult___sfd__h509679 : + sfdin__h508943[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 = - (guard__h578913 == 2'b0 || + (guard__h578880 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h587139 : - _theResult___exp__h587868 ; + _theResult___fst_exp__h587106 : + _theResult___exp__h587835 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 = - (guard__h578913 == 2'b0) ? - _theResult___fst_exp__h587139 : + (guard__h578880 == 2'b0) ? + _theResult___fst_exp__h587106 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h587868 : - _theResult___fst_exp__h587139) ; + _theResult___exp__h587835 : + _theResult___fst_exp__h587106) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 = - (guard__h578913 == 2'b0 || + (guard__h578880 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h587133[56:5] : - _theResult___sfd__h587869 ; + sfdin__h587100[56:5] : + _theResult___sfd__h587836 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 = - (guard__h578913 == 2'b0) ? - sfdin__h587133[56:5] : + (guard__h578880 == 2'b0) ? + sfdin__h587100[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h587869 : - sfdin__h587133[56:5]) ; + _theResult___sfd__h587836 : + sfdin__h587100[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h361611 == 2'b0 || + (guard__h361578 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369839 : - _theResult___exp__h370355 ; + _theResult___fst_exp__h369806 : + _theResult___exp__h370322 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h361611 == 2'b0) ? - _theResult___fst_exp__h369839 : + (guard__h361578 == 2'b0) ? + _theResult___fst_exp__h369806 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h370355 : - _theResult___fst_exp__h369839) ; + _theResult___exp__h370322 : + _theResult___fst_exp__h369806) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h361611 == 2'b0 || + (guard__h361578 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369833[56:34] : - _theResult___sfd__h370356 ; + sfdin__h369800[56:34] : + _theResult___sfd__h370323 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h361611 == 2'b0) ? - sfdin__h369833[56:34] : + (guard__h361578 == 2'b0) ? + sfdin__h369800[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h370356 : - sfdin__h369833[56:34]) ; + _theResult___sfd__h370323 : + sfdin__h369800[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h407308 == 2'b0 || + (guard__h407275 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h415536 : - _theResult___exp__h416052 ; + _theResult___fst_exp__h415503 : + _theResult___exp__h416019 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h407308 == 2'b0) ? - _theResult___fst_exp__h415536 : + (guard__h407275 == 2'b0) ? + _theResult___fst_exp__h415503 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h416052 : - _theResult___fst_exp__h415536) ; + _theResult___exp__h416019 : + _theResult___fst_exp__h415503) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h407308 == 2'b0 || + (guard__h407275 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h415530[56:34] : - _theResult___sfd__h416053 ; + sfdin__h415497[56:34] : + _theResult___sfd__h416020 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h407308 == 2'b0) ? - sfdin__h415530[56:34] : + (guard__h407275 == 2'b0) ? + sfdin__h415497[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h416053 : - sfdin__h415530[56:34]) ; + _theResult___sfd__h416020 : + sfdin__h415497[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h453003 == 2'b0 || + (guard__h452970 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h461231 : - _theResult___exp__h461747 ; + _theResult___fst_exp__h461198 : + _theResult___exp__h461714 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h453003 == 2'b0) ? - _theResult___fst_exp__h461231 : + (guard__h452970 == 2'b0) ? + _theResult___fst_exp__h461198 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461747 : - _theResult___fst_exp__h461231) ; + _theResult___exp__h461714 : + _theResult___fst_exp__h461198) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h453003 == 2'b0 || + (guard__h452970 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h461225[56:34] : - _theResult___sfd__h461748 ; + sfdin__h461192[56:34] : + _theResult___sfd__h461715 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h453003 == 2'b0) ? - sfdin__h461225[56:34] : + (guard__h452970 == 2'b0) ? + sfdin__h461192[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461748 : - sfdin__h461225[56:34]) ; + _theResult___sfd__h461715 : + sfdin__h461192[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 = - (guard__h530297 == 2'b0 || + (guard__h530264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h538258 : - _theResult___exp__h538913 ; + _theResult___fst_exp__h538225 : + _theResult___exp__h538880 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 = - (guard__h530297 == 2'b0) ? - _theResult___fst_exp__h538258 : + (guard__h530264 == 2'b0) ? + _theResult___fst_exp__h538225 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h538913 : - _theResult___fst_exp__h538258) ; + _theResult___exp__h538880 : + _theResult___fst_exp__h538225) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 = - (guard__h548678 == 2'b0 || + (guard__h548645 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h556668 : - _theResult___exp__h557348 ; + _theResult___fst_exp__h556635 : + _theResult___exp__h557315 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 = - (guard__h548678 == 2'b0) ? - _theResult___fst_exp__h556668 : + (guard__h548645 == 2'b0) ? + _theResult___fst_exp__h556635 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h557348 : - _theResult___fst_exp__h556668) ; + _theResult___exp__h557315 : + _theResult___fst_exp__h556635) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 = - (guard__h530297 == 2'b0 || + (guard__h530264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h538209[56:5] : - _theResult___sfd__h538914 ; + _theResult___snd__h538176[56:5] : + _theResult___sfd__h538881 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 = - (guard__h530297 == 2'b0) ? - _theResult___snd__h538209[56:5] : + (guard__h530264 == 2'b0) ? + _theResult___snd__h538176[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h538914 : - _theResult___snd__h538209[56:5]) ; + _theResult___sfd__h538881 : + _theResult___snd__h538176[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 = - (guard__h548678 == 2'b0 || + (guard__h548645 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h556614[56:5] : - _theResult___sfd__h557349 ; + _theResult___snd__h556581[56:5] : + _theResult___sfd__h557316 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 = - (guard__h548678 == 2'b0) ? - _theResult___snd__h556614[56:5] : + (guard__h548645 == 2'b0) ? + _theResult___snd__h556581[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h557349 : - _theResult___snd__h556614[56:5]) ; + _theResult___sfd__h557316 : + _theResult___snd__h556581[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 = - (guard__h491444 == 2'b0 || + (guard__h491411 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h499405 : - _theResult___exp__h500060 ; + _theResult___fst_exp__h499372 : + _theResult___exp__h500027 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 = - (guard__h491444 == 2'b0) ? - _theResult___fst_exp__h499405 : + (guard__h491411 == 2'b0) ? + _theResult___fst_exp__h499372 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h500060 : - _theResult___fst_exp__h499405) ; + _theResult___exp__h500027 : + _theResult___fst_exp__h499372) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 = - (guard__h509825 == 2'b0 || + (guard__h509792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517815 : - _theResult___exp__h518495 ; + _theResult___fst_exp__h517782 : + _theResult___exp__h518462 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 = - (guard__h509825 == 2'b0) ? - _theResult___fst_exp__h517815 : + (guard__h509792 == 2'b0) ? + _theResult___fst_exp__h517782 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h518495 : - _theResult___fst_exp__h517815) ; + _theResult___exp__h518462 : + _theResult___fst_exp__h517782) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 = - (guard__h491444 == 2'b0 || + (guard__h491411 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h499356[56:5] : - _theResult___sfd__h500061 ; + _theResult___snd__h499323[56:5] : + _theResult___sfd__h500028 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 = - (guard__h491444 == 2'b0) ? - _theResult___snd__h499356[56:5] : + (guard__h491411 == 2'b0) ? + _theResult___snd__h499323[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h500061 : - _theResult___snd__h499356[56:5]) ; + _theResult___sfd__h500028 : + _theResult___snd__h499323[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 = - (guard__h509825 == 2'b0 || + (guard__h509792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517761[56:5] : - _theResult___sfd__h518496 ; + _theResult___snd__h517728[56:5] : + _theResult___sfd__h518463 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 = - (guard__h509825 == 2'b0) ? - _theResult___snd__h517761[56:5] : + (guard__h509792 == 2'b0) ? + _theResult___snd__h517728[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h518496 : - _theResult___snd__h517761[56:5]) ; + _theResult___sfd__h518463 : + _theResult___snd__h517728[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 = - (guard__h569601 == 2'b0 || + (guard__h569568 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h577562 : - _theResult___exp__h578217 ; + _theResult___fst_exp__h577529 : + _theResult___exp__h578184 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 = - (guard__h569601 == 2'b0) ? - _theResult___fst_exp__h577562 : + (guard__h569568 == 2'b0) ? + _theResult___fst_exp__h577529 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h578217 : - _theResult___fst_exp__h577562) ; + _theResult___exp__h578184 : + _theResult___fst_exp__h577529) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 = - (guard__h587982 == 2'b0 || + (guard__h587949 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595972 : - _theResult___exp__h596652 ; + _theResult___fst_exp__h595939 : + _theResult___exp__h596619 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 = - (guard__h587982 == 2'b0) ? - _theResult___fst_exp__h595972 : + (guard__h587949 == 2'b0) ? + _theResult___fst_exp__h595939 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h596652 : - _theResult___fst_exp__h595972) ; + _theResult___exp__h596619 : + _theResult___fst_exp__h595939) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 = - (guard__h569601 == 2'b0 || + (guard__h569568 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h577513[56:5] : - _theResult___sfd__h578218 ; + _theResult___snd__h577480[56:5] : + _theResult___sfd__h578185 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 = - (guard__h569601 == 2'b0) ? - _theResult___snd__h577513[56:5] : + (guard__h569568 == 2'b0) ? + _theResult___snd__h577480[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h578218 : - _theResult___snd__h577513[56:5]) ; + _theResult___sfd__h578185 : + _theResult___snd__h577480[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 = - (guard__h587982 == 2'b0 || + (guard__h587949 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595918[56:5] : - _theResult___sfd__h596653 ; + _theResult___snd__h595885[56:5] : + _theResult___sfd__h596620 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 = - (guard__h587982 == 2'b0) ? - _theResult___snd__h595918[56:5] : + (guard__h587949 == 2'b0) ? + _theResult___snd__h595885[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h596653 : - _theResult___snd__h595918[56:5]) ; + _theResult___sfd__h596620 : + _theResult___snd__h595885[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352681 == 2'b0 || + (guard__h352648 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360729 : - _theResult___exp__h361171 ; + _theResult___fst_exp__h360696 : + _theResult___exp__h361138 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352681 == 2'b0) ? - _theResult___fst_exp__h360729 : + (guard__h352648 == 2'b0) ? + _theResult___fst_exp__h360696 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h361171 : - _theResult___fst_exp__h360729) ; + _theResult___exp__h361138 : + _theResult___fst_exp__h360696) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h370447 == 2'b0 || + (guard__h370414 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h378524 : - _theResult___exp__h378991 ; + _theResult___fst_exp__h378491 : + _theResult___exp__h378958 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h370447 == 2'b0) ? - _theResult___fst_exp__h378524 : + (guard__h370414 == 2'b0) ? + _theResult___fst_exp__h378491 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378991 : - _theResult___fst_exp__h378524) ; + _theResult___exp__h378958 : + _theResult___fst_exp__h378491) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352681 == 2'b0 || + (guard__h352648 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360680[56:34] : - _theResult___sfd__h361172 ; + _theResult___snd__h360647[56:34] : + _theResult___sfd__h361139 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352681 == 2'b0) ? - _theResult___snd__h360680[56:34] : + (guard__h352648 == 2'b0) ? + _theResult___snd__h360647[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h361172 : - _theResult___snd__h360680[56:34]) ; + _theResult___sfd__h361139 : + _theResult___snd__h360647[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h370447 == 2'b0 || + (guard__h370414 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h378470[56:34] : - _theResult___sfd__h378992 ; + _theResult___snd__h378437[56:34] : + _theResult___sfd__h378959 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h370447 == 2'b0) ? - _theResult___snd__h378470[56:34] : + (guard__h370414 == 2'b0) ? + _theResult___snd__h378437[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378992 : - _theResult___snd__h378470[56:34]) ; + _theResult___sfd__h378959 : + _theResult___snd__h378437[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h398378 == 2'b0 || + (guard__h398345 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h406426 : - _theResult___exp__h406868 ; + _theResult___fst_exp__h406393 : + _theResult___exp__h406835 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h398378 == 2'b0) ? - _theResult___fst_exp__h406426 : + (guard__h398345 == 2'b0) ? + _theResult___fst_exp__h406393 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406868 : - _theResult___fst_exp__h406426) ; + _theResult___exp__h406835 : + _theResult___fst_exp__h406393) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h416144 == 2'b0 || + (guard__h416111 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h424221 : - _theResult___exp__h424688 ; + _theResult___fst_exp__h424188 : + _theResult___exp__h424655 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h416144 == 2'b0) ? - _theResult___fst_exp__h424221 : + (guard__h416111 == 2'b0) ? + _theResult___fst_exp__h424188 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424688 : - _theResult___fst_exp__h424221) ; + _theResult___exp__h424655 : + _theResult___fst_exp__h424188) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h398378 == 2'b0 || + (guard__h398345 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h406377[56:34] : - _theResult___sfd__h406869 ; + _theResult___snd__h406344[56:34] : + _theResult___sfd__h406836 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h398378 == 2'b0) ? - _theResult___snd__h406377[56:34] : + (guard__h398345 == 2'b0) ? + _theResult___snd__h406344[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406869 : - _theResult___snd__h406377[56:34]) ; + _theResult___sfd__h406836 : + _theResult___snd__h406344[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h416144 == 2'b0 || + (guard__h416111 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h424167[56:34] : - _theResult___sfd__h424689 ; + _theResult___snd__h424134[56:34] : + _theResult___sfd__h424656 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h416144 == 2'b0) ? - _theResult___snd__h424167[56:34] : + (guard__h416111 == 2'b0) ? + _theResult___snd__h424134[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424689 : - _theResult___snd__h424167[56:34]) ; + _theResult___sfd__h424656 : + _theResult___snd__h424134[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h444073 == 2'b0 || + (guard__h444040 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h452121 : - _theResult___exp__h452563 ; + _theResult___fst_exp__h452088 : + _theResult___exp__h452530 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h444073 == 2'b0) ? - _theResult___fst_exp__h452121 : + (guard__h444040 == 2'b0) ? + _theResult___fst_exp__h452088 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h452563 : - _theResult___fst_exp__h452121) ; + _theResult___exp__h452530 : + _theResult___fst_exp__h452088) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461839 == 2'b0 || + (guard__h461806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469916 : - _theResult___exp__h470383 ; + _theResult___fst_exp__h469883 : + _theResult___exp__h470350 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461839 == 2'b0) ? - _theResult___fst_exp__h469916 : + (guard__h461806 == 2'b0) ? + _theResult___fst_exp__h469883 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h470383 : - _theResult___fst_exp__h469916) ; + _theResult___exp__h470350 : + _theResult___fst_exp__h469883) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h444073 == 2'b0 || + (guard__h444040 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h452072[56:34] : - _theResult___sfd__h452564 ; + _theResult___snd__h452039[56:34] : + _theResult___sfd__h452531 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h444073 == 2'b0) ? - _theResult___snd__h452072[56:34] : + (guard__h444040 == 2'b0) ? + _theResult___snd__h452039[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h452564 : - _theResult___snd__h452072[56:34]) ; + _theResult___sfd__h452531 : + _theResult___snd__h452039[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461839 == 2'b0 || + (guard__h461806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469862[56:34] : - _theResult___sfd__h470384 ; + _theResult___snd__h469829[56:34] : + _theResult___sfd__h470351 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461839 == 2'b0) ? - _theResult___snd__h469862[56:34] : + (guard__h461806 == 2'b0) ? + _theResult___snd__h469829[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h470384 : - _theResult___snd__h469862[56:34]) ; + _theResult___sfd__h470351 : + _theResult___snd__h469829[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467 = - (_theResult___fst_exp__h556668 == 11'd2047) ? + (_theResult___fst_exp__h556635 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21079,10 +21079,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10673 = - (_theResult___fst_exp__h538258 == 11'd2047) ? + (_theResult___fst_exp__h538225 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21090,10 +21090,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10700 = - (_theResult___fst_exp__h556668 == 11'd2047) ? + (_theResult___fst_exp__h556635 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21101,10 +21101,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8982 = - (_theResult___fst_exp__h517815 == 11'd2047) ? + (_theResult___fst_exp__h517782 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21112,10 +21112,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697 = - (_theResult___fst_exp__h595972 == 11'd2047) ? + (_theResult___fst_exp__h595939 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21123,10 +21123,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904 = - (_theResult___fst_exp__h577562 == 11'd2047) ? + (_theResult___fst_exp__h577529 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21134,10 +21134,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931 = - (_theResult___fst_exp__h595972 == 11'd2047) ? + (_theResult___fst_exp__h595939 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21145,146 +21145,146 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771 = - (_theResult____h647786 == 16'd0 && + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767 = + (_theResult____h647726 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h648358 : - _theResult____h647786 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981 || + enabled_ints__h648298 : + _theResult____h647726 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 || fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 ; - assign IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] || - checkForException___d13619[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 ; + assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] || + checkForException___d13615[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 = - ((f2_exp__h519011 == 8'd0) ? - (f2_sfd__h519012[22] ? + ((f2_exp__h518978 == 8'd0) ? + (f2_sfd__h518979[22] ? 6'd2 : - (f2_sfd__h519012[21] ? + (f2_sfd__h518979[21] ? 6'd3 : - (f2_sfd__h519012[20] ? + (f2_sfd__h518979[20] ? 6'd4 : - (f2_sfd__h519012[19] ? + (f2_sfd__h518979[19] ? 6'd5 : - (f2_sfd__h519012[18] ? + (f2_sfd__h518979[18] ? 6'd6 : - (f2_sfd__h519012[17] ? + (f2_sfd__h518979[17] ? 6'd7 : - (f2_sfd__h519012[16] ? + (f2_sfd__h518979[16] ? 6'd8 : - (f2_sfd__h519012[15] ? + (f2_sfd__h518979[15] ? 6'd9 : - (f2_sfd__h519012[14] ? + (f2_sfd__h518979[14] ? 6'd10 : - (f2_sfd__h519012[13] ? + (f2_sfd__h518979[13] ? 6'd11 : - (f2_sfd__h519012[12] ? + (f2_sfd__h518979[12] ? 6'd12 : - (f2_sfd__h519012[11] ? + (f2_sfd__h518979[11] ? 6'd13 : - (f2_sfd__h519012[10] ? + (f2_sfd__h518979[10] ? 6'd14 : - (f2_sfd__h519012[9] ? + (f2_sfd__h518979[9] ? 6'd15 : - (f2_sfd__h519012[8] ? + (f2_sfd__h518979[8] ? 6'd16 : - (f2_sfd__h519012[7] ? + (f2_sfd__h518979[7] ? 6'd17 : - (f2_sfd__h519012[6] ? + (f2_sfd__h518979[6] ? 6'd18 : - (f2_sfd__h519012[5] ? + (f2_sfd__h518979[5] ? 6'd19 : - (f2_sfd__h519012[4] ? + (f2_sfd__h518979[4] ? 6'd20 : - (f2_sfd__h519012[3] ? + (f2_sfd__h518979[3] ? 6'd21 : - (f2_sfd__h519012[2] ? + (f2_sfd__h518979[2] ? 6'd22 : - (f2_sfd__h519012[1] ? + (f2_sfd__h518979[1] ? 6'd23 : - (f2_sfd__h519012[0] ? + (f2_sfd__h518979[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0 || - (f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 || + (f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h519011 == 8'd0) ? + ((f2_exp__h518978 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0) ? - _theResult___snd_fst_sfd__h519327 : - _theResult___fst_sfd__h557467 ; + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0) ? + _theResult___snd_fst_sfd__h519294 : + _theResult___fst_sfd__h557434 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649 = - { (f2_exp__h519011 == 8'd255) ? + { (f2_exp__h518978 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h557463, + _theResult___fst_exp__h557430, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21294,15 +21294,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704 = - (f2_exp__h519011 == 8'd255 && f2_sfd__h519012 != 23'd0 || - (f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + (f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 || + (f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[4] : @@ -21310,7 +21310,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[4] : @@ -21318,7 +21318,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[4] : @@ -21326,7 +21326,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[3] : @@ -21334,7 +21334,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[3] : @@ -21342,7 +21342,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[3] : @@ -21350,211 +21350,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 = - (f1_exp__h480017 == 8'd0) ? + (f1_exp__h479984 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999 = - (f2_exp__h519011 == 8'd0) ? + (f2_exp__h518978 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 = - ((f1_exp__h480017 == 8'd0) ? - (f1_sfd__h480018[22] ? + ((f1_exp__h479984 == 8'd0) ? + (f1_sfd__h479985[22] ? 6'd2 : - (f1_sfd__h480018[21] ? + (f1_sfd__h479985[21] ? 6'd3 : - (f1_sfd__h480018[20] ? + (f1_sfd__h479985[20] ? 6'd4 : - (f1_sfd__h480018[19] ? + (f1_sfd__h479985[19] ? 6'd5 : - (f1_sfd__h480018[18] ? + (f1_sfd__h479985[18] ? 6'd6 : - (f1_sfd__h480018[17] ? + (f1_sfd__h479985[17] ? 6'd7 : - (f1_sfd__h480018[16] ? + (f1_sfd__h479985[16] ? 6'd8 : - (f1_sfd__h480018[15] ? + (f1_sfd__h479985[15] ? 6'd9 : - (f1_sfd__h480018[14] ? + (f1_sfd__h479985[14] ? 6'd10 : - (f1_sfd__h480018[13] ? + (f1_sfd__h479985[13] ? 6'd11 : - (f1_sfd__h480018[12] ? + (f1_sfd__h479985[12] ? 6'd12 : - (f1_sfd__h480018[11] ? + (f1_sfd__h479985[11] ? 6'd13 : - (f1_sfd__h480018[10] ? + (f1_sfd__h479985[10] ? 6'd14 : - (f1_sfd__h480018[9] ? + (f1_sfd__h479985[9] ? 6'd15 : - (f1_sfd__h480018[8] ? + (f1_sfd__h479985[8] ? 6'd16 : - (f1_sfd__h480018[7] ? + (f1_sfd__h479985[7] ? 6'd17 : - (f1_sfd__h480018[6] ? + (f1_sfd__h479985[6] ? 6'd18 : - (f1_sfd__h480018[5] ? + (f1_sfd__h479985[5] ? 6'd19 : - (f1_sfd__h480018[4] ? + (f1_sfd__h479985[4] ? 6'd20 : - (f1_sfd__h480018[3] ? + (f1_sfd__h479985[3] ? 6'd21 : - (f1_sfd__h480018[2] ? + (f1_sfd__h479985[2] ? 6'd22 : - (f1_sfd__h480018[1] ? + (f1_sfd__h479985[1] ? 6'd23 : - (f1_sfd__h480018[0] ? + (f1_sfd__h479985[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986 = - (f1_exp__h480017 == 8'd255 && f1_sfd__h480018 != 23'd0 || - (f1_exp__h480017 == 8'd255 || f1_exp__h480017 == 8'd0) && - f1_sfd__h480018 == 23'd0) ? + (f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0 || + (f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) && + f1_sfd__h479985 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h480017 == 8'd0) ? + ((f1_exp__h479984 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8984) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 = - (f1_exp__h480017 == 8'd255 && f1_sfd__h480018 != 23'd0) ? - _theResult___snd_fst_sfd__h480333 : - _theResult___fst_sfd__h518614 ; + (f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0) ? + _theResult___snd_fst_sfd__h480300 : + _theResult___fst_sfd__h518581 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986, - (f1_exp__h480017 == 8'd255) ? + (f1_exp__h479984 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h518610, + _theResult___fst_exp__h518577, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 = - ((f3_exp__h558315 == 8'd0) ? - (f3_sfd__h558316[22] ? + ((f3_exp__h558282 == 8'd0) ? + (f3_sfd__h558283[22] ? 6'd2 : - (f3_sfd__h558316[21] ? + (f3_sfd__h558283[21] ? 6'd3 : - (f3_sfd__h558316[20] ? + (f3_sfd__h558283[20] ? 6'd4 : - (f3_sfd__h558316[19] ? + (f3_sfd__h558283[19] ? 6'd5 : - (f3_sfd__h558316[18] ? + (f3_sfd__h558283[18] ? 6'd6 : - (f3_sfd__h558316[17] ? + (f3_sfd__h558283[17] ? 6'd7 : - (f3_sfd__h558316[16] ? + (f3_sfd__h558283[16] ? 6'd8 : - (f3_sfd__h558316[15] ? + (f3_sfd__h558283[15] ? 6'd9 : - (f3_sfd__h558316[14] ? + (f3_sfd__h558283[14] ? 6'd10 : - (f3_sfd__h558316[13] ? + (f3_sfd__h558283[13] ? 6'd11 : - (f3_sfd__h558316[12] ? + (f3_sfd__h558283[12] ? 6'd12 : - (f3_sfd__h558316[11] ? + (f3_sfd__h558283[11] ? 6'd13 : - (f3_sfd__h558316[10] ? + (f3_sfd__h558283[10] ? 6'd14 : - (f3_sfd__h558316[9] ? + (f3_sfd__h558283[9] ? 6'd15 : - (f3_sfd__h558316[8] ? + (f3_sfd__h558283[8] ? 6'd16 : - (f3_sfd__h558316[7] ? + (f3_sfd__h558283[7] ? 6'd17 : - (f3_sfd__h558316[6] ? + (f3_sfd__h558283[6] ? 6'd18 : - (f3_sfd__h558316[5] ? + (f3_sfd__h558283[5] ? 6'd19 : - (f3_sfd__h558316[4] ? + (f3_sfd__h558283[4] ? 6'd20 : - (f3_sfd__h558316[3] ? + (f3_sfd__h558283[3] ? 6'd21 : - (f3_sfd__h558316[2] ? + (f3_sfd__h558283[2] ? 6'd22 : - (f3_sfd__h558316[1] ? + (f3_sfd__h558283[1] ? 6'd23 : - (f3_sfd__h558316[0] ? + (f3_sfd__h558283[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9701 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0 || - (f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 || + (f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h558315 == 8'd0) ? + ((f3_exp__h558282 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9699) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0) ? - _theResult___snd_fst_sfd__h558631 : - _theResult___fst_sfd__h596771 ; + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0) ? + _theResult___snd_fst_sfd__h558598 : + _theResult___fst_sfd__h596738 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 = - { (f3_exp__h558315 == 8'd255) ? + { (f3_exp__h558282 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h596767, + _theResult___fst_exp__h596734, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9934 = - (f3_exp__h558315 == 8'd0) ? + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21564,9 +21564,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9933 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935 = - (f3_exp__h558315 == 8'd255 && f3_sfd__h558316 != 23'd0 || - (f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + (f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 || + (f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21609,110 +21609,110 @@ module mkCore(CLK, (IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ? 4'd1 : IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855) ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134 = + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd12 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd12) ? 4'd13 : 4'd15 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135 = + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd11 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd11) ? 4'd12 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13134 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd10 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd10) ? 4'd11 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13135 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd9 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd9) ? 4'd9 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13136 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd8 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd8) ? 4'd8 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13137 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd7 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd7) ? 4'd7 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13138 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd6 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd6) ? 4'd6 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13139 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd5 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd5) ? 4'd5 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13140 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd4 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd4) ? 4'd4 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13141 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd3 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd3) ? 4'd3 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13142 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd2 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd2) ? 4'd2 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13143 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd1 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd1) ? 4'd1 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13144 ; - assign IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146 = + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 ; + assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 == 4'd0 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 == + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 == 4'd0) ? 4'd0 : - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13145 ; + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 ; assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 = { (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 : @@ -21775,7 +21775,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 || - _theResult___fst_exp__h538258 == 11'd2047) ? + _theResult___fst_exp__h538225 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21783,12 +21783,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 || - _theResult___fst_exp__h499405 == 11'd2047) ? + _theResult___fst_exp__h499372 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21796,12 +21796,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 || - _theResult___fst_exp__h577562 == 11'd2047) ? + _theResult___fst_exp__h577529 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21809,139 +21809,139 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; - assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 = - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] ? + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ? 4'd0 : - (IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] ? + (IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ? 4'd1 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2]) ? 4'd2 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3]) ? 4'd3 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4]) ? 4'd4 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6]) ? 4'd5 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7]) ? 4'd6 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8]) ? 4'd7 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10]) ? 4'd8 : - ((IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13]) ? 4'd9 : 4'd10))))))))) ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181 : + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12200 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 ? + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ? coreFix_aluExe_0_bypassWire_3$whas && coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12201 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213 : + coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12225 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 ? + coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ? coreFix_aluExe_0_bypassWire_3$whas && coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12226 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12399 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12411 ; + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 ; assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ? @@ -21982,30 +21982,30 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_1_dispToRegQ$first[76:70] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11392 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11753 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11765 ; + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 ; assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ? @@ -22199,102 +22199,102 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20 : CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13829 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 : + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2698_269_ETC___d13837 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836 : + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 ; - assign IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752 = + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ; + assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735 : + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) : - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750) ; - assign IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13836 = - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660 ? - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 || + (regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) : + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746) ; + assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 = + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 ? + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 ; - assign IF_NOT_renameStage_rg_m_halt_req_2727_BIT_4_27_ETC___d13219 = - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038 ? - IF_IF_fetchStage_pipelines_0_first__2700_BIT_6_ETC___d13146 : + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ; + assign IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 ? + IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd0 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd0) ? 4'd0 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd1 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd1) ? 4'd1 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd3 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd2) ? 4'd3 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd4 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd3) ? 4'd4 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd5 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd4) ? 4'd5 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd7 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd5) ? 4'd7 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd8 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd6) ? 4'd8 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd9 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd7) ? 4'd9 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd11 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd8) ? 4'd11 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd14 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3__ETC___d13179 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 == 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197 = + assign IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -22333,48 +22333,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[2] : - _theResult___fst_exp__h518598 == 11'd2047 && - _theResult___fst_sfd__h518599 == 52'd0 ; + _theResult___fst_exp__h518565 == 11'd2047 && + _theResult___fst_sfd__h518566 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[2] : - _theResult___fst_exp__h557451 == 11'd2047 && - _theResult___fst_sfd__h557452 == 52'd0 ; + _theResult___fst_exp__h557418 == 11'd2047 && + _theResult___fst_sfd__h557419 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[2] : - _theResult___fst_exp__h596755 == 11'd2047 && - _theResult___fst_sfd__h596756 == 52'd0 ; + _theResult___fst_exp__h596722 == 11'd2047 && + _theResult___fst_sfd__h596723 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[1] : - _theResult___fst_exp__h517815 == 11'd0 && - guard__h509825 != 2'b0 ; + _theResult___fst_exp__h517782 == 11'd0 && + guard__h509792 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[1] : - _theResult___fst_exp__h556668 == 11'd0 && - guard__h548678 != 2'b0 ; + _theResult___fst_exp__h556635 == 11'd0 && + guard__h548645 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[1] : - _theResult___fst_exp__h595972 == 11'd0 && - guard__h587982 != 2'b0 ; + _theResult___fst_exp__h595939 == 11'd0 && + guard__h587949 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[0] : - _theResult___fst_exp__h517815 != 11'd2047 && - guard__h509825 != 2'b0 ; + _theResult___fst_exp__h517782 != 11'd2047 && + guard__h509792 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[0] : - _theResult___fst_exp__h556668 != 11'd2047 && - guard__h548678 != 2'b0 ; + _theResult___fst_exp__h556635 != 11'd2047 && + guard__h548645 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[0] : - _theResult___fst_exp__h595972 != 11'd2047 && - guard__h587982 != 2'b0 ; + _theResult___fst_exp__h595939 != 11'd2047 && + guard__h587949 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22420,35 +22420,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369839 == 8'd255) ? + ((_theResult___fst_exp__h369806 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h378524 == 8'd255) ? + ((_theResult___fst_exp__h378491 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369839 == 8'd255) ? + ((_theResult___fst_exp__h369806 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h378524 == 8'd255) ? + ((_theResult___fst_exp__h378491 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h379072 == 8'd255 && - _theResult___fst_sfd__h379073 == 23'd0 ; + _theResult___fst_exp__h379039 == 8'd255 && + _theResult___fst_sfd__h379040 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h378524 == 8'd0 && - guard__h370447 != 2'b0 ; + _theResult___fst_exp__h378491 == 8'd0 && + guard__h370414 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h378524 != 8'd255 && - guard__h370447 != 2'b0 ; + _theResult___fst_exp__h378491 != 8'd255 && + guard__h370414 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22458,35 +22458,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h415536 == 8'd255) ? + ((_theResult___fst_exp__h415503 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h424221 == 8'd255) ? + ((_theResult___fst_exp__h424188 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h415536 == 8'd255) ? + ((_theResult___fst_exp__h415503 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h424221 == 8'd255) ? + ((_theResult___fst_exp__h424188 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424769 == 8'd255 && - _theResult___fst_sfd__h424770 == 23'd0 ; + _theResult___fst_exp__h424736 == 8'd255 && + _theResult___fst_sfd__h424737 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h424221 == 8'd0 && - guard__h416144 != 2'b0 ; + _theResult___fst_exp__h424188 == 8'd0 && + guard__h416111 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h424221 != 8'd255 && - guard__h416144 != 2'b0 ; + _theResult___fst_exp__h424188 != 8'd255 && + guard__h416111 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22496,51 +22496,51 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h461231 == 8'd255) ? + ((_theResult___fst_exp__h461198 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469916 == 8'd255) ? + ((_theResult___fst_exp__h469883 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h461231 == 8'd255) ? + ((_theResult___fst_exp__h461198 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469916 == 8'd255) ? + ((_theResult___fst_exp__h469883 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h470464 == 8'd255 && - _theResult___fst_sfd__h470465 == 23'd0 ; + _theResult___fst_exp__h470431 == 8'd255 && + _theResult___fst_sfd__h470432 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469916 == 8'd0 && - guard__h461839 != 2'b0 ; + _theResult___fst_exp__h469883 == 8'd0 && + guard__h461806 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469916 != 8'd255 && - guard__h461839 != 2'b0 ; - assign IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095 = - checkForException___d12946[4] ? - CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 : + _theResult___fst_exp__h469883 != 8'd255 && + guard__h461806 != 2'b0 ; + assign IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 = + checkForException___d12942[4] ? + CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) ? + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) ? + coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || @@ -23183,10 +23183,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 } ; - assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12641 = + assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h643363 : - w__h643358 ; + result__h643303 : + w__h643298 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23208,39 +23208,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h196409 : + n___1__h196376 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23293,7 +23293,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h195006 : + x__h194973 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -23305,7 +23305,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h294400 == v__h293820 ; + _theResult_____2__h294368 == v__h293788 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23314,7 +23314,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h302396 == v__h297165 ; + _theResult_____2__h302364 == v__h297133 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23343,7 +23343,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h300030 } ; + x__h299998 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -23441,35 +23441,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h192334 : + n__h192301 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23497,7 +23497,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h308390 == v__h307679 ; + _theResult_____2__h308358 == v__h307647 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23506,7 +23506,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h316244 == v__h311555 ; + _theResult_____2__h316212 == v__h311523 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23658,7 +23658,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329813 == v__h329381 ; + _theResult_____2__h329781 == v__h329349 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -23707,7 +23707,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h326588 == v__h326156 ; + _theResult_____2__h326556 == v__h326124 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -23739,79 +23739,79 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h710124 : + upd__h710029 : csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365 = + assign IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359) ? + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 = + assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2709_BITS_ETC___d13752 ; - assign IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 = + IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 ; + assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660) ? - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 && - (IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 || + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656) ? + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 && + (IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875 = - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + assign IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2700_BIT_160__ETC___d14055 = + assign IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 ? - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 : + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 ? + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 : { 1'h0, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 } } ; - assign IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 } } ; + assign IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969 = fetchStage$pipelines_0_first[173] ? - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 : + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 : 12'hCFF ; - assign IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005 = - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13754 && - (IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 || + assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 && + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 && + (IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 || rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999) ; - assign IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14225 = + fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995) ; + assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179) ? - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 : + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175) ? + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 : { 1'h0, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 } ; - assign IF_fetchStage_pipelines_1_first__2709_BIT_160__ETC___d14184 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } ; + assign IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 ? - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 : + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174, + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 ? + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 : { 1'h0, - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 } } ; + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -23836,58 +23836,58 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 = - rob$deqPort_0_canDeq ? y_avValue_fst__h712379 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 = + assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 = + rob$deqPort_0_canDeq ? y_avValue_fst__h712284 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h712827 : + y_avValue_snd_snd_snd_fst__h712732 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198 = + assign IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__4901_BIT_25_490_ETC___d15197 : + IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h508976[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h415530[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h443459[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h547829[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h352067[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h461225[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h369833[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h587133[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h397764[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h406377[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h517761[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h424167[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h538209[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h452072[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h556614[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h360680[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h469862[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h577513[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h378470[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h595918[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h499356[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h508943[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h415497[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h443426[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h547796[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h352034[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h461192[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h369800[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h587100[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h397731[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h406344[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h517728[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h424134[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h538176[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h452039[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h556581[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h360647[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h469829[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h577480[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h378437[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h595885[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h499323[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -23918,198 +23918,198 @@ module mkCore(CLK, (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[0] : _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[0]) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269 && + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 && (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 = - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] && - !checkForException___d13619[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__4893_4894_OR__ETC___d15203 = - (fflags__h714186 & csrf_fflags_reg) != fflags__h714186 || - !r__h610387 && - (IF_rob_deqPort_1_canDeq__4898_THEN_IF_NOT_rob__ETC___d15198 || - fflags__h714186 != 5'd0) ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] && + !checkForException___d13615[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 = + (fflags__h714091 & csrf_fflags_reg) != fflags__h714091 || + !r__h610340 && + (IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 || + fflags__h714091 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 = - !f2_sfd__h519012[21] && !f2_sfd__h519012[20] && - !f2_sfd__h519012[19] && - !f2_sfd__h519012[18] && - !f2_sfd__h519012[17] && - !f2_sfd__h519012[16] && - !f2_sfd__h519012[15] && - !f2_sfd__h519012[14] && - !f2_sfd__h519012[13] && - !f2_sfd__h519012[12] && - !f2_sfd__h519012[11] && - !f2_sfd__h519012[10] && - !f2_sfd__h519012[9] && - !f2_sfd__h519012[8] && - !f2_sfd__h519012[7] && - !f2_sfd__h519012[6] && - !f2_sfd__h519012[5] && - !f2_sfd__h519012[4] && - !f2_sfd__h519012[3] && - !f2_sfd__h519012[2] && - !f2_sfd__h519012[1] && - !f2_sfd__h519012[0] ; + !f2_sfd__h518979[21] && !f2_sfd__h518979[20] && + !f2_sfd__h518979[19] && + !f2_sfd__h518979[18] && + !f2_sfd__h518979[17] && + !f2_sfd__h518979[16] && + !f2_sfd__h518979[15] && + !f2_sfd__h518979[14] && + !f2_sfd__h518979[13] && + !f2_sfd__h518979[12] && + !f2_sfd__h518979[11] && + !f2_sfd__h518979[10] && + !f2_sfd__h518979[9] && + !f2_sfd__h518979[8] && + !f2_sfd__h518979[7] && + !f2_sfd__h518979[6] && + !f2_sfd__h518979[5] && + !f2_sfd__h518979[4] && + !f2_sfd__h518979[3] && + !f2_sfd__h518979[2] && + !f2_sfd__h518979[1] && + !f2_sfd__h518979[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 = - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 == 23'd0) && - (f1_exp__h480017 != 8'd255 || f1_sfd__h480018 != 23'd0) && - (f1_exp__h480017 != 8'd0 || f1_sfd__h480018 != 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) && + (f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) && + (f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 | - ((f2_exp__h519011 != 8'd255 || f2_sfd__h519012 == 23'd0) && - (f2_exp__h519011 != 8'd255 || f2_sfd__h519012 != 23'd0) && - (f2_exp__h519011 != 8'd0 || f2_sfd__h519012 != 23'd0) && + ((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) && + (f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) && + (f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 = - !f1_sfd__h480018[21] && !f1_sfd__h480018[20] && - !f1_sfd__h480018[19] && - !f1_sfd__h480018[18] && - !f1_sfd__h480018[17] && - !f1_sfd__h480018[16] && - !f1_sfd__h480018[15] && - !f1_sfd__h480018[14] && - !f1_sfd__h480018[13] && - !f1_sfd__h480018[12] && - !f1_sfd__h480018[11] && - !f1_sfd__h480018[10] && - !f1_sfd__h480018[9] && - !f1_sfd__h480018[8] && - !f1_sfd__h480018[7] && - !f1_sfd__h480018[6] && - !f1_sfd__h480018[5] && - !f1_sfd__h480018[4] && - !f1_sfd__h480018[3] && - !f1_sfd__h480018[2] && - !f1_sfd__h480018[1] && - !f1_sfd__h480018[0] ; + !f1_sfd__h479985[21] && !f1_sfd__h479985[20] && + !f1_sfd__h479985[19] && + !f1_sfd__h479985[18] && + !f1_sfd__h479985[17] && + !f1_sfd__h479985[16] && + !f1_sfd__h479985[15] && + !f1_sfd__h479985[14] && + !f1_sfd__h479985[13] && + !f1_sfd__h479985[12] && + !f1_sfd__h479985[11] && + !f1_sfd__h479985[10] && + !f1_sfd__h479985[9] && + !f1_sfd__h479985[8] && + !f1_sfd__h479985[7] && + !f1_sfd__h479985[6] && + !f1_sfd__h479985[5] && + !f1_sfd__h479985[4] && + !f1_sfd__h479985[3] && + !f1_sfd__h479985[2] && + !f1_sfd__h479985[1] && + !f1_sfd__h479985[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 = - !f3_sfd__h558316[21] && !f3_sfd__h558316[20] && - !f3_sfd__h558316[19] && - !f3_sfd__h558316[18] && - !f3_sfd__h558316[17] && - !f3_sfd__h558316[16] && - !f3_sfd__h558316[15] && - !f3_sfd__h558316[14] && - !f3_sfd__h558316[13] && - !f3_sfd__h558316[12] && - !f3_sfd__h558316[11] && - !f3_sfd__h558316[10] && - !f3_sfd__h558316[9] && - !f3_sfd__h558316[8] && - !f3_sfd__h558316[7] && - !f3_sfd__h558316[6] && - !f3_sfd__h558316[5] && - !f3_sfd__h558316[4] && - !f3_sfd__h558316[3] && - !f3_sfd__h558316[2] && - !f3_sfd__h558316[1] && - !f3_sfd__h558316[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 && + !f3_sfd__h558283[21] && !f3_sfd__h558283[20] && + !f3_sfd__h558283[19] && + !f3_sfd__h558283[18] && + !f3_sfd__h558283[17] && + !f3_sfd__h558283[16] && + !f3_sfd__h558283[15] && + !f3_sfd__h558283[14] && + !f3_sfd__h558283[13] && + !f3_sfd__h558283[12] && + !f3_sfd__h558283[11] && + !f3_sfd__h558283[10] && + !f3_sfd__h558283[9] && + !f3_sfd__h558283[8] && + !f3_sfd__h558283[7] && + !f3_sfd__h558283[6] && + !f3_sfd__h558283[5] && + !f3_sfd__h558283[4] && + !f3_sfd__h558283[3] && + !f3_sfd__h558283[2] && + !f3_sfd__h558283[1] && + !f3_sfd__h558283[0] ; + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 ; + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd0 || commitStage_commitTrap[3:0] == 4'd1 || @@ -24123,12 +24123,12 @@ module mkCore(CLK, (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14510 = - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14503 || + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 = + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 = + assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd14) && (!commitStage_commitTrap[4] || @@ -24145,25 +24145,25 @@ module mkCore(CLK, (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4247_4248_AND_NOT_ETC___d14700 = + assign NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 = !commitStage_rg_run_state && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 = + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181) && + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189) ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 = + !coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186) ; + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207) && + !coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213) && + !coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217) ; + !coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214) ; assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) && @@ -24642,7 +24642,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13269 = + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24652,9 +24652,9 @@ module mkCore(CLK, (!fetchStage$pipelines_0_first[75] || !fetchStage$pipelines_0_first[74])) && (fetchStage$pipelines_0_first[199:195] != 5'd13 || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265 && - !csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 = + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 && + !csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ; + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24666,7 +24666,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 = + assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -24678,195 +24678,195 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2730_ULE_1_4571_4612_OR_ETC___d14616 = - !csrf_prv_reg_read__2730_ULE_1___d14571 || + assign NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 = + !csrf_prv_reg_read__2727_ULE_1___d14567 || (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13735 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + (regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 = + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449) && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) && + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14011 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877 && - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 && + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108 = + fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395) && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 = + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 && + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14171 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ; + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14202 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 && + assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13265 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h651965 == 5'd0 && - imm__h651966 == 32'd0 || - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[11:10] != + rs1__h651905 == 5'd0 && + imm__h651906 == 32'd0 || + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13396 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374) ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13834 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ; + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14087 = + assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046) ? - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 : + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042) ? + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 : { 1'h0, - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 }, + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407 = + assign NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 = !fetchStage$pipelines_0_first[68] && - !checkForException___d12946[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13350 && + !checkForException___d12942[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_1_canDeq__2706_2707_O_ETC___d12715 = + assign NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 = !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13430 = + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428) ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13660 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424) ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13457 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 ; - assign NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d14124 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ; + assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14115 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 ; - assign NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 ; + assign NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13619[4] && - NOT_csrf_fs_reg_read__1527_EQ_0_2935_2936_OR_N_ETC___d13644 && + !checkForException___d13615[4] && + NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -24949,7 +24949,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 = + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -24960,8 +24960,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680 ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 ; + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -24972,14 +24972,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756 ; - assign NOT_regRenamingTable_rename_0_canRename__3333__ETC___d14103 = + fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 ; + assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722 = + assign NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -24990,58 +24990,58 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13038 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] && - !IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15]) ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357 = + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] && + !IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657 = + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797 ; - assign NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 ; + assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13646 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815 ; - assign NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_RDY_ETC___d14935 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 ; + assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 = (!rob$deqPort_0_canDeq || rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932) ; - assign NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 = + NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927) ; + assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25055,15 +25055,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] != 5'd19 && rob$deqPort_0_deq_data[186:182] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688 = + assign NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 != + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__4901_BIT_25_4902_4_ETC___d14932 = + assign NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -25077,18 +25077,18 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd20 || rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928 = + assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995 = + assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916 = @@ -25108,27 +25108,27 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h289495 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15608 = + x__h289463 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15564, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15582 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15573, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 = - { {4{f2_exp19011_MINUS_127__q176[7]}}, - f2_exp19011_MINUS_127__q176 } ; + { {4{f2_exp18978_MINUS_127__q176[7]}}, + f2_exp18978_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 ^ 12'h800) <= @@ -25138,8 +25138,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 = - { {4{f1_exp80017_MINUS_127__q136[7]}}, - f1_exp80017_MINUS_127__q136 } ; + { {4{f1_exp79984_MINUS_127__q136[7]}}, + f1_exp79984_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 ^ 12'h800) <= @@ -25149,8 +25149,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 = - { {4{f3_exp58315_MINUS_127__q153[7]}}, - f3_exp58315_MINUS_127__q153 } ; + { {4{f3_exp58282_MINUS_127__q153[7]}}, + f3_exp58282_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 ^ 12'h800) <= @@ -25235,15 +25235,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h352073 == 8'd0 && - (sfdin__h352067[56:34] == 23'd0 || guard__h343972 != 2'b0), + _theResult___fst_exp__h352040 == 8'd0 && + (sfdin__h352034[56:34] == 23'd0 || guard__h343939 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352670 == 8'd255 && - _theResult___fst_sfd__h352671 == 23'd0, + _theResult___fst_exp__h352637 == 8'd255 && + _theResult___fst_sfd__h352638 == 23'd0, 1'd0, - _theResult___fst_exp__h352073 != 8'd255 && - guard__h343972 != 2'b0 } ; + _theResult___fst_exp__h352040 != 8'd255 && + guard__h343939 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -25251,15 +25251,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397770 == 8'd0 && - (sfdin__h397764[56:34] == 23'd0 || guard__h389671 != 2'b0), + _theResult___fst_exp__h397737 == 8'd0 && + (sfdin__h397731[56:34] == 23'd0 || guard__h389638 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h398367 == 8'd255 && - _theResult___fst_sfd__h398368 == 23'd0, + _theResult___fst_exp__h398334 == 8'd255 && + _theResult___fst_sfd__h398335 == 23'd0, 1'd0, - _theResult___fst_exp__h397770 != 8'd255 && - guard__h389671 != 2'b0 } ; + _theResult___fst_exp__h397737 != 8'd255 && + guard__h389638 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -25267,15 +25267,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h443465 == 8'd0 && - (sfdin__h443459[56:34] == 23'd0 || guard__h435366 != 2'b0), + _theResult___fst_exp__h443432 == 8'd0 && + (sfdin__h443426[56:34] == 23'd0 || guard__h435333 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h444062 == 8'd255 && - _theResult___fst_sfd__h444063 == 23'd0, + _theResult___fst_exp__h444029 == 8'd255 && + _theResult___fst_sfd__h444030 == 23'd0, 1'd0, - _theResult___fst_exp__h443465 != 8'd255 && - guard__h435366 != 2'b0 } ; + _theResult___fst_exp__h443432 != 8'd255 && + guard__h435333 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ^ @@ -25283,37 +25283,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755 = { 3'd0, - _theResult___fst_exp__h508982 == 11'd0 && - (sfdin__h508976[56:5] == 52'd0 || guard__h500756 != 2'b0), + _theResult___fst_exp__h508949 == 11'd0 && + (sfdin__h508943[56:5] == 52'd0 || guard__h500723 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509814 == 11'd2047 && - _theResult___fst_sfd__h509815 == 52'd0, + _theResult___fst_exp__h509781 == 11'd2047 && + _theResult___fst_sfd__h509782 == 52'd0, 1'd0, - _theResult___fst_exp__h508982 != 11'd2047 && - guard__h500756 != 2'b0 } ; + _theResult___fst_exp__h508949 != 11'd2047 && + guard__h500723 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796 = { 3'd0, - _theResult___fst_exp__h547835 == 11'd0 && - (sfdin__h547829[56:5] == 52'd0 || guard__h539609 != 2'b0), + _theResult___fst_exp__h547802 == 11'd0 && + (sfdin__h547796[56:5] == 52'd0 || guard__h539576 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h548667 == 11'd2047 && - _theResult___fst_sfd__h548668 == 52'd0, + _theResult___fst_exp__h548634 == 11'd2047 && + _theResult___fst_sfd__h548635 == 52'd0, 1'd0, - _theResult___fst_exp__h547835 != 11'd2047 && - guard__h539609 != 2'b0 } ; + _theResult___fst_exp__h547802 != 11'd2047 && + guard__h539576 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840 = { 3'd0, - _theResult___fst_exp__h587139 == 11'd0 && - (sfdin__h587133[56:5] == 52'd0 || guard__h578913 != 2'b0), + _theResult___fst_exp__h587106 == 11'd0 && + (sfdin__h587100[56:5] == 52'd0 || guard__h578880 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587971 == 11'd2047 && - _theResult___fst_sfd__h587972 == 52'd0, + _theResult___fst_exp__h587938 == 11'd2047 && + _theResult___fst_sfd__h587939 == 52'd0, 1'd0, - _theResult___fst_exp__h587139 != 11'd2047 && - guard__h578913 != 2'b0 } ; + _theResult___fst_exp__h587106 != 11'd2047 && + guard__h578880 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ^ @@ -25331,15 +25331,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369839 == 8'd0 && - (sfdin__h369833[56:34] == 23'd0 || guard__h361611 != 2'b0), + _theResult___fst_exp__h369806 == 8'd0 && + (sfdin__h369800[56:34] == 23'd0 || guard__h361578 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h370436 == 8'd255 && - _theResult___fst_sfd__h370437 == 23'd0, + _theResult___fst_exp__h370403 == 8'd255 && + _theResult___fst_sfd__h370404 == 23'd0, 1'd0, - _theResult___fst_exp__h369839 != 8'd255 && - guard__h361611 != 2'b0 } ; + _theResult___fst_exp__h369806 != 8'd255 && + guard__h361578 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -25347,15 +25347,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h415536 == 8'd0 && - (sfdin__h415530[56:34] == 23'd0 || guard__h407308 != 2'b0), + _theResult___fst_exp__h415503 == 8'd0 && + (sfdin__h415497[56:34] == 23'd0 || guard__h407275 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h416133 == 8'd255 && - _theResult___fst_sfd__h416134 == 23'd0, + _theResult___fst_exp__h416100 == 8'd255 && + _theResult___fst_sfd__h416101 == 23'd0, 1'd0, - _theResult___fst_exp__h415536 != 8'd255 && - guard__h407308 != 2'b0 } ; + _theResult___fst_exp__h415503 != 8'd255 && + guard__h407275 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -25363,15 +25363,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h461231 == 8'd0 && - (sfdin__h461225[56:34] == 23'd0 || guard__h453003 != 2'b0), + _theResult___fst_exp__h461198 == 8'd0 && + (sfdin__h461192[56:34] == 23'd0 || guard__h452970 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461828 == 8'd255 && - _theResult___fst_sfd__h461829 == 23'd0, + _theResult___fst_exp__h461795 == 8'd255 && + _theResult___fst_sfd__h461796 == 23'd0, 1'd0, - _theResult___fst_exp__h461231 != 8'd255 && - guard__h453003 != 2'b0 } ; + _theResult___fst_exp__h461198 != 8'd255 && + guard__h452970 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ^ @@ -25385,37 +25385,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738 = { 3'd0, - _theResult___fst_exp__h499405 == 11'd0 && - guard__h491444 != 2'b0, + _theResult___fst_exp__h499372 == 11'd0 && + guard__h491411 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h500163 == 11'd2047 && - _theResult___fst_sfd__h500164 == 52'd0, + _theResult___fst_exp__h500130 == 11'd2047 && + _theResult___fst_sfd__h500131 == 52'd0, 1'd0, - _theResult___fst_exp__h499405 != 11'd2047 && - guard__h491444 != 2'b0 } ; + _theResult___fst_exp__h499372 != 11'd2047 && + guard__h491411 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779 = { 3'd0, - _theResult___fst_exp__h538258 == 11'd0 && - guard__h530297 != 2'b0, + _theResult___fst_exp__h538225 == 11'd0 && + guard__h530264 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h539016 == 11'd2047 && - _theResult___fst_sfd__h539017 == 52'd0, + _theResult___fst_exp__h538983 == 11'd2047 && + _theResult___fst_sfd__h538984 == 52'd0, 1'd0, - _theResult___fst_exp__h538258 != 11'd2047 && - guard__h530297 != 2'b0 } ; + _theResult___fst_exp__h538225 != 11'd2047 && + guard__h530264 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823 = { 3'd0, - _theResult___fst_exp__h577562 == 11'd0 && - guard__h569601 != 2'b0, + _theResult___fst_exp__h577529 == 11'd0 && + guard__h569568 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h578320 == 11'd2047 && - _theResult___fst_sfd__h578321 == 52'd0, + _theResult___fst_exp__h578287 == 11'd2047 && + _theResult___fst_sfd__h578288 == 52'd0, 1'd0, - _theResult___fst_exp__h577562 != 11'd2047 && - guard__h569601 != 2'b0 } ; + _theResult___fst_exp__h577529 != 11'd2047 && + guard__h569568 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ^ @@ -25451,15 +25451,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360729 == 8'd0 && - guard__h352681 != 2'b0, + _theResult___fst_exp__h360696 == 8'd0 && + guard__h352648 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h361252 == 8'd255 && - _theResult___fst_sfd__h361253 == 23'd0, + _theResult___fst_exp__h361219 == 8'd255 && + _theResult___fst_sfd__h361220 == 23'd0, 1'd0, - _theResult___fst_exp__h360729 != 8'd255 && - guard__h352681 != 2'b0 } ; + _theResult___fst_exp__h360696 != 8'd255 && + guard__h352648 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -25473,15 +25473,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h406426 == 8'd0 && - guard__h398378 != 2'b0, + _theResult___fst_exp__h406393 == 8'd0 && + guard__h398345 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406949 == 8'd255 && - _theResult___fst_sfd__h406950 == 23'd0, + _theResult___fst_exp__h406916 == 8'd255 && + _theResult___fst_sfd__h406917 == 23'd0, 1'd0, - _theResult___fst_exp__h406426 != 8'd255 && - guard__h398378 != 2'b0 } ; + _theResult___fst_exp__h406393 != 8'd255 && + guard__h398345 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -25495,73 +25495,71 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h452121 == 8'd0 && - guard__h444073 != 2'b0, + _theResult___fst_exp__h452088 == 8'd0 && + guard__h444040 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h452644 == 8'd255 && - _theResult___fst_sfd__h452645 == 23'd0, + _theResult___fst_exp__h452611 == 8'd255 && + _theResult___fst_sfd__h452612 == 23'd0, 1'd0, - _theResult___fst_exp__h452121 != 8'd255 && - guard__h444073 != 2'b0 } ; - assign _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739 = - { 1'd0, - csrf_debug_int_pend, - 2'b0, + _theResult___fst_exp__h452088 != 8'd255 && + guard__h444040 != 2'b0 } ; + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735 = + { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, 1'd0, csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1, csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ; - assign _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744 = - { _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12739, + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735, csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13750 = + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 || - NOT_regRenamingTable_rename_1_canRename__3460__ETC___d13722) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 || + NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 ; + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135 = - sfd__h519373 >> + sfd__h519340 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650 = - sfd__h480379 >> + sfd__h480346 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365 = - sfd__h558677 >> + sfd__h558644 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h336357 >> + sfd__h336324 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h382059 >> + sfd__h382026 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427754 >> + sfd__h427721 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591 = - medeleg_csr__read__h608188[i__h698137] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 = - mideleg_csr__read__h608283[i__h698297] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587 = + medeleg_csr__read__h608155[i__h698077] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 = + mideleg_csr__read__h608250[i__h698237] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -25967,51 +25965,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006 = 12'd3970 - { 7'd0, - f2_sfd__h519012[22] ? + f2_sfd__h518979[22] ? 5'd0 : - (f2_sfd__h519012[21] ? + (f2_sfd__h518979[21] ? 5'd1 : - (f2_sfd__h519012[20] ? + (f2_sfd__h518979[20] ? 5'd2 : - (f2_sfd__h519012[19] ? + (f2_sfd__h518979[19] ? 5'd3 : - (f2_sfd__h519012[18] ? + (f2_sfd__h518979[18] ? 5'd4 : - (f2_sfd__h519012[17] ? + (f2_sfd__h518979[17] ? 5'd5 : - (f2_sfd__h519012[16] ? + (f2_sfd__h518979[16] ? 5'd6 : - (f2_sfd__h519012[15] ? + (f2_sfd__h518979[15] ? 5'd7 : - (f2_sfd__h519012[14] ? + (f2_sfd__h518979[14] ? 5'd8 : - (f2_sfd__h519012[13] ? + (f2_sfd__h518979[13] ? 5'd9 : - (f2_sfd__h519012[12] ? + (f2_sfd__h518979[12] ? 5'd10 : - (f2_sfd__h519012[11] ? + (f2_sfd__h518979[11] ? 5'd11 : - (f2_sfd__h519012[10] ? + (f2_sfd__h518979[10] ? 5'd12 : - (f2_sfd__h519012[9] ? + (f2_sfd__h518979[9] ? 5'd13 : - (f2_sfd__h519012[8] ? + (f2_sfd__h518979[8] ? 5'd14 : - (f2_sfd__h519012[7] ? + (f2_sfd__h518979[7] ? 5'd15 : - (f2_sfd__h519012[6] ? + (f2_sfd__h518979[6] ? 5'd16 : - (f2_sfd__h519012[5] ? + (f2_sfd__h518979[5] ? 5'd17 : - (f2_sfd__h519012[4] ? + (f2_sfd__h518979[4] ? 5'd18 : - (f2_sfd__h519012[3] ? + (f2_sfd__h518979[3] ? 5'd19 : - (f2_sfd__h519012[2] ? + (f2_sfd__h518979[2] ? 5'd20 : - (f2_sfd__h519012[1] ? + (f2_sfd__h518979[1] ? 5'd21 : - (f2_sfd__h519012[0] ? + (f2_sfd__h518979[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 = @@ -26025,51 +26023,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506 = 12'd3970 - { 7'd0, - f1_sfd__h480018[22] ? + f1_sfd__h479985[22] ? 5'd0 : - (f1_sfd__h480018[21] ? + (f1_sfd__h479985[21] ? 5'd1 : - (f1_sfd__h480018[20] ? + (f1_sfd__h479985[20] ? 5'd2 : - (f1_sfd__h480018[19] ? + (f1_sfd__h479985[19] ? 5'd3 : - (f1_sfd__h480018[18] ? + (f1_sfd__h479985[18] ? 5'd4 : - (f1_sfd__h480018[17] ? + (f1_sfd__h479985[17] ? 5'd5 : - (f1_sfd__h480018[16] ? + (f1_sfd__h479985[16] ? 5'd6 : - (f1_sfd__h480018[15] ? + (f1_sfd__h479985[15] ? 5'd7 : - (f1_sfd__h480018[14] ? + (f1_sfd__h479985[14] ? 5'd8 : - (f1_sfd__h480018[13] ? + (f1_sfd__h479985[13] ? 5'd9 : - (f1_sfd__h480018[12] ? + (f1_sfd__h479985[12] ? 5'd10 : - (f1_sfd__h480018[11] ? + (f1_sfd__h479985[11] ? 5'd11 : - (f1_sfd__h480018[10] ? + (f1_sfd__h479985[10] ? 5'd12 : - (f1_sfd__h480018[9] ? + (f1_sfd__h479985[9] ? 5'd13 : - (f1_sfd__h480018[8] ? + (f1_sfd__h479985[8] ? 5'd14 : - (f1_sfd__h480018[7] ? + (f1_sfd__h479985[7] ? 5'd15 : - (f1_sfd__h480018[6] ? + (f1_sfd__h479985[6] ? 5'd16 : - (f1_sfd__h480018[5] ? + (f1_sfd__h479985[5] ? 5'd17 : - (f1_sfd__h480018[4] ? + (f1_sfd__h479985[4] ? 5'd18 : - (f1_sfd__h480018[3] ? + (f1_sfd__h479985[3] ? 5'd19 : - (f1_sfd__h480018[2] ? + (f1_sfd__h479985[2] ? 5'd20 : - (f1_sfd__h480018[1] ? + (f1_sfd__h479985[1] ? 5'd21 : - (f1_sfd__h480018[0] ? + (f1_sfd__h479985[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 = @@ -26083,51 +26081,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236 = 12'd3970 - { 7'd0, - f3_sfd__h558316[22] ? + f3_sfd__h558283[22] ? 5'd0 : - (f3_sfd__h558316[21] ? + (f3_sfd__h558283[21] ? 5'd1 : - (f3_sfd__h558316[20] ? + (f3_sfd__h558283[20] ? 5'd2 : - (f3_sfd__h558316[19] ? + (f3_sfd__h558283[19] ? 5'd3 : - (f3_sfd__h558316[18] ? + (f3_sfd__h558283[18] ? 5'd4 : - (f3_sfd__h558316[17] ? + (f3_sfd__h558283[17] ? 5'd5 : - (f3_sfd__h558316[16] ? + (f3_sfd__h558283[16] ? 5'd6 : - (f3_sfd__h558316[15] ? + (f3_sfd__h558283[15] ? 5'd7 : - (f3_sfd__h558316[14] ? + (f3_sfd__h558283[14] ? 5'd8 : - (f3_sfd__h558316[13] ? + (f3_sfd__h558283[13] ? 5'd9 : - (f3_sfd__h558316[12] ? + (f3_sfd__h558283[12] ? 5'd10 : - (f3_sfd__h558316[11] ? + (f3_sfd__h558283[11] ? 5'd11 : - (f3_sfd__h558316[10] ? + (f3_sfd__h558283[10] ? 5'd12 : - (f3_sfd__h558316[9] ? + (f3_sfd__h558283[9] ? 5'd13 : - (f3_sfd__h558316[8] ? + (f3_sfd__h558283[8] ? 5'd14 : - (f3_sfd__h558316[7] ? + (f3_sfd__h558283[7] ? 5'd15 : - (f3_sfd__h558316[6] ? + (f3_sfd__h558283[6] ? 5'd16 : - (f3_sfd__h558316[5] ? + (f3_sfd__h558283[5] ? 5'd17 : - (f3_sfd__h558316[4] ? + (f3_sfd__h558283[4] ? 5'd18 : - (f3_sfd__h558316[3] ? + (f3_sfd__h558283[3] ? 5'd19 : - (f3_sfd__h558316[2] ? + (f3_sfd__h558283[2] ? 5'd20 : - (f3_sfd__h558316[1] ? + (f3_sfd__h558283[1] ? 5'd21 : - (f3_sfd__h558316[0] ? + (f3_sfd__h558283[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 = @@ -26149,57 +26147,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h664143 == 1'd1 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 || - (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108) == + k__h664083 == 1'd1 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 || + (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ; assign _dfoo18 = - k__h664143 == 1'd0 && - fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 || - (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14108) == + k__h664083 == 1'd0 && + fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 || + (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14127 ; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || - NOT_commitStage_commitTrap_4249_BIT_4_4468_446_ETC___d14570 ; + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || + NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ; assign _dfoo24 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == + 6'd36 || + rob$deqPort_0_deq_data[186:182] == 5'd19 || + rob$deqPort_0_deq_data[186:182] == 5'd20 ; + assign _dfoo26 = + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo30 = + assign _dfoo32 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd8 || - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd18) || rob$deqPort_0_deq_data[186:182] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059 || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14113 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 || + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d14172 && + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -26274,1421 +26278,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h294400 = + assign _theResult_____2__h294368 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294679 : + next_deqP___1__h294647 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h302396 = + assign _theResult_____2__h302364 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302675 : + next_deqP___1__h302643 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h308390 = + assign _theResult_____2__h308358 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308956 : + next_deqP___1__h308924 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h316244 = + assign _theResult_____2__h316212 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316810 : + next_deqP___1__h316778 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h326588 = + assign _theResult_____2__h326556 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326867 : + next_deqP___1__h326835 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329813 = + assign _theResult_____2__h329781 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h330092 : + next_deqP___1__h330060 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343962 = - (value__h344584 == 54'd0) ? sfd__h336357 : 57'd1 ; - assign _theResult____h361601 = + assign _theResult____h343929 = + (value__h344551 == 54'd0) ? sfd__h336324 : 57'd1 ; + assign _theResult____h361568 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h362214 : - _theResult____h343962 ; - assign _theResult____h389661 = - (value__h390281 == 54'd0) ? sfd__h382059 : 57'd1 ; - assign _theResult____h407298 = + result__h362181 : + _theResult____h343929 ; + assign _theResult____h389628 = + (value__h390248 == 54'd0) ? sfd__h382026 : 57'd1 ; + assign _theResult____h407265 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407911 : - _theResult____h389661 ; - assign _theResult____h435356 = - (value__h435976 == 54'd0) ? sfd__h427754 : 57'd1 ; - assign _theResult____h452993 = + result__h407878 : + _theResult____h389628 ; + assign _theResult____h435323 = + (value__h435943 == 54'd0) ? sfd__h427721 : 57'd1 ; + assign _theResult____h452960 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h453606 : - _theResult____h435356 ; - assign _theResult____h500746 = + result__h453573 : + _theResult____h435323 ; + assign _theResult____h500713 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ^ 12'h800) < 12'd2105) ? - result__h501359 : - ((value__h484962 == 25'd0) ? sfd__h480379 : 57'd1) ; - assign _theResult____h539599 = + result__h501326 : + ((value__h484929 == 25'd0) ? sfd__h480346 : 57'd1) ; + assign _theResult____h539566 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ^ 12'h800) < 12'd2105) ? - result__h540212 : - ((value__h523815 == 25'd0) ? sfd__h519373 : 57'd1) ; - assign _theResult____h578903 = + result__h540179 : + ((value__h523782 == 25'd0) ? sfd__h519340 : 57'd1) ; + assign _theResult____h578870 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ^ 12'h800) < 12'd2105) ? - result__h579516 : - ((value__h563119 == 25'd0) ? sfd__h558677 : 57'd1) ; - assign _theResult____h647786 = + result__h579483 : + ((value__h563086 == 25'd0) ? sfd__h558644 : 57'd1) ; + assign _theResult____h647726 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h648311 : + enabled_ints___1__h648251 : 16'd0 ; - assign _theResult___exp__h352589 = - sfd__h352165[24] ? - ((_theResult___fst_exp__h352073 == 8'd254) ? + assign _theResult___exp__h352556 = + sfd__h352132[24] ? + ((_theResult___fst_exp__h352040 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379106) : - ((_theResult___fst_exp__h352073 == 8'd0 && - sfd__h352165[24:23] == 2'b01) ? + din_inc___2_exp__h379073) : + ((_theResult___fst_exp__h352040 == 8'd0 && + sfd__h352132[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h352073) ; - assign _theResult___exp__h361171 = - sfd__h360747[24] ? - ((_theResult___fst_exp__h360729 == 8'd254) ? + _theResult___fst_exp__h352040) ; + assign _theResult___exp__h361138 = + sfd__h360714[24] ? + ((_theResult___fst_exp__h360696 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379130) : - ((_theResult___fst_exp__h360729 == 8'd0 && - sfd__h360747[24:23] == 2'b01) ? + din_inc___2_exp__h379097) : + ((_theResult___fst_exp__h360696 == 8'd0 && + sfd__h360714[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360729) ; - assign _theResult___exp__h370355 = - sfd__h369931[24] ? - ((_theResult___fst_exp__h369839 == 8'd254) ? + _theResult___fst_exp__h360696) ; + assign _theResult___exp__h370322 = + sfd__h369898[24] ? + ((_theResult___fst_exp__h369806 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379160) : - ((_theResult___fst_exp__h369839 == 8'd0 && - sfd__h369931[24:23] == 2'b01) ? + din_inc___2_exp__h379127) : + ((_theResult___fst_exp__h369806 == 8'd0 && + sfd__h369898[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369839) ; - assign _theResult___exp__h378991 = - sfd__h378543[24] ? - ((_theResult___fst_exp__h378524 == 8'd254) ? + _theResult___fst_exp__h369806) ; + assign _theResult___exp__h378958 = + sfd__h378510[24] ? + ((_theResult___fst_exp__h378491 == 8'd254) ? 8'd255 : - din_inc___2_exp__h379184) : - ((_theResult___fst_exp__h378524 == 8'd0 && - sfd__h378543[24:23] == 2'b01) ? + din_inc___2_exp__h379151) : + ((_theResult___fst_exp__h378491 == 8'd0 && + sfd__h378510[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h378524) ; - assign _theResult___exp__h379093 = + _theResult___fst_exp__h378491) ; + assign _theResult___exp__h379060 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h379084 ; - assign _theResult___exp__h398286 = - sfd__h397862[24] ? - ((_theResult___fst_exp__h397770 == 8'd254) ? + _theResult___fst_exp__h379051 ; + assign _theResult___exp__h398253 = + sfd__h397829[24] ? + ((_theResult___fst_exp__h397737 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424803) : - ((_theResult___fst_exp__h397770 == 8'd0 && - sfd__h397862[24:23] == 2'b01) ? + din_inc___2_exp__h424770) : + ((_theResult___fst_exp__h397737 == 8'd0 && + sfd__h397829[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397770) ; - assign _theResult___exp__h406868 = - sfd__h406444[24] ? - ((_theResult___fst_exp__h406426 == 8'd254) ? + _theResult___fst_exp__h397737) ; + assign _theResult___exp__h406835 = + sfd__h406411[24] ? + ((_theResult___fst_exp__h406393 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424827) : - ((_theResult___fst_exp__h406426 == 8'd0 && - sfd__h406444[24:23] == 2'b01) ? + din_inc___2_exp__h424794) : + ((_theResult___fst_exp__h406393 == 8'd0 && + sfd__h406411[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h406426) ; - assign _theResult___exp__h416052 = - sfd__h415628[24] ? - ((_theResult___fst_exp__h415536 == 8'd254) ? + _theResult___fst_exp__h406393) ; + assign _theResult___exp__h416019 = + sfd__h415595[24] ? + ((_theResult___fst_exp__h415503 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424857) : - ((_theResult___fst_exp__h415536 == 8'd0 && - sfd__h415628[24:23] == 2'b01) ? + din_inc___2_exp__h424824) : + ((_theResult___fst_exp__h415503 == 8'd0 && + sfd__h415595[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h415536) ; - assign _theResult___exp__h424688 = - sfd__h424240[24] ? - ((_theResult___fst_exp__h424221 == 8'd254) ? + _theResult___fst_exp__h415503) ; + assign _theResult___exp__h424655 = + sfd__h424207[24] ? + ((_theResult___fst_exp__h424188 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424881) : - ((_theResult___fst_exp__h424221 == 8'd0 && - sfd__h424240[24:23] == 2'b01) ? + din_inc___2_exp__h424848) : + ((_theResult___fst_exp__h424188 == 8'd0 && + sfd__h424207[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h424221) ; - assign _theResult___exp__h424790 = + _theResult___fst_exp__h424188) ; + assign _theResult___exp__h424757 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424781 ; - assign _theResult___exp__h443981 = - sfd__h443557[24] ? - ((_theResult___fst_exp__h443465 == 8'd254) ? + _theResult___fst_exp__h424748 ; + assign _theResult___exp__h443948 = + sfd__h443524[24] ? + ((_theResult___fst_exp__h443432 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470498) : - ((_theResult___fst_exp__h443465 == 8'd0 && - sfd__h443557[24:23] == 2'b01) ? + din_inc___2_exp__h470465) : + ((_theResult___fst_exp__h443432 == 8'd0 && + sfd__h443524[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h443465) ; - assign _theResult___exp__h452563 = - sfd__h452139[24] ? - ((_theResult___fst_exp__h452121 == 8'd254) ? + _theResult___fst_exp__h443432) ; + assign _theResult___exp__h452530 = + sfd__h452106[24] ? + ((_theResult___fst_exp__h452088 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470522) : - ((_theResult___fst_exp__h452121 == 8'd0 && - sfd__h452139[24:23] == 2'b01) ? + din_inc___2_exp__h470489) : + ((_theResult___fst_exp__h452088 == 8'd0 && + sfd__h452106[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h452121) ; - assign _theResult___exp__h461747 = - sfd__h461323[24] ? - ((_theResult___fst_exp__h461231 == 8'd254) ? + _theResult___fst_exp__h452088) ; + assign _theResult___exp__h461714 = + sfd__h461290[24] ? + ((_theResult___fst_exp__h461198 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470552) : - ((_theResult___fst_exp__h461231 == 8'd0 && - sfd__h461323[24:23] == 2'b01) ? + din_inc___2_exp__h470519) : + ((_theResult___fst_exp__h461198 == 8'd0 && + sfd__h461290[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h461231) ; - assign _theResult___exp__h470383 = - sfd__h469935[24] ? - ((_theResult___fst_exp__h469916 == 8'd254) ? + _theResult___fst_exp__h461198) ; + assign _theResult___exp__h470350 = + sfd__h469902[24] ? + ((_theResult___fst_exp__h469883 == 8'd254) ? 8'd255 : - din_inc___2_exp__h470576) : - ((_theResult___fst_exp__h469916 == 8'd0 && - sfd__h469935[24:23] == 2'b01) ? + din_inc___2_exp__h470543) : + ((_theResult___fst_exp__h469883 == 8'd0 && + sfd__h469902[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469916) ; - assign _theResult___exp__h470485 = + _theResult___fst_exp__h469883) ; + assign _theResult___exp__h470452 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h470476 ; - assign _theResult___exp__h500060 = - sfd__h499423[53] ? - ((_theResult___fst_exp__h499405 == 11'd2046) ? + _theResult___fst_exp__h470443 ; + assign _theResult___exp__h500027 = + sfd__h499390[53] ? + ((_theResult___fst_exp__h499372 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518655) : - ((_theResult___fst_exp__h499405 == 11'd0 && - sfd__h499423[53:52] == 2'b01) ? + din_inc___2_exp__h518622) : + ((_theResult___fst_exp__h499372 == 11'd0 && + sfd__h499390[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h499405) ; - assign _theResult___exp__h509711 = - sfd__h509074[53] ? - ((_theResult___fst_exp__h508982 == 11'd2046) ? + _theResult___fst_exp__h499372) ; + assign _theResult___exp__h509678 = + sfd__h509041[53] ? + ((_theResult___fst_exp__h508949 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518690) : - ((_theResult___fst_exp__h508982 == 11'd0 && - sfd__h509074[53:52] == 2'b01) ? + din_inc___2_exp__h518657) : + ((_theResult___fst_exp__h508949 == 11'd0 && + sfd__h509041[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508982) ; - assign _theResult___exp__h518495 = - sfd__h517834[53] ? - ((_theResult___fst_exp__h517815 == 11'd2046) ? + _theResult___fst_exp__h508949) ; + assign _theResult___exp__h518462 = + sfd__h517801[53] ? + ((_theResult___fst_exp__h517782 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h518716) : - ((_theResult___fst_exp__h517815 == 11'd0 && - sfd__h517834[53:52] == 2'b01) ? + din_inc___2_exp__h518683) : + ((_theResult___fst_exp__h517782 == 11'd0 && + sfd__h517801[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517815) ; - assign _theResult___exp__h538913 = - sfd__h538276[53] ? - ((_theResult___fst_exp__h538258 == 11'd2046) ? + _theResult___fst_exp__h517782) ; + assign _theResult___exp__h538880 = + sfd__h538243[53] ? + ((_theResult___fst_exp__h538225 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557508) : - ((_theResult___fst_exp__h538258 == 11'd0 && - sfd__h538276[53:52] == 2'b01) ? + din_inc___2_exp__h557475) : + ((_theResult___fst_exp__h538225 == 11'd0 && + sfd__h538243[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h538258) ; - assign _theResult___exp__h548564 = - sfd__h547927[53] ? - ((_theResult___fst_exp__h547835 == 11'd2046) ? + _theResult___fst_exp__h538225) ; + assign _theResult___exp__h548531 = + sfd__h547894[53] ? + ((_theResult___fst_exp__h547802 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557543) : - ((_theResult___fst_exp__h547835 == 11'd0 && - sfd__h547927[53:52] == 2'b01) ? + din_inc___2_exp__h557510) : + ((_theResult___fst_exp__h547802 == 11'd0 && + sfd__h547894[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547835) ; - assign _theResult___exp__h557348 = - sfd__h556687[53] ? - ((_theResult___fst_exp__h556668 == 11'd2046) ? + _theResult___fst_exp__h547802) ; + assign _theResult___exp__h557315 = + sfd__h556654[53] ? + ((_theResult___fst_exp__h556635 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h557569) : - ((_theResult___fst_exp__h556668 == 11'd0 && - sfd__h556687[53:52] == 2'b01) ? + din_inc___2_exp__h557536) : + ((_theResult___fst_exp__h556635 == 11'd0 && + sfd__h556654[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h556668) ; - assign _theResult___exp__h578217 = - sfd__h577580[53] ? - ((_theResult___fst_exp__h577562 == 11'd2046) ? + _theResult___fst_exp__h556635) ; + assign _theResult___exp__h578184 = + sfd__h577547[53] ? + ((_theResult___fst_exp__h577529 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596812) : - ((_theResult___fst_exp__h577562 == 11'd0 && - sfd__h577580[53:52] == 2'b01) ? + din_inc___2_exp__h596779) : + ((_theResult___fst_exp__h577529 == 11'd0 && + sfd__h577547[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h577562) ; - assign _theResult___exp__h587868 = - sfd__h587231[53] ? - ((_theResult___fst_exp__h587139 == 11'd2046) ? + _theResult___fst_exp__h577529) ; + assign _theResult___exp__h587835 = + sfd__h587198[53] ? + ((_theResult___fst_exp__h587106 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596847) : - ((_theResult___fst_exp__h587139 == 11'd0 && - sfd__h587231[53:52] == 2'b01) ? + din_inc___2_exp__h596814) : + ((_theResult___fst_exp__h587106 == 11'd0 && + sfd__h587198[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h587139) ; - assign _theResult___exp__h596652 = - sfd__h595991[53] ? - ((_theResult___fst_exp__h595972 == 11'd2046) ? + _theResult___fst_exp__h587106) ; + assign _theResult___exp__h596619 = + sfd__h595958[53] ? + ((_theResult___fst_exp__h595939 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h596873) : - ((_theResult___fst_exp__h595972 == 11'd0 && - sfd__h595991[53:52] == 2'b01) ? + din_inc___2_exp__h596840) : + ((_theResult___fst_exp__h595939 == 11'd0 && + sfd__h595958[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595972) ; - assign _theResult___fst__h601247 = - a__h600825[63] ? a___1__h601252 : a__h600825 ; - assign _theResult___fst_exp__h352073 = - _theResult____h343962[56] ? + _theResult___fst_exp__h595939) ; + assign _theResult___fst__h601214 = + a__h600792[63] ? a___1__h601219 : a__h600792 ; + assign _theResult___fst_exp__h352040 = + _theResult____h343929[56] ? 8'd2 : - _theResult___fst_exp__h352147 ; - assign _theResult___fst_exp__h352138 = + _theResult___fst_exp__h352114 ; + assign _theResult___fst_exp__h352105 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h352144 = - (!_theResult____h343962[56] && !_theResult____h343962[55] && - !_theResult____h343962[54] && - !_theResult____h343962[53] && - !_theResult____h343962[52] && - !_theResult____h343962[51] && - !_theResult____h343962[50] && - !_theResult____h343962[49] && - !_theResult____h343962[48] && - !_theResult____h343962[47] && - !_theResult____h343962[46] && - !_theResult____h343962[45] && - !_theResult____h343962[44] && - !_theResult____h343962[43] && - !_theResult____h343962[42] && - !_theResult____h343962[41] && - !_theResult____h343962[40] && - !_theResult____h343962[39] && - !_theResult____h343962[38] && - !_theResult____h343962[37] && - !_theResult____h343962[36] && - !_theResult____h343962[35] && - !_theResult____h343962[34] && - !_theResult____h343962[33] && - !_theResult____h343962[32] && - !_theResult____h343962[31] && - !_theResult____h343962[30] && - !_theResult____h343962[29] && - !_theResult____h343962[28] && - !_theResult____h343962[27] && - !_theResult____h343962[26] && - !_theResult____h343962[25] && - !_theResult____h343962[24] && - !_theResult____h343962[23] && - !_theResult____h343962[22] && - !_theResult____h343962[21] && - !_theResult____h343962[20] && - !_theResult____h343962[19] && - !_theResult____h343962[18] && - !_theResult____h343962[17] && - !_theResult____h343962[16] && - !_theResult____h343962[15] && - !_theResult____h343962[14] && - !_theResult____h343962[13] && - !_theResult____h343962[12] && - !_theResult____h343962[11] && - !_theResult____h343962[10] && - !_theResult____h343962[9] && - !_theResult____h343962[8] && - !_theResult____h343962[7] && - !_theResult____h343962[6] && - !_theResult____h343962[5] && - !_theResult____h343962[4] && - !_theResult____h343962[3] && - !_theResult____h343962[2] && - !_theResult____h343962[1] && - !_theResult____h343962[0] || + assign _theResult___fst_exp__h352111 = + (!_theResult____h343929[56] && !_theResult____h343929[55] && + !_theResult____h343929[54] && + !_theResult____h343929[53] && + !_theResult____h343929[52] && + !_theResult____h343929[51] && + !_theResult____h343929[50] && + !_theResult____h343929[49] && + !_theResult____h343929[48] && + !_theResult____h343929[47] && + !_theResult____h343929[46] && + !_theResult____h343929[45] && + !_theResult____h343929[44] && + !_theResult____h343929[43] && + !_theResult____h343929[42] && + !_theResult____h343929[41] && + !_theResult____h343929[40] && + !_theResult____h343929[39] && + !_theResult____h343929[38] && + !_theResult____h343929[37] && + !_theResult____h343929[36] && + !_theResult____h343929[35] && + !_theResult____h343929[34] && + !_theResult____h343929[33] && + !_theResult____h343929[32] && + !_theResult____h343929[31] && + !_theResult____h343929[30] && + !_theResult____h343929[29] && + !_theResult____h343929[28] && + !_theResult____h343929[27] && + !_theResult____h343929[26] && + !_theResult____h343929[25] && + !_theResult____h343929[24] && + !_theResult____h343929[23] && + !_theResult____h343929[22] && + !_theResult____h343929[21] && + !_theResult____h343929[20] && + !_theResult____h343929[19] && + !_theResult____h343929[18] && + !_theResult____h343929[17] && + !_theResult____h343929[16] && + !_theResult____h343929[15] && + !_theResult____h343929[14] && + !_theResult____h343929[13] && + !_theResult____h343929[12] && + !_theResult____h343929[11] && + !_theResult____h343929[10] && + !_theResult____h343929[9] && + !_theResult____h343929[8] && + !_theResult____h343929[7] && + !_theResult____h343929[6] && + !_theResult____h343929[5] && + !_theResult____h343929[4] && + !_theResult____h343929[3] && + !_theResult____h343929[2] && + !_theResult____h343929[1] && + !_theResult____h343929[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h352138 ; - assign _theResult___fst_exp__h352147 = - (!_theResult____h343962[56] && _theResult____h343962[55]) ? + _theResult___fst_exp__h352105 ; + assign _theResult___fst_exp__h352114 = + (!_theResult____h343929[56] && _theResult____h343929[55]) ? 8'd1 : - _theResult___fst_exp__h352144 ; - assign _theResult___fst_exp__h352670 = - (_theResult___fst_exp__h352073 == 8'd255) ? - _theResult___fst_exp__h352073 : - _theResult___fst_exp__h352667 ; - assign _theResult___fst_exp__h360720 = + _theResult___fst_exp__h352111 ; + assign _theResult___fst_exp__h352637 = + (_theResult___fst_exp__h352040 == 8'd255) ? + _theResult___fst_exp__h352040 : + _theResult___fst_exp__h352634 ; + assign _theResult___fst_exp__h360687 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360726 = + assign _theResult___fst_exp__h360693 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360720 ; - assign _theResult___fst_exp__h360729 = + _theResult___fst_exp__h360687 ; + assign _theResult___fst_exp__h360696 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360726 : + _theResult___fst_exp__h360693 : 8'd129 ; - assign _theResult___fst_exp__h361252 = - (_theResult___fst_exp__h360729 == 8'd255) ? - _theResult___fst_exp__h360729 : - _theResult___fst_exp__h361249 ; - assign _theResult___fst_exp__h369839 = - _theResult____h361601[56] ? + assign _theResult___fst_exp__h361219 = + (_theResult___fst_exp__h360696 == 8'd255) ? + _theResult___fst_exp__h360696 : + _theResult___fst_exp__h361216 ; + assign _theResult___fst_exp__h369806 = + _theResult____h361568[56] ? 8'd2 : - _theResult___fst_exp__h369913 ; - assign _theResult___fst_exp__h369904 = + _theResult___fst_exp__h369880 ; + assign _theResult___fst_exp__h369871 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369910 = - (!_theResult____h361601[56] && !_theResult____h361601[55] && - !_theResult____h361601[54] && - !_theResult____h361601[53] && - !_theResult____h361601[52] && - !_theResult____h361601[51] && - !_theResult____h361601[50] && - !_theResult____h361601[49] && - !_theResult____h361601[48] && - !_theResult____h361601[47] && - !_theResult____h361601[46] && - !_theResult____h361601[45] && - !_theResult____h361601[44] && - !_theResult____h361601[43] && - !_theResult____h361601[42] && - !_theResult____h361601[41] && - !_theResult____h361601[40] && - !_theResult____h361601[39] && - !_theResult____h361601[38] && - !_theResult____h361601[37] && - !_theResult____h361601[36] && - !_theResult____h361601[35] && - !_theResult____h361601[34] && - !_theResult____h361601[33] && - !_theResult____h361601[32] && - !_theResult____h361601[31] && - !_theResult____h361601[30] && - !_theResult____h361601[29] && - !_theResult____h361601[28] && - !_theResult____h361601[27] && - !_theResult____h361601[26] && - !_theResult____h361601[25] && - !_theResult____h361601[24] && - !_theResult____h361601[23] && - !_theResult____h361601[22] && - !_theResult____h361601[21] && - !_theResult____h361601[20] && - !_theResult____h361601[19] && - !_theResult____h361601[18] && - !_theResult____h361601[17] && - !_theResult____h361601[16] && - !_theResult____h361601[15] && - !_theResult____h361601[14] && - !_theResult____h361601[13] && - !_theResult____h361601[12] && - !_theResult____h361601[11] && - !_theResult____h361601[10] && - !_theResult____h361601[9] && - !_theResult____h361601[8] && - !_theResult____h361601[7] && - !_theResult____h361601[6] && - !_theResult____h361601[5] && - !_theResult____h361601[4] && - !_theResult____h361601[3] && - !_theResult____h361601[2] && - !_theResult____h361601[1] && - !_theResult____h361601[0] || + assign _theResult___fst_exp__h369877 = + (!_theResult____h361568[56] && !_theResult____h361568[55] && + !_theResult____h361568[54] && + !_theResult____h361568[53] && + !_theResult____h361568[52] && + !_theResult____h361568[51] && + !_theResult____h361568[50] && + !_theResult____h361568[49] && + !_theResult____h361568[48] && + !_theResult____h361568[47] && + !_theResult____h361568[46] && + !_theResult____h361568[45] && + !_theResult____h361568[44] && + !_theResult____h361568[43] && + !_theResult____h361568[42] && + !_theResult____h361568[41] && + !_theResult____h361568[40] && + !_theResult____h361568[39] && + !_theResult____h361568[38] && + !_theResult____h361568[37] && + !_theResult____h361568[36] && + !_theResult____h361568[35] && + !_theResult____h361568[34] && + !_theResult____h361568[33] && + !_theResult____h361568[32] && + !_theResult____h361568[31] && + !_theResult____h361568[30] && + !_theResult____h361568[29] && + !_theResult____h361568[28] && + !_theResult____h361568[27] && + !_theResult____h361568[26] && + !_theResult____h361568[25] && + !_theResult____h361568[24] && + !_theResult____h361568[23] && + !_theResult____h361568[22] && + !_theResult____h361568[21] && + !_theResult____h361568[20] && + !_theResult____h361568[19] && + !_theResult____h361568[18] && + !_theResult____h361568[17] && + !_theResult____h361568[16] && + !_theResult____h361568[15] && + !_theResult____h361568[14] && + !_theResult____h361568[13] && + !_theResult____h361568[12] && + !_theResult____h361568[11] && + !_theResult____h361568[10] && + !_theResult____h361568[9] && + !_theResult____h361568[8] && + !_theResult____h361568[7] && + !_theResult____h361568[6] && + !_theResult____h361568[5] && + !_theResult____h361568[4] && + !_theResult____h361568[3] && + !_theResult____h361568[2] && + !_theResult____h361568[1] && + !_theResult____h361568[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369904 ; - assign _theResult___fst_exp__h369913 = - (!_theResult____h361601[56] && _theResult____h361601[55]) ? + _theResult___fst_exp__h369871 ; + assign _theResult___fst_exp__h369880 = + (!_theResult____h361568[56] && _theResult____h361568[55]) ? 8'd1 : - _theResult___fst_exp__h369910 ; - assign _theResult___fst_exp__h370436 = - (_theResult___fst_exp__h369839 == 8'd255) ? - _theResult___fst_exp__h369839 : - _theResult___fst_exp__h370433 ; - assign _theResult___fst_exp__h378476 = + _theResult___fst_exp__h369877 ; + assign _theResult___fst_exp__h370403 = + (_theResult___fst_exp__h369806 == 8'd255) ? + _theResult___fst_exp__h369806 : + _theResult___fst_exp__h370400 ; + assign _theResult___fst_exp__h378443 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h378515 = + assign _theResult___fst_exp__h378482 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h378521 = + assign _theResult___fst_exp__h378488 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h378515 ; - assign _theResult___fst_exp__h378524 = + _theResult___fst_exp__h378482 ; + assign _theResult___fst_exp__h378491 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h378521 : - _theResult___fst_exp__h378476 ; - assign _theResult___fst_exp__h379072 = - (_theResult___fst_exp__h378524 == 8'd255) ? - _theResult___fst_exp__h378524 : - _theResult___fst_exp__h379069 ; - assign _theResult___fst_exp__h379081 = + _theResult___fst_exp__h378488 : + _theResult___fst_exp__h378443 ; + assign _theResult___fst_exp__h379039 = + (_theResult___fst_exp__h378491 == 8'd255) ? + _theResult___fst_exp__h378491 : + _theResult___fst_exp__h379036 ; + assign _theResult___fst_exp__h379048 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h361255 : - _theResult___fst_exp__h343944) : + _theResult___snd_fst_exp__h361222 : + _theResult___fst_exp__h343911) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h379075 : - _theResult___fst_exp__h343944) ; - assign _theResult___fst_exp__h379084 = + _theResult___snd_fst_exp__h379042 : + _theResult___fst_exp__h343911) ; + assign _theResult___fst_exp__h379051 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h379081 ; - assign _theResult___fst_exp__h397770 = - _theResult____h389661[56] ? + _theResult___fst_exp__h379048 ; + assign _theResult___fst_exp__h397737 = + _theResult____h389628[56] ? 8'd2 : - _theResult___fst_exp__h397844 ; - assign _theResult___fst_exp__h397835 = + _theResult___fst_exp__h397811 ; + assign _theResult___fst_exp__h397802 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397841 = - (!_theResult____h389661[56] && !_theResult____h389661[55] && - !_theResult____h389661[54] && - !_theResult____h389661[53] && - !_theResult____h389661[52] && - !_theResult____h389661[51] && - !_theResult____h389661[50] && - !_theResult____h389661[49] && - !_theResult____h389661[48] && - !_theResult____h389661[47] && - !_theResult____h389661[46] && - !_theResult____h389661[45] && - !_theResult____h389661[44] && - !_theResult____h389661[43] && - !_theResult____h389661[42] && - !_theResult____h389661[41] && - !_theResult____h389661[40] && - !_theResult____h389661[39] && - !_theResult____h389661[38] && - !_theResult____h389661[37] && - !_theResult____h389661[36] && - !_theResult____h389661[35] && - !_theResult____h389661[34] && - !_theResult____h389661[33] && - !_theResult____h389661[32] && - !_theResult____h389661[31] && - !_theResult____h389661[30] && - !_theResult____h389661[29] && - !_theResult____h389661[28] && - !_theResult____h389661[27] && - !_theResult____h389661[26] && - !_theResult____h389661[25] && - !_theResult____h389661[24] && - !_theResult____h389661[23] && - !_theResult____h389661[22] && - !_theResult____h389661[21] && - !_theResult____h389661[20] && - !_theResult____h389661[19] && - !_theResult____h389661[18] && - !_theResult____h389661[17] && - !_theResult____h389661[16] && - !_theResult____h389661[15] && - !_theResult____h389661[14] && - !_theResult____h389661[13] && - !_theResult____h389661[12] && - !_theResult____h389661[11] && - !_theResult____h389661[10] && - !_theResult____h389661[9] && - !_theResult____h389661[8] && - !_theResult____h389661[7] && - !_theResult____h389661[6] && - !_theResult____h389661[5] && - !_theResult____h389661[4] && - !_theResult____h389661[3] && - !_theResult____h389661[2] && - !_theResult____h389661[1] && - !_theResult____h389661[0] || + assign _theResult___fst_exp__h397808 = + (!_theResult____h389628[56] && !_theResult____h389628[55] && + !_theResult____h389628[54] && + !_theResult____h389628[53] && + !_theResult____h389628[52] && + !_theResult____h389628[51] && + !_theResult____h389628[50] && + !_theResult____h389628[49] && + !_theResult____h389628[48] && + !_theResult____h389628[47] && + !_theResult____h389628[46] && + !_theResult____h389628[45] && + !_theResult____h389628[44] && + !_theResult____h389628[43] && + !_theResult____h389628[42] && + !_theResult____h389628[41] && + !_theResult____h389628[40] && + !_theResult____h389628[39] && + !_theResult____h389628[38] && + !_theResult____h389628[37] && + !_theResult____h389628[36] && + !_theResult____h389628[35] && + !_theResult____h389628[34] && + !_theResult____h389628[33] && + !_theResult____h389628[32] && + !_theResult____h389628[31] && + !_theResult____h389628[30] && + !_theResult____h389628[29] && + !_theResult____h389628[28] && + !_theResult____h389628[27] && + !_theResult____h389628[26] && + !_theResult____h389628[25] && + !_theResult____h389628[24] && + !_theResult____h389628[23] && + !_theResult____h389628[22] && + !_theResult____h389628[21] && + !_theResult____h389628[20] && + !_theResult____h389628[19] && + !_theResult____h389628[18] && + !_theResult____h389628[17] && + !_theResult____h389628[16] && + !_theResult____h389628[15] && + !_theResult____h389628[14] && + !_theResult____h389628[13] && + !_theResult____h389628[12] && + !_theResult____h389628[11] && + !_theResult____h389628[10] && + !_theResult____h389628[9] && + !_theResult____h389628[8] && + !_theResult____h389628[7] && + !_theResult____h389628[6] && + !_theResult____h389628[5] && + !_theResult____h389628[4] && + !_theResult____h389628[3] && + !_theResult____h389628[2] && + !_theResult____h389628[1] && + !_theResult____h389628[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397835 ; - assign _theResult___fst_exp__h397844 = - (!_theResult____h389661[56] && _theResult____h389661[55]) ? + _theResult___fst_exp__h397802 ; + assign _theResult___fst_exp__h397811 = + (!_theResult____h389628[56] && _theResult____h389628[55]) ? 8'd1 : - _theResult___fst_exp__h397841 ; - assign _theResult___fst_exp__h398367 = - (_theResult___fst_exp__h397770 == 8'd255) ? - _theResult___fst_exp__h397770 : - _theResult___fst_exp__h398364 ; - assign _theResult___fst_exp__h406417 = + _theResult___fst_exp__h397808 ; + assign _theResult___fst_exp__h398334 = + (_theResult___fst_exp__h397737 == 8'd255) ? + _theResult___fst_exp__h397737 : + _theResult___fst_exp__h398331 ; + assign _theResult___fst_exp__h406384 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h406423 = + assign _theResult___fst_exp__h406390 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h406417 ; - assign _theResult___fst_exp__h406426 = + _theResult___fst_exp__h406384 ; + assign _theResult___fst_exp__h406393 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h406423 : + _theResult___fst_exp__h406390 : 8'd129 ; - assign _theResult___fst_exp__h406949 = - (_theResult___fst_exp__h406426 == 8'd255) ? - _theResult___fst_exp__h406426 : - _theResult___fst_exp__h406946 ; - assign _theResult___fst_exp__h415536 = - _theResult____h407298[56] ? + assign _theResult___fst_exp__h406916 = + (_theResult___fst_exp__h406393 == 8'd255) ? + _theResult___fst_exp__h406393 : + _theResult___fst_exp__h406913 ; + assign _theResult___fst_exp__h415503 = + _theResult____h407265[56] ? 8'd2 : - _theResult___fst_exp__h415610 ; - assign _theResult___fst_exp__h415601 = + _theResult___fst_exp__h415577 ; + assign _theResult___fst_exp__h415568 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h415607 = - (!_theResult____h407298[56] && !_theResult____h407298[55] && - !_theResult____h407298[54] && - !_theResult____h407298[53] && - !_theResult____h407298[52] && - !_theResult____h407298[51] && - !_theResult____h407298[50] && - !_theResult____h407298[49] && - !_theResult____h407298[48] && - !_theResult____h407298[47] && - !_theResult____h407298[46] && - !_theResult____h407298[45] && - !_theResult____h407298[44] && - !_theResult____h407298[43] && - !_theResult____h407298[42] && - !_theResult____h407298[41] && - !_theResult____h407298[40] && - !_theResult____h407298[39] && - !_theResult____h407298[38] && - !_theResult____h407298[37] && - !_theResult____h407298[36] && - !_theResult____h407298[35] && - !_theResult____h407298[34] && - !_theResult____h407298[33] && - !_theResult____h407298[32] && - !_theResult____h407298[31] && - !_theResult____h407298[30] && - !_theResult____h407298[29] && - !_theResult____h407298[28] && - !_theResult____h407298[27] && - !_theResult____h407298[26] && - !_theResult____h407298[25] && - !_theResult____h407298[24] && - !_theResult____h407298[23] && - !_theResult____h407298[22] && - !_theResult____h407298[21] && - !_theResult____h407298[20] && - !_theResult____h407298[19] && - !_theResult____h407298[18] && - !_theResult____h407298[17] && - !_theResult____h407298[16] && - !_theResult____h407298[15] && - !_theResult____h407298[14] && - !_theResult____h407298[13] && - !_theResult____h407298[12] && - !_theResult____h407298[11] && - !_theResult____h407298[10] && - !_theResult____h407298[9] && - !_theResult____h407298[8] && - !_theResult____h407298[7] && - !_theResult____h407298[6] && - !_theResult____h407298[5] && - !_theResult____h407298[4] && - !_theResult____h407298[3] && - !_theResult____h407298[2] && - !_theResult____h407298[1] && - !_theResult____h407298[0] || + assign _theResult___fst_exp__h415574 = + (!_theResult____h407265[56] && !_theResult____h407265[55] && + !_theResult____h407265[54] && + !_theResult____h407265[53] && + !_theResult____h407265[52] && + !_theResult____h407265[51] && + !_theResult____h407265[50] && + !_theResult____h407265[49] && + !_theResult____h407265[48] && + !_theResult____h407265[47] && + !_theResult____h407265[46] && + !_theResult____h407265[45] && + !_theResult____h407265[44] && + !_theResult____h407265[43] && + !_theResult____h407265[42] && + !_theResult____h407265[41] && + !_theResult____h407265[40] && + !_theResult____h407265[39] && + !_theResult____h407265[38] && + !_theResult____h407265[37] && + !_theResult____h407265[36] && + !_theResult____h407265[35] && + !_theResult____h407265[34] && + !_theResult____h407265[33] && + !_theResult____h407265[32] && + !_theResult____h407265[31] && + !_theResult____h407265[30] && + !_theResult____h407265[29] && + !_theResult____h407265[28] && + !_theResult____h407265[27] && + !_theResult____h407265[26] && + !_theResult____h407265[25] && + !_theResult____h407265[24] && + !_theResult____h407265[23] && + !_theResult____h407265[22] && + !_theResult____h407265[21] && + !_theResult____h407265[20] && + !_theResult____h407265[19] && + !_theResult____h407265[18] && + !_theResult____h407265[17] && + !_theResult____h407265[16] && + !_theResult____h407265[15] && + !_theResult____h407265[14] && + !_theResult____h407265[13] && + !_theResult____h407265[12] && + !_theResult____h407265[11] && + !_theResult____h407265[10] && + !_theResult____h407265[9] && + !_theResult____h407265[8] && + !_theResult____h407265[7] && + !_theResult____h407265[6] && + !_theResult____h407265[5] && + !_theResult____h407265[4] && + !_theResult____h407265[3] && + !_theResult____h407265[2] && + !_theResult____h407265[1] && + !_theResult____h407265[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h415601 ; - assign _theResult___fst_exp__h415610 = - (!_theResult____h407298[56] && _theResult____h407298[55]) ? + _theResult___fst_exp__h415568 ; + assign _theResult___fst_exp__h415577 = + (!_theResult____h407265[56] && _theResult____h407265[55]) ? 8'd1 : - _theResult___fst_exp__h415607 ; - assign _theResult___fst_exp__h416133 = - (_theResult___fst_exp__h415536 == 8'd255) ? - _theResult___fst_exp__h415536 : - _theResult___fst_exp__h416130 ; - assign _theResult___fst_exp__h424173 = + _theResult___fst_exp__h415574 ; + assign _theResult___fst_exp__h416100 = + (_theResult___fst_exp__h415503 == 8'd255) ? + _theResult___fst_exp__h415503 : + _theResult___fst_exp__h416097 ; + assign _theResult___fst_exp__h424140 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h424212 = + assign _theResult___fst_exp__h424179 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h424218 = + assign _theResult___fst_exp__h424185 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h424212 ; - assign _theResult___fst_exp__h424221 = + _theResult___fst_exp__h424179 ; + assign _theResult___fst_exp__h424188 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h424218 : - _theResult___fst_exp__h424173 ; - assign _theResult___fst_exp__h424769 = - (_theResult___fst_exp__h424221 == 8'd255) ? - _theResult___fst_exp__h424221 : - _theResult___fst_exp__h424766 ; - assign _theResult___fst_exp__h424778 = + _theResult___fst_exp__h424185 : + _theResult___fst_exp__h424140 ; + assign _theResult___fst_exp__h424736 = + (_theResult___fst_exp__h424188 == 8'd255) ? + _theResult___fst_exp__h424188 : + _theResult___fst_exp__h424733 ; + assign _theResult___fst_exp__h424745 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406952 : - _theResult___fst_exp__h389643) : + _theResult___snd_fst_exp__h406919 : + _theResult___fst_exp__h389610) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424772 : - _theResult___fst_exp__h389643) ; - assign _theResult___fst_exp__h424781 = + _theResult___snd_fst_exp__h424739 : + _theResult___fst_exp__h389610) ; + assign _theResult___fst_exp__h424748 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424778 ; - assign _theResult___fst_exp__h443465 = - _theResult____h435356[56] ? + _theResult___fst_exp__h424745 ; + assign _theResult___fst_exp__h443432 = + _theResult____h435323[56] ? 8'd2 : - _theResult___fst_exp__h443539 ; - assign _theResult___fst_exp__h443530 = + _theResult___fst_exp__h443506 ; + assign _theResult___fst_exp__h443497 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h443536 = - (!_theResult____h435356[56] && !_theResult____h435356[55] && - !_theResult____h435356[54] && - !_theResult____h435356[53] && - !_theResult____h435356[52] && - !_theResult____h435356[51] && - !_theResult____h435356[50] && - !_theResult____h435356[49] && - !_theResult____h435356[48] && - !_theResult____h435356[47] && - !_theResult____h435356[46] && - !_theResult____h435356[45] && - !_theResult____h435356[44] && - !_theResult____h435356[43] && - !_theResult____h435356[42] && - !_theResult____h435356[41] && - !_theResult____h435356[40] && - !_theResult____h435356[39] && - !_theResult____h435356[38] && - !_theResult____h435356[37] && - !_theResult____h435356[36] && - !_theResult____h435356[35] && - !_theResult____h435356[34] && - !_theResult____h435356[33] && - !_theResult____h435356[32] && - !_theResult____h435356[31] && - !_theResult____h435356[30] && - !_theResult____h435356[29] && - !_theResult____h435356[28] && - !_theResult____h435356[27] && - !_theResult____h435356[26] && - !_theResult____h435356[25] && - !_theResult____h435356[24] && - !_theResult____h435356[23] && - !_theResult____h435356[22] && - !_theResult____h435356[21] && - !_theResult____h435356[20] && - !_theResult____h435356[19] && - !_theResult____h435356[18] && - !_theResult____h435356[17] && - !_theResult____h435356[16] && - !_theResult____h435356[15] && - !_theResult____h435356[14] && - !_theResult____h435356[13] && - !_theResult____h435356[12] && - !_theResult____h435356[11] && - !_theResult____h435356[10] && - !_theResult____h435356[9] && - !_theResult____h435356[8] && - !_theResult____h435356[7] && - !_theResult____h435356[6] && - !_theResult____h435356[5] && - !_theResult____h435356[4] && - !_theResult____h435356[3] && - !_theResult____h435356[2] && - !_theResult____h435356[1] && - !_theResult____h435356[0] || + assign _theResult___fst_exp__h443503 = + (!_theResult____h435323[56] && !_theResult____h435323[55] && + !_theResult____h435323[54] && + !_theResult____h435323[53] && + !_theResult____h435323[52] && + !_theResult____h435323[51] && + !_theResult____h435323[50] && + !_theResult____h435323[49] && + !_theResult____h435323[48] && + !_theResult____h435323[47] && + !_theResult____h435323[46] && + !_theResult____h435323[45] && + !_theResult____h435323[44] && + !_theResult____h435323[43] && + !_theResult____h435323[42] && + !_theResult____h435323[41] && + !_theResult____h435323[40] && + !_theResult____h435323[39] && + !_theResult____h435323[38] && + !_theResult____h435323[37] && + !_theResult____h435323[36] && + !_theResult____h435323[35] && + !_theResult____h435323[34] && + !_theResult____h435323[33] && + !_theResult____h435323[32] && + !_theResult____h435323[31] && + !_theResult____h435323[30] && + !_theResult____h435323[29] && + !_theResult____h435323[28] && + !_theResult____h435323[27] && + !_theResult____h435323[26] && + !_theResult____h435323[25] && + !_theResult____h435323[24] && + !_theResult____h435323[23] && + !_theResult____h435323[22] && + !_theResult____h435323[21] && + !_theResult____h435323[20] && + !_theResult____h435323[19] && + !_theResult____h435323[18] && + !_theResult____h435323[17] && + !_theResult____h435323[16] && + !_theResult____h435323[15] && + !_theResult____h435323[14] && + !_theResult____h435323[13] && + !_theResult____h435323[12] && + !_theResult____h435323[11] && + !_theResult____h435323[10] && + !_theResult____h435323[9] && + !_theResult____h435323[8] && + !_theResult____h435323[7] && + !_theResult____h435323[6] && + !_theResult____h435323[5] && + !_theResult____h435323[4] && + !_theResult____h435323[3] && + !_theResult____h435323[2] && + !_theResult____h435323[1] && + !_theResult____h435323[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h443530 ; - assign _theResult___fst_exp__h443539 = - (!_theResult____h435356[56] && _theResult____h435356[55]) ? + _theResult___fst_exp__h443497 ; + assign _theResult___fst_exp__h443506 = + (!_theResult____h435323[56] && _theResult____h435323[55]) ? 8'd1 : - _theResult___fst_exp__h443536 ; - assign _theResult___fst_exp__h444062 = - (_theResult___fst_exp__h443465 == 8'd255) ? - _theResult___fst_exp__h443465 : - _theResult___fst_exp__h444059 ; - assign _theResult___fst_exp__h452112 = + _theResult___fst_exp__h443503 ; + assign _theResult___fst_exp__h444029 = + (_theResult___fst_exp__h443432 == 8'd255) ? + _theResult___fst_exp__h443432 : + _theResult___fst_exp__h444026 ; + assign _theResult___fst_exp__h452079 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h452118 = + assign _theResult___fst_exp__h452085 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h452112 ; - assign _theResult___fst_exp__h452121 = + _theResult___fst_exp__h452079 ; + assign _theResult___fst_exp__h452088 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h452118 : + _theResult___fst_exp__h452085 : 8'd129 ; - assign _theResult___fst_exp__h452644 = - (_theResult___fst_exp__h452121 == 8'd255) ? - _theResult___fst_exp__h452121 : - _theResult___fst_exp__h452641 ; - assign _theResult___fst_exp__h461231 = - _theResult____h452993[56] ? + assign _theResult___fst_exp__h452611 = + (_theResult___fst_exp__h452088 == 8'd255) ? + _theResult___fst_exp__h452088 : + _theResult___fst_exp__h452608 ; + assign _theResult___fst_exp__h461198 = + _theResult____h452960[56] ? 8'd2 : - _theResult___fst_exp__h461305 ; - assign _theResult___fst_exp__h461296 = + _theResult___fst_exp__h461272 ; + assign _theResult___fst_exp__h461263 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h461302 = - (!_theResult____h452993[56] && !_theResult____h452993[55] && - !_theResult____h452993[54] && - !_theResult____h452993[53] && - !_theResult____h452993[52] && - !_theResult____h452993[51] && - !_theResult____h452993[50] && - !_theResult____h452993[49] && - !_theResult____h452993[48] && - !_theResult____h452993[47] && - !_theResult____h452993[46] && - !_theResult____h452993[45] && - !_theResult____h452993[44] && - !_theResult____h452993[43] && - !_theResult____h452993[42] && - !_theResult____h452993[41] && - !_theResult____h452993[40] && - !_theResult____h452993[39] && - !_theResult____h452993[38] && - !_theResult____h452993[37] && - !_theResult____h452993[36] && - !_theResult____h452993[35] && - !_theResult____h452993[34] && - !_theResult____h452993[33] && - !_theResult____h452993[32] && - !_theResult____h452993[31] && - !_theResult____h452993[30] && - !_theResult____h452993[29] && - !_theResult____h452993[28] && - !_theResult____h452993[27] && - !_theResult____h452993[26] && - !_theResult____h452993[25] && - !_theResult____h452993[24] && - !_theResult____h452993[23] && - !_theResult____h452993[22] && - !_theResult____h452993[21] && - !_theResult____h452993[20] && - !_theResult____h452993[19] && - !_theResult____h452993[18] && - !_theResult____h452993[17] && - !_theResult____h452993[16] && - !_theResult____h452993[15] && - !_theResult____h452993[14] && - !_theResult____h452993[13] && - !_theResult____h452993[12] && - !_theResult____h452993[11] && - !_theResult____h452993[10] && - !_theResult____h452993[9] && - !_theResult____h452993[8] && - !_theResult____h452993[7] && - !_theResult____h452993[6] && - !_theResult____h452993[5] && - !_theResult____h452993[4] && - !_theResult____h452993[3] && - !_theResult____h452993[2] && - !_theResult____h452993[1] && - !_theResult____h452993[0] || + assign _theResult___fst_exp__h461269 = + (!_theResult____h452960[56] && !_theResult____h452960[55] && + !_theResult____h452960[54] && + !_theResult____h452960[53] && + !_theResult____h452960[52] && + !_theResult____h452960[51] && + !_theResult____h452960[50] && + !_theResult____h452960[49] && + !_theResult____h452960[48] && + !_theResult____h452960[47] && + !_theResult____h452960[46] && + !_theResult____h452960[45] && + !_theResult____h452960[44] && + !_theResult____h452960[43] && + !_theResult____h452960[42] && + !_theResult____h452960[41] && + !_theResult____h452960[40] && + !_theResult____h452960[39] && + !_theResult____h452960[38] && + !_theResult____h452960[37] && + !_theResult____h452960[36] && + !_theResult____h452960[35] && + !_theResult____h452960[34] && + !_theResult____h452960[33] && + !_theResult____h452960[32] && + !_theResult____h452960[31] && + !_theResult____h452960[30] && + !_theResult____h452960[29] && + !_theResult____h452960[28] && + !_theResult____h452960[27] && + !_theResult____h452960[26] && + !_theResult____h452960[25] && + !_theResult____h452960[24] && + !_theResult____h452960[23] && + !_theResult____h452960[22] && + !_theResult____h452960[21] && + !_theResult____h452960[20] && + !_theResult____h452960[19] && + !_theResult____h452960[18] && + !_theResult____h452960[17] && + !_theResult____h452960[16] && + !_theResult____h452960[15] && + !_theResult____h452960[14] && + !_theResult____h452960[13] && + !_theResult____h452960[12] && + !_theResult____h452960[11] && + !_theResult____h452960[10] && + !_theResult____h452960[9] && + !_theResult____h452960[8] && + !_theResult____h452960[7] && + !_theResult____h452960[6] && + !_theResult____h452960[5] && + !_theResult____h452960[4] && + !_theResult____h452960[3] && + !_theResult____h452960[2] && + !_theResult____h452960[1] && + !_theResult____h452960[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h461296 ; - assign _theResult___fst_exp__h461305 = - (!_theResult____h452993[56] && _theResult____h452993[55]) ? + _theResult___fst_exp__h461263 ; + assign _theResult___fst_exp__h461272 = + (!_theResult____h452960[56] && _theResult____h452960[55]) ? 8'd1 : - _theResult___fst_exp__h461302 ; - assign _theResult___fst_exp__h461828 = - (_theResult___fst_exp__h461231 == 8'd255) ? - _theResult___fst_exp__h461231 : - _theResult___fst_exp__h461825 ; - assign _theResult___fst_exp__h469868 = + _theResult___fst_exp__h461269 ; + assign _theResult___fst_exp__h461795 = + (_theResult___fst_exp__h461198 == 8'd255) ? + _theResult___fst_exp__h461198 : + _theResult___fst_exp__h461792 ; + assign _theResult___fst_exp__h469835 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h469907 = + assign _theResult___fst_exp__h469874 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469913 = + assign _theResult___fst_exp__h469880 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469907 ; - assign _theResult___fst_exp__h469916 = + _theResult___fst_exp__h469874 ; + assign _theResult___fst_exp__h469883 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469913 : - _theResult___fst_exp__h469868 ; - assign _theResult___fst_exp__h470464 = - (_theResult___fst_exp__h469916 == 8'd255) ? - _theResult___fst_exp__h469916 : - _theResult___fst_exp__h470461 ; - assign _theResult___fst_exp__h470473 = + _theResult___fst_exp__h469880 : + _theResult___fst_exp__h469835 ; + assign _theResult___fst_exp__h470431 = + (_theResult___fst_exp__h469883 == 8'd255) ? + _theResult___fst_exp__h469883 : + _theResult___fst_exp__h470428 ; + assign _theResult___fst_exp__h470440 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h452647 : - _theResult___fst_exp__h435338) : + _theResult___snd_fst_exp__h452614 : + _theResult___fst_exp__h435305) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h470467 : - _theResult___fst_exp__h435338) ; - assign _theResult___fst_exp__h470476 = + _theResult___snd_fst_exp__h470434 : + _theResult___fst_exp__h435305) ; + assign _theResult___fst_exp__h470443 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h470473 ; - assign _theResult___fst_exp__h484332 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? - 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_exp__h499396 = - 11'd897 - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; - assign _theResult___fst_exp__h499402 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582) ? - 11'd0 : - _theResult___fst_exp__h499396 ; - assign _theResult___fst_exp__h499405 = - (f1_exp__h480017 == 8'd0) ? - _theResult___fst_exp__h499402 : - 11'd897 ; - assign _theResult___fst_exp__h500160 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 ; - assign _theResult___fst_exp__h500163 = - (_theResult___fst_exp__h499405 == 11'd2047) ? - _theResult___fst_exp__h499405 : - _theResult___fst_exp__h500160 ; - assign _theResult___fst_exp__h508982 = - _theResult____h500746[56] ? - 11'd2 : - _theResult___fst_exp__h509056 ; - assign _theResult___fst_exp__h509047 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ; - assign _theResult___fst_exp__h509053 = - (!_theResult____h500746[56] && !_theResult____h500746[55] && - !_theResult____h500746[54] && - !_theResult____h500746[53] && - !_theResult____h500746[52] && - !_theResult____h500746[51] && - !_theResult____h500746[50] && - !_theResult____h500746[49] && - !_theResult____h500746[48] && - !_theResult____h500746[47] && - !_theResult____h500746[46] && - !_theResult____h500746[45] && - !_theResult____h500746[44] && - !_theResult____h500746[43] && - !_theResult____h500746[42] && - !_theResult____h500746[41] && - !_theResult____h500746[40] && - !_theResult____h500746[39] && - !_theResult____h500746[38] && - !_theResult____h500746[37] && - !_theResult____h500746[36] && - !_theResult____h500746[35] && - !_theResult____h500746[34] && - !_theResult____h500746[33] && - !_theResult____h500746[32] && - !_theResult____h500746[31] && - !_theResult____h500746[30] && - !_theResult____h500746[29] && - !_theResult____h500746[28] && - !_theResult____h500746[27] && - !_theResult____h500746[26] && - !_theResult____h500746[25] && - !_theResult____h500746[24] && - !_theResult____h500746[23] && - !_theResult____h500746[22] && - !_theResult____h500746[21] && - !_theResult____h500746[20] && - !_theResult____h500746[19] && - !_theResult____h500746[18] && - !_theResult____h500746[17] && - !_theResult____h500746[16] && - !_theResult____h500746[15] && - !_theResult____h500746[14] && - !_theResult____h500746[13] && - !_theResult____h500746[12] && - !_theResult____h500746[11] && - !_theResult____h500746[10] && - !_theResult____h500746[9] && - !_theResult____h500746[8] && - !_theResult____h500746[7] && - !_theResult____h500746[6] && - !_theResult____h500746[5] && - !_theResult____h500746[4] && - !_theResult____h500746[3] && - !_theResult____h500746[2] && - !_theResult____h500746[1] && - !_theResult____h500746[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894) ? - 11'd0 : - _theResult___fst_exp__h509047 ; - assign _theResult___fst_exp__h509056 = - (!_theResult____h500746[56] && _theResult____h500746[55]) ? - 11'd1 : - _theResult___fst_exp__h509053 ; - assign _theResult___fst_exp__h509811 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 ; - assign _theResult___fst_exp__h509814 = - (_theResult___fst_exp__h508982 == 11'd2047) ? - _theResult___fst_exp__h508982 : - _theResult___fst_exp__h509811 ; - assign _theResult___fst_exp__h517767 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h517806 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; - assign _theResult___fst_exp__h517812 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944) ? - 11'd0 : - _theResult___fst_exp__h517806 ; - assign _theResult___fst_exp__h517815 = - (f1_exp__h480017 == 8'd0) ? - _theResult___fst_exp__h517812 : - _theResult___fst_exp__h517767 ; - assign _theResult___fst_exp__h518595 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 ; - assign _theResult___fst_exp__h518598 = - (_theResult___fst_exp__h517815 == 11'd2047) ? - _theResult___fst_exp__h517815 : - _theResult___fst_exp__h518595 ; - assign _theResult___fst_exp__h518607 = - (f1_exp__h480017 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? - _theResult___snd_fst_exp__h500166 : - _theResult___fst_exp__h484332) : - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? - _theResult___snd_fst_exp__h518601 : - _theResult___fst_exp__h484332) ; - assign _theResult___fst_exp__h518610 = - (f1_exp__h480017 == 8'd0 && f1_sfd__h480018 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h518607 ; - assign _theResult___fst_exp__h523185 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? - 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_exp__h538249 = - 11'd897 - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; - assign _theResult___fst_exp__h538255 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082) ? - 11'd0 : - _theResult___fst_exp__h538249 ; - assign _theResult___fst_exp__h538258 = - (f2_exp__h519011 == 8'd0) ? - _theResult___fst_exp__h538255 : - 11'd897 ; - assign _theResult___fst_exp__h539013 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 ; - assign _theResult___fst_exp__h539016 = - (_theResult___fst_exp__h538258 == 11'd2047) ? - _theResult___fst_exp__h538258 : - _theResult___fst_exp__h539013 ; - assign _theResult___fst_exp__h547835 = - _theResult____h539599[56] ? - 11'd2 : - _theResult___fst_exp__h547909 ; - assign _theResult___fst_exp__h547900 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ; - assign _theResult___fst_exp__h547906 = - (!_theResult____h539599[56] && !_theResult____h539599[55] && - !_theResult____h539599[54] && - !_theResult____h539599[53] && - !_theResult____h539599[52] && - !_theResult____h539599[51] && - !_theResult____h539599[50] && - !_theResult____h539599[49] && - !_theResult____h539599[48] && - !_theResult____h539599[47] && - !_theResult____h539599[46] && - !_theResult____h539599[45] && - !_theResult____h539599[44] && - !_theResult____h539599[43] && - !_theResult____h539599[42] && - !_theResult____h539599[41] && - !_theResult____h539599[40] && - !_theResult____h539599[39] && - !_theResult____h539599[38] && - !_theResult____h539599[37] && - !_theResult____h539599[36] && - !_theResult____h539599[35] && - !_theResult____h539599[34] && - !_theResult____h539599[33] && - !_theResult____h539599[32] && - !_theResult____h539599[31] && - !_theResult____h539599[30] && - !_theResult____h539599[29] && - !_theResult____h539599[28] && - !_theResult____h539599[27] && - !_theResult____h539599[26] && - !_theResult____h539599[25] && - !_theResult____h539599[24] && - !_theResult____h539599[23] && - !_theResult____h539599[22] && - !_theResult____h539599[21] && - !_theResult____h539599[20] && - !_theResult____h539599[19] && - !_theResult____h539599[18] && - !_theResult____h539599[17] && - !_theResult____h539599[16] && - !_theResult____h539599[15] && - !_theResult____h539599[14] && - !_theResult____h539599[13] && - !_theResult____h539599[12] && - !_theResult____h539599[11] && - !_theResult____h539599[10] && - !_theResult____h539599[9] && - !_theResult____h539599[8] && - !_theResult____h539599[7] && - !_theResult____h539599[6] && - !_theResult____h539599[5] && - !_theResult____h539599[4] && - !_theResult____h539599[3] && - !_theResult____h539599[2] && - !_theResult____h539599[1] && - !_theResult____h539599[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379) ? - 11'd0 : - _theResult___fst_exp__h547900 ; - assign _theResult___fst_exp__h547909 = - (!_theResult____h539599[56] && _theResult____h539599[55]) ? - 11'd1 : - _theResult___fst_exp__h547906 ; - assign _theResult___fst_exp__h548664 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 ; - assign _theResult___fst_exp__h548667 = - (_theResult___fst_exp__h547835 == 11'd2047) ? - _theResult___fst_exp__h547835 : - _theResult___fst_exp__h548664 ; - assign _theResult___fst_exp__h556620 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h556659 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - - { 5'd0, - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; - assign _theResult___fst_exp__h556665 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || - !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429) ? - 11'd0 : - _theResult___fst_exp__h556659 ; - assign _theResult___fst_exp__h556668 = - (f2_exp__h519011 == 8'd0) ? - _theResult___fst_exp__h556665 : - _theResult___fst_exp__h556620 ; - assign _theResult___fst_exp__h557448 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 : - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 ; - assign _theResult___fst_exp__h557451 = - (_theResult___fst_exp__h556668 == 11'd2047) ? - _theResult___fst_exp__h556668 : - _theResult___fst_exp__h557448 ; - assign _theResult___fst_exp__h557460 = - (f2_exp__h519011 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? - _theResult___snd_fst_exp__h539019 : - _theResult___fst_exp__h523185) : - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? - _theResult___snd_fst_exp__h557454 : - _theResult___fst_exp__h523185) ; - assign _theResult___fst_exp__h557463 = - (f2_exp__h519011 == 8'd0 && f2_sfd__h519012 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h557460 ; - assign _theResult___fst_exp__h562489 = + _theResult___fst_exp__h470440 ; + assign _theResult___fst_exp__h484299 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; - assign _theResult___fst_exp__h577553 = + assign _theResult___fst_exp__h499363 = + 11'd897 - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; + assign _theResult___fst_exp__h499369 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582) ? + 11'd0 : + _theResult___fst_exp__h499363 ; + assign _theResult___fst_exp__h499372 = + (f1_exp__h479984 == 8'd0) ? + _theResult___fst_exp__h499369 : + 11'd897 ; + assign _theResult___fst_exp__h500127 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 ; + assign _theResult___fst_exp__h500130 = + (_theResult___fst_exp__h499372 == 11'd2047) ? + _theResult___fst_exp__h499372 : + _theResult___fst_exp__h500127 ; + assign _theResult___fst_exp__h508949 = + _theResult____h500713[56] ? + 11'd2 : + _theResult___fst_exp__h509023 ; + assign _theResult___fst_exp__h509014 = + 11'd0 - + { 5'd0, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ; + assign _theResult___fst_exp__h509020 = + (!_theResult____h500713[56] && !_theResult____h500713[55] && + !_theResult____h500713[54] && + !_theResult____h500713[53] && + !_theResult____h500713[52] && + !_theResult____h500713[51] && + !_theResult____h500713[50] && + !_theResult____h500713[49] && + !_theResult____h500713[48] && + !_theResult____h500713[47] && + !_theResult____h500713[46] && + !_theResult____h500713[45] && + !_theResult____h500713[44] && + !_theResult____h500713[43] && + !_theResult____h500713[42] && + !_theResult____h500713[41] && + !_theResult____h500713[40] && + !_theResult____h500713[39] && + !_theResult____h500713[38] && + !_theResult____h500713[37] && + !_theResult____h500713[36] && + !_theResult____h500713[35] && + !_theResult____h500713[34] && + !_theResult____h500713[33] && + !_theResult____h500713[32] && + !_theResult____h500713[31] && + !_theResult____h500713[30] && + !_theResult____h500713[29] && + !_theResult____h500713[28] && + !_theResult____h500713[27] && + !_theResult____h500713[26] && + !_theResult____h500713[25] && + !_theResult____h500713[24] && + !_theResult____h500713[23] && + !_theResult____h500713[22] && + !_theResult____h500713[21] && + !_theResult____h500713[20] && + !_theResult____h500713[19] && + !_theResult____h500713[18] && + !_theResult____h500713[17] && + !_theResult____h500713[16] && + !_theResult____h500713[15] && + !_theResult____h500713[14] && + !_theResult____h500713[13] && + !_theResult____h500713[12] && + !_theResult____h500713[11] && + !_theResult____h500713[10] && + !_theResult____h500713[9] && + !_theResult____h500713[8] && + !_theResult____h500713[7] && + !_theResult____h500713[6] && + !_theResult____h500713[5] && + !_theResult____h500713[4] && + !_theResult____h500713[3] && + !_theResult____h500713[2] && + !_theResult____h500713[1] && + !_theResult____h500713[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894) ? + 11'd0 : + _theResult___fst_exp__h509014 ; + assign _theResult___fst_exp__h509023 = + (!_theResult____h500713[56] && _theResult____h500713[55]) ? + 11'd1 : + _theResult___fst_exp__h509020 ; + assign _theResult___fst_exp__h509778 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 ; + assign _theResult___fst_exp__h509781 = + (_theResult___fst_exp__h508949 == 11'd2047) ? + _theResult___fst_exp__h508949 : + _theResult___fst_exp__h509778 ; + assign _theResult___fst_exp__h517734 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == + 11'd0) ? + 11'd1 : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; + assign _theResult___fst_exp__h517773 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ; + assign _theResult___fst_exp__h517779 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944) ? + 11'd0 : + _theResult___fst_exp__h517773 ; + assign _theResult___fst_exp__h517782 = + (f1_exp__h479984 == 8'd0) ? + _theResult___fst_exp__h517779 : + _theResult___fst_exp__h517734 ; + assign _theResult___fst_exp__h518562 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 ; + assign _theResult___fst_exp__h518565 = + (_theResult___fst_exp__h517782 == 11'd2047) ? + _theResult___fst_exp__h517782 : + _theResult___fst_exp__h518562 ; + assign _theResult___fst_exp__h518574 = + (f1_exp__h479984 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? + _theResult___snd_fst_exp__h500133 : + _theResult___fst_exp__h484299) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? + _theResult___snd_fst_exp__h518568 : + _theResult___fst_exp__h484299) ; + assign _theResult___fst_exp__h518577 = + (f1_exp__h479984 == 8'd0 && f1_sfd__h479985 == 23'd0) ? + 11'd0 : + _theResult___fst_exp__h518574 ; + assign _theResult___fst_exp__h523152 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? + 11'd2047 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + assign _theResult___fst_exp__h538216 = + 11'd897 - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; + assign _theResult___fst_exp__h538222 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082) ? + 11'd0 : + _theResult___fst_exp__h538216 ; + assign _theResult___fst_exp__h538225 = + (f2_exp__h518978 == 8'd0) ? + _theResult___fst_exp__h538222 : + 11'd897 ; + assign _theResult___fst_exp__h538980 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 ; + assign _theResult___fst_exp__h538983 = + (_theResult___fst_exp__h538225 == 11'd2047) ? + _theResult___fst_exp__h538225 : + _theResult___fst_exp__h538980 ; + assign _theResult___fst_exp__h547802 = + _theResult____h539566[56] ? + 11'd2 : + _theResult___fst_exp__h547876 ; + assign _theResult___fst_exp__h547867 = + 11'd0 - + { 5'd0, + IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ; + assign _theResult___fst_exp__h547873 = + (!_theResult____h539566[56] && !_theResult____h539566[55] && + !_theResult____h539566[54] && + !_theResult____h539566[53] && + !_theResult____h539566[52] && + !_theResult____h539566[51] && + !_theResult____h539566[50] && + !_theResult____h539566[49] && + !_theResult____h539566[48] && + !_theResult____h539566[47] && + !_theResult____h539566[46] && + !_theResult____h539566[45] && + !_theResult____h539566[44] && + !_theResult____h539566[43] && + !_theResult____h539566[42] && + !_theResult____h539566[41] && + !_theResult____h539566[40] && + !_theResult____h539566[39] && + !_theResult____h539566[38] && + !_theResult____h539566[37] && + !_theResult____h539566[36] && + !_theResult____h539566[35] && + !_theResult____h539566[34] && + !_theResult____h539566[33] && + !_theResult____h539566[32] && + !_theResult____h539566[31] && + !_theResult____h539566[30] && + !_theResult____h539566[29] && + !_theResult____h539566[28] && + !_theResult____h539566[27] && + !_theResult____h539566[26] && + !_theResult____h539566[25] && + !_theResult____h539566[24] && + !_theResult____h539566[23] && + !_theResult____h539566[22] && + !_theResult____h539566[21] && + !_theResult____h539566[20] && + !_theResult____h539566[19] && + !_theResult____h539566[18] && + !_theResult____h539566[17] && + !_theResult____h539566[16] && + !_theResult____h539566[15] && + !_theResult____h539566[14] && + !_theResult____h539566[13] && + !_theResult____h539566[12] && + !_theResult____h539566[11] && + !_theResult____h539566[10] && + !_theResult____h539566[9] && + !_theResult____h539566[8] && + !_theResult____h539566[7] && + !_theResult____h539566[6] && + !_theResult____h539566[5] && + !_theResult____h539566[4] && + !_theResult____h539566[3] && + !_theResult____h539566[2] && + !_theResult____h539566[1] && + !_theResult____h539566[0] || + !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379) ? + 11'd0 : + _theResult___fst_exp__h547867 ; + assign _theResult___fst_exp__h547876 = + (!_theResult____h539566[56] && _theResult____h539566[55]) ? + 11'd1 : + _theResult___fst_exp__h547873 ; + assign _theResult___fst_exp__h548631 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 ; + assign _theResult___fst_exp__h548634 = + (_theResult___fst_exp__h547802 == 11'd2047) ? + _theResult___fst_exp__h547802 : + _theResult___fst_exp__h548631 ; + assign _theResult___fst_exp__h556587 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == + 11'd0) ? + 11'd1 : + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; + assign _theResult___fst_exp__h556626 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - + { 5'd0, + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ; + assign _theResult___fst_exp__h556632 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 || + !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429) ? + 11'd0 : + _theResult___fst_exp__h556626 ; + assign _theResult___fst_exp__h556635 = + (f2_exp__h518978 == 8'd0) ? + _theResult___fst_exp__h556632 : + _theResult___fst_exp__h556587 ; + assign _theResult___fst_exp__h557415 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 : + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 ; + assign _theResult___fst_exp__h557418 = + (_theResult___fst_exp__h556635 == 11'd2047) ? + _theResult___fst_exp__h556635 : + _theResult___fst_exp__h557415 ; + assign _theResult___fst_exp__h557427 = + (f2_exp__h518978 == 8'd0) ? + (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? + _theResult___snd_fst_exp__h538986 : + _theResult___fst_exp__h523152) : + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? + _theResult___snd_fst_exp__h557421 : + _theResult___fst_exp__h523152) ; + assign _theResult___fst_exp__h557430 = + (f2_exp__h518978 == 8'd0 && f2_sfd__h518979 == 23'd0) ? + 11'd0 : + _theResult___fst_exp__h557427 ; + assign _theResult___fst_exp__h562456 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? + 11'd2047 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; + assign _theResult___fst_exp__h577520 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ; - assign _theResult___fst_exp__h577559 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___fst_exp__h577526 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312) ? 11'd0 : - _theResult___fst_exp__h577553 ; - assign _theResult___fst_exp__h577562 = - (f3_exp__h558315 == 8'd0) ? - _theResult___fst_exp__h577559 : + _theResult___fst_exp__h577520 ; + assign _theResult___fst_exp__h577529 = + (f3_exp__h558282 == 8'd0) ? + _theResult___fst_exp__h577526 : 11'd897 ; - assign _theResult___fst_exp__h578317 = + assign _theResult___fst_exp__h578284 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 : + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 ; - assign _theResult___fst_exp__h578320 = - (_theResult___fst_exp__h577562 == 11'd2047) ? - _theResult___fst_exp__h577562 : - _theResult___fst_exp__h578317 ; - assign _theResult___fst_exp__h587139 = - _theResult____h578903[56] ? + assign _theResult___fst_exp__h578287 = + (_theResult___fst_exp__h577529 == 11'd2047) ? + _theResult___fst_exp__h577529 : + _theResult___fst_exp__h578284 ; + assign _theResult___fst_exp__h587106 = + _theResult____h578870[56] ? 11'd2 : - _theResult___fst_exp__h587213 ; - assign _theResult___fst_exp__h587204 = + _theResult___fst_exp__h587180 ; + assign _theResult___fst_exp__h587171 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 } ; - assign _theResult___fst_exp__h587210 = - (!_theResult____h578903[56] && !_theResult____h578903[55] && - !_theResult____h578903[54] && - !_theResult____h578903[53] && - !_theResult____h578903[52] && - !_theResult____h578903[51] && - !_theResult____h578903[50] && - !_theResult____h578903[49] && - !_theResult____h578903[48] && - !_theResult____h578903[47] && - !_theResult____h578903[46] && - !_theResult____h578903[45] && - !_theResult____h578903[44] && - !_theResult____h578903[43] && - !_theResult____h578903[42] && - !_theResult____h578903[41] && - !_theResult____h578903[40] && - !_theResult____h578903[39] && - !_theResult____h578903[38] && - !_theResult____h578903[37] && - !_theResult____h578903[36] && - !_theResult____h578903[35] && - !_theResult____h578903[34] && - !_theResult____h578903[33] && - !_theResult____h578903[32] && - !_theResult____h578903[31] && - !_theResult____h578903[30] && - !_theResult____h578903[29] && - !_theResult____h578903[28] && - !_theResult____h578903[27] && - !_theResult____h578903[26] && - !_theResult____h578903[25] && - !_theResult____h578903[24] && - !_theResult____h578903[23] && - !_theResult____h578903[22] && - !_theResult____h578903[21] && - !_theResult____h578903[20] && - !_theResult____h578903[19] && - !_theResult____h578903[18] && - !_theResult____h578903[17] && - !_theResult____h578903[16] && - !_theResult____h578903[15] && - !_theResult____h578903[14] && - !_theResult____h578903[13] && - !_theResult____h578903[12] && - !_theResult____h578903[11] && - !_theResult____h578903[10] && - !_theResult____h578903[9] && - !_theResult____h578903[8] && - !_theResult____h578903[7] && - !_theResult____h578903[6] && - !_theResult____h578903[5] && - !_theResult____h578903[4] && - !_theResult____h578903[3] && - !_theResult____h578903[2] && - !_theResult____h578903[1] && - !_theResult____h578903[0] || + assign _theResult___fst_exp__h587177 = + (!_theResult____h578870[56] && !_theResult____h578870[55] && + !_theResult____h578870[54] && + !_theResult____h578870[53] && + !_theResult____h578870[52] && + !_theResult____h578870[51] && + !_theResult____h578870[50] && + !_theResult____h578870[49] && + !_theResult____h578870[48] && + !_theResult____h578870[47] && + !_theResult____h578870[46] && + !_theResult____h578870[45] && + !_theResult____h578870[44] && + !_theResult____h578870[43] && + !_theResult____h578870[42] && + !_theResult____h578870[41] && + !_theResult____h578870[40] && + !_theResult____h578870[39] && + !_theResult____h578870[38] && + !_theResult____h578870[37] && + !_theResult____h578870[36] && + !_theResult____h578870[35] && + !_theResult____h578870[34] && + !_theResult____h578870[33] && + !_theResult____h578870[32] && + !_theResult____h578870[31] && + !_theResult____h578870[30] && + !_theResult____h578870[29] && + !_theResult____h578870[28] && + !_theResult____h578870[27] && + !_theResult____h578870[26] && + !_theResult____h578870[25] && + !_theResult____h578870[24] && + !_theResult____h578870[23] && + !_theResult____h578870[22] && + !_theResult____h578870[21] && + !_theResult____h578870[20] && + !_theResult____h578870[19] && + !_theResult____h578870[18] && + !_theResult____h578870[17] && + !_theResult____h578870[16] && + !_theResult____h578870[15] && + !_theResult____h578870[14] && + !_theResult____h578870[13] && + !_theResult____h578870[12] && + !_theResult____h578870[11] && + !_theResult____h578870[10] && + !_theResult____h578870[9] && + !_theResult____h578870[8] && + !_theResult____h578870[7] && + !_theResult____h578870[6] && + !_theResult____h578870[5] && + !_theResult____h578870[4] && + !_theResult____h578870[3] && + !_theResult____h578870[2] && + !_theResult____h578870[1] && + !_theResult____h578870[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609) ? 11'd0 : - _theResult___fst_exp__h587204 ; - assign _theResult___fst_exp__h587213 = - (!_theResult____h578903[56] && _theResult____h578903[55]) ? + _theResult___fst_exp__h587171 ; + assign _theResult___fst_exp__h587180 = + (!_theResult____h578870[56] && _theResult____h578870[55]) ? 11'd1 : - _theResult___fst_exp__h587210 ; - assign _theResult___fst_exp__h587968 = + _theResult___fst_exp__h587177 ; + assign _theResult___fst_exp__h587935 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 : + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 ; - assign _theResult___fst_exp__h587971 = - (_theResult___fst_exp__h587139 == 11'd2047) ? - _theResult___fst_exp__h587139 : - _theResult___fst_exp__h587968 ; - assign _theResult___fst_exp__h595924 = + assign _theResult___fst_exp__h587938 = + (_theResult___fst_exp__h587106 == 11'd2047) ? + _theResult___fst_exp__h587106 : + _theResult___fst_exp__h587935 ; + assign _theResult___fst_exp__h595891 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h595963 = + assign _theResult___fst_exp__h595930 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ; - assign _theResult___fst_exp__h595969 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___fst_exp__h595936 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659) ? 11'd0 : - _theResult___fst_exp__h595963 ; - assign _theResult___fst_exp__h595972 = - (f3_exp__h558315 == 8'd0) ? - _theResult___fst_exp__h595969 : - _theResult___fst_exp__h595924 ; - assign _theResult___fst_exp__h596752 = + _theResult___fst_exp__h595930 ; + assign _theResult___fst_exp__h595939 = + (f3_exp__h558282 == 8'd0) ? + _theResult___fst_exp__h595936 : + _theResult___fst_exp__h595891 ; + assign _theResult___fst_exp__h596719 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 : + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 ; - assign _theResult___fst_exp__h596755 = - (_theResult___fst_exp__h595972 == 11'd2047) ? - _theResult___fst_exp__h595972 : - _theResult___fst_exp__h596752 ; - assign _theResult___fst_exp__h596764 = - (f3_exp__h558315 == 8'd0) ? + assign _theResult___fst_exp__h596722 = + (_theResult___fst_exp__h595939 == 11'd2047) ? + _theResult___fst_exp__h595939 : + _theResult___fst_exp__h596719 ; + assign _theResult___fst_exp__h596731 = + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? - _theResult___snd_fst_exp__h578323 : - _theResult___fst_exp__h562489) : + _theResult___snd_fst_exp__h578290 : + _theResult___fst_exp__h562456) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ? - _theResult___snd_fst_exp__h596758 : - _theResult___fst_exp__h562489) ; - assign _theResult___fst_exp__h596767 = - (f3_exp__h558315 == 8'd0 && f3_sfd__h558316 == 23'd0) ? + _theResult___snd_fst_exp__h596725 : + _theResult___fst_exp__h562456) ; + assign _theResult___fst_exp__h596734 = + (f3_exp__h558282 == 8'd0 && f3_sfd__h558283 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h596764 ; - assign _theResult___fst_sfd__h352671 = - (_theResult___fst_exp__h352073 == 8'd255) ? - sfdin__h352067[56:34] : - _theResult___fst_sfd__h352668 ; - assign _theResult___fst_sfd__h361253 = - (_theResult___fst_exp__h360729 == 8'd255) ? - _theResult___snd__h360680[56:34] : - _theResult___fst_sfd__h361250 ; - assign _theResult___fst_sfd__h370437 = - (_theResult___fst_exp__h369839 == 8'd255) ? - sfdin__h369833[56:34] : - _theResult___fst_sfd__h370434 ; - assign _theResult___fst_sfd__h379073 = - (_theResult___fst_exp__h378524 == 8'd255) ? - _theResult___snd__h378470[56:34] : - _theResult___fst_sfd__h379070 ; - assign _theResult___fst_sfd__h379082 = + _theResult___fst_exp__h596731 ; + assign _theResult___fst_sfd__h352638 = + (_theResult___fst_exp__h352040 == 8'd255) ? + sfdin__h352034[56:34] : + _theResult___fst_sfd__h352635 ; + assign _theResult___fst_sfd__h361220 = + (_theResult___fst_exp__h360696 == 8'd255) ? + _theResult___snd__h360647[56:34] : + _theResult___fst_sfd__h361217 ; + assign _theResult___fst_sfd__h370404 = + (_theResult___fst_exp__h369806 == 8'd255) ? + sfdin__h369800[56:34] : + _theResult___fst_sfd__h370401 ; + assign _theResult___fst_sfd__h379040 = + (_theResult___fst_exp__h378491 == 8'd255) ? + _theResult___snd__h378437[56:34] : + _theResult___fst_sfd__h379037 ; + assign _theResult___fst_sfd__h379049 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h361256 : - _theResult___fst_sfd__h343945) : + _theResult___snd_fst_sfd__h361223 : + _theResult___fst_sfd__h343912) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h379076 : - _theResult___fst_sfd__h343945) ; - assign _theResult___fst_sfd__h379088 = + _theResult___snd_fst_sfd__h379043 : + _theResult___fst_sfd__h343912) ; + assign _theResult___fst_sfd__h379055 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -27696,33 +27700,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h379082 ; - assign _theResult___fst_sfd__h398368 = - (_theResult___fst_exp__h397770 == 8'd255) ? - sfdin__h397764[56:34] : - _theResult___fst_sfd__h398365 ; - assign _theResult___fst_sfd__h406950 = - (_theResult___fst_exp__h406426 == 8'd255) ? - _theResult___snd__h406377[56:34] : - _theResult___fst_sfd__h406947 ; - assign _theResult___fst_sfd__h416134 = - (_theResult___fst_exp__h415536 == 8'd255) ? - sfdin__h415530[56:34] : - _theResult___fst_sfd__h416131 ; - assign _theResult___fst_sfd__h424770 = - (_theResult___fst_exp__h424221 == 8'd255) ? - _theResult___snd__h424167[56:34] : - _theResult___fst_sfd__h424767 ; - assign _theResult___fst_sfd__h424779 = + _theResult___fst_sfd__h379049 ; + assign _theResult___fst_sfd__h398335 = + (_theResult___fst_exp__h397737 == 8'd255) ? + sfdin__h397731[56:34] : + _theResult___fst_sfd__h398332 ; + assign _theResult___fst_sfd__h406917 = + (_theResult___fst_exp__h406393 == 8'd255) ? + _theResult___snd__h406344[56:34] : + _theResult___fst_sfd__h406914 ; + assign _theResult___fst_sfd__h416101 = + (_theResult___fst_exp__h415503 == 8'd255) ? + sfdin__h415497[56:34] : + _theResult___fst_sfd__h416098 ; + assign _theResult___fst_sfd__h424737 = + (_theResult___fst_exp__h424188 == 8'd255) ? + _theResult___snd__h424134[56:34] : + _theResult___fst_sfd__h424734 ; + assign _theResult___fst_sfd__h424746 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406953 : - _theResult___fst_sfd__h389644) : + _theResult___snd_fst_sfd__h406920 : + _theResult___fst_sfd__h389611) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424773 : - _theResult___fst_sfd__h389644) ; - assign _theResult___fst_sfd__h424785 = + _theResult___snd_fst_sfd__h424740 : + _theResult___fst_sfd__h389611) ; + assign _theResult___fst_sfd__h424752 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -27730,33 +27734,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424779 ; - assign _theResult___fst_sfd__h444063 = - (_theResult___fst_exp__h443465 == 8'd255) ? - sfdin__h443459[56:34] : - _theResult___fst_sfd__h444060 ; - assign _theResult___fst_sfd__h452645 = - (_theResult___fst_exp__h452121 == 8'd255) ? - _theResult___snd__h452072[56:34] : - _theResult___fst_sfd__h452642 ; - assign _theResult___fst_sfd__h461829 = - (_theResult___fst_exp__h461231 == 8'd255) ? - sfdin__h461225[56:34] : - _theResult___fst_sfd__h461826 ; - assign _theResult___fst_sfd__h470465 = - (_theResult___fst_exp__h469916 == 8'd255) ? - _theResult___snd__h469862[56:34] : - _theResult___fst_sfd__h470462 ; - assign _theResult___fst_sfd__h470474 = + _theResult___fst_sfd__h424746 ; + assign _theResult___fst_sfd__h444030 = + (_theResult___fst_exp__h443432 == 8'd255) ? + sfdin__h443426[56:34] : + _theResult___fst_sfd__h444027 ; + assign _theResult___fst_sfd__h452612 = + (_theResult___fst_exp__h452088 == 8'd255) ? + _theResult___snd__h452039[56:34] : + _theResult___fst_sfd__h452609 ; + assign _theResult___fst_sfd__h461796 = + (_theResult___fst_exp__h461198 == 8'd255) ? + sfdin__h461192[56:34] : + _theResult___fst_sfd__h461793 ; + assign _theResult___fst_sfd__h470432 = + (_theResult___fst_exp__h469883 == 8'd255) ? + _theResult___snd__h469829[56:34] : + _theResult___fst_sfd__h470429 ; + assign _theResult___fst_sfd__h470441 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h452648 : - _theResult___fst_sfd__h435339) : + _theResult___snd_fst_sfd__h452615 : + _theResult___fst_sfd__h435306) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h470468 : - _theResult___fst_sfd__h435339) ; - assign _theResult___fst_sfd__h470480 = + _theResult___snd_fst_sfd__h470435 : + _theResult___fst_sfd__h435306) ; + assign _theResult___fst_sfd__h470447 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -27764,1309 +27768,1309 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h470474 ; - assign _theResult___fst_sfd__h484333 = + _theResult___fst_sfd__h470441 ; + assign _theResult___fst_sfd__h484300 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_sfd__h500161 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + assign _theResult___fst_sfd__h500128 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 : + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 ; - assign _theResult___fst_sfd__h500164 = - (_theResult___fst_exp__h499405 == 11'd2047) ? - _theResult___snd__h499356[56:5] : - _theResult___fst_sfd__h500161 ; - assign _theResult___fst_sfd__h509812 = + assign _theResult___fst_sfd__h500131 = + (_theResult___fst_exp__h499372 == 11'd2047) ? + _theResult___snd__h499323[56:5] : + _theResult___fst_sfd__h500128 ; + assign _theResult___fst_sfd__h509779 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 ; - assign _theResult___fst_sfd__h509815 = - (_theResult___fst_exp__h508982 == 11'd2047) ? - sfdin__h508976[56:5] : - _theResult___fst_sfd__h509812 ; - assign _theResult___fst_sfd__h518596 = + assign _theResult___fst_sfd__h509782 = + (_theResult___fst_exp__h508949 == 11'd2047) ? + sfdin__h508943[56:5] : + _theResult___fst_sfd__h509779 ; + assign _theResult___fst_sfd__h518563 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 : + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 ; - assign _theResult___fst_sfd__h518599 = - (_theResult___fst_exp__h517815 == 11'd2047) ? - _theResult___snd__h517761[56:5] : - _theResult___fst_sfd__h518596 ; - assign _theResult___fst_sfd__h518608 = - (f1_exp__h480017 == 8'd0) ? + assign _theResult___fst_sfd__h518566 = + (_theResult___fst_exp__h517782 == 11'd2047) ? + _theResult___snd__h517728[56:5] : + _theResult___fst_sfd__h518563 ; + assign _theResult___fst_sfd__h518575 = + (f1_exp__h479984 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ? - _theResult___snd_fst_sfd__h500167 : - _theResult___fst_sfd__h484333) : + _theResult___snd_fst_sfd__h500134 : + _theResult___fst_sfd__h484300) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ? - _theResult___snd_fst_sfd__h518602 : - _theResult___fst_sfd__h484333) ; - assign _theResult___fst_sfd__h518614 = - ((f1_exp__h480017 == 8'd255 || f1_exp__h480017 == 8'd0) && - f1_sfd__h480018 == 23'd0) ? + _theResult___snd_fst_sfd__h518569 : + _theResult___fst_sfd__h484300) ; + assign _theResult___fst_sfd__h518581 = + ((f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) && + f1_sfd__h479985 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h518608 ; - assign _theResult___fst_sfd__h523186 = + _theResult___fst_sfd__h518575 ; + assign _theResult___fst_sfd__h523153 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_sfd__h539014 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; + assign _theResult___fst_sfd__h538981 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 : + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 ; - assign _theResult___fst_sfd__h539017 = - (_theResult___fst_exp__h538258 == 11'd2047) ? - _theResult___snd__h538209[56:5] : - _theResult___fst_sfd__h539014 ; - assign _theResult___fst_sfd__h548665 = + assign _theResult___fst_sfd__h538984 = + (_theResult___fst_exp__h538225 == 11'd2047) ? + _theResult___snd__h538176[56:5] : + _theResult___fst_sfd__h538981 ; + assign _theResult___fst_sfd__h548632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 ; - assign _theResult___fst_sfd__h548668 = - (_theResult___fst_exp__h547835 == 11'd2047) ? - sfdin__h547829[56:5] : - _theResult___fst_sfd__h548665 ; - assign _theResult___fst_sfd__h557449 = + assign _theResult___fst_sfd__h548635 = + (_theResult___fst_exp__h547802 == 11'd2047) ? + sfdin__h547796[56:5] : + _theResult___fst_sfd__h548632 ; + assign _theResult___fst_sfd__h557416 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 : + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 ; - assign _theResult___fst_sfd__h557452 = - (_theResult___fst_exp__h556668 == 11'd2047) ? - _theResult___snd__h556614[56:5] : - _theResult___fst_sfd__h557449 ; - assign _theResult___fst_sfd__h557461 = - (f2_exp__h519011 == 8'd0) ? + assign _theResult___fst_sfd__h557419 = + (_theResult___fst_exp__h556635 == 11'd2047) ? + _theResult___snd__h556581[56:5] : + _theResult___fst_sfd__h557416 ; + assign _theResult___fst_sfd__h557428 = + (f2_exp__h518978 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ? - _theResult___snd_fst_sfd__h539020 : - _theResult___fst_sfd__h523186) : + _theResult___snd_fst_sfd__h538987 : + _theResult___fst_sfd__h523153) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ? - _theResult___snd_fst_sfd__h557455 : - _theResult___fst_sfd__h523186) ; - assign _theResult___fst_sfd__h557467 = - ((f2_exp__h519011 == 8'd255 || f2_exp__h519011 == 8'd0) && - f2_sfd__h519012 == 23'd0) ? + _theResult___snd_fst_sfd__h557422 : + _theResult___fst_sfd__h523153) ; + assign _theResult___fst_sfd__h557434 = + ((f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) && + f2_sfd__h518979 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h557461 ; - assign _theResult___fst_sfd__h562490 = + _theResult___fst_sfd__h557428 ; + assign _theResult___fst_sfd__h562457 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h578318 = + assign _theResult___fst_sfd__h578285 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 : + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 ; - assign _theResult___fst_sfd__h578321 = - (_theResult___fst_exp__h577562 == 11'd2047) ? - _theResult___snd__h577513[56:5] : - _theResult___fst_sfd__h578318 ; - assign _theResult___fst_sfd__h587969 = + assign _theResult___fst_sfd__h578288 = + (_theResult___fst_exp__h577529 == 11'd2047) ? + _theResult___snd__h577480[56:5] : + _theResult___fst_sfd__h578285 ; + assign _theResult___fst_sfd__h587936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 ; - assign _theResult___fst_sfd__h587972 = - (_theResult___fst_exp__h587139 == 11'd2047) ? - sfdin__h587133[56:5] : - _theResult___fst_sfd__h587969 ; - assign _theResult___fst_sfd__h596753 = + assign _theResult___fst_sfd__h587939 = + (_theResult___fst_exp__h587106 == 11'd2047) ? + sfdin__h587100[56:5] : + _theResult___fst_sfd__h587936 ; + assign _theResult___fst_sfd__h596720 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 : + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 ; - assign _theResult___fst_sfd__h596756 = - (_theResult___fst_exp__h595972 == 11'd2047) ? - _theResult___snd__h595918[56:5] : - _theResult___fst_sfd__h596753 ; - assign _theResult___fst_sfd__h596765 = - (f3_exp__h558315 == 8'd0) ? + assign _theResult___fst_sfd__h596723 = + (_theResult___fst_exp__h595939 == 11'd2047) ? + _theResult___snd__h595885[56:5] : + _theResult___fst_sfd__h596720 ; + assign _theResult___fst_sfd__h596732 = + (f3_exp__h558282 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ? - _theResult___snd_fst_sfd__h578324 : - _theResult___fst_sfd__h562490) : + _theResult___snd_fst_sfd__h578291 : + _theResult___fst_sfd__h562457) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ? - _theResult___snd_fst_sfd__h596759 : - _theResult___fst_sfd__h562490) ; - assign _theResult___fst_sfd__h596771 = - ((f3_exp__h558315 == 8'd255 || f3_exp__h558315 == 8'd0) && - f3_sfd__h558316 == 23'd0) ? + _theResult___snd_fst_sfd__h596726 : + _theResult___fst_sfd__h562457) ; + assign _theResult___fst_sfd__h596738 = + ((f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) && + f3_sfd__h558283 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h596765 ; - assign _theResult___sfd__h352590 = - sfd__h352165[24] ? - ((_theResult___fst_exp__h352073 == 8'd254) ? + _theResult___fst_sfd__h596732 ; + assign _theResult___sfd__h352557 = + sfd__h352132[24] ? + ((_theResult___fst_exp__h352040 == 8'd254) ? 23'd0 : - sfd__h352165[23:1]) : - sfd__h352165[22:0] ; - assign _theResult___sfd__h361172 = - sfd__h360747[24] ? - ((_theResult___fst_exp__h360729 == 8'd254) ? + sfd__h352132[23:1]) : + sfd__h352132[22:0] ; + assign _theResult___sfd__h361139 = + sfd__h360714[24] ? + ((_theResult___fst_exp__h360696 == 8'd254) ? 23'd0 : - sfd__h360747[23:1]) : - sfd__h360747[22:0] ; - assign _theResult___sfd__h370356 = - sfd__h369931[24] ? - ((_theResult___fst_exp__h369839 == 8'd254) ? + sfd__h360714[23:1]) : + sfd__h360714[22:0] ; + assign _theResult___sfd__h370323 = + sfd__h369898[24] ? + ((_theResult___fst_exp__h369806 == 8'd254) ? 23'd0 : - sfd__h369931[23:1]) : - sfd__h369931[22:0] ; - assign _theResult___sfd__h378992 = - sfd__h378543[24] ? - ((_theResult___fst_exp__h378524 == 8'd254) ? + sfd__h369898[23:1]) : + sfd__h369898[22:0] ; + assign _theResult___sfd__h378959 = + sfd__h378510[24] ? + ((_theResult___fst_exp__h378491 == 8'd254) ? 23'd0 : - sfd__h378543[23:1]) : - sfd__h378543[22:0] ; - assign _theResult___sfd__h379094 = + sfd__h378510[23:1]) : + sfd__h378510[22:0] ; + assign _theResult___sfd__h379061 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h336307 : - _theResult___fst_sfd__h379088 ; - assign _theResult___sfd__h398287 = - sfd__h397862[24] ? - ((_theResult___fst_exp__h397770 == 8'd254) ? + _theResult___snd_fst_sfd__h336274 : + _theResult___fst_sfd__h379055 ; + assign _theResult___sfd__h398254 = + sfd__h397829[24] ? + ((_theResult___fst_exp__h397737 == 8'd254) ? 23'd0 : - sfd__h397862[23:1]) : - sfd__h397862[22:0] ; - assign _theResult___sfd__h406869 = - sfd__h406444[24] ? - ((_theResult___fst_exp__h406426 == 8'd254) ? + sfd__h397829[23:1]) : + sfd__h397829[22:0] ; + assign _theResult___sfd__h406836 = + sfd__h406411[24] ? + ((_theResult___fst_exp__h406393 == 8'd254) ? 23'd0 : - sfd__h406444[23:1]) : - sfd__h406444[22:0] ; - assign _theResult___sfd__h416053 = - sfd__h415628[24] ? - ((_theResult___fst_exp__h415536 == 8'd254) ? + sfd__h406411[23:1]) : + sfd__h406411[22:0] ; + assign _theResult___sfd__h416020 = + sfd__h415595[24] ? + ((_theResult___fst_exp__h415503 == 8'd254) ? 23'd0 : - sfd__h415628[23:1]) : - sfd__h415628[22:0] ; - assign _theResult___sfd__h424689 = - sfd__h424240[24] ? - ((_theResult___fst_exp__h424221 == 8'd254) ? + sfd__h415595[23:1]) : + sfd__h415595[22:0] ; + assign _theResult___sfd__h424656 = + sfd__h424207[24] ? + ((_theResult___fst_exp__h424188 == 8'd254) ? 23'd0 : - sfd__h424240[23:1]) : - sfd__h424240[22:0] ; - assign _theResult___sfd__h424791 = + sfd__h424207[23:1]) : + sfd__h424207[22:0] ; + assign _theResult___sfd__h424758 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h382009 : - _theResult___fst_sfd__h424785 ; - assign _theResult___sfd__h443982 = - sfd__h443557[24] ? - ((_theResult___fst_exp__h443465 == 8'd254) ? + _theResult___snd_fst_sfd__h381976 : + _theResult___fst_sfd__h424752 ; + assign _theResult___sfd__h443949 = + sfd__h443524[24] ? + ((_theResult___fst_exp__h443432 == 8'd254) ? 23'd0 : - sfd__h443557[23:1]) : - sfd__h443557[22:0] ; - assign _theResult___sfd__h452564 = - sfd__h452139[24] ? - ((_theResult___fst_exp__h452121 == 8'd254) ? + sfd__h443524[23:1]) : + sfd__h443524[22:0] ; + assign _theResult___sfd__h452531 = + sfd__h452106[24] ? + ((_theResult___fst_exp__h452088 == 8'd254) ? 23'd0 : - sfd__h452139[23:1]) : - sfd__h452139[22:0] ; - assign _theResult___sfd__h461748 = - sfd__h461323[24] ? - ((_theResult___fst_exp__h461231 == 8'd254) ? + sfd__h452106[23:1]) : + sfd__h452106[22:0] ; + assign _theResult___sfd__h461715 = + sfd__h461290[24] ? + ((_theResult___fst_exp__h461198 == 8'd254) ? 23'd0 : - sfd__h461323[23:1]) : - sfd__h461323[22:0] ; - assign _theResult___sfd__h470384 = - sfd__h469935[24] ? - ((_theResult___fst_exp__h469916 == 8'd254) ? + sfd__h461290[23:1]) : + sfd__h461290[22:0] ; + assign _theResult___sfd__h470351 = + sfd__h469902[24] ? + ((_theResult___fst_exp__h469883 == 8'd254) ? 23'd0 : - sfd__h469935[23:1]) : - sfd__h469935[22:0] ; - assign _theResult___sfd__h470486 = + sfd__h469902[23:1]) : + sfd__h469902[22:0] ; + assign _theResult___sfd__h470453 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427704 : - _theResult___fst_sfd__h470480 ; - assign _theResult___sfd__h500061 = - sfd__h499423[53] ? - ((_theResult___fst_exp__h499405 == 11'd2046) ? + _theResult___snd_fst_sfd__h427671 : + _theResult___fst_sfd__h470447 ; + assign _theResult___sfd__h500028 = + sfd__h499390[53] ? + ((_theResult___fst_exp__h499372 == 11'd2046) ? 52'd0 : - sfd__h499423[52:1]) : - sfd__h499423[51:0] ; - assign _theResult___sfd__h509712 = - sfd__h509074[53] ? - ((_theResult___fst_exp__h508982 == 11'd2046) ? + sfd__h499390[52:1]) : + sfd__h499390[51:0] ; + assign _theResult___sfd__h509679 = + sfd__h509041[53] ? + ((_theResult___fst_exp__h508949 == 11'd2046) ? 52'd0 : - sfd__h509074[52:1]) : - sfd__h509074[51:0] ; - assign _theResult___sfd__h518496 = - sfd__h517834[53] ? - ((_theResult___fst_exp__h517815 == 11'd2046) ? + sfd__h509041[52:1]) : + sfd__h509041[51:0] ; + assign _theResult___sfd__h518463 = + sfd__h517801[53] ? + ((_theResult___fst_exp__h517782 == 11'd2046) ? 52'd0 : - sfd__h517834[52:1]) : - sfd__h517834[51:0] ; - assign _theResult___sfd__h538914 = - sfd__h538276[53] ? - ((_theResult___fst_exp__h538258 == 11'd2046) ? + sfd__h517801[52:1]) : + sfd__h517801[51:0] ; + assign _theResult___sfd__h538881 = + sfd__h538243[53] ? + ((_theResult___fst_exp__h538225 == 11'd2046) ? 52'd0 : - sfd__h538276[52:1]) : - sfd__h538276[51:0] ; - assign _theResult___sfd__h548565 = - sfd__h547927[53] ? - ((_theResult___fst_exp__h547835 == 11'd2046) ? + sfd__h538243[52:1]) : + sfd__h538243[51:0] ; + assign _theResult___sfd__h548532 = + sfd__h547894[53] ? + ((_theResult___fst_exp__h547802 == 11'd2046) ? 52'd0 : - sfd__h547927[52:1]) : - sfd__h547927[51:0] ; - assign _theResult___sfd__h557349 = - sfd__h556687[53] ? - ((_theResult___fst_exp__h556668 == 11'd2046) ? + sfd__h547894[52:1]) : + sfd__h547894[51:0] ; + assign _theResult___sfd__h557316 = + sfd__h556654[53] ? + ((_theResult___fst_exp__h556635 == 11'd2046) ? 52'd0 : - sfd__h556687[52:1]) : - sfd__h556687[51:0] ; - assign _theResult___sfd__h578218 = - sfd__h577580[53] ? - ((_theResult___fst_exp__h577562 == 11'd2046) ? + sfd__h556654[52:1]) : + sfd__h556654[51:0] ; + assign _theResult___sfd__h578185 = + sfd__h577547[53] ? + ((_theResult___fst_exp__h577529 == 11'd2046) ? 52'd0 : - sfd__h577580[52:1]) : - sfd__h577580[51:0] ; - assign _theResult___sfd__h587869 = - sfd__h587231[53] ? - ((_theResult___fst_exp__h587139 == 11'd2046) ? + sfd__h577547[52:1]) : + sfd__h577547[51:0] ; + assign _theResult___sfd__h587836 = + sfd__h587198[53] ? + ((_theResult___fst_exp__h587106 == 11'd2046) ? 52'd0 : - sfd__h587231[52:1]) : - sfd__h587231[51:0] ; - assign _theResult___sfd__h596653 = - sfd__h595991[53] ? - ((_theResult___fst_exp__h595972 == 11'd2046) ? + sfd__h587198[52:1]) : + sfd__h587198[51:0] ; + assign _theResult___sfd__h596620 = + sfd__h595958[53] ? + ((_theResult___fst_exp__h595939 == 11'd2046) ? 52'd0 : - sfd__h595991[52:1]) : - sfd__h595991[51:0] ; - assign _theResult___snd__h352084 = { _theResult____h343962[55:0], 1'd0 } ; - assign _theResult___snd__h352095 = - (!_theResult____h343962[56] && _theResult____h343962[55]) ? - _theResult___snd__h352097 : - _theResult___snd__h352107 ; - assign _theResult___snd__h352097 = { _theResult____h343962[54:0], 2'd0 } ; - assign _theResult___snd__h352107 = - (!_theResult____h343962[56] && !_theResult____h343962[55] && - !_theResult____h343962[54] && - !_theResult____h343962[53] && - !_theResult____h343962[52] && - !_theResult____h343962[51] && - !_theResult____h343962[50] && - !_theResult____h343962[49] && - !_theResult____h343962[48] && - !_theResult____h343962[47] && - !_theResult____h343962[46] && - !_theResult____h343962[45] && - !_theResult____h343962[44] && - !_theResult____h343962[43] && - !_theResult____h343962[42] && - !_theResult____h343962[41] && - !_theResult____h343962[40] && - !_theResult____h343962[39] && - !_theResult____h343962[38] && - !_theResult____h343962[37] && - !_theResult____h343962[36] && - !_theResult____h343962[35] && - !_theResult____h343962[34] && - !_theResult____h343962[33] && - !_theResult____h343962[32] && - !_theResult____h343962[31] && - !_theResult____h343962[30] && - !_theResult____h343962[29] && - !_theResult____h343962[28] && - !_theResult____h343962[27] && - !_theResult____h343962[26] && - !_theResult____h343962[25] && - !_theResult____h343962[24] && - !_theResult____h343962[23] && - !_theResult____h343962[22] && - !_theResult____h343962[21] && - !_theResult____h343962[20] && - !_theResult____h343962[19] && - !_theResult____h343962[18] && - !_theResult____h343962[17] && - !_theResult____h343962[16] && - !_theResult____h343962[15] && - !_theResult____h343962[14] && - !_theResult____h343962[13] && - !_theResult____h343962[12] && - !_theResult____h343962[11] && - !_theResult____h343962[10] && - !_theResult____h343962[9] && - !_theResult____h343962[8] && - !_theResult____h343962[7] && - !_theResult____h343962[6] && - !_theResult____h343962[5] && - !_theResult____h343962[4] && - !_theResult____h343962[3] && - !_theResult____h343962[2] && - !_theResult____h343962[1] && - !_theResult____h343962[0]) ? - _theResult____h343962 : - _theResult___snd__h352113 ; - assign _theResult___snd__h352113 = + sfd__h595958[52:1]) : + sfd__h595958[51:0] ; + assign _theResult___snd__h352051 = { _theResult____h343929[55:0], 1'd0 } ; + assign _theResult___snd__h352062 = + (!_theResult____h343929[56] && _theResult____h343929[55]) ? + _theResult___snd__h352064 : + _theResult___snd__h352074 ; + assign _theResult___snd__h352064 = { _theResult____h343929[54:0], 2'd0 } ; + assign _theResult___snd__h352074 = + (!_theResult____h343929[56] && !_theResult____h343929[55] && + !_theResult____h343929[54] && + !_theResult____h343929[53] && + !_theResult____h343929[52] && + !_theResult____h343929[51] && + !_theResult____h343929[50] && + !_theResult____h343929[49] && + !_theResult____h343929[48] && + !_theResult____h343929[47] && + !_theResult____h343929[46] && + !_theResult____h343929[45] && + !_theResult____h343929[44] && + !_theResult____h343929[43] && + !_theResult____h343929[42] && + !_theResult____h343929[41] && + !_theResult____h343929[40] && + !_theResult____h343929[39] && + !_theResult____h343929[38] && + !_theResult____h343929[37] && + !_theResult____h343929[36] && + !_theResult____h343929[35] && + !_theResult____h343929[34] && + !_theResult____h343929[33] && + !_theResult____h343929[32] && + !_theResult____h343929[31] && + !_theResult____h343929[30] && + !_theResult____h343929[29] && + !_theResult____h343929[28] && + !_theResult____h343929[27] && + !_theResult____h343929[26] && + !_theResult____h343929[25] && + !_theResult____h343929[24] && + !_theResult____h343929[23] && + !_theResult____h343929[22] && + !_theResult____h343929[21] && + !_theResult____h343929[20] && + !_theResult____h343929[19] && + !_theResult____h343929[18] && + !_theResult____h343929[17] && + !_theResult____h343929[16] && + !_theResult____h343929[15] && + !_theResult____h343929[14] && + !_theResult____h343929[13] && + !_theResult____h343929[12] && + !_theResult____h343929[11] && + !_theResult____h343929[10] && + !_theResult____h343929[9] && + !_theResult____h343929[8] && + !_theResult____h343929[7] && + !_theResult____h343929[6] && + !_theResult____h343929[5] && + !_theResult____h343929[4] && + !_theResult____h343929[3] && + !_theResult____h343929[2] && + !_theResult____h343929[1] && + !_theResult____h343929[0]) ? + _theResult____h343929 : + _theResult___snd__h352080 ; + assign _theResult___snd__h352080 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h352136 = - _theResult____h343962 << + assign _theResult___snd__h352103 = + _theResult____h343929 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360680 = + assign _theResult___snd__h360647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360689 : - _theResult___snd__h360682 ; - assign _theResult___snd__h360682 = + _theResult___snd__h360656 : + _theResult___snd__h360649 ; + assign _theResult___snd__h360649 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360689 = + assign _theResult___snd__h360656 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h336357 : - _theResult___snd__h360695 ; - assign _theResult___snd__h360695 = + sfd__h336324 : + _theResult___snd__h360662 ; + assign _theResult___snd__h360662 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h360718 = - sfd__h336357 << + assign _theResult___snd__h360685 = + sfd__h336324 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369850 = { _theResult____h361601[55:0], 1'd0 } ; - assign _theResult___snd__h369861 = - (!_theResult____h361601[56] && _theResult____h361601[55]) ? - _theResult___snd__h369863 : - _theResult___snd__h369873 ; - assign _theResult___snd__h369863 = { _theResult____h361601[54:0], 2'd0 } ; - assign _theResult___snd__h369873 = - (!_theResult____h361601[56] && !_theResult____h361601[55] && - !_theResult____h361601[54] && - !_theResult____h361601[53] && - !_theResult____h361601[52] && - !_theResult____h361601[51] && - !_theResult____h361601[50] && - !_theResult____h361601[49] && - !_theResult____h361601[48] && - !_theResult____h361601[47] && - !_theResult____h361601[46] && - !_theResult____h361601[45] && - !_theResult____h361601[44] && - !_theResult____h361601[43] && - !_theResult____h361601[42] && - !_theResult____h361601[41] && - !_theResult____h361601[40] && - !_theResult____h361601[39] && - !_theResult____h361601[38] && - !_theResult____h361601[37] && - !_theResult____h361601[36] && - !_theResult____h361601[35] && - !_theResult____h361601[34] && - !_theResult____h361601[33] && - !_theResult____h361601[32] && - !_theResult____h361601[31] && - !_theResult____h361601[30] && - !_theResult____h361601[29] && - !_theResult____h361601[28] && - !_theResult____h361601[27] && - !_theResult____h361601[26] && - !_theResult____h361601[25] && - !_theResult____h361601[24] && - !_theResult____h361601[23] && - !_theResult____h361601[22] && - !_theResult____h361601[21] && - !_theResult____h361601[20] && - !_theResult____h361601[19] && - !_theResult____h361601[18] && - !_theResult____h361601[17] && - !_theResult____h361601[16] && - !_theResult____h361601[15] && - !_theResult____h361601[14] && - !_theResult____h361601[13] && - !_theResult____h361601[12] && - !_theResult____h361601[11] && - !_theResult____h361601[10] && - !_theResult____h361601[9] && - !_theResult____h361601[8] && - !_theResult____h361601[7] && - !_theResult____h361601[6] && - !_theResult____h361601[5] && - !_theResult____h361601[4] && - !_theResult____h361601[3] && - !_theResult____h361601[2] && - !_theResult____h361601[1] && - !_theResult____h361601[0]) ? - _theResult____h361601 : - _theResult___snd__h369879 ; - assign _theResult___snd__h369879 = + assign _theResult___snd__h369817 = { _theResult____h361568[55:0], 1'd0 } ; + assign _theResult___snd__h369828 = + (!_theResult____h361568[56] && _theResult____h361568[55]) ? + _theResult___snd__h369830 : + _theResult___snd__h369840 ; + assign _theResult___snd__h369830 = { _theResult____h361568[54:0], 2'd0 } ; + assign _theResult___snd__h369840 = + (!_theResult____h361568[56] && !_theResult____h361568[55] && + !_theResult____h361568[54] && + !_theResult____h361568[53] && + !_theResult____h361568[52] && + !_theResult____h361568[51] && + !_theResult____h361568[50] && + !_theResult____h361568[49] && + !_theResult____h361568[48] && + !_theResult____h361568[47] && + !_theResult____h361568[46] && + !_theResult____h361568[45] && + !_theResult____h361568[44] && + !_theResult____h361568[43] && + !_theResult____h361568[42] && + !_theResult____h361568[41] && + !_theResult____h361568[40] && + !_theResult____h361568[39] && + !_theResult____h361568[38] && + !_theResult____h361568[37] && + !_theResult____h361568[36] && + !_theResult____h361568[35] && + !_theResult____h361568[34] && + !_theResult____h361568[33] && + !_theResult____h361568[32] && + !_theResult____h361568[31] && + !_theResult____h361568[30] && + !_theResult____h361568[29] && + !_theResult____h361568[28] && + !_theResult____h361568[27] && + !_theResult____h361568[26] && + !_theResult____h361568[25] && + !_theResult____h361568[24] && + !_theResult____h361568[23] && + !_theResult____h361568[22] && + !_theResult____h361568[21] && + !_theResult____h361568[20] && + !_theResult____h361568[19] && + !_theResult____h361568[18] && + !_theResult____h361568[17] && + !_theResult____h361568[16] && + !_theResult____h361568[15] && + !_theResult____h361568[14] && + !_theResult____h361568[13] && + !_theResult____h361568[12] && + !_theResult____h361568[11] && + !_theResult____h361568[10] && + !_theResult____h361568[9] && + !_theResult____h361568[8] && + !_theResult____h361568[7] && + !_theResult____h361568[6] && + !_theResult____h361568[5] && + !_theResult____h361568[4] && + !_theResult____h361568[3] && + !_theResult____h361568[2] && + !_theResult____h361568[1] && + !_theResult____h361568[0]) ? + _theResult____h361568 : + _theResult___snd__h369846 ; + assign _theResult___snd__h369846 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h369902 = - _theResult____h361601 << + assign _theResult___snd__h369869 = + _theResult____h361568 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h378470 = + assign _theResult___snd__h378437 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h378484 : - _theResult___snd__h360682 ; - assign _theResult___snd__h378484 = + _theResult___snd__h378451 : + _theResult___snd__h360649 ; + assign _theResult___snd__h378451 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h336357 : - _theResult___snd__h378490 ; - assign _theResult___snd__h378490 = + sfd__h336324 : + _theResult___snd__h378457 ; + assign _theResult___snd__h378457 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h378508 = - sfd__h336357 << + assign _theResult___snd__h378475 = + sfd__h336324 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397781 = { _theResult____h389661[55:0], 1'd0 } ; - assign _theResult___snd__h397792 = - (!_theResult____h389661[56] && _theResult____h389661[55]) ? - _theResult___snd__h397794 : - _theResult___snd__h397804 ; - assign _theResult___snd__h397794 = { _theResult____h389661[54:0], 2'd0 } ; - assign _theResult___snd__h397804 = - (!_theResult____h389661[56] && !_theResult____h389661[55] && - !_theResult____h389661[54] && - !_theResult____h389661[53] && - !_theResult____h389661[52] && - !_theResult____h389661[51] && - !_theResult____h389661[50] && - !_theResult____h389661[49] && - !_theResult____h389661[48] && - !_theResult____h389661[47] && - !_theResult____h389661[46] && - !_theResult____h389661[45] && - !_theResult____h389661[44] && - !_theResult____h389661[43] && - !_theResult____h389661[42] && - !_theResult____h389661[41] && - !_theResult____h389661[40] && - !_theResult____h389661[39] && - !_theResult____h389661[38] && - !_theResult____h389661[37] && - !_theResult____h389661[36] && - !_theResult____h389661[35] && - !_theResult____h389661[34] && - !_theResult____h389661[33] && - !_theResult____h389661[32] && - !_theResult____h389661[31] && - !_theResult____h389661[30] && - !_theResult____h389661[29] && - !_theResult____h389661[28] && - !_theResult____h389661[27] && - !_theResult____h389661[26] && - !_theResult____h389661[25] && - !_theResult____h389661[24] && - !_theResult____h389661[23] && - !_theResult____h389661[22] && - !_theResult____h389661[21] && - !_theResult____h389661[20] && - !_theResult____h389661[19] && - !_theResult____h389661[18] && - !_theResult____h389661[17] && - !_theResult____h389661[16] && - !_theResult____h389661[15] && - !_theResult____h389661[14] && - !_theResult____h389661[13] && - !_theResult____h389661[12] && - !_theResult____h389661[11] && - !_theResult____h389661[10] && - !_theResult____h389661[9] && - !_theResult____h389661[8] && - !_theResult____h389661[7] && - !_theResult____h389661[6] && - !_theResult____h389661[5] && - !_theResult____h389661[4] && - !_theResult____h389661[3] && - !_theResult____h389661[2] && - !_theResult____h389661[1] && - !_theResult____h389661[0]) ? - _theResult____h389661 : - _theResult___snd__h397810 ; - assign _theResult___snd__h397810 = + assign _theResult___snd__h397748 = { _theResult____h389628[55:0], 1'd0 } ; + assign _theResult___snd__h397759 = + (!_theResult____h389628[56] && _theResult____h389628[55]) ? + _theResult___snd__h397761 : + _theResult___snd__h397771 ; + assign _theResult___snd__h397761 = { _theResult____h389628[54:0], 2'd0 } ; + assign _theResult___snd__h397771 = + (!_theResult____h389628[56] && !_theResult____h389628[55] && + !_theResult____h389628[54] && + !_theResult____h389628[53] && + !_theResult____h389628[52] && + !_theResult____h389628[51] && + !_theResult____h389628[50] && + !_theResult____h389628[49] && + !_theResult____h389628[48] && + !_theResult____h389628[47] && + !_theResult____h389628[46] && + !_theResult____h389628[45] && + !_theResult____h389628[44] && + !_theResult____h389628[43] && + !_theResult____h389628[42] && + !_theResult____h389628[41] && + !_theResult____h389628[40] && + !_theResult____h389628[39] && + !_theResult____h389628[38] && + !_theResult____h389628[37] && + !_theResult____h389628[36] && + !_theResult____h389628[35] && + !_theResult____h389628[34] && + !_theResult____h389628[33] && + !_theResult____h389628[32] && + !_theResult____h389628[31] && + !_theResult____h389628[30] && + !_theResult____h389628[29] && + !_theResult____h389628[28] && + !_theResult____h389628[27] && + !_theResult____h389628[26] && + !_theResult____h389628[25] && + !_theResult____h389628[24] && + !_theResult____h389628[23] && + !_theResult____h389628[22] && + !_theResult____h389628[21] && + !_theResult____h389628[20] && + !_theResult____h389628[19] && + !_theResult____h389628[18] && + !_theResult____h389628[17] && + !_theResult____h389628[16] && + !_theResult____h389628[15] && + !_theResult____h389628[14] && + !_theResult____h389628[13] && + !_theResult____h389628[12] && + !_theResult____h389628[11] && + !_theResult____h389628[10] && + !_theResult____h389628[9] && + !_theResult____h389628[8] && + !_theResult____h389628[7] && + !_theResult____h389628[6] && + !_theResult____h389628[5] && + !_theResult____h389628[4] && + !_theResult____h389628[3] && + !_theResult____h389628[2] && + !_theResult____h389628[1] && + !_theResult____h389628[0]) ? + _theResult____h389628 : + _theResult___snd__h397777 ; + assign _theResult___snd__h397777 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h397833 = - _theResult____h389661 << + assign _theResult___snd__h397800 = + _theResult____h389628 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h406377 = + assign _theResult___snd__h406344 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h406386 : - _theResult___snd__h406379 ; - assign _theResult___snd__h406379 = + _theResult___snd__h406353 : + _theResult___snd__h406346 ; + assign _theResult___snd__h406346 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h406386 = + assign _theResult___snd__h406353 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h382059 : - _theResult___snd__h406392 ; - assign _theResult___snd__h406392 = + sfd__h382026 : + _theResult___snd__h406359 ; + assign _theResult___snd__h406359 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h406415 = - sfd__h382059 << + assign _theResult___snd__h406382 = + sfd__h382026 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h415547 = { _theResult____h407298[55:0], 1'd0 } ; - assign _theResult___snd__h415558 = - (!_theResult____h407298[56] && _theResult____h407298[55]) ? - _theResult___snd__h415560 : - _theResult___snd__h415570 ; - assign _theResult___snd__h415560 = { _theResult____h407298[54:0], 2'd0 } ; - assign _theResult___snd__h415570 = - (!_theResult____h407298[56] && !_theResult____h407298[55] && - !_theResult____h407298[54] && - !_theResult____h407298[53] && - !_theResult____h407298[52] && - !_theResult____h407298[51] && - !_theResult____h407298[50] && - !_theResult____h407298[49] && - !_theResult____h407298[48] && - !_theResult____h407298[47] && - !_theResult____h407298[46] && - !_theResult____h407298[45] && - !_theResult____h407298[44] && - !_theResult____h407298[43] && - !_theResult____h407298[42] && - !_theResult____h407298[41] && - !_theResult____h407298[40] && - !_theResult____h407298[39] && - !_theResult____h407298[38] && - !_theResult____h407298[37] && - !_theResult____h407298[36] && - !_theResult____h407298[35] && - !_theResult____h407298[34] && - !_theResult____h407298[33] && - !_theResult____h407298[32] && - !_theResult____h407298[31] && - !_theResult____h407298[30] && - !_theResult____h407298[29] && - !_theResult____h407298[28] && - !_theResult____h407298[27] && - !_theResult____h407298[26] && - !_theResult____h407298[25] && - !_theResult____h407298[24] && - !_theResult____h407298[23] && - !_theResult____h407298[22] && - !_theResult____h407298[21] && - !_theResult____h407298[20] && - !_theResult____h407298[19] && - !_theResult____h407298[18] && - !_theResult____h407298[17] && - !_theResult____h407298[16] && - !_theResult____h407298[15] && - !_theResult____h407298[14] && - !_theResult____h407298[13] && - !_theResult____h407298[12] && - !_theResult____h407298[11] && - !_theResult____h407298[10] && - !_theResult____h407298[9] && - !_theResult____h407298[8] && - !_theResult____h407298[7] && - !_theResult____h407298[6] && - !_theResult____h407298[5] && - !_theResult____h407298[4] && - !_theResult____h407298[3] && - !_theResult____h407298[2] && - !_theResult____h407298[1] && - !_theResult____h407298[0]) ? - _theResult____h407298 : - _theResult___snd__h415576 ; - assign _theResult___snd__h415576 = + assign _theResult___snd__h415514 = { _theResult____h407265[55:0], 1'd0 } ; + assign _theResult___snd__h415525 = + (!_theResult____h407265[56] && _theResult____h407265[55]) ? + _theResult___snd__h415527 : + _theResult___snd__h415537 ; + assign _theResult___snd__h415527 = { _theResult____h407265[54:0], 2'd0 } ; + assign _theResult___snd__h415537 = + (!_theResult____h407265[56] && !_theResult____h407265[55] && + !_theResult____h407265[54] && + !_theResult____h407265[53] && + !_theResult____h407265[52] && + !_theResult____h407265[51] && + !_theResult____h407265[50] && + !_theResult____h407265[49] && + !_theResult____h407265[48] && + !_theResult____h407265[47] && + !_theResult____h407265[46] && + !_theResult____h407265[45] && + !_theResult____h407265[44] && + !_theResult____h407265[43] && + !_theResult____h407265[42] && + !_theResult____h407265[41] && + !_theResult____h407265[40] && + !_theResult____h407265[39] && + !_theResult____h407265[38] && + !_theResult____h407265[37] && + !_theResult____h407265[36] && + !_theResult____h407265[35] && + !_theResult____h407265[34] && + !_theResult____h407265[33] && + !_theResult____h407265[32] && + !_theResult____h407265[31] && + !_theResult____h407265[30] && + !_theResult____h407265[29] && + !_theResult____h407265[28] && + !_theResult____h407265[27] && + !_theResult____h407265[26] && + !_theResult____h407265[25] && + !_theResult____h407265[24] && + !_theResult____h407265[23] && + !_theResult____h407265[22] && + !_theResult____h407265[21] && + !_theResult____h407265[20] && + !_theResult____h407265[19] && + !_theResult____h407265[18] && + !_theResult____h407265[17] && + !_theResult____h407265[16] && + !_theResult____h407265[15] && + !_theResult____h407265[14] && + !_theResult____h407265[13] && + !_theResult____h407265[12] && + !_theResult____h407265[11] && + !_theResult____h407265[10] && + !_theResult____h407265[9] && + !_theResult____h407265[8] && + !_theResult____h407265[7] && + !_theResult____h407265[6] && + !_theResult____h407265[5] && + !_theResult____h407265[4] && + !_theResult____h407265[3] && + !_theResult____h407265[2] && + !_theResult____h407265[1] && + !_theResult____h407265[0]) ? + _theResult____h407265 : + _theResult___snd__h415543 ; + assign _theResult___snd__h415543 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h415599 = - _theResult____h407298 << + assign _theResult___snd__h415566 = + _theResult____h407265 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h424167 = + assign _theResult___snd__h424134 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h424181 : - _theResult___snd__h406379 ; - assign _theResult___snd__h424181 = + _theResult___snd__h424148 : + _theResult___snd__h406346 ; + assign _theResult___snd__h424148 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h382059 : - _theResult___snd__h424187 ; - assign _theResult___snd__h424187 = + sfd__h382026 : + _theResult___snd__h424154 ; + assign _theResult___snd__h424154 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h424205 = - sfd__h382059 << + assign _theResult___snd__h424172 = + sfd__h382026 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h443476 = { _theResult____h435356[55:0], 1'd0 } ; - assign _theResult___snd__h443487 = - (!_theResult____h435356[56] && _theResult____h435356[55]) ? - _theResult___snd__h443489 : - _theResult___snd__h443499 ; - assign _theResult___snd__h443489 = { _theResult____h435356[54:0], 2'd0 } ; - assign _theResult___snd__h443499 = - (!_theResult____h435356[56] && !_theResult____h435356[55] && - !_theResult____h435356[54] && - !_theResult____h435356[53] && - !_theResult____h435356[52] && - !_theResult____h435356[51] && - !_theResult____h435356[50] && - !_theResult____h435356[49] && - !_theResult____h435356[48] && - !_theResult____h435356[47] && - !_theResult____h435356[46] && - !_theResult____h435356[45] && - !_theResult____h435356[44] && - !_theResult____h435356[43] && - !_theResult____h435356[42] && - !_theResult____h435356[41] && - !_theResult____h435356[40] && - !_theResult____h435356[39] && - !_theResult____h435356[38] && - !_theResult____h435356[37] && - !_theResult____h435356[36] && - !_theResult____h435356[35] && - !_theResult____h435356[34] && - !_theResult____h435356[33] && - !_theResult____h435356[32] && - !_theResult____h435356[31] && - !_theResult____h435356[30] && - !_theResult____h435356[29] && - !_theResult____h435356[28] && - !_theResult____h435356[27] && - !_theResult____h435356[26] && - !_theResult____h435356[25] && - !_theResult____h435356[24] && - !_theResult____h435356[23] && - !_theResult____h435356[22] && - !_theResult____h435356[21] && - !_theResult____h435356[20] && - !_theResult____h435356[19] && - !_theResult____h435356[18] && - !_theResult____h435356[17] && - !_theResult____h435356[16] && - !_theResult____h435356[15] && - !_theResult____h435356[14] && - !_theResult____h435356[13] && - !_theResult____h435356[12] && - !_theResult____h435356[11] && - !_theResult____h435356[10] && - !_theResult____h435356[9] && - !_theResult____h435356[8] && - !_theResult____h435356[7] && - !_theResult____h435356[6] && - !_theResult____h435356[5] && - !_theResult____h435356[4] && - !_theResult____h435356[3] && - !_theResult____h435356[2] && - !_theResult____h435356[1] && - !_theResult____h435356[0]) ? - _theResult____h435356 : - _theResult___snd__h443505 ; - assign _theResult___snd__h443505 = + assign _theResult___snd__h443443 = { _theResult____h435323[55:0], 1'd0 } ; + assign _theResult___snd__h443454 = + (!_theResult____h435323[56] && _theResult____h435323[55]) ? + _theResult___snd__h443456 : + _theResult___snd__h443466 ; + assign _theResult___snd__h443456 = { _theResult____h435323[54:0], 2'd0 } ; + assign _theResult___snd__h443466 = + (!_theResult____h435323[56] && !_theResult____h435323[55] && + !_theResult____h435323[54] && + !_theResult____h435323[53] && + !_theResult____h435323[52] && + !_theResult____h435323[51] && + !_theResult____h435323[50] && + !_theResult____h435323[49] && + !_theResult____h435323[48] && + !_theResult____h435323[47] && + !_theResult____h435323[46] && + !_theResult____h435323[45] && + !_theResult____h435323[44] && + !_theResult____h435323[43] && + !_theResult____h435323[42] && + !_theResult____h435323[41] && + !_theResult____h435323[40] && + !_theResult____h435323[39] && + !_theResult____h435323[38] && + !_theResult____h435323[37] && + !_theResult____h435323[36] && + !_theResult____h435323[35] && + !_theResult____h435323[34] && + !_theResult____h435323[33] && + !_theResult____h435323[32] && + !_theResult____h435323[31] && + !_theResult____h435323[30] && + !_theResult____h435323[29] && + !_theResult____h435323[28] && + !_theResult____h435323[27] && + !_theResult____h435323[26] && + !_theResult____h435323[25] && + !_theResult____h435323[24] && + !_theResult____h435323[23] && + !_theResult____h435323[22] && + !_theResult____h435323[21] && + !_theResult____h435323[20] && + !_theResult____h435323[19] && + !_theResult____h435323[18] && + !_theResult____h435323[17] && + !_theResult____h435323[16] && + !_theResult____h435323[15] && + !_theResult____h435323[14] && + !_theResult____h435323[13] && + !_theResult____h435323[12] && + !_theResult____h435323[11] && + !_theResult____h435323[10] && + !_theResult____h435323[9] && + !_theResult____h435323[8] && + !_theResult____h435323[7] && + !_theResult____h435323[6] && + !_theResult____h435323[5] && + !_theResult____h435323[4] && + !_theResult____h435323[3] && + !_theResult____h435323[2] && + !_theResult____h435323[1] && + !_theResult____h435323[0]) ? + _theResult____h435323 : + _theResult___snd__h443472 ; + assign _theResult___snd__h443472 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h443528 = - _theResult____h435356 << + assign _theResult___snd__h443495 = + _theResult____h435323 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h452072 = + assign _theResult___snd__h452039 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h452081 : - _theResult___snd__h452074 ; - assign _theResult___snd__h452074 = + _theResult___snd__h452048 : + _theResult___snd__h452041 ; + assign _theResult___snd__h452041 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h452081 = + assign _theResult___snd__h452048 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427754 : - _theResult___snd__h452087 ; - assign _theResult___snd__h452087 = + sfd__h427721 : + _theResult___snd__h452054 ; + assign _theResult___snd__h452054 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h452110 = - sfd__h427754 << + assign _theResult___snd__h452077 = + sfd__h427721 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h461242 = { _theResult____h452993[55:0], 1'd0 } ; - assign _theResult___snd__h461253 = - (!_theResult____h452993[56] && _theResult____h452993[55]) ? - _theResult___snd__h461255 : - _theResult___snd__h461265 ; - assign _theResult___snd__h461255 = { _theResult____h452993[54:0], 2'd0 } ; - assign _theResult___snd__h461265 = - (!_theResult____h452993[56] && !_theResult____h452993[55] && - !_theResult____h452993[54] && - !_theResult____h452993[53] && - !_theResult____h452993[52] && - !_theResult____h452993[51] && - !_theResult____h452993[50] && - !_theResult____h452993[49] && - !_theResult____h452993[48] && - !_theResult____h452993[47] && - !_theResult____h452993[46] && - !_theResult____h452993[45] && - !_theResult____h452993[44] && - !_theResult____h452993[43] && - !_theResult____h452993[42] && - !_theResult____h452993[41] && - !_theResult____h452993[40] && - !_theResult____h452993[39] && - !_theResult____h452993[38] && - !_theResult____h452993[37] && - !_theResult____h452993[36] && - !_theResult____h452993[35] && - !_theResult____h452993[34] && - !_theResult____h452993[33] && - !_theResult____h452993[32] && - !_theResult____h452993[31] && - !_theResult____h452993[30] && - !_theResult____h452993[29] && - !_theResult____h452993[28] && - !_theResult____h452993[27] && - !_theResult____h452993[26] && - !_theResult____h452993[25] && - !_theResult____h452993[24] && - !_theResult____h452993[23] && - !_theResult____h452993[22] && - !_theResult____h452993[21] && - !_theResult____h452993[20] && - !_theResult____h452993[19] && - !_theResult____h452993[18] && - !_theResult____h452993[17] && - !_theResult____h452993[16] && - !_theResult____h452993[15] && - !_theResult____h452993[14] && - !_theResult____h452993[13] && - !_theResult____h452993[12] && - !_theResult____h452993[11] && - !_theResult____h452993[10] && - !_theResult____h452993[9] && - !_theResult____h452993[8] && - !_theResult____h452993[7] && - !_theResult____h452993[6] && - !_theResult____h452993[5] && - !_theResult____h452993[4] && - !_theResult____h452993[3] && - !_theResult____h452993[2] && - !_theResult____h452993[1] && - !_theResult____h452993[0]) ? - _theResult____h452993 : - _theResult___snd__h461271 ; - assign _theResult___snd__h461271 = + assign _theResult___snd__h461209 = { _theResult____h452960[55:0], 1'd0 } ; + assign _theResult___snd__h461220 = + (!_theResult____h452960[56] && _theResult____h452960[55]) ? + _theResult___snd__h461222 : + _theResult___snd__h461232 ; + assign _theResult___snd__h461222 = { _theResult____h452960[54:0], 2'd0 } ; + assign _theResult___snd__h461232 = + (!_theResult____h452960[56] && !_theResult____h452960[55] && + !_theResult____h452960[54] && + !_theResult____h452960[53] && + !_theResult____h452960[52] && + !_theResult____h452960[51] && + !_theResult____h452960[50] && + !_theResult____h452960[49] && + !_theResult____h452960[48] && + !_theResult____h452960[47] && + !_theResult____h452960[46] && + !_theResult____h452960[45] && + !_theResult____h452960[44] && + !_theResult____h452960[43] && + !_theResult____h452960[42] && + !_theResult____h452960[41] && + !_theResult____h452960[40] && + !_theResult____h452960[39] && + !_theResult____h452960[38] && + !_theResult____h452960[37] && + !_theResult____h452960[36] && + !_theResult____h452960[35] && + !_theResult____h452960[34] && + !_theResult____h452960[33] && + !_theResult____h452960[32] && + !_theResult____h452960[31] && + !_theResult____h452960[30] && + !_theResult____h452960[29] && + !_theResult____h452960[28] && + !_theResult____h452960[27] && + !_theResult____h452960[26] && + !_theResult____h452960[25] && + !_theResult____h452960[24] && + !_theResult____h452960[23] && + !_theResult____h452960[22] && + !_theResult____h452960[21] && + !_theResult____h452960[20] && + !_theResult____h452960[19] && + !_theResult____h452960[18] && + !_theResult____h452960[17] && + !_theResult____h452960[16] && + !_theResult____h452960[15] && + !_theResult____h452960[14] && + !_theResult____h452960[13] && + !_theResult____h452960[12] && + !_theResult____h452960[11] && + !_theResult____h452960[10] && + !_theResult____h452960[9] && + !_theResult____h452960[8] && + !_theResult____h452960[7] && + !_theResult____h452960[6] && + !_theResult____h452960[5] && + !_theResult____h452960[4] && + !_theResult____h452960[3] && + !_theResult____h452960[2] && + !_theResult____h452960[1] && + !_theResult____h452960[0]) ? + _theResult____h452960 : + _theResult___snd__h461238 ; + assign _theResult___snd__h461238 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h461294 = - _theResult____h452993 << + assign _theResult___snd__h461261 = + _theResult____h452960 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469862 = + assign _theResult___snd__h469829 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469876 : - _theResult___snd__h452074 ; - assign _theResult___snd__h469876 = + _theResult___snd__h469843 : + _theResult___snd__h452041 ; + assign _theResult___snd__h469843 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427754 : - _theResult___snd__h469882 ; - assign _theResult___snd__h469882 = + sfd__h427721 : + _theResult___snd__h469849 ; + assign _theResult___snd__h469849 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h469900 = - sfd__h427754 << + assign _theResult___snd__h469867 = + sfd__h427721 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h499356 = - (f1_exp__h480017 == 8'd0) ? - _theResult___snd__h499365 : - _theResult___snd__h499358 ; - assign _theResult___snd__h499358 = { f1_sfd__h480018, 34'd0 } ; - assign _theResult___snd__h499365 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && + assign _theResult___snd__h499323 = + (f1_exp__h479984 == 8'd0) ? + _theResult___snd__h499332 : + _theResult___snd__h499325 ; + assign _theResult___snd__h499325 = { f1_sfd__h479985, 34'd0 } ; + assign _theResult___snd__h499332 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ? - sfd__h480379 : - _theResult___snd__h499371 ; - assign _theResult___snd__h499371 = + sfd__h480346 : + _theResult___snd__h499338 ; + assign _theResult___snd__h499338 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h499394 = - sfd__h480379 << + assign _theResult___snd__h499361 = + sfd__h480346 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 ; - assign _theResult___snd__h508993 = { _theResult____h500746[55:0], 1'd0 } ; - assign _theResult___snd__h509004 = - (!_theResult____h500746[56] && _theResult____h500746[55]) ? - _theResult___snd__h509006 : - _theResult___snd__h509016 ; - assign _theResult___snd__h509006 = { _theResult____h500746[54:0], 2'd0 } ; - assign _theResult___snd__h509016 = - (!_theResult____h500746[56] && !_theResult____h500746[55] && - !_theResult____h500746[54] && - !_theResult____h500746[53] && - !_theResult____h500746[52] && - !_theResult____h500746[51] && - !_theResult____h500746[50] && - !_theResult____h500746[49] && - !_theResult____h500746[48] && - !_theResult____h500746[47] && - !_theResult____h500746[46] && - !_theResult____h500746[45] && - !_theResult____h500746[44] && - !_theResult____h500746[43] && - !_theResult____h500746[42] && - !_theResult____h500746[41] && - !_theResult____h500746[40] && - !_theResult____h500746[39] && - !_theResult____h500746[38] && - !_theResult____h500746[37] && - !_theResult____h500746[36] && - !_theResult____h500746[35] && - !_theResult____h500746[34] && - !_theResult____h500746[33] && - !_theResult____h500746[32] && - !_theResult____h500746[31] && - !_theResult____h500746[30] && - !_theResult____h500746[29] && - !_theResult____h500746[28] && - !_theResult____h500746[27] && - !_theResult____h500746[26] && - !_theResult____h500746[25] && - !_theResult____h500746[24] && - !_theResult____h500746[23] && - !_theResult____h500746[22] && - !_theResult____h500746[21] && - !_theResult____h500746[20] && - !_theResult____h500746[19] && - !_theResult____h500746[18] && - !_theResult____h500746[17] && - !_theResult____h500746[16] && - !_theResult____h500746[15] && - !_theResult____h500746[14] && - !_theResult____h500746[13] && - !_theResult____h500746[12] && - !_theResult____h500746[11] && - !_theResult____h500746[10] && - !_theResult____h500746[9] && - !_theResult____h500746[8] && - !_theResult____h500746[7] && - !_theResult____h500746[6] && - !_theResult____h500746[5] && - !_theResult____h500746[4] && - !_theResult____h500746[3] && - !_theResult____h500746[2] && - !_theResult____h500746[1] && - !_theResult____h500746[0]) ? - _theResult____h500746 : - _theResult___snd__h509022 ; - assign _theResult___snd__h509022 = + assign _theResult___snd__h508960 = { _theResult____h500713[55:0], 1'd0 } ; + assign _theResult___snd__h508971 = + (!_theResult____h500713[56] && _theResult____h500713[55]) ? + _theResult___snd__h508973 : + _theResult___snd__h508983 ; + assign _theResult___snd__h508973 = { _theResult____h500713[54:0], 2'd0 } ; + assign _theResult___snd__h508983 = + (!_theResult____h500713[56] && !_theResult____h500713[55] && + !_theResult____h500713[54] && + !_theResult____h500713[53] && + !_theResult____h500713[52] && + !_theResult____h500713[51] && + !_theResult____h500713[50] && + !_theResult____h500713[49] && + !_theResult____h500713[48] && + !_theResult____h500713[47] && + !_theResult____h500713[46] && + !_theResult____h500713[45] && + !_theResult____h500713[44] && + !_theResult____h500713[43] && + !_theResult____h500713[42] && + !_theResult____h500713[41] && + !_theResult____h500713[40] && + !_theResult____h500713[39] && + !_theResult____h500713[38] && + !_theResult____h500713[37] && + !_theResult____h500713[36] && + !_theResult____h500713[35] && + !_theResult____h500713[34] && + !_theResult____h500713[33] && + !_theResult____h500713[32] && + !_theResult____h500713[31] && + !_theResult____h500713[30] && + !_theResult____h500713[29] && + !_theResult____h500713[28] && + !_theResult____h500713[27] && + !_theResult____h500713[26] && + !_theResult____h500713[25] && + !_theResult____h500713[24] && + !_theResult____h500713[23] && + !_theResult____h500713[22] && + !_theResult____h500713[21] && + !_theResult____h500713[20] && + !_theResult____h500713[19] && + !_theResult____h500713[18] && + !_theResult____h500713[17] && + !_theResult____h500713[16] && + !_theResult____h500713[15] && + !_theResult____h500713[14] && + !_theResult____h500713[13] && + !_theResult____h500713[12] && + !_theResult____h500713[11] && + !_theResult____h500713[10] && + !_theResult____h500713[9] && + !_theResult____h500713[8] && + !_theResult____h500713[7] && + !_theResult____h500713[6] && + !_theResult____h500713[5] && + !_theResult____h500713[4] && + !_theResult____h500713[3] && + !_theResult____h500713[2] && + !_theResult____h500713[1] && + !_theResult____h500713[0]) ? + _theResult____h500713 : + _theResult___snd__h508989 ; + assign _theResult___snd__h508989 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h509045 = - _theResult____h500746 << + assign _theResult___snd__h509012 = + _theResult____h500713 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 ; - assign _theResult___snd__h517761 = - (f1_exp__h480017 == 8'd0) ? - _theResult___snd__h517775 : - _theResult___snd__h499358 ; - assign _theResult___snd__h517775 = - (f1_exp__h480017 == 8'd0 && !f1_sfd__h480018[22] && + assign _theResult___snd__h517728 = + (f1_exp__h479984 == 8'd0) ? + _theResult___snd__h517742 : + _theResult___snd__h499325 ; + assign _theResult___snd__h517742 = + (f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ? - sfd__h480379 : - _theResult___snd__h517781 ; - assign _theResult___snd__h517781 = + sfd__h480346 : + _theResult___snd__h517748 ; + assign _theResult___snd__h517748 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h517799 = - sfd__h480379 << + assign _theResult___snd__h517766 = + sfd__h480346 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 ; - assign _theResult___snd__h538209 = - (f2_exp__h519011 == 8'd0) ? - _theResult___snd__h538218 : - _theResult___snd__h538211 ; - assign _theResult___snd__h538211 = { f2_sfd__h519012, 34'd0 } ; - assign _theResult___snd__h538218 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && + assign _theResult___snd__h538176 = + (f2_exp__h518978 == 8'd0) ? + _theResult___snd__h538185 : + _theResult___snd__h538178 ; + assign _theResult___snd__h538178 = { f2_sfd__h518979, 34'd0 } ; + assign _theResult___snd__h538185 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ? - sfd__h519373 : - _theResult___snd__h538224 ; - assign _theResult___snd__h538224 = + sfd__h519340 : + _theResult___snd__h538191 ; + assign _theResult___snd__h538191 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h538247 = - sfd__h519373 << + assign _theResult___snd__h538214 = + sfd__h519340 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 ; - assign _theResult___snd__h547846 = { _theResult____h539599[55:0], 1'd0 } ; - assign _theResult___snd__h547857 = - (!_theResult____h539599[56] && _theResult____h539599[55]) ? - _theResult___snd__h547859 : - _theResult___snd__h547869 ; - assign _theResult___snd__h547859 = { _theResult____h539599[54:0], 2'd0 } ; - assign _theResult___snd__h547869 = - (!_theResult____h539599[56] && !_theResult____h539599[55] && - !_theResult____h539599[54] && - !_theResult____h539599[53] && - !_theResult____h539599[52] && - !_theResult____h539599[51] && - !_theResult____h539599[50] && - !_theResult____h539599[49] && - !_theResult____h539599[48] && - !_theResult____h539599[47] && - !_theResult____h539599[46] && - !_theResult____h539599[45] && - !_theResult____h539599[44] && - !_theResult____h539599[43] && - !_theResult____h539599[42] && - !_theResult____h539599[41] && - !_theResult____h539599[40] && - !_theResult____h539599[39] && - !_theResult____h539599[38] && - !_theResult____h539599[37] && - !_theResult____h539599[36] && - !_theResult____h539599[35] && - !_theResult____h539599[34] && - !_theResult____h539599[33] && - !_theResult____h539599[32] && - !_theResult____h539599[31] && - !_theResult____h539599[30] && - !_theResult____h539599[29] && - !_theResult____h539599[28] && - !_theResult____h539599[27] && - !_theResult____h539599[26] && - !_theResult____h539599[25] && - !_theResult____h539599[24] && - !_theResult____h539599[23] && - !_theResult____h539599[22] && - !_theResult____h539599[21] && - !_theResult____h539599[20] && - !_theResult____h539599[19] && - !_theResult____h539599[18] && - !_theResult____h539599[17] && - !_theResult____h539599[16] && - !_theResult____h539599[15] && - !_theResult____h539599[14] && - !_theResult____h539599[13] && - !_theResult____h539599[12] && - !_theResult____h539599[11] && - !_theResult____h539599[10] && - !_theResult____h539599[9] && - !_theResult____h539599[8] && - !_theResult____h539599[7] && - !_theResult____h539599[6] && - !_theResult____h539599[5] && - !_theResult____h539599[4] && - !_theResult____h539599[3] && - !_theResult____h539599[2] && - !_theResult____h539599[1] && - !_theResult____h539599[0]) ? - _theResult____h539599 : - _theResult___snd__h547875 ; - assign _theResult___snd__h547875 = + assign _theResult___snd__h547813 = { _theResult____h539566[55:0], 1'd0 } ; + assign _theResult___snd__h547824 = + (!_theResult____h539566[56] && _theResult____h539566[55]) ? + _theResult___snd__h547826 : + _theResult___snd__h547836 ; + assign _theResult___snd__h547826 = { _theResult____h539566[54:0], 2'd0 } ; + assign _theResult___snd__h547836 = + (!_theResult____h539566[56] && !_theResult____h539566[55] && + !_theResult____h539566[54] && + !_theResult____h539566[53] && + !_theResult____h539566[52] && + !_theResult____h539566[51] && + !_theResult____h539566[50] && + !_theResult____h539566[49] && + !_theResult____h539566[48] && + !_theResult____h539566[47] && + !_theResult____h539566[46] && + !_theResult____h539566[45] && + !_theResult____h539566[44] && + !_theResult____h539566[43] && + !_theResult____h539566[42] && + !_theResult____h539566[41] && + !_theResult____h539566[40] && + !_theResult____h539566[39] && + !_theResult____h539566[38] && + !_theResult____h539566[37] && + !_theResult____h539566[36] && + !_theResult____h539566[35] && + !_theResult____h539566[34] && + !_theResult____h539566[33] && + !_theResult____h539566[32] && + !_theResult____h539566[31] && + !_theResult____h539566[30] && + !_theResult____h539566[29] && + !_theResult____h539566[28] && + !_theResult____h539566[27] && + !_theResult____h539566[26] && + !_theResult____h539566[25] && + !_theResult____h539566[24] && + !_theResult____h539566[23] && + !_theResult____h539566[22] && + !_theResult____h539566[21] && + !_theResult____h539566[20] && + !_theResult____h539566[19] && + !_theResult____h539566[18] && + !_theResult____h539566[17] && + !_theResult____h539566[16] && + !_theResult____h539566[15] && + !_theResult____h539566[14] && + !_theResult____h539566[13] && + !_theResult____h539566[12] && + !_theResult____h539566[11] && + !_theResult____h539566[10] && + !_theResult____h539566[9] && + !_theResult____h539566[8] && + !_theResult____h539566[7] && + !_theResult____h539566[6] && + !_theResult____h539566[5] && + !_theResult____h539566[4] && + !_theResult____h539566[3] && + !_theResult____h539566[2] && + !_theResult____h539566[1] && + !_theResult____h539566[0]) ? + _theResult____h539566 : + _theResult___snd__h547842 ; + assign _theResult___snd__h547842 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h547898 = - _theResult____h539599 << + assign _theResult___snd__h547865 = + _theResult____h539566 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 ; - assign _theResult___snd__h556614 = - (f2_exp__h519011 == 8'd0) ? - _theResult___snd__h556628 : - _theResult___snd__h538211 ; - assign _theResult___snd__h556628 = - (f2_exp__h519011 == 8'd0 && !f2_sfd__h519012[22] && + assign _theResult___snd__h556581 = + (f2_exp__h518978 == 8'd0) ? + _theResult___snd__h556595 : + _theResult___snd__h538178 ; + assign _theResult___snd__h556595 = + (f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ? - sfd__h519373 : - _theResult___snd__h556634 ; - assign _theResult___snd__h556634 = + sfd__h519340 : + _theResult___snd__h556601 ; + assign _theResult___snd__h556601 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h556652 = - sfd__h519373 << + assign _theResult___snd__h556619 = + sfd__h519340 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428 ; - assign _theResult___snd__h577513 = - (f3_exp__h558315 == 8'd0) ? - _theResult___snd__h577522 : - _theResult___snd__h577515 ; - assign _theResult___snd__h577515 = { f3_sfd__h558316, 34'd0 } ; - assign _theResult___snd__h577522 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___snd__h577480 = + (f3_exp__h558282 == 8'd0) ? + _theResult___snd__h577489 : + _theResult___snd__h577482 ; + assign _theResult___snd__h577482 = { f3_sfd__h558283, 34'd0 } ; + assign _theResult___snd__h577489 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ? - sfd__h558677 : - _theResult___snd__h577528 ; - assign _theResult___snd__h577528 = + sfd__h558644 : + _theResult___snd__h577495 ; + assign _theResult___snd__h577495 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h577551 = - sfd__h558677 << + assign _theResult___snd__h577518 = + sfd__h558644 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 ; - assign _theResult___snd__h587150 = { _theResult____h578903[55:0], 1'd0 } ; - assign _theResult___snd__h587161 = - (!_theResult____h578903[56] && _theResult____h578903[55]) ? - _theResult___snd__h587163 : - _theResult___snd__h587173 ; - assign _theResult___snd__h587163 = { _theResult____h578903[54:0], 2'd0 } ; - assign _theResult___snd__h587173 = - (!_theResult____h578903[56] && !_theResult____h578903[55] && - !_theResult____h578903[54] && - !_theResult____h578903[53] && - !_theResult____h578903[52] && - !_theResult____h578903[51] && - !_theResult____h578903[50] && - !_theResult____h578903[49] && - !_theResult____h578903[48] && - !_theResult____h578903[47] && - !_theResult____h578903[46] && - !_theResult____h578903[45] && - !_theResult____h578903[44] && - !_theResult____h578903[43] && - !_theResult____h578903[42] && - !_theResult____h578903[41] && - !_theResult____h578903[40] && - !_theResult____h578903[39] && - !_theResult____h578903[38] && - !_theResult____h578903[37] && - !_theResult____h578903[36] && - !_theResult____h578903[35] && - !_theResult____h578903[34] && - !_theResult____h578903[33] && - !_theResult____h578903[32] && - !_theResult____h578903[31] && - !_theResult____h578903[30] && - !_theResult____h578903[29] && - !_theResult____h578903[28] && - !_theResult____h578903[27] && - !_theResult____h578903[26] && - !_theResult____h578903[25] && - !_theResult____h578903[24] && - !_theResult____h578903[23] && - !_theResult____h578903[22] && - !_theResult____h578903[21] && - !_theResult____h578903[20] && - !_theResult____h578903[19] && - !_theResult____h578903[18] && - !_theResult____h578903[17] && - !_theResult____h578903[16] && - !_theResult____h578903[15] && - !_theResult____h578903[14] && - !_theResult____h578903[13] && - !_theResult____h578903[12] && - !_theResult____h578903[11] && - !_theResult____h578903[10] && - !_theResult____h578903[9] && - !_theResult____h578903[8] && - !_theResult____h578903[7] && - !_theResult____h578903[6] && - !_theResult____h578903[5] && - !_theResult____h578903[4] && - !_theResult____h578903[3] && - !_theResult____h578903[2] && - !_theResult____h578903[1] && - !_theResult____h578903[0]) ? - _theResult____h578903 : - _theResult___snd__h587179 ; - assign _theResult___snd__h587179 = + assign _theResult___snd__h587117 = { _theResult____h578870[55:0], 1'd0 } ; + assign _theResult___snd__h587128 = + (!_theResult____h578870[56] && _theResult____h578870[55]) ? + _theResult___snd__h587130 : + _theResult___snd__h587140 ; + assign _theResult___snd__h587130 = { _theResult____h578870[54:0], 2'd0 } ; + assign _theResult___snd__h587140 = + (!_theResult____h578870[56] && !_theResult____h578870[55] && + !_theResult____h578870[54] && + !_theResult____h578870[53] && + !_theResult____h578870[52] && + !_theResult____h578870[51] && + !_theResult____h578870[50] && + !_theResult____h578870[49] && + !_theResult____h578870[48] && + !_theResult____h578870[47] && + !_theResult____h578870[46] && + !_theResult____h578870[45] && + !_theResult____h578870[44] && + !_theResult____h578870[43] && + !_theResult____h578870[42] && + !_theResult____h578870[41] && + !_theResult____h578870[40] && + !_theResult____h578870[39] && + !_theResult____h578870[38] && + !_theResult____h578870[37] && + !_theResult____h578870[36] && + !_theResult____h578870[35] && + !_theResult____h578870[34] && + !_theResult____h578870[33] && + !_theResult____h578870[32] && + !_theResult____h578870[31] && + !_theResult____h578870[30] && + !_theResult____h578870[29] && + !_theResult____h578870[28] && + !_theResult____h578870[27] && + !_theResult____h578870[26] && + !_theResult____h578870[25] && + !_theResult____h578870[24] && + !_theResult____h578870[23] && + !_theResult____h578870[22] && + !_theResult____h578870[21] && + !_theResult____h578870[20] && + !_theResult____h578870[19] && + !_theResult____h578870[18] && + !_theResult____h578870[17] && + !_theResult____h578870[16] && + !_theResult____h578870[15] && + !_theResult____h578870[14] && + !_theResult____h578870[13] && + !_theResult____h578870[12] && + !_theResult____h578870[11] && + !_theResult____h578870[10] && + !_theResult____h578870[9] && + !_theResult____h578870[8] && + !_theResult____h578870[7] && + !_theResult____h578870[6] && + !_theResult____h578870[5] && + !_theResult____h578870[4] && + !_theResult____h578870[3] && + !_theResult____h578870[2] && + !_theResult____h578870[1] && + !_theResult____h578870[0]) ? + _theResult____h578870 : + _theResult___snd__h587146 ; + assign _theResult___snd__h587146 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h587202 = - _theResult____h578903 << + assign _theResult___snd__h587169 = + _theResult____h578870 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 ; - assign _theResult___snd__h595918 = - (f3_exp__h558315 == 8'd0) ? - _theResult___snd__h595932 : - _theResult___snd__h577515 ; - assign _theResult___snd__h595932 = - (f3_exp__h558315 == 8'd0 && !f3_sfd__h558316[22] && + assign _theResult___snd__h595885 = + (f3_exp__h558282 == 8'd0) ? + _theResult___snd__h595899 : + _theResult___snd__h577482 ; + assign _theResult___snd__h595899 = + (f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ? - sfd__h558677 : - _theResult___snd__h595938 ; - assign _theResult___snd__h595938 = + sfd__h558644 : + _theResult___snd__h595905 ; + assign _theResult___snd__h595905 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h595956 = - sfd__h558677 << + assign _theResult___snd__h595923 = + sfd__h558644 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658 ; - assign _theResult___snd__h601248 = - b__h600826[63] ? b___1__h601297 : b__h600826 ; - assign _theResult___snd_fst_exp__h361255 = + assign _theResult___snd__h601215 = + b__h600793[63] ? b___1__h601264 : b__h600793 ; + assign _theResult___snd_fst_exp__h361222 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352670 : - _theResult___fst_exp__h361252 ; - assign _theResult___snd_fst_exp__h379075 = + _theResult___fst_exp__h352637 : + _theResult___fst_exp__h361219 ; + assign _theResult___snd_fst_exp__h379042 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h370436 : - _theResult___fst_exp__h379072 ; - assign _theResult___snd_fst_exp__h406952 = + _theResult___fst_exp__h370403 : + _theResult___fst_exp__h379039 ; + assign _theResult___snd_fst_exp__h406919 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h398367 : - _theResult___fst_exp__h406949 ; - assign _theResult___snd_fst_exp__h424772 = + _theResult___fst_exp__h398334 : + _theResult___fst_exp__h406916 ; + assign _theResult___snd_fst_exp__h424739 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h416133 : - _theResult___fst_exp__h424769 ; - assign _theResult___snd_fst_exp__h452647 = + _theResult___fst_exp__h416100 : + _theResult___fst_exp__h424736 ; + assign _theResult___snd_fst_exp__h452614 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h444062 : - _theResult___fst_exp__h452644 ; - assign _theResult___snd_fst_exp__h470467 = + _theResult___fst_exp__h444029 : + _theResult___fst_exp__h452611 ; + assign _theResult___snd_fst_exp__h470434 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461828 : - _theResult___fst_exp__h470464 ; - assign _theResult___snd_fst_exp__h500166 = + _theResult___fst_exp__h461795 : + _theResult___fst_exp__h470431 ; + assign _theResult___snd_fst_exp__h500133 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ? 11'd0 : - _theResult___fst_exp__h500163 ; - assign _theResult___snd_fst_exp__h518601 = + _theResult___fst_exp__h500130 ; + assign _theResult___snd_fst_exp__h518568 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? - _theResult___fst_exp__h509814 : - _theResult___fst_exp__h518598 ; - assign _theResult___snd_fst_exp__h539019 = + _theResult___fst_exp__h509781 : + _theResult___fst_exp__h518565 ; + assign _theResult___snd_fst_exp__h538986 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? 11'd0 : - _theResult___fst_exp__h539016 ; - assign _theResult___snd_fst_exp__h557454 = + _theResult___fst_exp__h538983 ; + assign _theResult___snd_fst_exp__h557421 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? - _theResult___fst_exp__h548667 : - _theResult___fst_exp__h557451 ; - assign _theResult___snd_fst_exp__h578323 = + _theResult___fst_exp__h548634 : + _theResult___fst_exp__h557418 ; + assign _theResult___snd_fst_exp__h578290 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? 11'd0 : - _theResult___fst_exp__h578320 ; - assign _theResult___snd_fst_exp__h596758 = + _theResult___fst_exp__h578287 ; + assign _theResult___snd_fst_exp__h596725 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? - _theResult___fst_exp__h587971 : - _theResult___fst_exp__h596755 ; - assign _theResult___snd_fst_sfd__h336307 = + _theResult___fst_exp__h587938 : + _theResult___fst_exp__h596722 ; + assign _theResult___snd_fst_sfd__h336274 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h361256 = + assign _theResult___snd_fst_sfd__h361223 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352671 : - _theResult___fst_sfd__h361253 ; - assign _theResult___snd_fst_sfd__h379076 = + _theResult___fst_sfd__h352638 : + _theResult___fst_sfd__h361220 ; + assign _theResult___snd_fst_sfd__h379043 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h370437 : - _theResult___fst_sfd__h379073 ; - assign _theResult___snd_fst_sfd__h382009 = + _theResult___fst_sfd__h370404 : + _theResult___fst_sfd__h379040 ; + assign _theResult___snd_fst_sfd__h381976 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406953 = + assign _theResult___snd_fst_sfd__h406920 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h398368 : - _theResult___fst_sfd__h406950 ; - assign _theResult___snd_fst_sfd__h424773 = + _theResult___fst_sfd__h398335 : + _theResult___fst_sfd__h406917 ; + assign _theResult___snd_fst_sfd__h424740 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h416134 : - _theResult___fst_sfd__h424770 ; - assign _theResult___snd_fst_sfd__h427704 = + _theResult___fst_sfd__h416101 : + _theResult___fst_sfd__h424737 ; + assign _theResult___snd_fst_sfd__h427671 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h452648 = + assign _theResult___snd_fst_sfd__h452615 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h444063 : - _theResult___fst_sfd__h452645 ; - assign _theResult___snd_fst_sfd__h470468 = + _theResult___fst_sfd__h444030 : + _theResult___fst_sfd__h452612 ; + assign _theResult___snd_fst_sfd__h470435 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461829 : - _theResult___fst_sfd__h470465 ; - assign _theResult___snd_fst_sfd__h480333 = - (f1_sfd__h480018 == 23'd0) ? + _theResult___fst_sfd__h461796 : + _theResult___fst_sfd__h470432 ; + assign _theResult___snd_fst_sfd__h480300 = + (f1_sfd__h479985 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h480081 ; - assign _theResult___snd_fst_sfd__h500167 = + out___1_sfd__h480048 ; + assign _theResult___snd_fst_sfd__h500134 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ? 52'd0 : - _theResult___fst_sfd__h500164 ; - assign _theResult___snd_fst_sfd__h518602 = + _theResult___fst_sfd__h500131 ; + assign _theResult___snd_fst_sfd__h518569 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ? - _theResult___fst_sfd__h509815 : - _theResult___fst_sfd__h518599 ; - assign _theResult___snd_fst_sfd__h519327 = - (f2_sfd__h519012 == 23'd0) ? + _theResult___fst_sfd__h509782 : + _theResult___fst_sfd__h518566 ; + assign _theResult___snd_fst_sfd__h519294 = + (f2_sfd__h518979 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h519075 ; - assign _theResult___snd_fst_sfd__h539020 = + out___1_sfd__h519042 ; + assign _theResult___snd_fst_sfd__h538987 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ? 52'd0 : - _theResult___fst_sfd__h539017 ; - assign _theResult___snd_fst_sfd__h557455 = + _theResult___fst_sfd__h538984 ; + assign _theResult___snd_fst_sfd__h557422 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ? - _theResult___fst_sfd__h548668 : - _theResult___fst_sfd__h557452 ; - assign _theResult___snd_fst_sfd__h558631 = - (f3_sfd__h558316 == 23'd0) ? + _theResult___fst_sfd__h548635 : + _theResult___fst_sfd__h557419 ; + assign _theResult___snd_fst_sfd__h558598 = + (f3_sfd__h558283 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h558379 ; - assign _theResult___snd_fst_sfd__h578324 = + out___1_sfd__h558346 ; + assign _theResult___snd_fst_sfd__h578291 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ? 52'd0 : - _theResult___fst_sfd__h578321 ; - assign _theResult___snd_fst_sfd__h596759 = + _theResult___fst_sfd__h578288 ; + assign _theResult___snd_fst_sfd__h596726 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ? - _theResult___fst_sfd__h587972 : - _theResult___fst_sfd__h596756 ; - assign a___1__h600966 = + _theResult___fst_sfd__h587939 : + _theResult___fst_sfd__h596723 ; + assign a___1__h600933 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 } ; - assign a___1__h601252 = 64'd0 - a__h600825 ; - assign a__h600825 = + assign a___1__h601219 = 64'd0 - a__h600792 ; + assign a__h600792 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h600966 : + a___1__h600933 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h600967 = + assign b___1__h600934 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h601297 = 64'd0 - b__h600826 ; - assign b__h600826 = + assign b___1__h601264 = 64'd0 - b__h600793 ; + assign b__h600793 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h600967 : + b___1__h600934 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h700740 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h700943 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h698122 = - commitStage_commitTrap[4] ? i__h698297 : i__h698137 ; - assign commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 = + assign base__h700680 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h700883 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h698062 = + commitStage_commitTrap[4] ? i__h698237 : i__h698077 ; + assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 = commitStage_commitTrap[4] && commitStage_commitTrap[3:0] != 4'd0 && commitStage_commitTrap[3:0] != 4'd1 && @@ -29080,44 +29084,44 @@ module mkCore(CLK, !commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14534 = - commitStage_commitTrap_4249_BIT_4_4468_AND_com_ETC___d14533 || + assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 = + commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12168 = + assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_0_wget__2166_BITS__ETC___d12207 = + assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12181 = + assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2179_BITS__ETC___d12213 = + assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12189 = + assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2187_BITS__ETC___d12217 = + assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_dispToRegQ_first__2145_BIT_13_ETC___d12230 = + assign coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 = (coreFix_aluExe_0_dispToRegQ$first[131] || sbCons$lazyLookup_0_get[3] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12176 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12202) && + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199) && (sbCons$lazyLookup_0_get[2] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2144_ETC___d12210 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12227) ; - assign coreFix_aluExe_0_exeToFinQ_RDY_first__2584_AND_ETC___d12623 = + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224) ; + assign coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 = coreFix_aluExe_0_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_0_set && (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334 = @@ -29146,7 +29150,7 @@ module mkCore(CLK, (sbCons$lazyLookup_1_get[2] || IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376 && IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11393) ; - assign coreFix_aluExe_1_exeToFinQ_RDY_first__1938_AND_ETC___d11978 = + assign coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 = coreFix_aluExe_1_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_1_set && (coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 && @@ -29235,9 +29239,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29245,9 +29249,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29255,9 +29259,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29265,9 +29269,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29275,19 +29279,19 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 | - ((f3_exp__h558315 != 8'd255 || f3_sfd__h558316 == 23'd0) && - (f3_exp__h558315 != 8'd255 || f3_sfd__h558316 != 23'd0) && - (f3_exp__h558315 != 8'd0 || f3_sfd__h558316 != 23'd0) && + ((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) && + (f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) && + (f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) ; + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) ; assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -29317,7 +29321,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252683 ; + y__h252650 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -29605,7 +29609,7 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d12981 = + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29615,9 +29619,9 @@ module mkCore(CLK, fetchStage$pipelines_0_first[75] && fetchStage$pipelines_0_first[74]) || fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976 || - csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978) ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 = + (fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 || + csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ; + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29629,7 +29633,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 = + assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -29641,32 +29645,32 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2730_ULE_1_4571_AND_IF_comm_ETC___d14593 = - csrf_prv_reg_read__2730_ULE_1___d14571 && + assign csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 = + csrf_prv_reg_read__2727_ULE_1___d14567 && (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14573 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14591) ; - assign csrf_prv_reg_read__2730_ULE_1___d14571 = csrf_prv_reg <= 2'd1 ; - assign csrf_prv_reg_read__2730_ULT_IF_fetchStage_pipe_ETC___d12978 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ; + assign csrf_prv_reg_read__2727_ULE_1___d14567 = csrf_prv_reg <= 2'd1 ; + assign csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974 = csrf_prv_reg < - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[9:8] ; - assign csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428 = + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[9:8] ; + assign csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2697_AND__ETC___d13365 ; - assign data73159_BITS_31_TO_0__q13 = data__h473159[31:0] ; - assign data___1__h472885 = + IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 ; + assign data73126_BITS_31_TO_0__q13 = data__h473126[31:0] ; + assign data___1__h472852 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h473693 = - { {32{data73159_BITS_31_TO_0__q13[31]}}, - data73159_BITS_31_TO_0__q13 } ; - assign data__h473159 = + assign data___1__h473660 = + { {32{data73126_BITS_31_TO_0__q13[31]}}, + data73126_BITS_31_TO_0__q13 } ; + assign data__h473126 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h473073 : - x_remainder__h473074 ; - assign dcsr_cause__h697642 = + x_quotient__h473040 : + x_remainder__h473041 ; + assign dcsr_cause__h697582 = (commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd14) ? 3'd3 : @@ -29683,232 +29687,232 @@ module mkCore(CLK, commitStage_commitTrap[3:0] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h379106 = _theResult___fst_exp__h352073 + 8'd1 ; - assign din_inc___2_exp__h379130 = _theResult___fst_exp__h360729 + 8'd1 ; - assign din_inc___2_exp__h379160 = _theResult___fst_exp__h369839 + 8'd1 ; - assign din_inc___2_exp__h379184 = _theResult___fst_exp__h378524 + 8'd1 ; - assign din_inc___2_exp__h424803 = _theResult___fst_exp__h397770 + 8'd1 ; - assign din_inc___2_exp__h424827 = _theResult___fst_exp__h406426 + 8'd1 ; - assign din_inc___2_exp__h424857 = _theResult___fst_exp__h415536 + 8'd1 ; - assign din_inc___2_exp__h424881 = _theResult___fst_exp__h424221 + 8'd1 ; - assign din_inc___2_exp__h470498 = _theResult___fst_exp__h443465 + 8'd1 ; - assign din_inc___2_exp__h470522 = _theResult___fst_exp__h452121 + 8'd1 ; - assign din_inc___2_exp__h470552 = _theResult___fst_exp__h461231 + 8'd1 ; - assign din_inc___2_exp__h470576 = _theResult___fst_exp__h469916 + 8'd1 ; - assign din_inc___2_exp__h518655 = _theResult___fst_exp__h499405 + 11'd1 ; - assign din_inc___2_exp__h518690 = _theResult___fst_exp__h508982 + 11'd1 ; - assign din_inc___2_exp__h518716 = _theResult___fst_exp__h517815 + 11'd1 ; - assign din_inc___2_exp__h557508 = _theResult___fst_exp__h538258 + 11'd1 ; - assign din_inc___2_exp__h557543 = _theResult___fst_exp__h547835 + 11'd1 ; - assign din_inc___2_exp__h557569 = _theResult___fst_exp__h556668 + 11'd1 ; - assign din_inc___2_exp__h596812 = _theResult___fst_exp__h577562 + 11'd1 ; - assign din_inc___2_exp__h596847 = _theResult___fst_exp__h587139 + 11'd1 ; - assign din_inc___2_exp__h596873 = _theResult___fst_exp__h595972 + 11'd1 ; - assign enabled_ints___1__h648311 = pend_ints__h647784 & y__h648323 ; - assign enabled_ints__h648358 = - pend_ints__h647784 & - { r1__read_BITS_13_TO_0___h648334, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13655 = + assign din_inc___2_exp__h379073 = _theResult___fst_exp__h352040 + 8'd1 ; + assign din_inc___2_exp__h379097 = _theResult___fst_exp__h360696 + 8'd1 ; + assign din_inc___2_exp__h379127 = _theResult___fst_exp__h369806 + 8'd1 ; + assign din_inc___2_exp__h379151 = _theResult___fst_exp__h378491 + 8'd1 ; + assign din_inc___2_exp__h424770 = _theResult___fst_exp__h397737 + 8'd1 ; + assign din_inc___2_exp__h424794 = _theResult___fst_exp__h406393 + 8'd1 ; + assign din_inc___2_exp__h424824 = _theResult___fst_exp__h415503 + 8'd1 ; + assign din_inc___2_exp__h424848 = _theResult___fst_exp__h424188 + 8'd1 ; + assign din_inc___2_exp__h470465 = _theResult___fst_exp__h443432 + 8'd1 ; + assign din_inc___2_exp__h470489 = _theResult___fst_exp__h452088 + 8'd1 ; + assign din_inc___2_exp__h470519 = _theResult___fst_exp__h461198 + 8'd1 ; + assign din_inc___2_exp__h470543 = _theResult___fst_exp__h469883 + 8'd1 ; + assign din_inc___2_exp__h518622 = _theResult___fst_exp__h499372 + 11'd1 ; + assign din_inc___2_exp__h518657 = _theResult___fst_exp__h508949 + 11'd1 ; + assign din_inc___2_exp__h518683 = _theResult___fst_exp__h517782 + 11'd1 ; + assign din_inc___2_exp__h557475 = _theResult___fst_exp__h538225 + 11'd1 ; + assign din_inc___2_exp__h557510 = _theResult___fst_exp__h547802 + 11'd1 ; + assign din_inc___2_exp__h557536 = _theResult___fst_exp__h556635 + 11'd1 ; + assign din_inc___2_exp__h596779 = _theResult___fst_exp__h577529 + 11'd1 ; + assign din_inc___2_exp__h596814 = _theResult___fst_exp__h587106 + 11'd1 ; + assign din_inc___2_exp__h596840 = _theResult___fst_exp__h595939 + 11'd1 ; + assign enabled_ints___1__h648251 = pend_ints__h647724 & y__h648263 ; + assign enabled_ints__h648298 = + pend_ints__h647724 & + { r1__read_BITS_13_TO_0___h648274, csrf_mideleg_1_0_reg } ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13797 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13815 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811) ; - assign f1_exp80017_MINUS_127__q136 = f1_exp__h480017 - 8'd127 ; - assign f1_exp__h480017 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807) ; + assign f1_exp79984_MINUS_127__q136 = f1_exp__h479984 - 8'd127 ; + assign f1_exp__h479984 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h480018 = + assign f1_sfd__h479985 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp19011_MINUS_127__q176 = f2_exp__h519011 - 8'd127 ; - assign f2_exp__h519011 = + assign f2_exp18978_MINUS_127__q176 = f2_exp__h518978 - 8'd127 ; + assign f2_exp__h518978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h519012 = + assign f2_sfd__h518979 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp58315_MINUS_127__q153 = f3_exp__h558315 - 8'd127 ; - assign f3_exp__h558315 = + assign f3_exp58282_MINUS_127__q153 = f3_exp__h558282 - 8'd127 ; + assign f3_exp__h558282 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h558316 = + assign f3_sfd__h558283 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5313_AND_f_csr_reqs_firs_ETC___d15408 = + assign f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h607196 = { 56'd0, x__h610340 } ; - assign fetchStage_RDY_pipelines_1_deq__2712_AND_NOT_f_ETC___d13999 = + assign fcsr_csr__read__h607163 = { 56'd0, x__h610293 } ; + assign fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13995) && + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991) && (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939 = + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14021 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d14095 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d14018 && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2698_AND_fetchS_ETC___d14009 = + assign fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883 || + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894 || + (fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906 || - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d14005) && - IF_fetchStage_RDY_pipelines_1_first__2708_AND__ETC___d13826 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 = + fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 || + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001) && + IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 = + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 || + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961) ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13758 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977) ; - assign fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d14215 = + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973) ; + assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2698_AND_specTa_ETC___d14073 = + assign fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d12976 = + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h651965 != 5'd0 || - imm__h651966 != 32'd0) && - IF_fetchStage_pipelines_0_first__2700_BIT_173__ETC___d12973[11:10] == + rs1__h651905 != 5'd0 || + imm__h651906 != 32'd0) && + IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13666 = + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374) ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765 = + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13877 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13875 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13883 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919 = + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3333__ETC___d13682 || + NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13935 = + coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 || + fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 ; - assign fetchStage_pipelines_0_first__2700_BITS_199_TO_ETC___d13439 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ; + assign fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -29920,22 +29924,22 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2700_BIT_68_2729_ETC___d13756 = + assign fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 = fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13432 || + checkForException___d12942[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2709_BITS_194_TO_ETC___d13894 = + assign fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891 || + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2709_BITS_199_TO_ETC___d13906 = + assign fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -29947,116 +29951,116 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13619[4] || - csrf_fs_reg_read__1527_EQ_0_2935_AND_fetchStag_ETC___d13712 || + checkForException___d13615[4] || + csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13900 ; - assign fetchStage_pipelines_1_first__2709_BIT_173_351_ETC___d13598 = + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 ; + assign fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h714186 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_fst__h714129 : - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 ; - assign fflags_csr__read__h607171 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h607182 = { 61'd0, csrf_frm_reg } ; - assign guard__h343972 = - { IF_sfdin52067_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h352067[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352681 = - { IF_theResult___snd60680_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h360680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361611 = - { IF_sfdin69833_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h369833[32:0], 23'd0 } != 56'd0 } ; - assign guard__h362209 = x__h362311 != 57'd0 ; - assign guard__h370447 = - { IF_theResult___snd78470_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h378470[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389671 = - { IF_sfdin97764_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h397764[32:0], 23'd0 } != 56'd0 } ; - assign guard__h398378 = - { IF_theResult___snd06377_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h406377[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407308 = - { IF_sfdin15530_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h415530[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407906 = x__h408008 != 57'd0 ; - assign guard__h416144 = - { IF_theResult___snd24167_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h424167[32:0], 23'd0 } != 56'd0 } ; - assign guard__h435366 = - { IF_sfdin43459_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h443459[32:0], 23'd0 } != 56'd0 } ; - assign guard__h444073 = - { IF_theResult___snd52072_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h452072[32:0], 23'd0 } != 56'd0 } ; - assign guard__h453003 = - { IF_sfdin61225_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h461225[32:0], 23'd0 } != 56'd0 } ; - assign guard__h453601 = x__h453703 != 57'd0 ; - assign guard__h461839 = - { IF_theResult___snd69862_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h469862[32:0], 23'd0 } != 56'd0 } ; - assign guard__h491444 = - { IF_theResult___snd99356_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h499356[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500756 = - { IF_sfdin08976_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h508976[3:0], 52'd0 } != 56'd0 } ; - assign guard__h501354 = x__h501454 != 57'd0 ; - assign guard__h509825 = - { IF_theResult___snd17761_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h517761[3:0], 52'd0 } != 56'd0 } ; - assign guard__h530297 = - { IF_theResult___snd38209_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h538209[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539609 = - { IF_sfdin47829_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h547829[3:0], 52'd0 } != 56'd0 } ; - assign guard__h540207 = x__h540307 != 57'd0 ; - assign guard__h548678 = - { IF_theResult___snd56614_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h556614[3:0], 52'd0 } != 56'd0 } ; - assign guard__h569601 = - { IF_theResult___snd77513_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h577513[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578913 = - { IF_sfdin87133_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h587133[3:0], 52'd0 } != 56'd0 } ; - assign guard__h579511 = x__h579611 != 57'd0 ; - assign guard__h587982 = - { IF_theResult___snd95918_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h595918[3:0], 52'd0 } != 56'd0 } ; - assign idx__h678765 = + assign fflags__h714091 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_fst__h714034 : + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 ; + assign fflags_csr__read__h607138 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h607149 = { 61'd0, csrf_frm_reg } ; + assign guard__h343939 = + { IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h352034[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352648 = + { IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h360647[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361578 = + { IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h369800[32:0], 23'd0 } != 56'd0 } ; + assign guard__h362176 = x__h362278 != 57'd0 ; + assign guard__h370414 = + { IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h378437[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389638 = + { IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h397731[32:0], 23'd0 } != 56'd0 } ; + assign guard__h398345 = + { IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h406344[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407275 = + { IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h415497[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407873 = x__h407975 != 57'd0 ; + assign guard__h416111 = + { IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h424134[32:0], 23'd0 } != 56'd0 } ; + assign guard__h435333 = + { IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h443426[32:0], 23'd0 } != 56'd0 } ; + assign guard__h444040 = + { IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h452039[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452970 = + { IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h461192[32:0], 23'd0 } != 56'd0 } ; + assign guard__h453568 = x__h453670 != 57'd0 ; + assign guard__h461806 = + { IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h469829[32:0], 23'd0 } != 56'd0 } ; + assign guard__h491411 = + { IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h499323[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500723 = + { IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h508943[3:0], 52'd0 } != 56'd0 } ; + assign guard__h501321 = x__h501421 != 57'd0 ; + assign guard__h509792 = + { IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h517728[3:0], 52'd0 } != 56'd0 } ; + assign guard__h530264 = + { IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h538176[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539576 = + { IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h547796[3:0], 52'd0 } != 56'd0 } ; + assign guard__h540174 = x__h540274 != 57'd0 ; + assign guard__h548645 = + { IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h556581[3:0], 52'd0 } != 56'd0 } ; + assign guard__h569568 = + { IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h577480[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578880 = + { IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h587100[3:0], 52'd0 } != 56'd0 } ; + assign guard__h579478 = x__h579578 != 57'd0 ; + assign guard__h587949 = + { IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h595885[3:0], 52'd0 } != 56'd0 } ; + assign idx__h678705 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13691 ; - assign imm__h651966 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 ; + assign imm__h651906 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h664143 = + assign k__h664083 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3372__ETC___d13374 ; - assign mcause_csr__read__h608843 = - { r1__read__h611868, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h608588 = - { r1__read__h611855, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h608188 = - { r1__read__h611691, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h608283 = - { r1__read__h611708, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h608414 = - { r1__read__h611732, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h609083 = - { r1__read__h611874, csrf_software_int_pend_vec_0 } ; + !coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ; + assign mcause_csr__read__h608803 = + { r1__read__h611814, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h608548 = + { r1__read__h611801, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h608155 = + { r1__read__h611644, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h608250 = + { r1__read__h611661, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h608374 = + { r1__read__h611685, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h609036 = + { r1__read__h611820, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30089,18 +30093,18 @@ module mkCore(CLK, !mmio_dataRespQ_deqReq_lat_0$whas && !mmio_dataRespQ_deqReq_rl) && mmio_dataRespQ_full ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12991 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12988) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984) ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13276 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13297 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13279 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 && (fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30111,13 +30115,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_273_ETC___d13352 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14015 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14013 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -30140,292 +30144,292 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h75940 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h608040 = { r1__read__h611566, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h608496 = - { r1__read__h611850, csrf_mtvec_mode_low_reg } ; - assign n___1__h196409 = + assign msip__h75907 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h608007 = { r1__read__h611519, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h608456 = + { r1__read__h611796, csrf_mtvec_mode_low_reg } ; + assign n___1__h196376 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h195006[63:56], + x__h194973[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h195006[55:48], + x__h194973[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h195006[47:40], + x__h194973[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h195006[39:32], + x__h194973[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h195006[31:24], + x__h194973[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h195006[23:16], + x__h194973[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h195006[15:8], + x__h194973[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h195006[7:0] } ; - assign n__read__h609187 = + x__h194973[7:0] } ; + assign n__read__h609140 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h609378 = + assign n__read__h609331 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6636 = + assign n__read__h6604 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6750 : + upd__h6718 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h710013 = + assign n__read__h709918 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294679 = + assign next_deqP___1__h294647 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302675 = + assign next_deqP___1__h302643 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308956 = + assign next_deqP___1__h308924 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316810 = + assign next_deqP___1__h316778 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326867 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h330092 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h709359 = + assign next_deqP___1__h326835 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h330060 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h709264 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h480081 = { f1_sfd__h480018, 29'd0 } ; - assign out___1_sfd__h519075 = { f2_sfd__h519012, 29'd0 } ; - assign out___1_sfd__h558379 = { f3_sfd__h558316, 29'd0 } ; - assign out_exp__h352592 = - sfdin__h352067[34] ? - _theResult___exp__h352589 : - _theResult___fst_exp__h352073 ; - assign out_exp__h361174 = - _theResult___snd__h360680[34] ? - _theResult___exp__h361171 : - _theResult___fst_exp__h360729 ; - assign out_exp__h370358 = - sfdin__h369833[34] ? - _theResult___exp__h370355 : - _theResult___fst_exp__h369839 ; - assign out_exp__h378994 = - _theResult___snd__h378470[34] ? - _theResult___exp__h378991 : - _theResult___fst_exp__h378524 ; - assign out_exp__h398289 = - sfdin__h397764[34] ? - _theResult___exp__h398286 : - _theResult___fst_exp__h397770 ; - assign out_exp__h406871 = - _theResult___snd__h406377[34] ? - _theResult___exp__h406868 : - _theResult___fst_exp__h406426 ; - assign out_exp__h416055 = - sfdin__h415530[34] ? - _theResult___exp__h416052 : - _theResult___fst_exp__h415536 ; - assign out_exp__h424691 = - _theResult___snd__h424167[34] ? - _theResult___exp__h424688 : - _theResult___fst_exp__h424221 ; - assign out_exp__h443984 = - sfdin__h443459[34] ? - _theResult___exp__h443981 : - _theResult___fst_exp__h443465 ; - assign out_exp__h452566 = - _theResult___snd__h452072[34] ? - _theResult___exp__h452563 : - _theResult___fst_exp__h452121 ; - assign out_exp__h461750 = - sfdin__h461225[34] ? - _theResult___exp__h461747 : - _theResult___fst_exp__h461231 ; - assign out_exp__h470386 = - _theResult___snd__h469862[34] ? - _theResult___exp__h470383 : - _theResult___fst_exp__h469916 ; - assign out_exp__h500063 = - _theResult___snd__h499356[5] ? - _theResult___exp__h500060 : - _theResult___fst_exp__h499405 ; - assign out_exp__h509714 = - sfdin__h508976[5] ? - _theResult___exp__h509711 : - _theResult___fst_exp__h508982 ; - assign out_exp__h518498 = - _theResult___snd__h517761[5] ? - _theResult___exp__h518495 : - _theResult___fst_exp__h517815 ; - assign out_exp__h538916 = - _theResult___snd__h538209[5] ? - _theResult___exp__h538913 : - _theResult___fst_exp__h538258 ; - assign out_exp__h548567 = - sfdin__h547829[5] ? - _theResult___exp__h548564 : - _theResult___fst_exp__h547835 ; - assign out_exp__h557351 = - _theResult___snd__h556614[5] ? - _theResult___exp__h557348 : - _theResult___fst_exp__h556668 ; - assign out_exp__h578220 = - _theResult___snd__h577513[5] ? - _theResult___exp__h578217 : - _theResult___fst_exp__h577562 ; - assign out_exp__h587871 = - sfdin__h587133[5] ? - _theResult___exp__h587868 : - _theResult___fst_exp__h587139 ; - assign out_exp__h596655 = - _theResult___snd__h595918[5] ? - _theResult___exp__h596652 : - _theResult___fst_exp__h595972 ; - assign out_f_exp__h379370 = - (_theResult___exp__h379093 == 8'd255 && - _theResult___sfd__h379094 != 23'd0 || + assign out___1_sfd__h480048 = { f1_sfd__h479985, 29'd0 } ; + assign out___1_sfd__h519042 = { f2_sfd__h518979, 29'd0 } ; + assign out___1_sfd__h558346 = { f3_sfd__h558283, 29'd0 } ; + assign out_exp__h352559 = + sfdin__h352034[34] ? + _theResult___exp__h352556 : + _theResult___fst_exp__h352040 ; + assign out_exp__h361141 = + _theResult___snd__h360647[34] ? + _theResult___exp__h361138 : + _theResult___fst_exp__h360696 ; + assign out_exp__h370325 = + sfdin__h369800[34] ? + _theResult___exp__h370322 : + _theResult___fst_exp__h369806 ; + assign out_exp__h378961 = + _theResult___snd__h378437[34] ? + _theResult___exp__h378958 : + _theResult___fst_exp__h378491 ; + assign out_exp__h398256 = + sfdin__h397731[34] ? + _theResult___exp__h398253 : + _theResult___fst_exp__h397737 ; + assign out_exp__h406838 = + _theResult___snd__h406344[34] ? + _theResult___exp__h406835 : + _theResult___fst_exp__h406393 ; + assign out_exp__h416022 = + sfdin__h415497[34] ? + _theResult___exp__h416019 : + _theResult___fst_exp__h415503 ; + assign out_exp__h424658 = + _theResult___snd__h424134[34] ? + _theResult___exp__h424655 : + _theResult___fst_exp__h424188 ; + assign out_exp__h443951 = + sfdin__h443426[34] ? + _theResult___exp__h443948 : + _theResult___fst_exp__h443432 ; + assign out_exp__h452533 = + _theResult___snd__h452039[34] ? + _theResult___exp__h452530 : + _theResult___fst_exp__h452088 ; + assign out_exp__h461717 = + sfdin__h461192[34] ? + _theResult___exp__h461714 : + _theResult___fst_exp__h461198 ; + assign out_exp__h470353 = + _theResult___snd__h469829[34] ? + _theResult___exp__h470350 : + _theResult___fst_exp__h469883 ; + assign out_exp__h500030 = + _theResult___snd__h499323[5] ? + _theResult___exp__h500027 : + _theResult___fst_exp__h499372 ; + assign out_exp__h509681 = + sfdin__h508943[5] ? + _theResult___exp__h509678 : + _theResult___fst_exp__h508949 ; + assign out_exp__h518465 = + _theResult___snd__h517728[5] ? + _theResult___exp__h518462 : + _theResult___fst_exp__h517782 ; + assign out_exp__h538883 = + _theResult___snd__h538176[5] ? + _theResult___exp__h538880 : + _theResult___fst_exp__h538225 ; + assign out_exp__h548534 = + sfdin__h547796[5] ? + _theResult___exp__h548531 : + _theResult___fst_exp__h547802 ; + assign out_exp__h557318 = + _theResult___snd__h556581[5] ? + _theResult___exp__h557315 : + _theResult___fst_exp__h556635 ; + assign out_exp__h578187 = + _theResult___snd__h577480[5] ? + _theResult___exp__h578184 : + _theResult___fst_exp__h577529 ; + assign out_exp__h587838 = + sfdin__h587100[5] ? + _theResult___exp__h587835 : + _theResult___fst_exp__h587106 ; + assign out_exp__h596622 = + _theResult___snd__h595885[5] ? + _theResult___exp__h596619 : + _theResult___fst_exp__h595939 ; + assign out_f_exp__h379337 = + (_theResult___exp__h379060 == 8'd255 && + _theResult___sfd__h379061 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h379084 ; - assign out_f_exp__h425067 = - (_theResult___exp__h424790 == 8'd255 && - _theResult___sfd__h424791 != 23'd0 || + _theResult___fst_exp__h379051 ; + assign out_f_exp__h425034 = + (_theResult___exp__h424757 == 8'd255 && + _theResult___sfd__h424758 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424781 ; - assign out_f_exp__h470762 = - (_theResult___exp__h470485 == 8'd255 && - _theResult___sfd__h470486 != 23'd0 || + _theResult___fst_exp__h424748 ; + assign out_f_exp__h470729 = + (_theResult___exp__h470452 == 8'd255 && + _theResult___sfd__h470453 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h470476 ; - assign out_f_sfd__h379371 = - (_theResult___exp__h379093 == 8'd255 && - _theResult___sfd__h379094 != 23'd0) ? + _theResult___fst_exp__h470443 ; + assign out_f_sfd__h379338 = + (_theResult___exp__h379060 == 8'd255 && + _theResult___sfd__h379061 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h379094 ; - assign out_f_sfd__h425068 = - (_theResult___exp__h424790 == 8'd255 && - _theResult___sfd__h424791 != 23'd0) ? + _theResult___sfd__h379061 ; + assign out_f_sfd__h425035 = + (_theResult___exp__h424757 == 8'd255 && + _theResult___sfd__h424758 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424791 ; - assign out_f_sfd__h470763 = - (_theResult___exp__h470485 == 8'd255 && - _theResult___sfd__h470486 != 23'd0) ? + _theResult___sfd__h424758 ; + assign out_f_sfd__h470730 = + (_theResult___exp__h470452 == 8'd255 && + _theResult___sfd__h470453 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h470486 ; - assign out_sfd__h352593 = - sfdin__h352067[34] ? - _theResult___sfd__h352590 : - sfdin__h352067[56:34] ; - assign out_sfd__h361175 = - _theResult___snd__h360680[34] ? - _theResult___sfd__h361172 : - _theResult___snd__h360680[56:34] ; - assign out_sfd__h370359 = - sfdin__h369833[34] ? - _theResult___sfd__h370356 : - sfdin__h369833[56:34] ; - assign out_sfd__h378995 = - _theResult___snd__h378470[34] ? - _theResult___sfd__h378992 : - _theResult___snd__h378470[56:34] ; - assign out_sfd__h398290 = - sfdin__h397764[34] ? - _theResult___sfd__h398287 : - sfdin__h397764[56:34] ; - assign out_sfd__h406872 = - _theResult___snd__h406377[34] ? - _theResult___sfd__h406869 : - _theResult___snd__h406377[56:34] ; - assign out_sfd__h416056 = - sfdin__h415530[34] ? - _theResult___sfd__h416053 : - sfdin__h415530[56:34] ; - assign out_sfd__h424692 = - _theResult___snd__h424167[34] ? - _theResult___sfd__h424689 : - _theResult___snd__h424167[56:34] ; - assign out_sfd__h443985 = - sfdin__h443459[34] ? - _theResult___sfd__h443982 : - sfdin__h443459[56:34] ; - assign out_sfd__h452567 = - _theResult___snd__h452072[34] ? - _theResult___sfd__h452564 : - _theResult___snd__h452072[56:34] ; - assign out_sfd__h461751 = - sfdin__h461225[34] ? - _theResult___sfd__h461748 : - sfdin__h461225[56:34] ; - assign out_sfd__h470387 = - _theResult___snd__h469862[34] ? - _theResult___sfd__h470384 : - _theResult___snd__h469862[56:34] ; - assign out_sfd__h500064 = - _theResult___snd__h499356[5] ? - _theResult___sfd__h500061 : - _theResult___snd__h499356[56:5] ; - assign out_sfd__h509715 = - sfdin__h508976[5] ? - _theResult___sfd__h509712 : - sfdin__h508976[56:5] ; - assign out_sfd__h518499 = - _theResult___snd__h517761[5] ? - _theResult___sfd__h518496 : - _theResult___snd__h517761[56:5] ; - assign out_sfd__h538917 = - _theResult___snd__h538209[5] ? - _theResult___sfd__h538914 : - _theResult___snd__h538209[56:5] ; - assign out_sfd__h548568 = - sfdin__h547829[5] ? - _theResult___sfd__h548565 : - sfdin__h547829[56:5] ; - assign out_sfd__h557352 = - _theResult___snd__h556614[5] ? - _theResult___sfd__h557349 : - _theResult___snd__h556614[56:5] ; - assign out_sfd__h578221 = - _theResult___snd__h577513[5] ? - _theResult___sfd__h578218 : - _theResult___snd__h577513[56:5] ; - assign out_sfd__h587872 = - sfdin__h587133[5] ? - _theResult___sfd__h587869 : - sfdin__h587133[56:5] ; - assign out_sfd__h596656 = - _theResult___snd__h595918[5] ? - _theResult___sfd__h596653 : - _theResult___snd__h595918[56:5] ; - assign pend_ints__h647784 = - { _0_CONCAT_csrf_debug_int_pend_read__1683_CONCAT_ETC___d12744, + _theResult___sfd__h470453 ; + assign out_sfd__h352560 = + sfdin__h352034[34] ? + _theResult___sfd__h352557 : + sfdin__h352034[56:34] ; + assign out_sfd__h361142 = + _theResult___snd__h360647[34] ? + _theResult___sfd__h361139 : + _theResult___snd__h360647[56:34] ; + assign out_sfd__h370326 = + sfdin__h369800[34] ? + _theResult___sfd__h370323 : + sfdin__h369800[56:34] ; + assign out_sfd__h378962 = + _theResult___snd__h378437[34] ? + _theResult___sfd__h378959 : + _theResult___snd__h378437[56:34] ; + assign out_sfd__h398257 = + sfdin__h397731[34] ? + _theResult___sfd__h398254 : + sfdin__h397731[56:34] ; + assign out_sfd__h406839 = + _theResult___snd__h406344[34] ? + _theResult___sfd__h406836 : + _theResult___snd__h406344[56:34] ; + assign out_sfd__h416023 = + sfdin__h415497[34] ? + _theResult___sfd__h416020 : + sfdin__h415497[56:34] ; + assign out_sfd__h424659 = + _theResult___snd__h424134[34] ? + _theResult___sfd__h424656 : + _theResult___snd__h424134[56:34] ; + assign out_sfd__h443952 = + sfdin__h443426[34] ? + _theResult___sfd__h443949 : + sfdin__h443426[56:34] ; + assign out_sfd__h452534 = + _theResult___snd__h452039[34] ? + _theResult___sfd__h452531 : + _theResult___snd__h452039[56:34] ; + assign out_sfd__h461718 = + sfdin__h461192[34] ? + _theResult___sfd__h461715 : + sfdin__h461192[56:34] ; + assign out_sfd__h470354 = + _theResult___snd__h469829[34] ? + _theResult___sfd__h470351 : + _theResult___snd__h469829[56:34] ; + assign out_sfd__h500031 = + _theResult___snd__h499323[5] ? + _theResult___sfd__h500028 : + _theResult___snd__h499323[56:5] ; + assign out_sfd__h509682 = + sfdin__h508943[5] ? + _theResult___sfd__h509679 : + sfdin__h508943[56:5] ; + assign out_sfd__h518466 = + _theResult___snd__h517728[5] ? + _theResult___sfd__h518463 : + _theResult___snd__h517728[56:5] ; + assign out_sfd__h538884 = + _theResult___snd__h538176[5] ? + _theResult___sfd__h538881 : + _theResult___snd__h538176[56:5] ; + assign out_sfd__h548535 = + sfdin__h547796[5] ? + _theResult___sfd__h548532 : + sfdin__h547796[56:5] ; + assign out_sfd__h557319 = + _theResult___snd__h556581[5] ? + _theResult___sfd__h557316 : + _theResult___snd__h556581[56:5] ; + assign out_sfd__h578188 = + _theResult___snd__h577480[5] ? + _theResult___sfd__h578185 : + _theResult___snd__h577480[56:5] ; + assign out_sfd__h587839 = + sfdin__h587100[5] ? + _theResult___sfd__h587836 : + sfdin__h587100[56:5] ; + assign out_sfd__h596623 = + _theResult___snd__h595885[5] ? + _theResult___sfd__h596620 : + _theResult___snd__h595885[56:5] ; + assign pend_ints__h647724 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h715821 = csrf_prv_reg ; - assign prv__h715865 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473758 = + assign prv__h715726 = csrf_prv_reg ; + assign prv__h715770 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473725 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h648334 = + assign r1__read_BITS_13_TO_0___h648274 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30433,137 +30437,134 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h651834 = csrf_fs_reg ; - assign r1__read_BIT_20___h652494 = csrf_tw_reg ; - assign r1__read__h610355 = { r1__read__h610357, csrf_ie_vec_1 } ; - assign r1__read__h610357 = { r1__read__h610359, 2'b0 } ; - assign r1__read__h610359 = { r1__read__h610361, csrf_prev_ie_vec_0 } ; - assign r1__read__h610361 = { r1__read__h610363, csrf_prev_ie_vec_1 } ; - assign r1__read__h610363 = { r1__read__h610365, 2'b0 } ; - assign r1__read__h610365 = { r1__read__h610367, csrf_spp_reg } ; - assign r1__read__h610367 = { r1__read__h610369, 4'b0 } ; - assign r1__read__h610369 = { r1__read__h610371, csrf_fs_reg } ; - assign r1__read__h610371 = { r1__read__h610373, 2'd0 } ; - assign r1__read__h610373 = { r1__read__h610375, 1'b0 } ; - assign r1__read__h610375 = { r1__read__h610377, csrf_sum_reg } ; - assign r1__read__h610377 = { r1__read__h610379, csrf_mxr_reg } ; - assign r1__read__h610379 = { r1__read__h610381, 12'b0 } ; - assign r1__read__h610381 = { r1__read__h610383, 2'b10 } ; - assign r1__read__h610383 = { r__h610387, 29'b0 } ; - assign r1__read__h610759 = - { r1__read__h610761, csrf_software_int_en_vec_1 } ; - assign r1__read__h610761 = { r1__read__h610763, 2'b0 } ; - assign r1__read__h610763 = { r1__read__h610765, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610765 = { r1__read__h610767, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610767 = { r1__read__h610769, 2'b0 } ; - assign r1__read__h610769 = - { r1__read__h610771, csrf_external_int_en_vec_0 } ; - assign r1__read__h610771 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h611289 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h611294 = { r1__read__h611296, csrf_scounteren_tm_reg } ; - assign r1__read__h611296 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h611307 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h611313 = - { r1__read__h611315, csrf_software_int_pend_vec_1 } ; - assign r1__read__h611315 = { r1__read__h611317, 2'b0 } ; - assign r1__read__h611317 = - { r1__read__h611319, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h611319 = - { r1__read__h611321, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h611321 = { r1__read__h611323, 2'b0 } ; - assign r1__read__h611323 = - { r1__read__h611325, csrf_external_int_pend_vec_0 } ; - assign r1__read__h611325 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h611543 = { vm_mode_reg__read__h611549, 16'd0 } ; - assign r1__read__h611566 = { r1__read__h611568, csrf_ie_vec_1 } ; - assign r1__read__h611568 = { r1__read__h611570, 1'b0 } ; - assign r1__read__h611570 = { r1__read__h611572, csrf_ie_vec_3 } ; - assign r1__read__h611572 = { r1__read__h611574, csrf_prev_ie_vec_0 } ; - assign r1__read__h611574 = { r1__read__h611576, csrf_prev_ie_vec_1 } ; - assign r1__read__h611576 = { r1__read__h611578, 1'b0 } ; - assign r1__read__h611578 = { r1__read__h611580, csrf_prev_ie_vec_3 } ; - assign r1__read__h611580 = { r1__read__h611582, csrf_spp_reg } ; - assign r1__read__h611582 = { r1__read__h611584, 2'b0 } ; - assign r1__read__h611584 = { r1__read__h611586, csrf_mpp_reg } ; - assign r1__read__h611586 = { r1__read__h611588, csrf_fs_reg } ; - assign r1__read__h611588 = { r1__read__h611590, 2'd0 } ; - assign r1__read__h611590 = { r1__read__h611592, csrf_mprv_reg } ; - assign r1__read__h611592 = { r1__read__h611594, csrf_sum_reg } ; - assign r1__read__h611594 = { r1__read__h611596, csrf_mxr_reg } ; - assign r1__read__h611596 = { r1__read__h611598, csrf_tvm_reg } ; - assign r1__read__h611598 = { r1__read__h611600, csrf_tw_reg } ; - assign r1__read__h611600 = { r1__read__h611602, csrf_tsr_reg } ; - assign r1__read__h611602 = { r1__read__h611604, 9'b0 } ; - assign r1__read__h611604 = { r1__read__h611606, 2'b10 } ; - assign r1__read__h611606 = { r1__read__h611608, 2'b10 } ; - assign r1__read__h611608 = { r__h610387, 27'b0 } ; - assign r1__read__h611691 = { r1__read__h611693, 1'b0 } ; - assign r1__read__h611693 = { r1__read__h611695, csrf_medeleg_13_11_reg } ; + assign r1__read_BITS_13_TO_12___h651774 = csrf_fs_reg ; + assign r1__read_BIT_20___h652434 = csrf_tw_reg ; + assign r1__read__h610308 = { r1__read__h610310, csrf_ie_vec_1 } ; + assign r1__read__h610310 = { r1__read__h610312, 2'b0 } ; + assign r1__read__h610312 = { r1__read__h610314, csrf_prev_ie_vec_0 } ; + assign r1__read__h610314 = { r1__read__h610316, csrf_prev_ie_vec_1 } ; + assign r1__read__h610316 = { r1__read__h610318, 2'b0 } ; + assign r1__read__h610318 = { r1__read__h610320, csrf_spp_reg } ; + assign r1__read__h610320 = { r1__read__h610322, 4'b0 } ; + assign r1__read__h610322 = { r1__read__h610324, csrf_fs_reg } ; + assign r1__read__h610324 = { r1__read__h610326, 2'd0 } ; + assign r1__read__h610326 = { r1__read__h610328, 1'b0 } ; + assign r1__read__h610328 = { r1__read__h610330, csrf_sum_reg } ; + assign r1__read__h610330 = { r1__read__h610332, csrf_mxr_reg } ; + assign r1__read__h610332 = { r1__read__h610334, 12'b0 } ; + assign r1__read__h610334 = { r1__read__h610336, 2'b10 } ; + assign r1__read__h610336 = { r__h610340, 29'b0 } ; + assign r1__read__h610712 = + { r1__read__h610714, csrf_software_int_en_vec_1 } ; + assign r1__read__h610714 = { r1__read__h610716, 2'b0 } ; + assign r1__read__h610716 = { r1__read__h610718, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610718 = { r1__read__h610720, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610720 = { r1__read__h610722, 2'b0 } ; + assign r1__read__h610722 = + { r1__read__h610724, csrf_external_int_en_vec_0 } ; + assign r1__read__h610724 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h611242 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h611247 = { r1__read__h611249, csrf_scounteren_tm_reg } ; + assign r1__read__h611249 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h611260 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h611266 = + { r1__read__h611268, csrf_software_int_pend_vec_1 } ; + assign r1__read__h611268 = { r1__read__h611270, 2'b0 } ; + assign r1__read__h611270 = + { r1__read__h611272, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h611272 = + { r1__read__h611274, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h611274 = { r1__read__h611276, 2'b0 } ; + assign r1__read__h611276 = + { r1__read__h611278, csrf_external_int_pend_vec_0 } ; + assign r1__read__h611278 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h611496 = { vm_mode_reg__read__h611502, 16'd0 } ; + assign r1__read__h611519 = { r1__read__h611521, csrf_ie_vec_1 } ; + assign r1__read__h611521 = { r1__read__h611523, 1'b0 } ; + assign r1__read__h611523 = { r1__read__h611525, csrf_ie_vec_3 } ; + assign r1__read__h611525 = { r1__read__h611527, csrf_prev_ie_vec_0 } ; + assign r1__read__h611527 = { r1__read__h611529, csrf_prev_ie_vec_1 } ; + assign r1__read__h611529 = { r1__read__h611531, 1'b0 } ; + assign r1__read__h611531 = { r1__read__h611533, csrf_prev_ie_vec_3 } ; + assign r1__read__h611533 = { r1__read__h611535, csrf_spp_reg } ; + assign r1__read__h611535 = { r1__read__h611537, 2'b0 } ; + assign r1__read__h611537 = { r1__read__h611539, csrf_mpp_reg } ; + assign r1__read__h611539 = { r1__read__h611541, csrf_fs_reg } ; + assign r1__read__h611541 = { r1__read__h611543, 2'd0 } ; + assign r1__read__h611543 = { r1__read__h611545, csrf_mprv_reg } ; + assign r1__read__h611545 = { r1__read__h611547, csrf_sum_reg } ; + assign r1__read__h611547 = { r1__read__h611549, csrf_mxr_reg } ; + assign r1__read__h611549 = { r1__read__h611551, csrf_tvm_reg } ; + assign r1__read__h611551 = { r1__read__h611553, csrf_tw_reg } ; + assign r1__read__h611553 = { r1__read__h611555, csrf_tsr_reg } ; + assign r1__read__h611555 = { r1__read__h611557, 9'b0 } ; + assign r1__read__h611557 = { r1__read__h611559, 2'b10 } ; + assign r1__read__h611559 = { r1__read__h611561, 2'b10 } ; + assign r1__read__h611561 = { r__h610340, 27'b0 } ; + assign r1__read__h611644 = { r1__read__h611646, 1'b0 } ; + assign r1__read__h611646 = { r1__read__h611648, csrf_medeleg_13_11_reg } ; + assign r1__read__h611648 = { r1__read__h611650, 1'b0 } ; + assign r1__read__h611650 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h611661 = { r1__read__h611663, 1'b0 } ; + assign r1__read__h611663 = { r1__read__h611665, csrf_mideleg_5_3_reg } ; + assign r1__read__h611665 = { r1__read__h611667, 1'b0 } ; + assign r1__read__h611667 = { r1__read__h611669, csrf_mideleg_9_7_reg } ; + assign r1__read__h611669 = { r1__read__h611671, 1'b0 } ; + assign r1__read__h611671 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h611685 = + { r1__read__h611687, csrf_software_int_en_vec_1 } ; + assign r1__read__h611687 = { r1__read__h611689, 1'b0 } ; + assign r1__read__h611689 = + { r1__read__h611691, csrf_software_int_en_vec_3 } ; + assign r1__read__h611691 = { r1__read__h611693, csrf_timer_int_en_vec_0 } ; + assign r1__read__h611693 = { r1__read__h611695, csrf_timer_int_en_vec_1 } ; assign r1__read__h611695 = { r1__read__h611697, 1'b0 } ; - assign r1__read__h611697 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h611708 = { r1__read__h611710, 1'b0 } ; - assign r1__read__h611710 = { r1__read__h611712, csrf_mideleg_5_3_reg } ; - assign r1__read__h611712 = { r1__read__h611714, 1'b0 } ; - assign r1__read__h611714 = { r1__read__h611716, csrf_mideleg_9_7_reg } ; - assign r1__read__h611716 = { r1__read__h611718, 1'b0 } ; - assign r1__read__h611718 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h611732 = - { r1__read__h611734, csrf_software_int_en_vec_1 } ; - assign r1__read__h611734 = { r1__read__h611736, 1'b0 } ; - assign r1__read__h611736 = - { r1__read__h611738, csrf_software_int_en_vec_3 } ; - assign r1__read__h611738 = { r1__read__h611740, csrf_timer_int_en_vec_0 } ; - assign r1__read__h611740 = { r1__read__h611742, csrf_timer_int_en_vec_1 } ; - assign r1__read__h611742 = { r1__read__h611744, 1'b0 } ; - assign r1__read__h611744 = { r1__read__h611746, csrf_timer_int_en_vec_3 } ; - assign r1__read__h611746 = - { r1__read__h611748, csrf_external_int_en_vec_0 } ; - assign r1__read__h611748 = - { r1__read__h611750, csrf_external_int_en_vec_1 } ; - assign r1__read__h611750 = { r1__read__h611752, 1'b0 } ; - assign r1__read__h611752 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h611850 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h611855 = { r1__read__h611857, csrf_mcounteren_tm_reg } ; - assign r1__read__h611857 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h611868 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h611874 = - { r1__read__h611876, csrf_software_int_pend_vec_1 } ; - assign r1__read__h611876 = { r1__read__h611878, 1'b0 } ; - assign r1__read__h611878 = - { r1__read__h611880, csrf_software_int_pend_vec_3 } ; - assign r1__read__h611880 = - { r1__read__h611882, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h611882 = - { r1__read__h611884, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h611884 = { r1__read__h611886, 1'b0 } ; - assign r1__read__h611886 = - { r1__read__h611888, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h611888 = - { r1__read__h611890, csrf_external_int_pend_vec_0 } ; - assign r1__read__h611890 = - { r1__read__h611892, csrf_external_int_pend_vec_1 } ; - assign r1__read__h611892 = { r1__read__h611894, 1'b0 } ; - assign r1__read__h611894 = - { r1__read__h611896, csrf_external_int_pend_vec_3 } ; - assign r1__read__h611896 = { r1__read__h611898, 2'b0 } ; - assign r1__read__h611898 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h479638 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h479639 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473784 = + assign r1__read__h611697 = { r1__read__h611699, csrf_timer_int_en_vec_3 } ; + assign r1__read__h611699 = + { r1__read__h611701, csrf_external_int_en_vec_0 } ; + assign r1__read__h611701 = + { r1__read__h611703, csrf_external_int_en_vec_1 } ; + assign r1__read__h611703 = { r1__read__h611705, 1'b0 } ; + assign r1__read__h611705 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h611796 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h611801 = { r1__read__h611803, csrf_mcounteren_tm_reg } ; + assign r1__read__h611803 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h611814 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h611820 = + { r1__read__h611822, csrf_software_int_pend_vec_1 } ; + assign r1__read__h611822 = { r1__read__h611824, 1'b0 } ; + assign r1__read__h611824 = + { r1__read__h611826, csrf_software_int_pend_vec_3 } ; + assign r1__read__h611826 = + { r1__read__h611828, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h611828 = + { r1__read__h611830, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h611830 = { r1__read__h611832, 1'b0 } ; + assign r1__read__h611832 = + { r1__read__h611834, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h611834 = + { r1__read__h611836, csrf_external_int_pend_vec_0 } ; + assign r1__read__h611836 = + { r1__read__h611838, csrf_external_int_pend_vec_1 } ; + assign r1__read__h611838 = { r1__read__h611840, 1'b0 } ; + assign r1__read__h611840 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign rVal1__h479605 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h479606 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473751 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h610387 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862 = + assign r__h610340 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943 = + assign regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3331_3422_OR_NOT__ETC___d13928) && - _0_OR_NOT_fetchStage_pipelines_1_first__2709_BI_ETC___d13941 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 = + NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) && + _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30574,8 +30575,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13357 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30586,64 +30587,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2700_BIT_68__ETC___d13407 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13423 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 && + NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 ; + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13744 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13409 && + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d13891 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14033 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14039 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14059 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14067 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3333_AND__ETC___d14213 = + assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 = regRenamingTable$rename_0_canRename && - !checkForException___d12946[4] && + !checkForException___d12942[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30654,8 +30655,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13657 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30666,8 +30667,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13799 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30678,8 +30679,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2727_BIT_4_2728__ETC___d13817 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 = + NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -30690,85 +30691,85 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2709_BIT_68__ETC___d14121 ; - assign regRenamingTable_rename_1_canRename__3460_AND__ETC___d14167 = - regRenamingTable_rename_1_canRename__3460_AND__ETC___d14123 && + NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 ; + assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && (!fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 = renameStage_rg_m_halt_req[4] || !fetchStage$pipelines_0_first[68] && - (IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15]) ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13233 = - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_N_ETC___d13004 || + (IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 || (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 : - IF_checkForException_2946_BIT_4_2947_THEN_IF_c_ETC___d13095) == + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 : + IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091) == 4'd3 ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13680 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13677 || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13720 = + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d13714 || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1703_BIT_2_2998_OR_NOT_fetc_ETC___d13428 ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 = + csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[0] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[1] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[2] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[3] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[4] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[5] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[6] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[7] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[8] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[9] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[10] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[11] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[12] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[13] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[14] || - IF_IF_NOT_csrf_prv_reg_read__2730_EQ_3_2731_27_ETC___d12771[15] ; - assign renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13841 = + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] || + IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ; + assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d12946[4] || + checkForException___d12942[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h678634 = + assign renaming_spec_bits__h678574 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h675097 : + y_avValue_fst__h675037 : specTagManager$currentSpecBits ; - assign res_data__h335746 = { 32'hFFFFFFFF, x__h335761 } ; - assign res_data__h335751 = + assign res_data__h335713 = { 32'hFFFFFFFF, x__h335728 } ; + assign res_data__h335718 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -30781,8 +30782,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h381448 = { 32'hFFFFFFFF, x__h381463 } ; - assign res_data__h381453 = + assign res_data__h381415 = { 32'hFFFFFFFF, x__h381430 } ; + assign res_data__h381420 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -30795,8 +30796,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h427143 = { 32'hFFFFFFFF, x__h427158 } ; - assign res_data__h427148 = + assign res_data__h427110 = { 32'hFFFFFFFF, x__h427125 } ; + assign res_data__h427115 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -30809,7 +30810,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335747 = + assign res_fflags__h335714 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -30877,7 +30878,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h381449 = + assign res_fflags__h381416 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -30888,8 +30889,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590, @@ -30901,8 +30901,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601, @@ -30914,8 +30913,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617, @@ -30927,8 +30925,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630, @@ -30940,12 +30937,11 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0 || + (value_BIT_52___h399003 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h427144 = + assign res_fflags__h427111 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31013,49 +31009,49 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289850 = + assign resp_addr__h289818 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h362214 = + assign result__h362181 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h362209 } ; - assign result__h407911 = + guard__h362176 } ; + assign result__h407878 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407906 } ; - assign result__h453606 = + guard__h407873 } ; + assign result__h453573 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h453601 } ; - assign result__h501359 = + guard__h453568 } ; + assign result__h501326 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[0] | - guard__h501354 } ; - assign result__h540212 = + guard__h501321 } ; + assign result__h540179 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[0] | - guard__h540207 } ; - assign result__h579516 = + guard__h540174 } ; + assign result__h579483 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[0] | - guard__h579511 } ; - assign result__h643363 = w__h643358 & y__h643392 ; - assign result__h643414 = ~x__h643413 ; - assign rg_core_run_state_read__2994_EQ_2_2995_AND_NOT_ETC___d15252 = + guard__h579478 } ; + assign result__h643303 = w__h643298 & y__h643332 ; + assign result__h643354 = ~x__h643353 ; + assign rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rob_RDY_deqPort_0_deq_data__4238_AND_rob_RDY_d_ETC___d14693 = + assign rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 = rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4241_BITS_186_TO_1_ETC___d14688 ; - assign rob_RDY_enqPort_0_enq__2722_AND_regRenamingTab_ETC___d13243 = + NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 ; + assign rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && @@ -31063,19 +31059,19 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4241_BIT_166_4257_CONC_ETC___d14306 = + assign rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 : CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q270 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h651965 = + assign rs1__h651905 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h607897 = { r1__read__h611543, csrf_ppn_reg } ; + assign satp_csr__read__h607864 = { r1__read__h611496, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -31095,461 +31091,463 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 && IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ; - assign sbIdx__h156904 = + assign sbIdx__h156870 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h607695 = - { r1__read__h611307, csrf_scause_code_reg } ; - assign scounteren_csr__read__h607557 = - { r1__read__h611294, csrf_scounteren_cy_reg } ; - assign sfd__h336357 = { value__h344584, 3'd0 } ; - assign sfd__h352165 = + assign scause_csr__read__h607662 = + { r1__read__h611260, csrf_scause_code_reg } ; + assign scounteren_csr__read__h607524 = + { r1__read__h611247, csrf_scounteren_cy_reg } ; + assign sfd__h336324 = { value__h344551, 3'd0 } ; + assign sfd__h352132 = { 1'b0, - _theResult___fst_exp__h352073 != 8'd0, - sfdin__h352067[56:34] } + + _theResult___fst_exp__h352040 != 8'd0, + sfdin__h352034[56:34] } + 25'd1 ; - assign sfd__h360747 = + assign sfd__h360714 = { 1'b0, - _theResult___fst_exp__h360729 != 8'd0, - _theResult___snd__h360680[56:34] } + + _theResult___fst_exp__h360696 != 8'd0, + _theResult___snd__h360647[56:34] } + 25'd1 ; - assign sfd__h369931 = + assign sfd__h369898 = { 1'b0, - _theResult___fst_exp__h369839 != 8'd0, - sfdin__h369833[56:34] } + + _theResult___fst_exp__h369806 != 8'd0, + sfdin__h369800[56:34] } + 25'd1 ; - assign sfd__h378543 = + assign sfd__h378510 = { 1'b0, - _theResult___fst_exp__h378524 != 8'd0, - _theResult___snd__h378470[56:34] } + + _theResult___fst_exp__h378491 != 8'd0, + _theResult___snd__h378437[56:34] } + 25'd1 ; - assign sfd__h382059 = { value__h390281, 3'd0 } ; - assign sfd__h397862 = + assign sfd__h382026 = { value__h390248, 3'd0 } ; + assign sfd__h397829 = { 1'b0, - _theResult___fst_exp__h397770 != 8'd0, - sfdin__h397764[56:34] } + + _theResult___fst_exp__h397737 != 8'd0, + sfdin__h397731[56:34] } + 25'd1 ; - assign sfd__h406444 = + assign sfd__h406411 = { 1'b0, - _theResult___fst_exp__h406426 != 8'd0, - _theResult___snd__h406377[56:34] } + + _theResult___fst_exp__h406393 != 8'd0, + _theResult___snd__h406344[56:34] } + 25'd1 ; - assign sfd__h415628 = + assign sfd__h415595 = { 1'b0, - _theResult___fst_exp__h415536 != 8'd0, - sfdin__h415530[56:34] } + + _theResult___fst_exp__h415503 != 8'd0, + sfdin__h415497[56:34] } + 25'd1 ; - assign sfd__h424240 = + assign sfd__h424207 = { 1'b0, - _theResult___fst_exp__h424221 != 8'd0, - _theResult___snd__h424167[56:34] } + + _theResult___fst_exp__h424188 != 8'd0, + _theResult___snd__h424134[56:34] } + 25'd1 ; - assign sfd__h427754 = { value__h435976, 3'd0 } ; - assign sfd__h443557 = + assign sfd__h427721 = { value__h435943, 3'd0 } ; + assign sfd__h443524 = { 1'b0, - _theResult___fst_exp__h443465 != 8'd0, - sfdin__h443459[56:34] } + + _theResult___fst_exp__h443432 != 8'd0, + sfdin__h443426[56:34] } + 25'd1 ; - assign sfd__h452139 = + assign sfd__h452106 = { 1'b0, - _theResult___fst_exp__h452121 != 8'd0, - _theResult___snd__h452072[56:34] } + + _theResult___fst_exp__h452088 != 8'd0, + _theResult___snd__h452039[56:34] } + 25'd1 ; - assign sfd__h461323 = + assign sfd__h461290 = { 1'b0, - _theResult___fst_exp__h461231 != 8'd0, - sfdin__h461225[56:34] } + + _theResult___fst_exp__h461198 != 8'd0, + sfdin__h461192[56:34] } + 25'd1 ; - assign sfd__h469935 = + assign sfd__h469902 = { 1'b0, - _theResult___fst_exp__h469916 != 8'd0, - _theResult___snd__h469862[56:34] } + + _theResult___fst_exp__h469883 != 8'd0, + _theResult___snd__h469829[56:34] } + 25'd1 ; - assign sfd__h480379 = { value__h484962, 32'd0 } ; - assign sfd__h499423 = + assign sfd__h480346 = { value__h484929, 32'd0 } ; + assign sfd__h499390 = { 1'b0, - _theResult___fst_exp__h499405 != 11'd0, - _theResult___snd__h499356[56:5] } + + _theResult___fst_exp__h499372 != 11'd0, + _theResult___snd__h499323[56:5] } + 54'd1 ; - assign sfd__h509074 = + assign sfd__h509041 = { 1'b0, - _theResult___fst_exp__h508982 != 11'd0, - sfdin__h508976[56:5] } + + _theResult___fst_exp__h508949 != 11'd0, + sfdin__h508943[56:5] } + 54'd1 ; - assign sfd__h517834 = + assign sfd__h517801 = { 1'b0, - _theResult___fst_exp__h517815 != 11'd0, - _theResult___snd__h517761[56:5] } + + _theResult___fst_exp__h517782 != 11'd0, + _theResult___snd__h517728[56:5] } + 54'd1 ; - assign sfd__h519373 = { value__h523815, 32'd0 } ; - assign sfd__h538276 = + assign sfd__h519340 = { value__h523782, 32'd0 } ; + assign sfd__h538243 = { 1'b0, - _theResult___fst_exp__h538258 != 11'd0, - _theResult___snd__h538209[56:5] } + + _theResult___fst_exp__h538225 != 11'd0, + _theResult___snd__h538176[56:5] } + 54'd1 ; - assign sfd__h547927 = + assign sfd__h547894 = { 1'b0, - _theResult___fst_exp__h547835 != 11'd0, - sfdin__h547829[56:5] } + + _theResult___fst_exp__h547802 != 11'd0, + sfdin__h547796[56:5] } + 54'd1 ; - assign sfd__h556687 = + assign sfd__h556654 = { 1'b0, - _theResult___fst_exp__h556668 != 11'd0, - _theResult___snd__h556614[56:5] } + + _theResult___fst_exp__h556635 != 11'd0, + _theResult___snd__h556581[56:5] } + 54'd1 ; - assign sfd__h558677 = { value__h563119, 32'd0 } ; - assign sfd__h577580 = + assign sfd__h558644 = { value__h563086, 32'd0 } ; + assign sfd__h577547 = { 1'b0, - _theResult___fst_exp__h577562 != 11'd0, - _theResult___snd__h577513[56:5] } + + _theResult___fst_exp__h577529 != 11'd0, + _theResult___snd__h577480[56:5] } + 54'd1 ; - assign sfd__h587231 = + assign sfd__h587198 = { 1'b0, - _theResult___fst_exp__h587139 != 11'd0, - sfdin__h587133[56:5] } + + _theResult___fst_exp__h587106 != 11'd0, + sfdin__h587100[56:5] } + 54'd1 ; - assign sfd__h595991 = + assign sfd__h595958 = { 1'b0, - _theResult___fst_exp__h595972 != 11'd0, - _theResult___snd__h595918[56:5] } + + _theResult___fst_exp__h595939 != 11'd0, + _theResult___snd__h595885[56:5] } + 54'd1 ; - assign sfdin__h352067 = - _theResult____h343962[56] ? - _theResult___snd__h352084 : - _theResult___snd__h352095 ; - assign sfdin__h369833 = - _theResult____h361601[56] ? - _theResult___snd__h369850 : - _theResult___snd__h369861 ; - assign sfdin__h397764 = - _theResult____h389661[56] ? - _theResult___snd__h397781 : - _theResult___snd__h397792 ; - assign sfdin__h415530 = - _theResult____h407298[56] ? - _theResult___snd__h415547 : - _theResult___snd__h415558 ; - assign sfdin__h443459 = - _theResult____h435356[56] ? - _theResult___snd__h443476 : - _theResult___snd__h443487 ; - assign sfdin__h461225 = - _theResult____h452993[56] ? - _theResult___snd__h461242 : - _theResult___snd__h461253 ; - assign sfdin__h508976 = - _theResult____h500746[56] ? - _theResult___snd__h508993 : - _theResult___snd__h509004 ; - assign sfdin__h547829 = - _theResult____h539599[56] ? - _theResult___snd__h547846 : - _theResult___snd__h547857 ; - assign sfdin__h587133 = - _theResult____h578903[56] ? - _theResult___snd__h587150 : - _theResult___snd__h587161 ; - assign shiftData__h181173 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181305 ; - assign sie_csr__read__h607461 = - { r1__read__h610759, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h607834 = - { r1__read__h611313, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h681761 = specTagManager$currentSpecBits | y__h681774 ; - assign sstatus_csr__read__h607392 = { r1__read__h610355, csrf_ie_vec_0 } ; - assign stvec_csr__read__h607504 = - { r1__read__h611289, csrf_stvec_mode_low_reg } ; - assign upd__h4024 = + assign sfdin__h352034 = + _theResult____h343929[56] ? + _theResult___snd__h352051 : + _theResult___snd__h352062 ; + assign sfdin__h369800 = + _theResult____h361568[56] ? + _theResult___snd__h369817 : + _theResult___snd__h369828 ; + assign sfdin__h397731 = + _theResult____h389628[56] ? + _theResult___snd__h397748 : + _theResult___snd__h397759 ; + assign sfdin__h415497 = + _theResult____h407265[56] ? + _theResult___snd__h415514 : + _theResult___snd__h415525 ; + assign sfdin__h443426 = + _theResult____h435323[56] ? + _theResult___snd__h443443 : + _theResult___snd__h443454 ; + assign sfdin__h461192 = + _theResult____h452960[56] ? + _theResult___snd__h461209 : + _theResult___snd__h461220 ; + assign sfdin__h508943 = + _theResult____h500713[56] ? + _theResult___snd__h508960 : + _theResult___snd__h508971 ; + assign sfdin__h547796 = + _theResult____h539566[56] ? + _theResult___snd__h547813 : + _theResult___snd__h547824 ; + assign sfdin__h587100 = + _theResult____h578870[56] ? + _theResult___snd__h587117 : + _theResult___snd__h587128 ; + assign shiftData__h181140 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181272 ; + assign sie_csr__read__h607428 = + { r1__read__h610712, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h607801 = + { r1__read__h611266, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h681701 = specTagManager$currentSpecBits | y__h681714 ; + assign sstatus_csr__read__h607359 = { r1__read__h610308, csrf_ie_vec_0 } ; + assign stvec_csr__read__h607471 = + { r1__read__h611242, csrf_stvec_mode_low_reg } ; + assign upd__h3992 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5341 = n__read__h6636 + 64'd1 ; - assign upd__h6750 = + assign upd__h5309 = n__read__h6604 + 64'd1 ; + assign upd__h6718 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h710124 = + assign upd__h710029 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h293820 = + assign v__h293788 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h294051 : + v__h294019 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h294051 = + assign v__h294019 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h297165 = + assign v__h297133 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297683 : + v__h297651 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297683 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307679 = + assign v__h297651 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307647 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307910 : + v__h307878 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307910 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h311555 = + assign v__h307878 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h311523 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311786 : + v__h311754 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311786 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h326156 = + assign v__h311754 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h326124 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h326387 : + v__h326355 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h326387 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h329381 = + assign v__h326355 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h329349 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h329612 : + v__h329580 : coreFix_memExe_forwardQ_enqP ; - assign v__h329612 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h601760 = + assign v__h329580 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h601727 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h601770 : + v__h601737 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h601770 = + assign v__h601737 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h602405 = v__h601760 - 2'd1 ; - assign v__h605779 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h606684 ; - assign v__h630099 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h630852 ; - assign vaddr__h181168 = + assign v__h602372 = v__h601727 - 2'd1 ; + assign v__h605746 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h606651 ; + assign v__h630040 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h630793 ; + assign vaddr__h181135 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12 } ; - assign value__h344584 = + assign value_BIT_52___h399003 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != + 11'd0 ; + assign value__h344551 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h390281 = + assign value__h390248 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != - 11'd0, + value_BIT_52___h399003, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435976 = + assign value__h435943 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484962 = { 1'b0, f1_exp__h480017 != 8'd0, f1_sfd__h480018 } ; - assign value__h523815 = { 1'b0, f2_exp__h519011 != 8'd0, f2_sfd__h519012 } ; - assign value__h563119 = { 1'b0, f3_exp__h558315 != 8'd0, f3_sfd__h558316 } ; - assign vm_mode_reg__read__h611549 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h643358 = + assign value__h484929 = { 1'b0, f1_exp__h479984 != 8'd0, f1_sfd__h479985 } ; + assign value__h523782 = { 1'b0, f2_exp__h518978 != 8'd0, f2_sfd__h518979 } ; + assign value__h563086 = { 1'b0, f3_exp__h558282 != 8'd0, f3_sfd__h558283 } ; + assign vm_mode_reg__read__h611502 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h643298 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h643414 : + result__h643354 : 12'd4095 ; - assign x__h153478 = + assign x__h153444 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153484 = + assign x__h153450 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157025 = { 3'd0, sbIdx__h156904 } ; - assign x__h157031 = + assign x__h156991 = { 3'd0, sbIdx__h156870 } ; + assign x__h156997 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h159841 = + assign x__h159807 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h159845 = + assign x__h159811 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161693 = + assign x__h161659 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181082 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180170 ; - assign x__h181083 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180776 ; - assign x__h181305 = { vaddr__h181168[2:0], 3'b0 } ; - assign x__h18203 = + assign x__h181049 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180137 ; + assign x__h181050 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180743 ; + assign x__h181272 = { vaddr__h181135[2:0], 3'b0 } ; + assign x__h18170 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h191559 = + assign x__h191526 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190796[63:32] : - curData__h190796[31:0] ; - assign x__h20741 = + curData__h190763[63:32] : + curData__h190763[31:0] ; + assign x__h20708 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h285158 = + assign x__h285126 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h285170 = + assign x__h285138 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h287024 = + assign x__h286992 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h300030 = + assign x__h299998 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335761 = - { (_theResult___exp__h379093 != 8'd255 || - _theResult___sfd__h379094 == 23'd0) && + assign x__h335728 = + { (_theResult___exp__h379060 != 8'd255 || + _theResult___sfd__h379061 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h379370, - out_f_sfd__h379371 } ; + out_f_exp__h379337, + out_f_sfd__h379338 } ; + assign x__h362278 = + sfd__h336324 << (x__h362311[11] ? 12'hAAA : x__h362311) ; assign x__h362311 = - sfd__h336357 << (x__h362344[11] ? 12'hAAA : x__h362344) ; - assign x__h362344 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h381463 = - { (_theResult___exp__h424790 != 8'd255 || - _theResult___sfd__h424791 == 23'd0) && + assign x__h381430 = + { (_theResult___exp__h424757 != 8'd255 || + _theResult___sfd__h424758 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h425067, - out_f_sfd__h425068 } ; + out_f_exp__h425034, + out_f_sfd__h425035 } ; + assign x__h407975 = + sfd__h382026 << (x__h408008[11] ? 12'hAAA : x__h408008) ; assign x__h408008 = - sfd__h382059 << (x__h408041[11] ? 12'hAAA : x__h408041) ; - assign x__h408041 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h427158 = - { (_theResult___exp__h470485 != 8'd255 || - _theResult___sfd__h470486 == 23'd0) && + assign x__h427125 = + { (_theResult___exp__h470452 != 8'd255 || + _theResult___sfd__h470453 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470762, - out_f_sfd__h470763 } ; + out_f_exp__h470729, + out_f_sfd__h470730 } ; + assign x__h453670 = + sfd__h427721 << (x__h453703[11] ? 12'hAAA : x__h453703) ; assign x__h453703 = - sfd__h427754 << (x__h453736[11] ? 12'hAAA : x__h453736) ; - assign x__h453736 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; - assign x__h46110 = + assign x__h46077 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h479547 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476683 ; - assign x__h479548 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477291 ; - assign x__h479549 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477893 ; - assign x__h48646 = + assign x__h479514 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476650 ; + assign x__h479515 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477258 ; + assign x__h479516 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477860 ; + assign x__h48613 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h501454 = sfd__h480379 << x__h501487 ; - assign x__h501487 = + assign x__h501421 = sfd__h480346 << x__h501454 ; + assign x__h501454 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ; - assign x__h540307 = sfd__h519373 << x__h540340 ; - assign x__h540340 = + assign x__h540274 = sfd__h519340 << x__h540307 ; + assign x__h540307 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ; - assign x__h579611 = sfd__h558677 << x__h579644 ; - assign x__h579644 = + assign x__h579578 = sfd__h558644 << x__h579611 ; + assign x__h579611 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ; - assign x__h601261 = a__h600825[63] ^ b__h600826[63] ; - assign x__h610340 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h614583 = + assign x__h601228 = a__h600792[63] ^ b__h600793[63] ; + assign x__h610293 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h614524 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h606894 : - v__h605779 ; - assign x__h614584 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h612440 ; - assign x__h636445 = + rVal1__h606861 : + v__h605746 ; + assign x__h614525 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h612381 ; + assign x__h636385 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h631060 : - v__h630099 ; - assign x__h636446 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634312 ; - assign x__h643362 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h643413 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h692296 = + rVal1__h631001 : + v__h630040 ; + assign x__h636386 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634252 ; + assign x__h643302 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h643353 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h692236 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h700755 = { cause_code__h698122, 2'b0 } ; - assign x__h709419 = { 1'b0, csrf_spp_reg } ; - assign x__h712792 = commitStage_rg_serialnum + y__h712818 ; - assign x__h714428 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_snd_snd_snd_fst__h714252 : - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 ; - assign x__h76055 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311953 = + assign x__h700695 = { cause_code__h698062, 2'b0 } ; + assign x__h709324 = { 1'b0, csrf_spp_reg } ; + assign x__h712697 = commitStage_rg_serialnum + y__h712723 ; + assign x__h714333 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_snd_snd_snd_fst__h714157 : + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 ; + assign x__h76022 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h311921 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65904 = + assign x_data__h65871 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h671111 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h686042 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h651649 = csrf_frm_reg ; - assign x_quotient__h473073 = + assign x_data_imm__h671051 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h685982 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h651589 = csrf_frm_reg ; + assign x_quotient__h473040 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473758 : + q___1__h473725 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h607301 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h473074 = + assign x_reg_ifc__read__h607268 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h473041 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473784 : + r___1__h473751 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252683 = + assign y__h252650 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h643392 = ~x__h643362 ; - assign y__h648323 = + assign y__h643332 = ~x__h643302 ; + assign y__h648263 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -31558,74 +31556,74 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h681774 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h712818 = + assign y__h681714 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h712723 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h712833 : + y_avValue_snd_snd_snd_snd_snd__h712738 : 64'd0 ; - assign y__h714209 = - NOT_rob_deqPort_0_canDeq__4893_4894_OR_rob_deq_ETC___d15177 ? - y_avValue_snd_snd_snd_snd_snd__h714258 : - y__h712818 ; - assign y_avValue__h180170 = + assign y__h714114 = + NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ? + y_avValue_snd_snd_snd_snd_snd__h714163 : + y__h712723 ; + assign y_avValue__h180137 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180776 = + assign y_avValue__h180743 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476683 = + assign y_avValue__h476650 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h477291 = + assign y_avValue__h477258 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477893 = + assign y_avValue__h477860 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h606684 = + assign y_avValue__h606651 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11754 ; - assign y_avValue__h612440 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 ; + assign y_avValue__h612381 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11766 ; - assign y_avValue__h630852 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12192 ? + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 ; + assign y_avValue__h630793 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12400 ; - assign y_avValue__h634312 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2165_2_ETC___d12220 ? + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 ; + assign y_avValue__h634252 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12412 ; - assign y_avValue__h699008 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 ; + assign y_avValue__h698948 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h700740 + { 58'd0, x__h700755 } : - base__h700740 ; - assign y_avValue__h700777 = + base__h700680 + { 58'd0, x__h700695 } : + base__h700680 ; + assign y_avValue__h700717 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h700943 + { 58'd0, x__h700755 } : - base__h700943 ; - assign y_avValue_fst__h675034 = + base__h700883 + { 58'd0, x__h700695 } : + base__h700883 ; + assign y_avValue_fst__h674974 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h681761 : + spec_bits__h681701 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h675063 = - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 ? - y_avValue_fst__h675034 : + assign y_avValue_fst__h675003 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ? + y_avValue_fst__h674974 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h675097 = + assign y_avValue_fst__h675037 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359) ? - y_avValue_fst__h675063 : + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ? + y_avValue_fst__h675003 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h712379 = + assign y_avValue_fst__h712284 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31639,10 +31637,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h714101 = - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 | + assign y_avValue_fst__h714006 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h714129 = + assign y_avValue_fst__h714034 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31654,9 +31652,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15184 : - y_avValue_fst__h714101 ; - assign y_avValue_snd_snd_snd_fst__h712827 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 : + y_avValue_fst__h714006 ; + assign y_avValue_snd_snd_snd_fst__h712732 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31670,7 +31668,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h714252 = + assign y_avValue_snd_snd_snd_fst__h714157 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31682,12 +31680,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 : - y_avValue_snd_snd_snd_fst__h714281 ; - assign y_avValue_snd_snd_snd_fst__h714281 = - IF_rob_deqPort_0_canDeq__4893_THEN_IF_NOT_rob__ETC___d15206 + + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 : + y_avValue_snd_snd_snd_fst__h714186 ; + assign y_avValue_snd_snd_snd_fst__h714186 = + IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h712833 = + assign y_avValue_snd_snd_snd_snd_snd__h712738 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -31701,7 +31699,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h714258 = + assign y_avValue_snd_snd_snd_snd_snd__h714163 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -31713,9 +31711,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - y__h712818 : - y_avValue_snd_snd_snd_snd_snd__h714287 ; - assign y_avValue_snd_snd_snd_snd_snd__h714287 = y__h712818 + 64'd1 ; + y__h712723 : + y_avValue_snd_snd_snd_snd_snd__h714192 ; + assign y_avValue_snd_snd_snd_snd_snd__h714192 = y__h712723 + 64'd1 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[153:142]) @@ -31908,28 +31906,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h195006 = + x__h194973 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -31945,28 +31943,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283725 = + x__h283692 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -31976,10 +31974,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287946 = + addr__h287914 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287946 = + addr__h287914 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -31988,36 +31986,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190796 = + curData__h190763 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h699161 = commitStage_commitTrap[132:69]; - default: trap_val__h699161 = + 4'd0, 4'd3: trap_val__h699101 = commitStage_commitTrap[132:69]; + default: trap_val__h699101 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -32032,222 +32030,336 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h289495 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h289495 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h718266 = fflags_csr__read__h607171; - 12'd2: data_out__h718266 = frm_csr__read__h607182; - 12'd3: data_out__h718266 = fcsr_csr__read__h607196; - 12'd256: data_out__h718266 = sstatus_csr__read__h607392; - 12'd260: data_out__h718266 = sie_csr__read__h607461; - 12'd261: data_out__h718266 = stvec_csr__read__h607504; - 12'd262: data_out__h718266 = scounteren_csr__read__h607557; - 12'd320: data_out__h718266 = csrf_sscratch_csr; - 12'd321: data_out__h718266 = csrf_sepc_csr; - 12'd322: data_out__h718266 = scause_csr__read__h607695; - 12'd323: data_out__h718266 = csrf_stval_csr; - 12'd324: data_out__h718266 = sip_csr__read__h607834; - 12'd384: data_out__h718266 = satp_csr__read__h607897; - 12'd768: data_out__h718266 = mstatus_csr__read__h608040; - 12'd769: data_out__h718266 = 64'h800000000014112D; - 12'd770: data_out__h718266 = medeleg_csr__read__h608188; - 12'd771: data_out__h718266 = mideleg_csr__read__h608283; - 12'd772: data_out__h718266 = mie_csr__read__h608414; - 12'd773: data_out__h718266 = mtvec_csr__read__h608496; - 12'd774: data_out__h718266 = mcounteren_csr__read__h608588; - 12'd832: data_out__h718266 = csrf_mscratch_csr; - 12'd833: data_out__h718266 = csrf_mepc_csr; - 12'd834: data_out__h718266 = mcause_csr__read__h608843; - 12'd835: data_out__h718266 = csrf_mtval_csr; - 12'd836: data_out__h718266 = mip_csr__read__h609083; - 12'd1968: data_out__h718266 = csrf_rg_dcsr; - 12'd1969: data_out__h718266 = csrf_rg_dpc; - 12'd1970: data_out__h718266 = csrf_rg_dscratch0; - 12'd1971: data_out__h718266 = csrf_rg_dscratch1; + 12'd1: data_out__h718171 = fflags_csr__read__h607138; + 12'd2: data_out__h718171 = frm_csr__read__h607149; + 12'd3: data_out__h718171 = fcsr_csr__read__h607163; + 12'd256: data_out__h718171 = sstatus_csr__read__h607359; + 12'd260: data_out__h718171 = sie_csr__read__h607428; + 12'd261: data_out__h718171 = stvec_csr__read__h607471; + 12'd262: data_out__h718171 = scounteren_csr__read__h607524; + 12'd320: data_out__h718171 = csrf_sscratch_csr; + 12'd321: data_out__h718171 = csrf_sepc_csr; + 12'd322: data_out__h718171 = scause_csr__read__h607662; + 12'd323: data_out__h718171 = csrf_stval_csr; + 12'd324: data_out__h718171 = sip_csr__read__h607801; + 12'd384: data_out__h718171 = satp_csr__read__h607864; + 12'd768: data_out__h718171 = mstatus_csr__read__h608007; + 12'd769: data_out__h718171 = 64'h800000000014112D; + 12'd770: data_out__h718171 = medeleg_csr__read__h608155; + 12'd771: data_out__h718171 = mideleg_csr__read__h608250; + 12'd772: data_out__h718171 = mie_csr__read__h608374; + 12'd773: data_out__h718171 = mtvec_csr__read__h608456; + 12'd774: data_out__h718171 = mcounteren_csr__read__h608548; + 12'd832: data_out__h718171 = csrf_mscratch_csr; + 12'd833: data_out__h718171 = csrf_mepc_csr; + 12'd834: data_out__h718171 = mcause_csr__read__h608803; + 12'd835: data_out__h718171 = csrf_mtval_csr; + 12'd836: data_out__h718171 = mip_csr__read__h609036; + 12'd1968: data_out__h718171 = csrf_rg_dcsr; + 12'd1969: data_out__h718171 = csrf_rg_dpc; + 12'd1970: data_out__h718171 = csrf_rg_dscratch0; + 12'd1971: data_out__h718171 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h718266 = 64'd0; - 12'd2049: data_out__h718266 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: data_out__h718266 = n__read__h609187; - 12'd2818, 12'd3074: data_out__h718266 = n__read__h609378; - 12'd3073: data_out__h718266 = csrf_time_reg; - default: data_out__h718266 = 64'b0; + data_out__h718171 = 64'd0; + 12'd2049: data_out__h718171 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: data_out__h718171 = n__read__h609140; + 12'd2818, 12'd3074: data_out__h718171 = n__read__h609331; + 12'd3073: data_out__h718171 = csrf_time_reg; + default: data_out__h718171 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h606894 = fflags_csr__read__h607171; - 12'd2: rVal1__h606894 = frm_csr__read__h607182; - 12'd3: rVal1__h606894 = fcsr_csr__read__h607196; - 12'd256: rVal1__h606894 = sstatus_csr__read__h607392; - 12'd260: rVal1__h606894 = sie_csr__read__h607461; - 12'd261: rVal1__h606894 = stvec_csr__read__h607504; - 12'd262: rVal1__h606894 = scounteren_csr__read__h607557; - 12'd320: rVal1__h606894 = csrf_sscratch_csr; - 12'd321: rVal1__h606894 = csrf_sepc_csr; - 12'd322: rVal1__h606894 = scause_csr__read__h607695; - 12'd323: rVal1__h606894 = csrf_stval_csr; - 12'd324: rVal1__h606894 = sip_csr__read__h607834; - 12'd384: rVal1__h606894 = satp_csr__read__h607897; - 12'd768: rVal1__h606894 = mstatus_csr__read__h608040; - 12'd769: rVal1__h606894 = 64'h800000000014112D; - 12'd770: rVal1__h606894 = medeleg_csr__read__h608188; - 12'd771: rVal1__h606894 = mideleg_csr__read__h608283; - 12'd772: rVal1__h606894 = mie_csr__read__h608414; - 12'd773: rVal1__h606894 = mtvec_csr__read__h608496; - 12'd774: rVal1__h606894 = mcounteren_csr__read__h608588; - 12'd832: rVal1__h606894 = csrf_mscratch_csr; - 12'd833: rVal1__h606894 = csrf_mepc_csr; - 12'd834: rVal1__h606894 = mcause_csr__read__h608843; - 12'd835: rVal1__h606894 = csrf_mtval_csr; - 12'd836: rVal1__h606894 = mip_csr__read__h609083; - 12'd1968: rVal1__h606894 = csrf_rg_dcsr; - 12'd1969: rVal1__h606894 = csrf_rg_dpc; - 12'd1970: rVal1__h606894 = csrf_rg_dscratch0; - 12'd1971: rVal1__h606894 = csrf_rg_dscratch1; + 12'd1: rVal1__h606861 = fflags_csr__read__h607138; + 12'd2: rVal1__h606861 = frm_csr__read__h607149; + 12'd3: rVal1__h606861 = fcsr_csr__read__h607163; + 12'd256: rVal1__h606861 = sstatus_csr__read__h607359; + 12'd260: rVal1__h606861 = sie_csr__read__h607428; + 12'd261: rVal1__h606861 = stvec_csr__read__h607471; + 12'd262: rVal1__h606861 = scounteren_csr__read__h607524; + 12'd320: rVal1__h606861 = csrf_sscratch_csr; + 12'd321: rVal1__h606861 = csrf_sepc_csr; + 12'd322: rVal1__h606861 = scause_csr__read__h607662; + 12'd323: rVal1__h606861 = csrf_stval_csr; + 12'd324: rVal1__h606861 = sip_csr__read__h607801; + 12'd384: rVal1__h606861 = satp_csr__read__h607864; + 12'd768: rVal1__h606861 = mstatus_csr__read__h608007; + 12'd769: rVal1__h606861 = 64'h800000000014112D; + 12'd770: rVal1__h606861 = medeleg_csr__read__h608155; + 12'd771: rVal1__h606861 = mideleg_csr__read__h608250; + 12'd772: rVal1__h606861 = mie_csr__read__h608374; + 12'd773: rVal1__h606861 = mtvec_csr__read__h608456; + 12'd774: rVal1__h606861 = mcounteren_csr__read__h608548; + 12'd832: rVal1__h606861 = csrf_mscratch_csr; + 12'd833: rVal1__h606861 = csrf_mepc_csr; + 12'd834: rVal1__h606861 = mcause_csr__read__h608803; + 12'd835: rVal1__h606861 = csrf_mtval_csr; + 12'd836: rVal1__h606861 = mip_csr__read__h609036; + 12'd1968: rVal1__h606861 = csrf_rg_dcsr; + 12'd1969: rVal1__h606861 = csrf_rg_dpc; + 12'd1970: rVal1__h606861 = csrf_rg_dscratch0; + 12'd1971: rVal1__h606861 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h606894 = 64'd0; - 12'd2049: rVal1__h606894 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: rVal1__h606894 = n__read__h609187; - 12'd2818, 12'd3074: rVal1__h606894 = n__read__h609378; - 12'd3073: rVal1__h606894 = csrf_time_reg; - default: rVal1__h606894 = 64'b0; + rVal1__h606861 = 64'd0; + 12'd2049: rVal1__h606861 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: rVal1__h606861 = n__read__h609140; + 12'd2818, 12'd3074: rVal1__h606861 = n__read__h609331; + 12'd3073: rVal1__h606861 = csrf_time_reg; + default: rVal1__h606861 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h607171 or - frm_csr__read__h607182 or - fcsr_csr__read__h607196 or - sstatus_csr__read__h607392 or - sie_csr__read__h607461 or - stvec_csr__read__h607504 or - scounteren_csr__read__h607557 or + fflags_csr__read__h607138 or + frm_csr__read__h607149 or + fcsr_csr__read__h607163 or + sstatus_csr__read__h607359 or + sie_csr__read__h607428 or + stvec_csr__read__h607471 or + scounteren_csr__read__h607524 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h607695 or + scause_csr__read__h607662 or csrf_stval_csr or - sip_csr__read__h607834 or - satp_csr__read__h607897 or - mstatus_csr__read__h608040 or - medeleg_csr__read__h608188 or - mideleg_csr__read__h608283 or - mie_csr__read__h608414 or - mtvec_csr__read__h608496 or - mcounteren_csr__read__h608588 or + sip_csr__read__h607801 or + satp_csr__read__h607864 or + mstatus_csr__read__h608007 or + medeleg_csr__read__h608155 or + mideleg_csr__read__h608250 or + mie_csr__read__h608374 or + mtvec_csr__read__h608456 or + mcounteren_csr__read__h608548 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h608843 or + mcause_csr__read__h608803 or csrf_mtval_csr or - mip_csr__read__h609083 or + mip_csr__read__h609036 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h607301 or - n__read__h609187 or n__read__h609378 or csrf_time_reg) + x_reg_ifc__read__h607268 or + n__read__h609140 or n__read__h609331 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h631060 = fflags_csr__read__h607171; - 12'd2: rVal1__h631060 = frm_csr__read__h607182; - 12'd3: rVal1__h631060 = fcsr_csr__read__h607196; - 12'd256: rVal1__h631060 = sstatus_csr__read__h607392; - 12'd260: rVal1__h631060 = sie_csr__read__h607461; - 12'd261: rVal1__h631060 = stvec_csr__read__h607504; - 12'd262: rVal1__h631060 = scounteren_csr__read__h607557; - 12'd320: rVal1__h631060 = csrf_sscratch_csr; - 12'd321: rVal1__h631060 = csrf_sepc_csr; - 12'd322: rVal1__h631060 = scause_csr__read__h607695; - 12'd323: rVal1__h631060 = csrf_stval_csr; - 12'd324: rVal1__h631060 = sip_csr__read__h607834; - 12'd384: rVal1__h631060 = satp_csr__read__h607897; - 12'd768: rVal1__h631060 = mstatus_csr__read__h608040; - 12'd769: rVal1__h631060 = 64'h800000000014112D; - 12'd770: rVal1__h631060 = medeleg_csr__read__h608188; - 12'd771: rVal1__h631060 = mideleg_csr__read__h608283; - 12'd772: rVal1__h631060 = mie_csr__read__h608414; - 12'd773: rVal1__h631060 = mtvec_csr__read__h608496; - 12'd774: rVal1__h631060 = mcounteren_csr__read__h608588; - 12'd832: rVal1__h631060 = csrf_mscratch_csr; - 12'd833: rVal1__h631060 = csrf_mepc_csr; - 12'd834: rVal1__h631060 = mcause_csr__read__h608843; - 12'd835: rVal1__h631060 = csrf_mtval_csr; - 12'd836: rVal1__h631060 = mip_csr__read__h609083; - 12'd1968: rVal1__h631060 = csrf_rg_dcsr; - 12'd1969: rVal1__h631060 = csrf_rg_dpc; - 12'd1970: rVal1__h631060 = csrf_rg_dscratch0; - 12'd1971: rVal1__h631060 = csrf_rg_dscratch1; + 12'd1: rVal1__h631001 = fflags_csr__read__h607138; + 12'd2: rVal1__h631001 = frm_csr__read__h607149; + 12'd3: rVal1__h631001 = fcsr_csr__read__h607163; + 12'd256: rVal1__h631001 = sstatus_csr__read__h607359; + 12'd260: rVal1__h631001 = sie_csr__read__h607428; + 12'd261: rVal1__h631001 = stvec_csr__read__h607471; + 12'd262: rVal1__h631001 = scounteren_csr__read__h607524; + 12'd320: rVal1__h631001 = csrf_sscratch_csr; + 12'd321: rVal1__h631001 = csrf_sepc_csr; + 12'd322: rVal1__h631001 = scause_csr__read__h607662; + 12'd323: rVal1__h631001 = csrf_stval_csr; + 12'd324: rVal1__h631001 = sip_csr__read__h607801; + 12'd384: rVal1__h631001 = satp_csr__read__h607864; + 12'd768: rVal1__h631001 = mstatus_csr__read__h608007; + 12'd769: rVal1__h631001 = 64'h800000000014112D; + 12'd770: rVal1__h631001 = medeleg_csr__read__h608155; + 12'd771: rVal1__h631001 = mideleg_csr__read__h608250; + 12'd772: rVal1__h631001 = mie_csr__read__h608374; + 12'd773: rVal1__h631001 = mtvec_csr__read__h608456; + 12'd774: rVal1__h631001 = mcounteren_csr__read__h608548; + 12'd832: rVal1__h631001 = csrf_mscratch_csr; + 12'd833: rVal1__h631001 = csrf_mepc_csr; + 12'd834: rVal1__h631001 = mcause_csr__read__h608803; + 12'd835: rVal1__h631001 = csrf_mtval_csr; + 12'd836: rVal1__h631001 = mip_csr__read__h609036; + 12'd1968: rVal1__h631001 = csrf_rg_dcsr; + 12'd1969: rVal1__h631001 = csrf_rg_dpc; + 12'd1970: rVal1__h631001 = csrf_rg_dscratch0; + 12'd1971: rVal1__h631001 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h631060 = 64'd0; - 12'd2049: rVal1__h631060 = x_reg_ifc__read__h607301; - 12'd2816, 12'd3072: rVal1__h631060 = n__read__h609187; - 12'd2818, 12'd3074: rVal1__h631060 = n__read__h609378; - 12'd3073: rVal1__h631060 = csrf_time_reg; - default: rVal1__h631060 = 64'b0; + rVal1__h631001 = 64'd0; + 12'd2049: rVal1__h631001 = x_reg_ifc__read__h607268; + 12'd2816, 12'd3072: rVal1__h631001 = n__read__h609140; + 12'd2818, 12'd3074: rVal1__h631001 = n__read__h609331; + 12'd3073: rVal1__h631001 = csrf_time_reg; + default: rVal1__h631001 = 64'b0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h343911 = 8'd255; + 3'd2: + _theResult___fst_exp__h343911 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h343911 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h343911 = 8'd254; + default: _theResult___fst_exp__h343911 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h343912 = 23'd0; + 3'd2: + _theResult___fst_sfd__h343912 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h343912 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h343912 = 23'd8388607; + default: _theResult___fst_sfd__h343912 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h389611 = 23'd0; + 3'd2: + _theResult___fst_sfd__h389611 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h389611 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h389611 = 23'd8388607; + default: _theResult___fst_sfd__h389611 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h389610 = 8'd255; + 3'd2: + _theResult___fst_exp__h389610 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h389610 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h389610 = 8'd254; + default: _theResult___fst_exp__h389610 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h435305 = 8'd255; + 3'd2: + _theResult___fst_exp__h435305 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h435305 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h435305 = 8'd254; + default: _theResult___fst_exp__h435305 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h435306 = 23'd0; + 3'd2: + _theResult___fst_sfd__h435306 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h435306 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h435306 = 23'd8388607; + default: _theResult___fst_sfd__h435306 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -32256,221 +32368,107 @@ module mkCore(CLK, 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343944 = 8'd255; - 3'd2: - _theResult___fst_exp__h343944 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h343944 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h343944 = 8'd254; - default: _theResult___fst_exp__h343944 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343945 = 23'd0; - 3'd2: - _theResult___fst_sfd__h343945 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h343945 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h343945 = 23'd8388607; - default: _theResult___fst_sfd__h343945 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h389643 = 8'd255; - 3'd2: - _theResult___fst_exp__h389643 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h389643 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h389643 = 8'd254; - default: _theResult___fst_exp__h389643 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h389644 = 23'd0; - 3'd2: - _theResult___fst_sfd__h389644 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h389644 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h389644 = 23'd8388607; - default: _theResult___fst_sfd__h389644 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h435338 = 8'd255; - 3'd2: - _theResult___fst_exp__h435338 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h435338 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h435338 = 8'd254; - default: _theResult___fst_exp__h435338 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h435339 = 23'd0; - 3'd2: - _theResult___fst_sfd__h435339 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h435339 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h435339 = 23'd8388607; - default: _theResult___fst_sfd__h435339 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -32512,16 +32510,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h698137 = commitStage_commitTrap[3:0]; - default: i__h698137 = 4'd15; + i__h698077 = commitStage_commitTrap[3:0]; + default: i__h698077 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h698297 = commitStage_commitTrap[3:0]; - default: i__h698297 = 4'd15; + i__h698237 = commitStage_commitTrap[3:0]; + default: i__h698237 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -32749,446 +32747,394 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h352681 or - _theResult___fst_exp__h360729 or - out_exp__h361174 or _theResult___exp__h361171) + always@(guard__h352648 or + _theResult___fst_exp__h360696 or + out_exp__h361141 or _theResult___exp__h361138) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - _theResult___fst_exp__h360729; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + _theResult___fst_exp__h360696; 2'b10: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - out_exp__h361174; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + out_exp__h361141; 2'b11: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 = - _theResult___exp__h361171; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 = + _theResult___exp__h361138; endcase end - always@(guard__h352681 or - _theResult___fst_exp__h360729 or _theResult___exp__h361171) + always@(guard__h352648 or + _theResult___fst_exp__h360696 or _theResult___exp__h361138) begin - case (guard__h352681) + case (guard__h352648) 2'b0: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 = - _theResult___fst_exp__h360729; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 = + _theResult___fst_exp__h360696; 2'b01, 2'b10, 2'b11: - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 = - _theResult___exp__h361171; + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 = + _theResult___exp__h361138; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32 or - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33 or + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 or + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360729) + _theResult___fst_exp__h360696) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h361249 = - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q32; + _theResult___fst_exp__h361216 = + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32; 3'd1: - _theResult___fst_exp__h361249 = - CASE_guard52681_0b0_theResult___fst_exp60729_0_ETC__q33; + _theResult___fst_exp__h361216 = + CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33; 3'd2: - _theResult___fst_exp__h361249 = + _theResult___fst_exp__h361216 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h361249 = + _theResult___fst_exp__h361216 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h361249 = _theResult___fst_exp__h360729; - default: _theResult___fst_exp__h361249 = 8'd0; + 3'd4: _theResult___fst_exp__h361216 = _theResult___fst_exp__h360696; + default: _theResult___fst_exp__h361216 = 8'd0; endcase end - always@(guard__h343972 or - _theResult___fst_exp__h352073 or - out_exp__h352592 or _theResult___exp__h352589) + always@(guard__h343939 or + _theResult___fst_exp__h352040 or + out_exp__h352559 or _theResult___exp__h352556) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - _theResult___fst_exp__h352073; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + _theResult___fst_exp__h352040; 2'b10: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - out_exp__h352592; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + out_exp__h352559; 2'b11: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 = - _theResult___exp__h352589; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 = + _theResult___exp__h352556; endcase end - always@(guard__h343972 or - _theResult___fst_exp__h352073 or _theResult___exp__h352589) + always@(guard__h343939 or + _theResult___fst_exp__h352040 or _theResult___exp__h352556) begin - case (guard__h343972) + case (guard__h343939) 2'b0: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 = - _theResult___fst_exp__h352073; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 = + _theResult___fst_exp__h352040; 2'b01, 2'b10, 2'b11: - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 = - _theResult___exp__h352589; + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 = + _theResult___exp__h352556; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34 or - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35 or + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 or + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h352073) + _theResult___fst_exp__h352040) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352667 = - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q34; + _theResult___fst_exp__h352634 = + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34; 3'd1: - _theResult___fst_exp__h352667 = - CASE_guard43972_0b0_theResult___fst_exp52073_0_ETC__q35; + _theResult___fst_exp__h352634 = + CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35; 3'd2: - _theResult___fst_exp__h352667 = + _theResult___fst_exp__h352634 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352667 = + _theResult___fst_exp__h352634 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352667 = _theResult___fst_exp__h352073; - default: _theResult___fst_exp__h352667 = 8'd0; + 3'd4: _theResult___fst_exp__h352634 = _theResult___fst_exp__h352040; + default: _theResult___fst_exp__h352634 = 8'd0; endcase end - always@(guard__h361611 or - _theResult___fst_exp__h369839 or - out_exp__h370358 or _theResult___exp__h370355) + always@(guard__h361578 or + _theResult___fst_exp__h369806 or + out_exp__h370325 or _theResult___exp__h370322) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - _theResult___fst_exp__h369839; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + _theResult___fst_exp__h369806; 2'b10: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - out_exp__h370358; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + out_exp__h370325; 2'b11: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 = - _theResult___exp__h370355; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 = + _theResult___exp__h370322; endcase end - always@(guard__h361611 or - _theResult___fst_exp__h369839 or _theResult___exp__h370355) + always@(guard__h361578 or + _theResult___fst_exp__h369806 or _theResult___exp__h370322) begin - case (guard__h361611) + case (guard__h361578) 2'b0: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 = - _theResult___fst_exp__h369839; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 = + _theResult___fst_exp__h369806; 2'b01, 2'b10, 2'b11: - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 = - _theResult___exp__h370355; + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 = + _theResult___exp__h370322; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40 or - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41 or + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 or + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369839) + _theResult___fst_exp__h369806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h370433 = - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q40; + _theResult___fst_exp__h370400 = + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40; 3'd1: - _theResult___fst_exp__h370433 = - CASE_guard61611_0b0_theResult___fst_exp69839_0_ETC__q41; + _theResult___fst_exp__h370400 = + CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41; 3'd2: - _theResult___fst_exp__h370433 = + _theResult___fst_exp__h370400 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h370433 = + _theResult___fst_exp__h370400 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h370433 = _theResult___fst_exp__h369839; - default: _theResult___fst_exp__h370433 = 8'd0; + 3'd4: _theResult___fst_exp__h370400 = _theResult___fst_exp__h369806; + default: _theResult___fst_exp__h370400 = 8'd0; endcase end - always@(guard__h370447 or - _theResult___fst_exp__h378524 or - out_exp__h378994 or _theResult___exp__h378991) + always@(guard__h370414 or + _theResult___fst_exp__h378491 or + out_exp__h378961 or _theResult___exp__h378958) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - _theResult___fst_exp__h378524; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + _theResult___fst_exp__h378491; 2'b10: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - out_exp__h378994; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + out_exp__h378961; 2'b11: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 = - _theResult___exp__h378991; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 = + _theResult___exp__h378958; endcase end - always@(guard__h370447 or - _theResult___fst_exp__h378524 or _theResult___exp__h378991) + always@(guard__h370414 or + _theResult___fst_exp__h378491 or _theResult___exp__h378958) begin - case (guard__h370447) + case (guard__h370414) 2'b0: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 = - _theResult___fst_exp__h378524; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 = + _theResult___fst_exp__h378491; 2'b01, 2'b10, 2'b11: - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 = - _theResult___exp__h378991; + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 = + _theResult___exp__h378958; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45 or - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46 or + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 or + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h378524) + _theResult___fst_exp__h378491) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h379069 = - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q45; + _theResult___fst_exp__h379036 = + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45; 3'd1: - _theResult___fst_exp__h379069 = - CASE_guard70447_0b0_theResult___fst_exp78524_0_ETC__q46; + _theResult___fst_exp__h379036 = + CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46; 3'd2: - _theResult___fst_exp__h379069 = + _theResult___fst_exp__h379036 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h379069 = + _theResult___fst_exp__h379036 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h379069 = _theResult___fst_exp__h378524; - default: _theResult___fst_exp__h379069 = 8'd0; + 3'd4: _theResult___fst_exp__h379036 = _theResult___fst_exp__h378491; + default: _theResult___fst_exp__h379036 = 8'd0; endcase end - always@(guard__h352681 or - _theResult___snd__h360680 or - out_sfd__h361175 or _theResult___sfd__h361172) + always@(guard__h352648 or + _theResult___snd__h360647 or + out_sfd__h361142 or _theResult___sfd__h361139) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - _theResult___snd__h360680[56:34]; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + _theResult___snd__h360647[56:34]; 2'b10: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - out_sfd__h361175; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + out_sfd__h361142; 2'b11: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 = - _theResult___sfd__h361172; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 = + _theResult___sfd__h361139; endcase end - always@(guard__h352681 or - _theResult___snd__h360680 or _theResult___sfd__h361172) + always@(guard__h352648 or + _theResult___snd__h360647 or _theResult___sfd__h361139) begin - case (guard__h352681) + case (guard__h352648) 2'b0: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 = - _theResult___snd__h360680[56:34]; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 = + _theResult___snd__h360647[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 = - _theResult___sfd__h361172; + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 = + _theResult___sfd__h361139; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47 or - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48 or + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 or + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360680) + _theResult___snd__h360647) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h361250 = - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q47; + _theResult___fst_sfd__h361217 = + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h361250 = - CASE_guard52681_0b0_theResult___snd60680_BITS__ETC__q48; + _theResult___fst_sfd__h361217 = + CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h361250 = + _theResult___fst_sfd__h361217 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h361250 = + _theResult___fst_sfd__h361217 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h361250 = _theResult___snd__h360680[56:34]; - default: _theResult___fst_sfd__h361250 = 23'd0; + 3'd4: _theResult___fst_sfd__h361217 = _theResult___snd__h360647[56:34]; + default: _theResult___fst_sfd__h361217 = 23'd0; endcase end - always@(guard__h343972 or - sfdin__h352067 or out_sfd__h352593 or _theResult___sfd__h352590) + always@(guard__h343939 or + sfdin__h352034 or out_sfd__h352560 or _theResult___sfd__h352557) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - sfdin__h352067[56:34]; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + sfdin__h352034[56:34]; 2'b10: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h352593; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h352560; 2'b11: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h352590; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h352557; endcase end - always@(guard__h343972 or sfdin__h352067 or _theResult___sfd__h352590) + always@(guard__h343939 or sfdin__h352034 or _theResult___sfd__h352557) begin - case (guard__h343972) + case (guard__h343939) 2'b0: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 = - sfdin__h352067[56:34]; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 = + sfdin__h352034[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h352590; + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h352557; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49 or - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50 or + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 or + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h352067) + sfdin__h352034) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352668 = - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h352635 = + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h352668 = - CASE_guard43972_0b0_sfdin52067_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h352635 = + CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h352668 = + _theResult___fst_sfd__h352635 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352668 = + _theResult___fst_sfd__h352635 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352668 = sfdin__h352067[56:34]; - default: _theResult___fst_sfd__h352668 = 23'd0; + 3'd4: _theResult___fst_sfd__h352635 = sfdin__h352034[56:34]; + default: _theResult___fst_sfd__h352635 = 23'd0; endcase end - always@(guard__h361611 or - sfdin__h369833 or out_sfd__h370359 or _theResult___sfd__h370356) + always@(guard__h361578 or + sfdin__h369800 or out_sfd__h370326 or _theResult___sfd__h370323) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - sfdin__h369833[56:34]; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + sfdin__h369800[56:34]; 2'b10: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h370359; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h370326; 2'b11: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h370356; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h370323; endcase end - always@(guard__h361611 or sfdin__h369833 or _theResult___sfd__h370356) + always@(guard__h361578 or sfdin__h369800 or _theResult___sfd__h370323) begin - case (guard__h361611) + case (guard__h361578) 2'b0: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 = - sfdin__h369833[56:34]; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 = + sfdin__h369800[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h370356; + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h370323; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51 or - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52 or + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 or + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369833) + sfdin__h369800) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h370434 = - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h370401 = + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h370434 = - CASE_guard61611_0b0_sfdin69833_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h370401 = + CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h370434 = + _theResult___fst_sfd__h370401 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h370434 = + _theResult___fst_sfd__h370401 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h370434 = sfdin__h369833[56:34]; - default: _theResult___fst_sfd__h370434 = 23'd0; + 3'd4: _theResult___fst_sfd__h370401 = sfdin__h369800[56:34]; + default: _theResult___fst_sfd__h370401 = 23'd0; endcase end - always@(guard__h370447 or - _theResult___snd__h378470 or - out_sfd__h378995 or _theResult___sfd__h378992) - begin - case (guard__h370447) - 2'b0, 2'b01: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - _theResult___snd__h378470[56:34]; - 2'b10: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - out_sfd__h378995; - 2'b11: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 = - _theResult___sfd__h378992; - endcase - end - always@(guard__h370447 or - _theResult___snd__h378470 or _theResult___sfd__h378992) - begin - case (guard__h370447) - 2'b0: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 = - _theResult___snd__h378470[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 = - _theResult___sfd__h378992; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53 or - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h378470) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h379070 = - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q53; - 3'd1: - _theResult___fst_sfd__h379070 = - CASE_guard70447_0b0_theResult___snd78470_BITS__ETC__q54; - 3'd2: - _theResult___fst_sfd__h379070 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; - 3'd3: - _theResult___fst_sfd__h379070 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h379070 = _theResult___snd__h378470[56:34]; - default: _theResult___fst_sfd__h379070 = 23'd0; - endcase - end - always@(guard__h343972 or + always@(guard__h343939 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01, 2'b10: - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h343972 == 2'b11 && + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + guard__h343939 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h343972) + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or + guard__h343939) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43972_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343972 == 2'b0) ? + (guard__h343939 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343972 == 2'b01 || guard__h343972 == 2'b10 || - guard__h343972 == 2'b11) && + (guard__h343939 == 2'b01 || guard__h343939 == 2'b10 || + guard__h343939 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -33199,34 +33145,86 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343972 or + always@(guard__h370414 or + _theResult___snd__h378437 or + out_sfd__h378962 or _theResult___sfd__h378959) + begin + case (guard__h370414) + 2'b0, 2'b01: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + _theResult___snd__h378437[56:34]; + 2'b10: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + out_sfd__h378962; + 2'b11: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 = + _theResult___sfd__h378959; + endcase + end + always@(guard__h370414 or + _theResult___snd__h378437 or _theResult___sfd__h378959) + begin + case (guard__h370414) + 2'b0: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 = + _theResult___snd__h378437[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 = + _theResult___sfd__h378959; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 or + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or + _theResult___snd__h378437) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h379037 = + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54; + 3'd1: + _theResult___fst_sfd__h379037 = + CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55; + 3'd2: + _theResult___fst_sfd__h379037 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; + 3'd3: + _theResult___fst_sfd__h379037 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; + 3'd4: _theResult___fst_sfd__h379037 = _theResult___snd__h378437[56:34]; + default: _theResult___fst_sfd__h379037 = 23'd0; + endcase + end + always@(guard__h343939 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343972) + case (guard__h343939) 2'b0, 2'b01, 2'b10: - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h343972 != 2'b11 || + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h343939 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h343972) + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h343939) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43972_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343972 == 2'b0) ? + (guard__h343939 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343972 != 2'b01 && guard__h343972 != 2'b10 && - guard__h343972 != 2'b11 || + guard__h343939 != 2'b01 && guard__h343939 != 2'b10 && + guard__h343939 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -33237,34 +33235,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352681 or + always@(guard__h352648 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01, 2'b10: - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h352681 == 2'b11 && + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h352648 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h352681) + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h352648) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52681_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352681 == 2'b0) ? + (guard__h352648 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352681 == 2'b01 || guard__h352681 == 2'b10 || - guard__h352681 == 2'b11) && + (guard__h352648 == 2'b01 || guard__h352648 == 2'b10 || + guard__h352648 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -33275,34 +33273,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352681 or + always@(guard__h352648 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352681) + case (guard__h352648) 2'b0, 2'b01, 2'b10: - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h352681 != 2'b11 || + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h352648 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h352681) + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h352648) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52681_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352681 == 2'b0) ? + (guard__h352648 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352681 != 2'b01 && guard__h352681 != 2'b10 && - guard__h352681 != 2'b11 || + guard__h352648 != 2'b01 && guard__h352648 != 2'b10 && + guard__h352648 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -33313,34 +33311,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h361611 or + always@(guard__h361578 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01, 2'b10: - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h361611 == 2'b11 && + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h361578 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h361611) + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h361578) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard61611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h361611 == 2'b0) ? + (guard__h361578 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h361611 == 2'b01 || guard__h361611 == 2'b10 || - guard__h361611 == 2'b11) && + (guard__h361578 == 2'b01 || guard__h361578 == 2'b10 || + guard__h361578 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -33351,34 +33349,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h361611 or + always@(guard__h361578 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h361611) + case (guard__h361578) 2'b0, 2'b01, 2'b10: - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h361611 != 2'b11 || + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h361578 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h361611) + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h361578) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard61611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h361611 == 2'b0) ? + (guard__h361578 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h361611 != 2'b01 && guard__h361611 != 2'b10 && - guard__h361611 != 2'b11 || + guard__h361578 != 2'b01 && guard__h361578 != 2'b10 && + guard__h361578 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -33389,34 +33387,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h370447 or + always@(guard__h370414 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01, 2'b10: - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h370447 == 2'b11 && + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h370414 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h370447) + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h370414) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard70447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h370447 == 2'b0) ? + (guard__h370414 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h370447 == 2'b01 || guard__h370447 == 2'b10 || - guard__h370447 == 2'b11) && + (guard__h370414 == 2'b01 || guard__h370414 == 2'b10 || + guard__h370414 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -33427,34 +33425,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h370447 or + always@(guard__h370414 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h370447) + case (guard__h370414) 2'b0, 2'b01, 2'b10: - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h370447 != 2'b11 || + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h370414 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h370447) + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h370414) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard70447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h370447 == 2'b0) ? + (guard__h370414 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h370447 != 2'b01 && guard__h370447 != 2'b10 && - guard__h370447 != 2'b11 || + guard__h370414 != 2'b01 && guard__h370414 != 2'b10 && + guard__h370414 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -33491,446 +33489,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h398378 or - _theResult___fst_exp__h406426 or - out_exp__h406871 or _theResult___exp__h406868) + always@(guard__h398345 or + _theResult___fst_exp__h406393 or + out_exp__h406838 or _theResult___exp__h406835) begin - case (guard__h398378) + case (guard__h398345) 2'b0, 2'b01: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - _theResult___fst_exp__h406426; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + _theResult___fst_exp__h406393; 2'b10: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - out_exp__h406871; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + out_exp__h406838; 2'b11: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 = - _theResult___exp__h406868; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 = + _theResult___exp__h406835; endcase end - always@(guard__h398378 or - _theResult___fst_exp__h406426 or _theResult___exp__h406868) + always@(guard__h398345 or + _theResult___fst_exp__h406393 or _theResult___exp__h406835) begin - case (guard__h398378) + case (guard__h398345) 2'b0: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 = - _theResult___fst_exp__h406426; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 = + _theResult___fst_exp__h406393; 2'b01, 2'b10, 2'b11: - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 = - _theResult___exp__h406868; + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 = + _theResult___exp__h406835; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67 or - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68 or + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 or + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h406426) + _theResult___fst_exp__h406393) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406946 = - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q67; + _theResult___fst_exp__h406913 = + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67; 3'd1: - _theResult___fst_exp__h406946 = - CASE_guard98378_0b0_theResult___fst_exp06426_0_ETC__q68; + _theResult___fst_exp__h406913 = + CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68; 3'd2: - _theResult___fst_exp__h406946 = + _theResult___fst_exp__h406913 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406946 = + _theResult___fst_exp__h406913 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406946 = _theResult___fst_exp__h406426; - default: _theResult___fst_exp__h406946 = 8'd0; + 3'd4: _theResult___fst_exp__h406913 = _theResult___fst_exp__h406393; + default: _theResult___fst_exp__h406913 = 8'd0; endcase end - always@(guard__h389671 or - _theResult___fst_exp__h397770 or - out_exp__h398289 or _theResult___exp__h398286) + always@(guard__h389638 or + _theResult___fst_exp__h397737 or + out_exp__h398256 or _theResult___exp__h398253) begin - case (guard__h389671) + case (guard__h389638) 2'b0, 2'b01: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - _theResult___fst_exp__h397770; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + _theResult___fst_exp__h397737; 2'b10: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - out_exp__h398289; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + out_exp__h398256; 2'b11: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 = - _theResult___exp__h398286; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 = + _theResult___exp__h398253; endcase end - always@(guard__h389671 or - _theResult___fst_exp__h397770 or _theResult___exp__h398286) + always@(guard__h389638 or + _theResult___fst_exp__h397737 or _theResult___exp__h398253) begin - case (guard__h389671) + case (guard__h389638) 2'b0: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 = - _theResult___fst_exp__h397770; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 = + _theResult___fst_exp__h397737; 2'b01, 2'b10, 2'b11: - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 = - _theResult___exp__h398286; + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 = + _theResult___exp__h398253; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69 or - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70 or + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 or + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397770) + _theResult___fst_exp__h397737) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h398364 = - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q69; + _theResult___fst_exp__h398331 = + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69; 3'd1: - _theResult___fst_exp__h398364 = - CASE_guard89671_0b0_theResult___fst_exp97770_0_ETC__q70; + _theResult___fst_exp__h398331 = + CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70; 3'd2: - _theResult___fst_exp__h398364 = + _theResult___fst_exp__h398331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h398364 = + _theResult___fst_exp__h398331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h398364 = _theResult___fst_exp__h397770; - default: _theResult___fst_exp__h398364 = 8'd0; + 3'd4: _theResult___fst_exp__h398331 = _theResult___fst_exp__h397737; + default: _theResult___fst_exp__h398331 = 8'd0; endcase end - always@(guard__h407308 or - _theResult___fst_exp__h415536 or - out_exp__h416055 or _theResult___exp__h416052) + always@(guard__h407275 or + _theResult___fst_exp__h415503 or + out_exp__h416022 or _theResult___exp__h416019) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - _theResult___fst_exp__h415536; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + _theResult___fst_exp__h415503; 2'b10: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - out_exp__h416055; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + out_exp__h416022; 2'b11: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 = - _theResult___exp__h416052; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 = + _theResult___exp__h416019; endcase end - always@(guard__h407308 or - _theResult___fst_exp__h415536 or _theResult___exp__h416052) + always@(guard__h407275 or + _theResult___fst_exp__h415503 or _theResult___exp__h416019) begin - case (guard__h407308) + case (guard__h407275) 2'b0: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 = - _theResult___fst_exp__h415536; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 = + _theResult___fst_exp__h415503; 2'b01, 2'b10, 2'b11: - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 = - _theResult___exp__h416052; + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 = + _theResult___exp__h416019; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75 or - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76 or + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 or + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h415536) + _theResult___fst_exp__h415503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h416130 = - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q75; + _theResult___fst_exp__h416097 = + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75; 3'd1: - _theResult___fst_exp__h416130 = - CASE_guard07308_0b0_theResult___fst_exp15536_0_ETC__q76; + _theResult___fst_exp__h416097 = + CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76; 3'd2: - _theResult___fst_exp__h416130 = + _theResult___fst_exp__h416097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h416130 = + _theResult___fst_exp__h416097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h416130 = _theResult___fst_exp__h415536; - default: _theResult___fst_exp__h416130 = 8'd0; + 3'd4: _theResult___fst_exp__h416097 = _theResult___fst_exp__h415503; + default: _theResult___fst_exp__h416097 = 8'd0; endcase end - always@(guard__h416144 or - _theResult___fst_exp__h424221 or - out_exp__h424691 or _theResult___exp__h424688) + always@(guard__h416111 or + _theResult___fst_exp__h424188 or + out_exp__h424658 or _theResult___exp__h424655) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - _theResult___fst_exp__h424221; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + _theResult___fst_exp__h424188; 2'b10: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - out_exp__h424691; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + out_exp__h424658; 2'b11: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 = - _theResult___exp__h424688; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 = + _theResult___exp__h424655; endcase end - always@(guard__h416144 or - _theResult___fst_exp__h424221 or _theResult___exp__h424688) + always@(guard__h416111 or + _theResult___fst_exp__h424188 or _theResult___exp__h424655) begin - case (guard__h416144) + case (guard__h416111) 2'b0: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 = - _theResult___fst_exp__h424221; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 = + _theResult___fst_exp__h424188; 2'b01, 2'b10, 2'b11: - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 = - _theResult___exp__h424688; + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 = + _theResult___exp__h424655; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80 or - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81 or + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 or + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h424221) + _theResult___fst_exp__h424188) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424766 = - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q80; + _theResult___fst_exp__h424733 = + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80; 3'd1: - _theResult___fst_exp__h424766 = - CASE_guard16144_0b0_theResult___fst_exp24221_0_ETC__q81; + _theResult___fst_exp__h424733 = + CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81; 3'd2: - _theResult___fst_exp__h424766 = + _theResult___fst_exp__h424733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424766 = + _theResult___fst_exp__h424733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424766 = _theResult___fst_exp__h424221; - default: _theResult___fst_exp__h424766 = 8'd0; + 3'd4: _theResult___fst_exp__h424733 = _theResult___fst_exp__h424188; + default: _theResult___fst_exp__h424733 = 8'd0; endcase end - always@(guard__h389671 or - sfdin__h397764 or out_sfd__h398290 or _theResult___sfd__h398287) + always@(guard__h398345 or + _theResult___snd__h406344 or + out_sfd__h406839 or _theResult___sfd__h406836) begin - case (guard__h389671) + case (guard__h398345) 2'b0, 2'b01: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - sfdin__h397764[56:34]; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + _theResult___snd__h406344[56:34]; 2'b10: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h398290; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + out_sfd__h406839; 2'b11: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h398287; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 = + _theResult___sfd__h406836; endcase end - always@(guard__h389671 or sfdin__h397764 or _theResult___sfd__h398287) + always@(guard__h398345 or + _theResult___snd__h406344 or _theResult___sfd__h406836) begin - case (guard__h389671) + case (guard__h398345) 2'b0: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 = - sfdin__h397764[56:34]; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 = + _theResult___snd__h406344[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h398287; + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 = + _theResult___sfd__h406836; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82 or - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397764) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h398365 = - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h398365 = - CASE_guard89671_0b0_sfdin97764_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h398365 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; - 3'd3: - _theResult___fst_sfd__h398365 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h398365 = sfdin__h397764[56:34]; - default: _theResult___fst_sfd__h398365 = 23'd0; - endcase - end - always@(guard__h398378 or - _theResult___snd__h406377 or - out_sfd__h406872 or _theResult___sfd__h406869) - begin - case (guard__h398378) - 2'b0, 2'b01: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - _theResult___snd__h406377[56:34]; - 2'b10: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - out_sfd__h406872; - 2'b11: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 = - _theResult___sfd__h406869; - endcase - end - always@(guard__h398378 or - _theResult___snd__h406377 or _theResult___sfd__h406869) - begin - case (guard__h398378) - 2'b0: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 = - _theResult___snd__h406377[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 = - _theResult___sfd__h406869; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84 or - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85 or + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 or + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h406377) + _theResult___snd__h406344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406947 = - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q84; + _theResult___fst_sfd__h406914 = + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h406947 = - CASE_guard98378_0b0_theResult___snd06377_BITS__ETC__q85; + _theResult___fst_sfd__h406914 = + CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h406947 = + _theResult___fst_sfd__h406914 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406947 = + _theResult___fst_sfd__h406914 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406947 = _theResult___snd__h406377[56:34]; - default: _theResult___fst_sfd__h406947 = 23'd0; + 3'd4: _theResult___fst_sfd__h406914 = _theResult___snd__h406344[56:34]; + default: _theResult___fst_sfd__h406914 = 23'd0; endcase end - always@(guard__h407308 or - sfdin__h415530 or out_sfd__h416056 or _theResult___sfd__h416053) + always@(guard__h389638 or + sfdin__h397731 or out_sfd__h398257 or _theResult___sfd__h398254) begin - case (guard__h407308) + case (guard__h389638) 2'b0, 2'b01: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - sfdin__h415530[56:34]; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + sfdin__h397731[56:34]; 2'b10: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h416056; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h398257; 2'b11: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h416053; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h398254; endcase end - always@(guard__h407308 or sfdin__h415530 or _theResult___sfd__h416053) + always@(guard__h389638 or sfdin__h397731 or _theResult___sfd__h398254) begin - case (guard__h407308) + case (guard__h389638) 2'b0: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 = - sfdin__h415530[56:34]; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 = + sfdin__h397731[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h416053; + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h398254; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86 or - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87 or + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 or + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or + sfdin__h397731) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h398332 = + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h398332 = + CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h398332 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; + 3'd3: + _theResult___fst_sfd__h398332 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; + 3'd4: _theResult___fst_sfd__h398332 = sfdin__h397731[56:34]; + default: _theResult___fst_sfd__h398332 = 23'd0; + endcase + end + always@(guard__h407275 or + sfdin__h415497 or out_sfd__h416023 or _theResult___sfd__h416020) + begin + case (guard__h407275) + 2'b0, 2'b01: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + sfdin__h415497[56:34]; + 2'b10: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h416023; + 2'b11: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h416020; + endcase + end + always@(guard__h407275 or sfdin__h415497 or _theResult___sfd__h416020) + begin + case (guard__h407275) + 2'b0: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 = + sfdin__h415497[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h416020; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 or + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h415530) + sfdin__h415497) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h416131 = - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h416098 = + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h416131 = - CASE_guard07308_0b0_sfdin15530_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h416098 = + CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h416131 = + _theResult___fst_sfd__h416098 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h416131 = + _theResult___fst_sfd__h416098 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h416131 = sfdin__h415530[56:34]; - default: _theResult___fst_sfd__h416131 = 23'd0; + 3'd4: _theResult___fst_sfd__h416098 = sfdin__h415497[56:34]; + default: _theResult___fst_sfd__h416098 = 23'd0; endcase end - always@(guard__h416144 or - _theResult___snd__h424167 or - out_sfd__h424692 or _theResult___sfd__h424689) + always@(guard__h416111 or + _theResult___snd__h424134 or + out_sfd__h424659 or _theResult___sfd__h424656) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - _theResult___snd__h424167[56:34]; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + _theResult___snd__h424134[56:34]; 2'b10: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - out_sfd__h424692; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + out_sfd__h424659; 2'b11: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 = - _theResult___sfd__h424689; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 = + _theResult___sfd__h424656; endcase end - always@(guard__h416144 or - _theResult___snd__h424167 or _theResult___sfd__h424689) + always@(guard__h416111 or + _theResult___snd__h424134 or _theResult___sfd__h424656) begin - case (guard__h416144) + case (guard__h416111) 2'b0: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 = - _theResult___snd__h424167[56:34]; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 = + _theResult___snd__h424134[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 = - _theResult___sfd__h424689; + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 = + _theResult___sfd__h424656; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88 or - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89 or + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 or + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h424167) + _theResult___snd__h424134) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424767 = - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q88; + _theResult___fst_sfd__h424734 = + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h424767 = - CASE_guard16144_0b0_theResult___snd24167_BITS__ETC__q89; + _theResult___fst_sfd__h424734 = + CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h424767 = + _theResult___fst_sfd__h424734 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424767 = + _theResult___fst_sfd__h424734 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424767 = _theResult___snd__h424167[56:34]; - default: _theResult___fst_sfd__h424767 = 23'd0; + 3'd4: _theResult___fst_sfd__h424734 = _theResult___snd__h424134[56:34]; + default: _theResult___fst_sfd__h424734 = 23'd0; endcase end - always@(guard__h389671 or + always@(guard__h389638 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389671) + case (guard__h389638) 2'b0, 2'b01, 2'b10: - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h389671 == 2'b11 && + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h389638 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h389671) + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h389638) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89671_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389671 == 2'b0) ? + (guard__h389638 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389671 == 2'b01 || guard__h389671 == 2'b10 || - guard__h389671 == 2'b11) && + (guard__h389638 == 2'b01 || guard__h389638 == 2'b10 || + guard__h389638 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -33941,72 +33939,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h398378 or + always@(guard__h389638 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h398378) + case (guard__h389638) 2'b0, 2'b01, 2'b10: - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - guard__h398378 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or - guard__h398378) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard98378_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h398378 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h398378 == 2'b01 || guard__h398378 == 2'b10 || - guard__h398378 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h389671 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h389671) - 2'b0, 2'b01, 2'b10: - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - guard__h389671 != 2'b11 || + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h389638 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or - guard__h389671) + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h389638) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89671_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; + CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389671 == 2'b0) ? + (guard__h389638 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389671 != 2'b01 && guard__h389671 != 2'b10 && - guard__h389671 != 2'b11 || + guard__h389638 != 2'b01 && guard__h389638 != 2'b10 && + guard__h389638 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -34017,34 +33977,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h398378 or + always@(guard__h398345 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h398378) + case (guard__h398345) 2'b0, 2'b01, 2'b10: - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h398345 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h398345) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + (guard__h398345 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + (guard__h398345 == 2'b01 || guard__h398345 == 2'b10 || + guard__h398345 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h398345 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h398345) + 2'b0, 2'b01, 2'b10: + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h398378 != 2'b11 || + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h398345 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h398378) + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h398345) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard98378_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h398378 == 2'b0) ? + (guard__h398345 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h398378 != 2'b01 && guard__h398378 != 2'b10 && - guard__h398378 != 2'b11 || + guard__h398345 != 2'b01 && guard__h398345 != 2'b10 && + guard__h398345 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -34055,34 +34053,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h407308 or + always@(guard__h407275 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01, 2'b10: - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h407308 == 2'b11 && + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h407275 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h407308) + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h407275) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard07308_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h407308 == 2'b0) ? + (guard__h407275 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h407308 == 2'b01 || guard__h407308 == 2'b10 || - guard__h407308 == 2'b11) && + (guard__h407275 == 2'b01 || guard__h407275 == 2'b10 || + guard__h407275 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -34093,34 +34091,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h407308 or + always@(guard__h407275 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h407308) + case (guard__h407275) 2'b0, 2'b01, 2'b10: - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h407308 != 2'b11 || + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h407275 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h407308) + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h407275) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard07308_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h407308 == 2'b0) ? + (guard__h407275 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h407308 != 2'b01 && guard__h407308 != 2'b10 && - guard__h407308 != 2'b11 || + guard__h407275 != 2'b01 && guard__h407275 != 2'b10 && + guard__h407275 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -34131,34 +34129,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h416144 or + always@(guard__h416111 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01, 2'b10: - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h416144 == 2'b11 && + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h416111 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h416144) + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h416111) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard16144_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h416144 == 2'b0) ? + (guard__h416111 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h416144 == 2'b01 || guard__h416144 == 2'b10 || - guard__h416144 == 2'b11) && + (guard__h416111 == 2'b01 || guard__h416111 == 2'b10 || + guard__h416111 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -34169,34 +34167,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h416144 or + always@(guard__h416111 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h416144) + case (guard__h416111) 2'b0, 2'b01, 2'b10: - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h416144 != 2'b11 || + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h416111 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h416144) + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h416111) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard16144_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h416144 == 2'b0) ? + (guard__h416111 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h416144 != 2'b01 && guard__h416144 != 2'b10 && - guard__h416144 != 2'b11 || + guard__h416111 != 2'b01 && guard__h416111 != 2'b10 && + guard__h416111 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -34233,484 +34231,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h444073 or - _theResult___fst_exp__h452121 or - out_exp__h452566 or _theResult___exp__h452563) + always@(guard__h444040 or + _theResult___fst_exp__h452088 or + out_exp__h452533 or _theResult___exp__h452530) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - _theResult___fst_exp__h452121; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + _theResult___fst_exp__h452088; 2'b10: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - out_exp__h452566; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + out_exp__h452533; 2'b11: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 = - _theResult___exp__h452563; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 = + _theResult___exp__h452530; endcase end - always@(guard__h444073 or - _theResult___fst_exp__h452121 or _theResult___exp__h452563) + always@(guard__h444040 or + _theResult___fst_exp__h452088 or _theResult___exp__h452530) begin - case (guard__h444073) + case (guard__h444040) 2'b0: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 = - _theResult___fst_exp__h452121; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 = + _theResult___fst_exp__h452088; 2'b01, 2'b10, 2'b11: - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 = - _theResult___exp__h452563; + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 = + _theResult___exp__h452530; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102 or - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103 or + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 or + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h452121) + _theResult___fst_exp__h452088) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h452641 = - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q102; + _theResult___fst_exp__h452608 = + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102; 3'd1: - _theResult___fst_exp__h452641 = - CASE_guard44073_0b0_theResult___fst_exp52121_0_ETC__q103; + _theResult___fst_exp__h452608 = + CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103; 3'd2: - _theResult___fst_exp__h452641 = + _theResult___fst_exp__h452608 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h452641 = + _theResult___fst_exp__h452608 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h452641 = _theResult___fst_exp__h452121; - default: _theResult___fst_exp__h452641 = 8'd0; + 3'd4: _theResult___fst_exp__h452608 = _theResult___fst_exp__h452088; + default: _theResult___fst_exp__h452608 = 8'd0; endcase end - always@(guard__h435366 or - _theResult___fst_exp__h443465 or - out_exp__h443984 or _theResult___exp__h443981) + always@(guard__h435333 or + _theResult___fst_exp__h443432 or + out_exp__h443951 or _theResult___exp__h443948) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - _theResult___fst_exp__h443465; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + _theResult___fst_exp__h443432; 2'b10: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - out_exp__h443984; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + out_exp__h443951; 2'b11: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 = - _theResult___exp__h443981; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 = + _theResult___exp__h443948; endcase end - always@(guard__h435366 or - _theResult___fst_exp__h443465 or _theResult___exp__h443981) + always@(guard__h435333 or + _theResult___fst_exp__h443432 or _theResult___exp__h443948) begin - case (guard__h435366) + case (guard__h435333) 2'b0: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 = - _theResult___fst_exp__h443465; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 = + _theResult___fst_exp__h443432; 2'b01, 2'b10, 2'b11: - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 = - _theResult___exp__h443981; + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 = + _theResult___exp__h443948; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104 or - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105 or + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 or + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h443465) + _theResult___fst_exp__h443432) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h444059 = - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q104; + _theResult___fst_exp__h444026 = + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104; 3'd1: - _theResult___fst_exp__h444059 = - CASE_guard35366_0b0_theResult___fst_exp43465_0_ETC__q105; + _theResult___fst_exp__h444026 = + CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105; 3'd2: - _theResult___fst_exp__h444059 = + _theResult___fst_exp__h444026 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h444059 = + _theResult___fst_exp__h444026 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h444059 = _theResult___fst_exp__h443465; - default: _theResult___fst_exp__h444059 = 8'd0; + 3'd4: _theResult___fst_exp__h444026 = _theResult___fst_exp__h443432; + default: _theResult___fst_exp__h444026 = 8'd0; endcase end - always@(guard__h453003 or - _theResult___fst_exp__h461231 or - out_exp__h461750 or _theResult___exp__h461747) + always@(guard__h452970 or + _theResult___fst_exp__h461198 or + out_exp__h461717 or _theResult___exp__h461714) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - _theResult___fst_exp__h461231; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + _theResult___fst_exp__h461198; 2'b10: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - out_exp__h461750; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + out_exp__h461717; 2'b11: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 = - _theResult___exp__h461747; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 = + _theResult___exp__h461714; endcase end - always@(guard__h453003 or - _theResult___fst_exp__h461231 or _theResult___exp__h461747) + always@(guard__h452970 or + _theResult___fst_exp__h461198 or _theResult___exp__h461714) begin - case (guard__h453003) + case (guard__h452970) 2'b0: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 = - _theResult___fst_exp__h461231; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 = + _theResult___fst_exp__h461198; 2'b01, 2'b10, 2'b11: - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 = - _theResult___exp__h461747; + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 = + _theResult___exp__h461714; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110 or - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111 or + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 or + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h461231) + _theResult___fst_exp__h461198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461825 = - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q110; + _theResult___fst_exp__h461792 = + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110; 3'd1: - _theResult___fst_exp__h461825 = - CASE_guard53003_0b0_theResult___fst_exp61231_0_ETC__q111; + _theResult___fst_exp__h461792 = + CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111; 3'd2: - _theResult___fst_exp__h461825 = + _theResult___fst_exp__h461792 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461825 = + _theResult___fst_exp__h461792 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461825 = _theResult___fst_exp__h461231; - default: _theResult___fst_exp__h461825 = 8'd0; + 3'd4: _theResult___fst_exp__h461792 = _theResult___fst_exp__h461198; + default: _theResult___fst_exp__h461792 = 8'd0; endcase end - always@(guard__h461839 or - _theResult___fst_exp__h469916 or - out_exp__h470386 or _theResult___exp__h470383) + always@(guard__h461806 or + _theResult___fst_exp__h469883 or + out_exp__h470353 or _theResult___exp__h470350) begin - case (guard__h461839) + case (guard__h461806) 2'b0, 2'b01: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - _theResult___fst_exp__h469916; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + _theResult___fst_exp__h469883; 2'b10: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - out_exp__h470386; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + out_exp__h470353; 2'b11: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 = - _theResult___exp__h470383; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 = + _theResult___exp__h470350; endcase end - always@(guard__h461839 or - _theResult___fst_exp__h469916 or _theResult___exp__h470383) + always@(guard__h461806 or + _theResult___fst_exp__h469883 or _theResult___exp__h470350) begin - case (guard__h461839) + case (guard__h461806) 2'b0: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 = - _theResult___fst_exp__h469916; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 = + _theResult___fst_exp__h469883; 2'b01, 2'b10, 2'b11: - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 = - _theResult___exp__h470383; + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 = + _theResult___exp__h470350; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115 or - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116 or + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 or + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469916) + _theResult___fst_exp__h469883) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h470461 = - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q115; + _theResult___fst_exp__h470428 = + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115; 3'd1: - _theResult___fst_exp__h470461 = - CASE_guard61839_0b0_theResult___fst_exp69916_0_ETC__q116; + _theResult___fst_exp__h470428 = + CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116; 3'd2: - _theResult___fst_exp__h470461 = + _theResult___fst_exp__h470428 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h470461 = + _theResult___fst_exp__h470428 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h470461 = _theResult___fst_exp__h469916; - default: _theResult___fst_exp__h470461 = 8'd0; + 3'd4: _theResult___fst_exp__h470428 = _theResult___fst_exp__h469883; + default: _theResult___fst_exp__h470428 = 8'd0; endcase end - always@(guard__h444073 or - _theResult___snd__h452072 or - out_sfd__h452567 or _theResult___sfd__h452564) + always@(guard__h444040 or + _theResult___snd__h452039 or + out_sfd__h452534 or _theResult___sfd__h452531) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - _theResult___snd__h452072[56:34]; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + _theResult___snd__h452039[56:34]; 2'b10: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - out_sfd__h452567; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + out_sfd__h452534; 2'b11: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 = - _theResult___sfd__h452564; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 = + _theResult___sfd__h452531; endcase end - always@(guard__h444073 or - _theResult___snd__h452072 or _theResult___sfd__h452564) + always@(guard__h444040 or + _theResult___snd__h452039 or _theResult___sfd__h452531) begin - case (guard__h444073) + case (guard__h444040) 2'b0: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 = - _theResult___snd__h452072[56:34]; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 = + _theResult___snd__h452039[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 = - _theResult___sfd__h452564; + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 = + _theResult___sfd__h452531; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117 or - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118 or + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 or + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h452072) + _theResult___snd__h452039) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h452642 = - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q117; + _theResult___fst_sfd__h452609 = + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h452642 = - CASE_guard44073_0b0_theResult___snd52072_BITS__ETC__q118; + _theResult___fst_sfd__h452609 = + CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h452642 = + _theResult___fst_sfd__h452609 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h452642 = + _theResult___fst_sfd__h452609 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h452642 = _theResult___snd__h452072[56:34]; - default: _theResult___fst_sfd__h452642 = 23'd0; + 3'd4: _theResult___fst_sfd__h452609 = _theResult___snd__h452039[56:34]; + default: _theResult___fst_sfd__h452609 = 23'd0; endcase end - always@(guard__h435366 or - sfdin__h443459 or out_sfd__h443985 or _theResult___sfd__h443982) + always@(guard__h435333 or + sfdin__h443426 or out_sfd__h443952 or _theResult___sfd__h443949) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - sfdin__h443459[56:34]; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + sfdin__h443426[56:34]; 2'b10: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h443985; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h443952; 2'b11: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h443982; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h443949; endcase end - always@(guard__h435366 or sfdin__h443459 or _theResult___sfd__h443982) + always@(guard__h435333 or sfdin__h443426 or _theResult___sfd__h443949) begin - case (guard__h435366) + case (guard__h435333) 2'b0: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 = - sfdin__h443459[56:34]; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 = + sfdin__h443426[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h443982; + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h443949; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119 or - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120 or + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 or + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h443459) + sfdin__h443426) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h444060 = - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h444027 = + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h444060 = - CASE_guard35366_0b0_sfdin43459_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h444027 = + CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h444060 = + _theResult___fst_sfd__h444027 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h444060 = + _theResult___fst_sfd__h444027 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h444060 = sfdin__h443459[56:34]; - default: _theResult___fst_sfd__h444060 = 23'd0; + 3'd4: _theResult___fst_sfd__h444027 = sfdin__h443426[56:34]; + default: _theResult___fst_sfd__h444027 = 23'd0; endcase end - always@(guard__h453003 or - sfdin__h461225 or out_sfd__h461751 or _theResult___sfd__h461748) + always@(guard__h452970 or + sfdin__h461192 or out_sfd__h461718 or _theResult___sfd__h461715) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - sfdin__h461225[56:34]; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + sfdin__h461192[56:34]; 2'b10: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h461751; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h461718; 2'b11: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h461748; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h461715; endcase end - always@(guard__h453003 or sfdin__h461225 or _theResult___sfd__h461748) + always@(guard__h452970 or sfdin__h461192 or _theResult___sfd__h461715) begin - case (guard__h453003) + case (guard__h452970) 2'b0: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 = - sfdin__h461225[56:34]; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 = + sfdin__h461192[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h461748; + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h461715; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121 or - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122 or + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 or + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h461225) + sfdin__h461192) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461826 = - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h461793 = + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h461826 = - CASE_guard53003_0b0_sfdin61225_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h461793 = + CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h461826 = + _theResult___fst_sfd__h461793 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461826 = + _theResult___fst_sfd__h461793 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461826 = sfdin__h461225[56:34]; - default: _theResult___fst_sfd__h461826 = 23'd0; + 3'd4: _theResult___fst_sfd__h461793 = sfdin__h461192[56:34]; + default: _theResult___fst_sfd__h461793 = 23'd0; endcase end - always@(guard__h461839 or - _theResult___snd__h469862 or - out_sfd__h470387 or _theResult___sfd__h470384) + always@(guard__h461806 or + _theResult___snd__h469829 or + out_sfd__h470354 or _theResult___sfd__h470351) begin - case (guard__h461839) + case (guard__h461806) 2'b0, 2'b01: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - _theResult___snd__h469862[56:34]; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + _theResult___snd__h469829[56:34]; 2'b10: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - out_sfd__h470387; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + out_sfd__h470354; 2'b11: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 = - _theResult___sfd__h470384; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 = + _theResult___sfd__h470351; endcase end - always@(guard__h461839 or - _theResult___snd__h469862 or _theResult___sfd__h470384) + always@(guard__h461806 or + _theResult___snd__h469829 or _theResult___sfd__h470351) begin - case (guard__h461839) + case (guard__h461806) 2'b0: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 = - _theResult___snd__h469862[56:34]; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 = + _theResult___snd__h469829[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 = - _theResult___sfd__h470384; + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 = + _theResult___sfd__h470351; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123 or - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124 or + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 or + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469862) + _theResult___snd__h469829) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h470462 = - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q123; + _theResult___fst_sfd__h470429 = + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123; 3'd1: - _theResult___fst_sfd__h470462 = - CASE_guard61839_0b0_theResult___snd69862_BITS__ETC__q124; + _theResult___fst_sfd__h470429 = + CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124; 3'd2: - _theResult___fst_sfd__h470462 = + _theResult___fst_sfd__h470429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h470462 = + _theResult___fst_sfd__h470429 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h470462 = _theResult___snd__h469862[56:34]; - default: _theResult___fst_sfd__h470462 = 23'd0; + 3'd4: _theResult___fst_sfd__h470429 = _theResult___snd__h469829[56:34]; + default: _theResult___fst_sfd__h470429 = 23'd0; endcase end - always@(guard__h435366 or + always@(guard__h435333 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h435366) + case (guard__h435333) 2'b0, 2'b01, 2'b10: - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - guard__h435366 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or - guard__h435366) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard35366_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h435366 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h435366 == 2'b01 || guard__h435366 == 2'b10 || - guard__h435366 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h435366 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h435366) - 2'b0, 2'b01, 2'b10: - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h435366 != 2'b11 || + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h435333 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h435366) + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h435333) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard35366_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; + CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h435366 == 2'b0) ? + (guard__h435333 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h435366 != 2'b01 && guard__h435366 != 2'b10 && - guard__h435366 != 2'b11 || + guard__h435333 != 2'b01 && guard__h435333 != 2'b10 && + guard__h435333 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -34721,34 +34681,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h444073 or + always@(guard__h435333 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h444073) + case (guard__h435333) 2'b0, 2'b01, 2'b10: - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = - guard__h444073 == 2'b11 && + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h435333 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or - guard__h444073) + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h435333) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + (guard__h435333 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h435333 == 2'b01 || guard__h435333 == 2'b10 || + guard__h435333 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h444040 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h444040) + 2'b0, 2'b01, 2'b10: + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + guard__h444040 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + guard__h444040) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard44073_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h444073 == 2'b0) ? + (guard__h444040 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h444073 == 2'b01 || guard__h444073 == 2'b10 || - guard__h444073 == 2'b11) && + (guard__h444040 == 2'b01 || guard__h444040 == 2'b10 || + guard__h444040 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -34759,34 +34757,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h444073 or + always@(guard__h444040 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h444073) + case (guard__h444040) 2'b0, 2'b01, 2'b10: - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h444073 != 2'b11 || + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h444040 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h444073) + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h444040) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard44073_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h444073 == 2'b0) ? + (guard__h444040 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h444073 != 2'b01 && guard__h444073 != 2'b10 && - guard__h444073 != 2'b11 || + guard__h444040 != 2'b01 && guard__h444040 != 2'b10 && + guard__h444040 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -34797,34 +34795,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h453003 or + always@(guard__h452970 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h453003) + case (guard__h452970) 2'b0, 2'b01, 2'b10: - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h453003 == 2'b11 && + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h452970 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h453003) + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h452970) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard53003_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h453003 == 2'b0) ? + (guard__h452970 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h453003 == 2'b01 || guard__h453003 == 2'b10 || - guard__h453003 == 2'b11) && + (guard__h452970 == 2'b01 || guard__h452970 == 2'b10 || + guard__h452970 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -34835,72 +34833,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h453003 or + always@(guard__h461806 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h453003) + case (guard__h461806) 2'b0, 2'b01, 2'b10: - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h453003 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h453003) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard53003_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h453003 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h453003 != 2'b01 && guard__h453003 != 2'b10 && - guard__h453003 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h461839 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h461839) - 2'b0, 2'b01, 2'b10: - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h461839 == 2'b11 && + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + guard__h461806 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h461839) + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or + guard__h461806) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61839_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461839 == 2'b0) ? + (guard__h461806 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461839 == 2'b01 || guard__h461839 == 2'b10 || - guard__h461839 == 2'b11) && + (guard__h461806 == 2'b01 || guard__h461806 == 2'b10 || + guard__h461806 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -34911,34 +34871,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461839 or + always@(guard__h452970 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461839) + case (guard__h452970) 2'b0, 2'b01, 2'b10: - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h461839 != 2'b11 || + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + guard__h452970 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h461839) + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or + guard__h452970) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + (guard__h452970 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h452970 != 2'b01 && guard__h452970 != 2'b10 && + guard__h452970 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h461806 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h461806) + 2'b0, 2'b01, 2'b10: + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h461806 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h461806) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61839_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461839 == 2'b0) ? + (guard__h461806 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461839 != 2'b01 && guard__h461839 != 2'b10 && - guard__h461839 != 2'b11 || + guard__h461806 != 2'b01 && guard__h461806 != 2'b10 && + guard__h461806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -34995,28 +34993,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h491444 or - _theResult___fst_exp__h499405 or _theResult___exp__h500060) + always@(guard__h491411 or + _theResult___fst_exp__h499372 or _theResult___exp__h500027) begin - case (guard__h491444) + case (guard__h491411) 2'b0: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143 = - _theResult___fst_exp__h499405; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 = + _theResult___fst_exp__h499372; 2'b01, 2'b10, 2'b11: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143 = - _theResult___exp__h500060; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 = + _theResult___exp__h500027; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h499405 or + _theResult___fst_exp__h499372 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 or - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143) + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = - _theResult___fst_exp__h499405; + _theResult___fst_exp__h499372; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012; @@ -35025,44 +35023,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q143; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 = 11'd0; endcase end - always@(guard__h491444 or - _theResult___fst_exp__h499405 or - out_exp__h500063 or _theResult___exp__h500060) + always@(guard__h491411 or + _theResult___fst_exp__h499372 or + out_exp__h500030 or _theResult___exp__h500027) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - _theResult___fst_exp__h499405; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + _theResult___fst_exp__h499372; 2'b10: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - out_exp__h500063; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + out_exp__h500030; 2'b11: - CASE_guard91444_0b0_theResult___fst_exp99405_0_ETC__q144 = - _theResult___exp__h500060; + CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 = + _theResult___exp__h500027; endcase end - always@(guard__h491444 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h491411 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01, 2'b10: - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard91444_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h491444 == 2'b11 && + CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h491411 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491444) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491411) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35072,12 +35070,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h491444 == 2'b0) ? + (guard__h491411 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h491444 == 2'b01 || guard__h491444 == 2'b10 || - guard__h491444 == 2'b11) && + (guard__h491411 == 2'b01 || guard__h491411 == 2'b10 || + guard__h491411 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35088,23 +35086,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509825 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500723 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509825) + case (guard__h500723) 2'b0, 2'b01, 2'b10: - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09825_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h509825 == 2'b11 && + CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h500723 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509825) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500723) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35114,12 +35112,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h509825 == 2'b0) ? + (guard__h500723 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509825 == 2'b01 || guard__h509825 == 2'b10 || - guard__h509825 == 2'b11) && + (guard__h500723 == 2'b01 || guard__h500723 == 2'b10 || + guard__h500723 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35130,23 +35128,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500756 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500756) + case (guard__h509792) 2'b0, 2'b01, 2'b10: - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00756_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h500756 == 2'b11 && + CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h509792 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500756) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35156,12 +35154,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h500756 == 2'b0) ? + (guard__h509792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500756 == 2'b01 || guard__h500756 == 2'b10 || - guard__h500756 == 2'b11) && + (guard__h509792 == 2'b01 || guard__h509792 == 2'b10 || + guard__h509792 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35172,28 +35170,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h569601 or - _theResult___fst_exp__h577562 or _theResult___exp__h578217) + always@(guard__h569568 or + _theResult___fst_exp__h577529 or _theResult___exp__h578184) begin - case (guard__h569601) + case (guard__h569568) 2'b0: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160 = - _theResult___fst_exp__h577562; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 = + _theResult___fst_exp__h577529; 2'b01, 2'b10, 2'b11: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160 = - _theResult___exp__h578217; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 = + _theResult___exp__h578184; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h577562 or + _theResult___fst_exp__h577529 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 or - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160) + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = - _theResult___fst_exp__h577562; + _theResult___fst_exp__h577529; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727; @@ -35202,42 +35200,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q160; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 = 11'd0; endcase end - always@(guard__h569601 or - _theResult___fst_exp__h577562 or - out_exp__h578220 or _theResult___exp__h578217) + always@(guard__h569568 or + _theResult___fst_exp__h577529 or + out_exp__h578187 or _theResult___exp__h578184) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - _theResult___fst_exp__h577562; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + _theResult___fst_exp__h577529; 2'b10: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - out_exp__h578220; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + out_exp__h578187; 2'b11: - CASE_guard69601_0b0_theResult___fst_exp77562_0_ETC__q161 = - _theResult___exp__h578217; + CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 = + _theResult___exp__h578184; endcase end - always@(guard__h569601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h569601) + case (guard__h578880) 2'b0, 2'b01, 2'b10: - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard69601_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h569601 == 2'b11 && + CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h578880 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35246,12 +35244,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h569601 == 2'b0) ? + (guard__h578880 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h569601 == 2'b01 || guard__h569601 == 2'b10 || - guard__h569601 == 2'b11) && + (guard__h578880 == 2'b01 || guard__h578880 == 2'b10 || + guard__h578880 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35262,21 +35260,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578913) + case (guard__h569568) 2'b0, 2'b01, 2'b10: - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78913_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h578913 == 2'b11 && + CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h569568 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35285,12 +35283,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h578913 == 2'b0) ? + (guard__h569568 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578913 == 2'b01 || guard__h578913 == 2'b10 || - guard__h578913 == 2'b11) && + (guard__h569568 == 2'b01 || guard__h569568 == 2'b10 || + guard__h569568 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35301,21 +35299,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01, 2'b10: - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87982_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h587982 == 2'b11 && + CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h587949 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35324,12 +35322,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h587982 == 2'b0) ? + (guard__h587949 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587982 == 2'b01 || guard__h587982 == 2'b10 || - guard__h587982 == 2'b11) && + (guard__h587949 == 2'b01 || guard__h587949 == 2'b10 || + guard__h587949 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35340,21 +35338,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578913 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578913) + case (guard__h578880) 2'b0, 2'b01, 2'b10: - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78913_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h578913 != 2'b11 || + CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h578880 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578913) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35363,12 +35361,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h578913 == 2'b0) ? + (guard__h578880 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578913 != 2'b01 && guard__h578913 != 2'b10 && - guard__h578913 != 2'b11 || + guard__h578880 != 2'b01 && guard__h578880 != 2'b10 && + guard__h578880 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35379,21 +35377,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587982 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01, 2'b10: - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87982_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h587982 != 2'b11 || + CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h587949 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587982) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35402,12 +35400,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h587982 == 2'b0) ? + (guard__h587949 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587982 != 2'b01 && guard__h587982 != 2'b10 && - guard__h587982 != 2'b11 || + guard__h587949 != 2'b01 && guard__h587949 != 2'b10 && + guard__h587949 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35418,21 +35416,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h569601 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01, 2'b10: - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard69601_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h569601 != 2'b11 || + CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h569568 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569601) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35441,12 +35439,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h569601 == 2'b0) ? + (guard__h569568 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h569601 != 2'b01 && guard__h569601 != 2'b10 && - guard__h569601 != 2'b11 || + guard__h569568 != 2'b01 && guard__h569568 != 2'b10 && + guard__h569568 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35457,28 +35455,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h530297 or - _theResult___fst_exp__h538258 or _theResult___exp__h538913) + always@(guard__h530264 or + _theResult___fst_exp__h538225 or _theResult___exp__h538880) begin - case (guard__h530297) + case (guard__h530264) 2'b0: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183 = - _theResult___fst_exp__h538258; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 = + _theResult___fst_exp__h538225; 2'b01, 2'b10, 2'b11: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183 = - _theResult___exp__h538913; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 = + _theResult___exp__h538880; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h538258 or + _theResult___fst_exp__h538225 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 or - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183) + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = - _theResult___fst_exp__h538258; + _theResult___fst_exp__h538225; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497; @@ -35487,49 +35485,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q183; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 = 11'd0; endcase end - always@(guard__h530297 or - _theResult___fst_exp__h538258 or - out_exp__h538916 or _theResult___exp__h538913) + always@(guard__h530264 or + _theResult___fst_exp__h538225 or + out_exp__h538883 or _theResult___exp__h538880) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - _theResult___fst_exp__h538258; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + _theResult___fst_exp__h538225; 2'b10: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - out_exp__h538916; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + out_exp__h538883; 2'b11: - CASE_guard30297_0b0_theResult___fst_exp38258_0_ETC__q184 = - _theResult___exp__h538913; + CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 = + _theResult___exp__h538880; endcase end - always@(guard__h539609 or - _theResult___fst_exp__h547835 or _theResult___exp__h548564) + always@(guard__h539576 or + _theResult___fst_exp__h547802 or _theResult___exp__h548531) begin - case (guard__h539609) + case (guard__h539576) 2'b0: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185 = - _theResult___fst_exp__h547835; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 = + _theResult___fst_exp__h547802; 2'b01, 2'b10, 2'b11: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185 = - _theResult___exp__h548564; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 = + _theResult___exp__h548531; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547835 or + _theResult___fst_exp__h547802 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 or - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185) + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = - _theResult___fst_exp__h547835; + _theResult___fst_exp__h547802; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535; @@ -35538,49 +35536,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q185; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 = 11'd0; endcase end - always@(guard__h539609 or - _theResult___fst_exp__h547835 or - out_exp__h548567 or _theResult___exp__h548564) + always@(guard__h539576 or + _theResult___fst_exp__h547802 or + out_exp__h548534 or _theResult___exp__h548531) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - _theResult___fst_exp__h547835; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + _theResult___fst_exp__h547802; 2'b10: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - out_exp__h548567; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + out_exp__h548534; 2'b11: - CASE_guard39609_0b0_theResult___fst_exp47835_0_ETC__q186 = - _theResult___exp__h548564; + CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 = + _theResult___exp__h548531; endcase end - always@(guard__h548678 or - _theResult___fst_exp__h556668 or _theResult___exp__h557348) + always@(guard__h548645 or + _theResult___fst_exp__h556635 or _theResult___exp__h557315) begin - case (guard__h548678) + case (guard__h548645) 2'b0: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187 = - _theResult___fst_exp__h556668; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 = + _theResult___fst_exp__h556635; 2'b01, 2'b10, 2'b11: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187 = - _theResult___exp__h557348; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 = + _theResult___exp__h557315; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h556668 or + _theResult___fst_exp__h556635 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 or - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187) + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = - _theResult___fst_exp__h556668; + _theResult___fst_exp__h556635; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566; @@ -35589,100 +35587,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q187; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 = 11'd0; endcase end - always@(guard__h548678 or - _theResult___fst_exp__h556668 or - out_exp__h557351 or _theResult___exp__h557348) + always@(guard__h548645 or + _theResult___fst_exp__h556635 or + out_exp__h557318 or _theResult___exp__h557315) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - _theResult___fst_exp__h556668; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + _theResult___fst_exp__h556635; 2'b10: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - out_exp__h557351; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + out_exp__h557318; 2'b11: - CASE_guard48678_0b0_theResult___fst_exp56668_0_ETC__q188 = - _theResult___exp__h557348; + CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 = + _theResult___exp__h557315; endcase end - always@(guard__h578913 or - _theResult___fst_exp__h587139 or _theResult___exp__h587868) + always@(guard__h587949 or + _theResult___fst_exp__h595939 or _theResult___exp__h596619) begin - case (guard__h578913) + case (guard__h587949) 2'b0: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189 = - _theResult___fst_exp__h587139; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 = + _theResult___fst_exp__h595939; 2'b01, 2'b10, 2'b11: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189 = - _theResult___exp__h587868; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 = + _theResult___exp__h596619; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h587139 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 or - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - _theResult___fst_exp__h587139; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q189; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = - 11'd0; - endcase - end - always@(guard__h578913 or - _theResult___fst_exp__h587139 or - out_exp__h587871 or _theResult___exp__h587868) - begin - case (guard__h578913) - 2'b0, 2'b01: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - _theResult___fst_exp__h587139; - 2'b10: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - out_exp__h587871; - 2'b11: - CASE_guard78913_0b0_theResult___fst_exp87139_0_ETC__q190 = - _theResult___exp__h587868; - endcase - end - always@(guard__h587982 or - _theResult___fst_exp__h595972 or _theResult___exp__h596652) - begin - case (guard__h587982) - 2'b0: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191 = - _theResult___fst_exp__h595972; - 2'b01, 2'b10, 2'b11: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191 = - _theResult___exp__h596652; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595972 or + _theResult___fst_exp__h595939 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 or - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191) + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = - _theResult___fst_exp__h595972; + _theResult___fst_exp__h595939; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796; @@ -35691,44 +35638,95 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q191; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 = 11'd0; endcase end - always@(guard__h587982 or - _theResult___fst_exp__h595972 or - out_exp__h596655 or _theResult___exp__h596652) + always@(guard__h587949 or + _theResult___fst_exp__h595939 or + out_exp__h596622 or _theResult___exp__h596619) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - _theResult___fst_exp__h595972; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + _theResult___fst_exp__h595939; 2'b10: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - out_exp__h596655; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + out_exp__h596622; 2'b11: - CASE_guard87982_0b0_theResult___fst_exp95972_0_ETC__q192 = - _theResult___exp__h596652; + CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 = + _theResult___exp__h596619; endcase end - always@(guard__h530297 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578880 or + _theResult___fst_exp__h587106 or _theResult___exp__h587835) begin - case (guard__h530297) + case (guard__h578880) + 2'b0: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 = + _theResult___fst_exp__h587106; + 2'b01, 2'b10, 2'b11: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 = + _theResult___exp__h587835; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h587106 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 or + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + _theResult___fst_exp__h587106; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 = + 11'd0; + endcase + end + always@(guard__h578880 or + _theResult___fst_exp__h587106 or + out_exp__h587838 or _theResult___exp__h587835) + begin + case (guard__h578880) + 2'b0, 2'b01: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + _theResult___fst_exp__h587106; + 2'b10: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + out_exp__h587838; + 2'b11: + CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 = + _theResult___exp__h587835; + endcase + end + always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h530264) 2'b0, 2'b01, 2'b10: - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard30297_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h530297 == 2'b11 && + CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h530264 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530297) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35738,12 +35736,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h530297 == 2'b0) ? + (guard__h530264 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h530297 == 2'b01 || guard__h530297 == 2'b10 || - guard__h530297 == 2'b11) && + (guard__h530264 == 2'b01 || guard__h530264 == 2'b10 || + guard__h530264 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35754,23 +35752,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h548678 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h548678) + case (guard__h539576) 2'b0, 2'b01, 2'b10: - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard48678_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h548678 == 2'b11 && + CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h539576 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548678) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35780,12 +35778,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h548678 == 2'b0) ? + (guard__h539576 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h548678 == 2'b01 || guard__h548678 == 2'b10 || - guard__h548678 == 2'b11) && + (guard__h539576 == 2'b01 || guard__h539576 == 2'b10 || + guard__h539576 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35796,23 +35794,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h539609 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h539609) + case (guard__h548645) 2'b0, 2'b01, 2'b10: - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard39609_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h539609 == 2'b11 && + CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h548645 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539609) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35822,12 +35820,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h539609 == 2'b0) ? + (guard__h548645 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h539609 == 2'b01 || guard__h539609 == 2'b10 || - guard__h539609 == 2'b11) && + (guard__h548645 == 2'b01 || guard__h548645 == 2'b10 || + guard__h548645 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35838,23 +35836,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h539609 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01, 2'b10: - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard39609_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h539609 != 2'b11 || + CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h539576 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539609) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35864,12 +35862,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h539609 == 2'b0) ? + (guard__h539576 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h539609 != 2'b01 && guard__h539609 != 2'b10 && - guard__h539609 != 2'b11 || + guard__h539576 != 2'b01 && guard__h539576 != 2'b10 && + guard__h539576 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35880,23 +35878,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h548678 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01, 2'b10: - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard48678_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h548678 != 2'b11 || + CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h548645 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548678) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35906,12 +35904,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h548678 == 2'b0) ? + (guard__h548645 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h548678 != 2'b01 && guard__h548678 != 2'b10 && - guard__h548678 != 2'b11 || + guard__h548645 != 2'b01 && guard__h548645 != 2'b10 && + guard__h548645 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35922,23 +35920,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h530297 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01, 2'b10: - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard30297_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h530297 != 2'b11 || + CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h530264 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530297) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35948,12 +35946,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h530297 == 2'b0) ? + (guard__h530264 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h530297 != 2'b01 && guard__h530297 != 2'b10 && - guard__h530297 != 2'b11 || + guard__h530264 != 2'b01 && guard__h530264 != 2'b10 && + guard__h530264 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -35964,28 +35962,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h530297 or - _theResult___snd__h538209 or _theResult___sfd__h538914) + always@(guard__h530264 or + _theResult___snd__h538176 or _theResult___sfd__h538881) begin - case (guard__h530297) + case (guard__h530264) 2'b0: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205 = - _theResult___snd__h538209[56:5]; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 = + _theResult___snd__h538176[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205 = - _theResult___sfd__h538914; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 = + _theResult___sfd__h538881; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h538209 or + _theResult___snd__h538176 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 or - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205) + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = - _theResult___snd__h538209[56:5]; + _theResult___snd__h538176[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592; @@ -35994,48 +35992,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q205; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 = 52'd0; endcase end - always@(guard__h530297 or - _theResult___snd__h538209 or - out_sfd__h538917 or _theResult___sfd__h538914) + always@(guard__h530264 or + _theResult___snd__h538176 or + out_sfd__h538884 or _theResult___sfd__h538881) begin - case (guard__h530297) + case (guard__h530264) 2'b0, 2'b01: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - _theResult___snd__h538209[56:5]; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + _theResult___snd__h538176[56:5]; 2'b10: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - out_sfd__h538917; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + out_sfd__h538884; 2'b11: - CASE_guard30297_0b0_theResult___snd38209_BITS__ETC__q206 = - _theResult___sfd__h538914; + CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 = + _theResult___sfd__h538881; endcase end - always@(guard__h539609 or sfdin__h547829 or _theResult___sfd__h548565) + always@(guard__h539576 or sfdin__h547796 or _theResult___sfd__h548532) begin - case (guard__h539609) + case (guard__h539576) 2'b0: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h547829[56:5]; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h547796[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h548565; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h548532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547829 or + sfdin__h547796 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 or - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207) + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = - sfdin__h547829[56:5]; + sfdin__h547796[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618; @@ -36044,48 +36042,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q207; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 = 52'd0; endcase end - always@(guard__h539609 or - sfdin__h547829 or out_sfd__h548568 or _theResult___sfd__h548565) + always@(guard__h539576 or + sfdin__h547796 or out_sfd__h548535 or _theResult___sfd__h548532) begin - case (guard__h539609) + case (guard__h539576) 2'b0, 2'b01: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h547829[56:5]; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h547796[56:5]; 2'b10: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h548568; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h548535; 2'b11: - CASE_guard39609_0b0_sfdin47829_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h548565; + CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h548532; endcase end - always@(guard__h548678 or - _theResult___snd__h556614 or _theResult___sfd__h557349) + always@(guard__h548645 or + _theResult___snd__h556581 or _theResult___sfd__h557316) begin - case (guard__h548678) + case (guard__h548645) 2'b0: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209 = - _theResult___snd__h556614[56:5]; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 = + _theResult___snd__h556581[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209 = - _theResult___sfd__h557349; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 = + _theResult___sfd__h557316; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h556614 or + _theResult___snd__h556581 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 or - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209) + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = - _theResult___snd__h556614[56:5]; + _theResult___snd__h556581[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637; @@ -36094,49 +36092,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q209; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 = 52'd0; endcase end - always@(guard__h548678 or - _theResult___snd__h556614 or - out_sfd__h557352 or _theResult___sfd__h557349) + always@(guard__h548645 or + _theResult___snd__h556581 or + out_sfd__h557319 or _theResult___sfd__h557316) begin - case (guard__h548678) + case (guard__h548645) 2'b0, 2'b01: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - _theResult___snd__h556614[56:5]; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + _theResult___snd__h556581[56:5]; 2'b10: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - out_sfd__h557352; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + out_sfd__h557319; 2'b11: - CASE_guard48678_0b0_theResult___snd56614_BITS__ETC__q210 = - _theResult___sfd__h557349; + CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 = + _theResult___sfd__h557316; endcase end - always@(guard__h500756 or - _theResult___fst_exp__h508982 or _theResult___exp__h509711) + always@(guard__h500723 or + _theResult___fst_exp__h508949 or _theResult___exp__h509678) begin - case (guard__h500756) + case (guard__h500723) 2'b0: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211 = - _theResult___fst_exp__h508982; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 = + _theResult___fst_exp__h508949; 2'b01, 2'b10, 2'b11: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211 = - _theResult___exp__h509711; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 = + _theResult___exp__h509678; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508982 or + _theResult___fst_exp__h508949 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 or - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211) + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = - _theResult___fst_exp__h508982; + _theResult___fst_exp__h508949; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055; @@ -36145,49 +36143,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q211; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 = 11'd0; endcase end - always@(guard__h500756 or - _theResult___fst_exp__h508982 or - out_exp__h509714 or _theResult___exp__h509711) + always@(guard__h500723 or + _theResult___fst_exp__h508949 or + out_exp__h509681 or _theResult___exp__h509678) begin - case (guard__h500756) + case (guard__h500723) 2'b0, 2'b01: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - _theResult___fst_exp__h508982; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + _theResult___fst_exp__h508949; 2'b10: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - out_exp__h509714; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + out_exp__h509681; 2'b11: - CASE_guard00756_0b0_theResult___fst_exp08982_0_ETC__q212 = - _theResult___exp__h509711; + CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 = + _theResult___exp__h509678; endcase end - always@(guard__h509825 or - _theResult___fst_exp__h517815 or _theResult___exp__h518495) + always@(guard__h509792 or + _theResult___fst_exp__h517782 or _theResult___exp__h518462) begin - case (guard__h509825) + case (guard__h509792) 2'b0: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213 = - _theResult___fst_exp__h517815; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 = + _theResult___fst_exp__h517782; 2'b01, 2'b10, 2'b11: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213 = - _theResult___exp__h518495; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 = + _theResult___exp__h518462; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517815 or + _theResult___fst_exp__h517782 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 or - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213) + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = - _theResult___fst_exp__h517815; + _theResult___fst_exp__h517782; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086; @@ -36196,49 +36194,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q213; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 = 11'd0; endcase end - always@(guard__h509825 or - _theResult___fst_exp__h517815 or - out_exp__h518498 or _theResult___exp__h518495) + always@(guard__h509792 or + _theResult___fst_exp__h517782 or + out_exp__h518465 or _theResult___exp__h518462) begin - case (guard__h509825) + case (guard__h509792) 2'b0, 2'b01: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - _theResult___fst_exp__h517815; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + _theResult___fst_exp__h517782; 2'b10: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - out_exp__h518498; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + out_exp__h518465; 2'b11: - CASE_guard09825_0b0_theResult___fst_exp17815_0_ETC__q214 = - _theResult___exp__h518495; + CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 = + _theResult___exp__h518462; endcase end - always@(guard__h491444 or - _theResult___snd__h499356 or _theResult___sfd__h500061) + always@(guard__h491411 or + _theResult___snd__h499323 or _theResult___sfd__h500028) begin - case (guard__h491444) + case (guard__h491411) 2'b0: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215 = - _theResult___snd__h499356[56:5]; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 = + _theResult___snd__h499323[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215 = - _theResult___sfd__h500061; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 = + _theResult___sfd__h500028; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h499356 or + _theResult___snd__h499323 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 or - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215) + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = - _theResult___snd__h499356[56:5]; + _theResult___snd__h499323[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112; @@ -36247,48 +36245,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q215; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 = 52'd0; endcase end - always@(guard__h491444 or - _theResult___snd__h499356 or - out_sfd__h500064 or _theResult___sfd__h500061) + always@(guard__h491411 or + _theResult___snd__h499323 or + out_sfd__h500031 or _theResult___sfd__h500028) begin - case (guard__h491444) + case (guard__h491411) 2'b0, 2'b01: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - _theResult___snd__h499356[56:5]; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + _theResult___snd__h499323[56:5]; 2'b10: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - out_sfd__h500064; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + out_sfd__h500031; 2'b11: - CASE_guard91444_0b0_theResult___snd99356_BITS__ETC__q216 = - _theResult___sfd__h500061; + CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 = + _theResult___sfd__h500028; endcase end - always@(guard__h500756 or sfdin__h508976 or _theResult___sfd__h509712) + always@(guard__h500723 or sfdin__h508943 or _theResult___sfd__h509679) begin - case (guard__h500756) + case (guard__h500723) 2'b0: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h508976[56:5]; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h508943[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h509712; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h509679; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508976 or + sfdin__h508943 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 or - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217) + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = - sfdin__h508976[56:5]; + sfdin__h508943[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139; @@ -36297,48 +36295,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q217; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 = 52'd0; endcase end - always@(guard__h500756 or - sfdin__h508976 or out_sfd__h509715 or _theResult___sfd__h509712) + always@(guard__h500723 or + sfdin__h508943 or out_sfd__h509682 or _theResult___sfd__h509679) begin - case (guard__h500756) + case (guard__h500723) 2'b0, 2'b01: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h508976[56:5]; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h508943[56:5]; 2'b10: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h509715; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h509682; 2'b11: - CASE_guard00756_0b0_sfdin08976_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h509712; + CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h509679; endcase end - always@(guard__h509825 or - _theResult___snd__h517761 or _theResult___sfd__h518496) + always@(guard__h509792 or + _theResult___snd__h517728 or _theResult___sfd__h518463) begin - case (guard__h509825) + case (guard__h509792) 2'b0: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219 = - _theResult___snd__h517761[56:5]; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 = + _theResult___snd__h517728[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219 = - _theResult___sfd__h518496; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 = + _theResult___sfd__h518463; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517761 or + _theResult___snd__h517728 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 or - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219) + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = - _theResult___snd__h517761[56:5]; + _theResult___snd__h517728[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158; @@ -36347,49 +36345,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q219; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 = 52'd0; endcase end - always@(guard__h509825 or - _theResult___snd__h517761 or - out_sfd__h518499 or _theResult___sfd__h518496) + always@(guard__h509792 or + _theResult___snd__h517728 or + out_sfd__h518466 or _theResult___sfd__h518463) begin - case (guard__h509825) + case (guard__h509792) 2'b0, 2'b01: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - _theResult___snd__h517761[56:5]; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + _theResult___snd__h517728[56:5]; 2'b10: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - out_sfd__h518499; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + out_sfd__h518466; 2'b11: - CASE_guard09825_0b0_theResult___snd17761_BITS__ETC__q220 = - _theResult___sfd__h518496; + CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 = + _theResult___sfd__h518463; endcase end - always@(guard__h569601 or - _theResult___snd__h577513 or _theResult___sfd__h578218) + always@(guard__h569568 or + _theResult___snd__h577480 or _theResult___sfd__h578185) begin - case (guard__h569601) + case (guard__h569568) 2'b0: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221 = - _theResult___snd__h577513[56:5]; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 = + _theResult___snd__h577480[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221 = - _theResult___sfd__h578218; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 = + _theResult___sfd__h578185; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h577513 or + _theResult___snd__h577480 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 or - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221) + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = - _theResult___snd__h577513[56:5]; + _theResult___snd__h577480[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822; @@ -36398,48 +36396,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q221; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 = 52'd0; endcase end - always@(guard__h569601 or - _theResult___snd__h577513 or - out_sfd__h578221 or _theResult___sfd__h578218) + always@(guard__h569568 or + _theResult___snd__h577480 or + out_sfd__h578188 or _theResult___sfd__h578185) begin - case (guard__h569601) + case (guard__h569568) 2'b0, 2'b01: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - _theResult___snd__h577513[56:5]; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + _theResult___snd__h577480[56:5]; 2'b10: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - out_sfd__h578221; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + out_sfd__h578188; 2'b11: - CASE_guard69601_0b0_theResult___snd77513_BITS__ETC__q222 = - _theResult___sfd__h578218; + CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 = + _theResult___sfd__h578185; endcase end - always@(guard__h578913 or sfdin__h587133 or _theResult___sfd__h587869) + always@(guard__h578880 or sfdin__h587100 or _theResult___sfd__h587836) begin - case (guard__h578913) + case (guard__h578880) 2'b0: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h587133[56:5]; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h587100[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h587869; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h587836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h587133 or + sfdin__h587100 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 or - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223) + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = - sfdin__h587133[56:5]; + sfdin__h587100[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848; @@ -36448,24 +36446,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q223; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 = 52'd0; endcase end - always@(guard__h578913 or - sfdin__h587133 or out_sfd__h587872 or _theResult___sfd__h587869) + always@(guard__h578880 or + sfdin__h587100 or out_sfd__h587839 or _theResult___sfd__h587836) begin - case (guard__h578913) + case (guard__h578880) 2'b0, 2'b01: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h587133[56:5]; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h587100[56:5]; 2'b10: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h587872; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h587839; 2'b11: - CASE_guard78913_0b0_sfdin87133_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h587869; + CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h587836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36500,28 +36498,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849; endcase end - always@(guard__h587982 or - _theResult___snd__h595918 or _theResult___sfd__h596653) + always@(guard__h587949 or + _theResult___snd__h595885 or _theResult___sfd__h596620) begin - case (guard__h587982) + case (guard__h587949) 2'b0: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225 = - _theResult___snd__h595918[56:5]; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 = + _theResult___snd__h595885[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225 = - _theResult___sfd__h596653; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 = + _theResult___sfd__h596620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595918 or + _theResult___snd__h595885 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 or - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225) + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = - _theResult___snd__h595918[56:5]; + _theResult___snd__h595885[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867; @@ -36530,25 +36528,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q225; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = 52'd0; endcase end - always@(guard__h587982 or - _theResult___snd__h595918 or - out_sfd__h596656 or _theResult___sfd__h596653) + always@(guard__h587949 or + _theResult___snd__h595885 or + out_sfd__h596623 or _theResult___sfd__h596620) begin - case (guard__h587982) + case (guard__h587949) 2'b0, 2'b01: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - _theResult___snd__h595918[56:5]; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + _theResult___snd__h595885[56:5]; 2'b10: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - out_sfd__h596656; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + out_sfd__h596623; 2'b11: - CASE_guard87982_0b0_theResult___snd95918_BITS__ETC__q226 = - _theResult___sfd__h596653; + CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 = + _theResult___sfd__h596620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36794,9 +36792,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 = + IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 = fetchStage$pipelines_0_first[172:161]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_172_ETC___d12912 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 = 12'd2303; endcase end @@ -36804,15 +36802,15 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[67:64]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = fetchStage$pipelines_0_first[67:64]; 4'd11: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd10; + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd10; 4'd12: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd11; + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd11; 4'd13: - IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2700_BIT_68_2_ETC___d13066 = + IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd12; + default: IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd13; endcase end @@ -36830,41 +36828,41 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = fetchStage$pipelines_0_first[194:174]; 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = { fetchStage$pipelines_0_first[194:192], 9'h0AA, fetchStage$pipelines_0_first[182:178], CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, fetchStage$pipelines_0_first[174] }; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d12830 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 = 21'd1485482; endcase end - always@(checkForException___d12946) + always@(checkForException___d12942) begin - case (checkForException___d12946[3:0]) + case (checkForException___d12942[3:0]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = - checkForException___d12946[3:0]; - 4'd11: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10; - 4'd12: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11; - 4'd13: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12; - default: CASE_checkForException_2946_BITS_3_TO_0_0_chec_ETC__q234 = + CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = + checkForException___d12942[3:0]; + 4'd11: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10; + 4'd12: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11; + 4'd13: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12; + default: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd13; endcase end - always@(k__h664143 or + always@(k__h664083 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h664143) + case (k__h664083) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -36873,65 +36871,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13395 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end - always@(k__h664143 or + always@(k__h664083 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h664143) + case (k__h664083) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414 or + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13414; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410; 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 && + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13419 = - regRenamingTable_rename_0_canRename__3333_AND__ETC___d13359; + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 = + regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355; endcase end always@(fetchStage$pipelines_0_first or @@ -36939,32 +36937,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13454 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_1_first) @@ -37030,36 +37028,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13514 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 = 21'd1485482; endcase end - always@(idx__h678765 or + always@(idx__h678705 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 or + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 or + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h678765) + case (idx__h678705) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13667 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2700_BITS_19_ETC___d13673 || + NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37075,61 +37073,61 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765 or + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13765; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 || + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761; 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13771 = - renameStage_rg_m_halt_req_2727_BIT_4_2728_OR_f_ETC___d13761; + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 = + renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13793 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13811 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end always@(fetchStage$pipelines_1_first or @@ -37144,31 +37142,43 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 or - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777 or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819 or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 or + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 or + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801) + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 && - NOT_fetchStage_pipelines_1_first__2709_BITS_19_ETC___d13777; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 && + NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773; 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13808 && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13819; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 && + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13790 && + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13801; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13823 = - regRenamingTable_rename_1_canRename__3460_AND__ETC___d13659; + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 = + regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655; + endcase + end + always@(k__h664083 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h664083) + 1'd0: + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + coreFix_aluExe_1_rsAlu$RDY_enq; endcase end always@(fetchStage$pipelines_0_first or @@ -37176,141 +37186,129 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = coreFix_memExe_lsq$RDY_enqSt; endcase end - always@(k__h664143 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h664143) - 1'd0: - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k64143_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13868 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849 or + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 || + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2700_BI_ETC___d13849; + _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13866 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 || - regRenamingTable_RDY_rename_0_getRename__3235__ETC___d13862; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 || + regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13882 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13412 && + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13889 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13391; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387; endcase end - always@(idx__h678765 or + always@(idx__h678705 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919 or + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h678765) + case (idx__h678705) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13912) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2700_BITS_194_TO_ETC___d13919) && + fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939 or + always@(fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2698_AND_NOT_fe_ETC___d13939) + case (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2698_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37326,79 +37324,79 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13965 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449); - endcase - end - always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378 or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3368_co_ETC___d13378; + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2700_BITS_194_ETC___d13977 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d13449; + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374; + default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445); endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693 or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974) + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2698_AN_ETC___d13693; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13974; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13989 = + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13986; + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 or - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943 or - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 or + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 or + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 or + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13923 || - regRenamingTable_RDY_rename_1_getRename__3925__ETC___d13943; + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 || + regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13945 || + IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13948; - default: IF_fetchStage_pipelines_1_first__2709_BITS_194_ETC___d13962 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944; + default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2698_AND_regRen_ETC___d13952 || + fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2698_2699_O_ETC___d13957; + NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953; endcase end always@(fetchStage$pipelines_0_first or @@ -37406,9 +37404,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14046 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37417,9 +37415,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14043 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37428,9 +37426,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14052 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37439,9 +37437,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 = + IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2700_BITS_191_ETC___d14049 = + default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37450,9 +37448,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14181 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37461,9 +37459,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14179 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37472,9 +37470,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14178 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37483,9 +37481,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 = + IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2709_BITS_191_ETC___d14180 = + default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37519,86 +37517,86 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd0; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd1; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd2; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd8; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd9; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd10; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd11; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd12; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd13; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd14; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd15; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd16; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd17; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd18; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd19; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd20; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd21; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd22; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd23; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd24; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd25; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd26; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd27; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd28; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd29; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd29; 12'd1968: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd36; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd36; 12'd1969: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd37; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd37; 12'd1970: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd38; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd38; 12'd1971: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd39; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd39; 12'd2048: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd6; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd7; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd30; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd31; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd3; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd4; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd5; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd32; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd33; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd34; + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 = + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd40; endcase end @@ -38970,7 +38968,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0; csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -39392,9 +39389,6 @@ module mkCore(CLK, if (csrInstOrInterruptInflight_rl$EN) csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY csrInstOrInterruptInflight_rl$D_IN; - if (csrf_debug_int_pend$EN) - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY - csrf_debug_int_pend$D_IN; if (csrf_external_int_en_vec_0$EN) csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_external_int_en_vec_0$D_IN; @@ -39833,7 +39827,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full = 1'h0; coreFix_memExe_waitLrScAmoMMIOResp = 3'h2; csrInstOrInterruptInflight_rl = 1'h0; - csrf_debug_int_pend = 1'h0; csrf_external_int_en_vec_0 = 1'h0; csrf_external_int_en_vec_1 = 1'h0; csrf_external_int_en_vec_3 = 1'h0; @@ -40217,7 +40210,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4241_BIT_181_4311_T_ETC___d14678 == 6'd6) + IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -40329,7 +40322,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] != 5'd19 && rob$deqPort_1_deq_data[186:182] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - x__h712792, + x__h712697, rob$deqPort_1_deq_data[282:219], rob$deqPort_1_deq_data[218:187], " iType:"); @@ -40488,7 +40481,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h601760 == 2'd0) + v__h601727 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 76997ba..b23200e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -7,9 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const -// RDY_set_htif_addrs O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg +// RDY_start O 1 // cpu_imem_master_awvalid O 1 // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg @@ -22,7 +20,6 @@ // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg @@ -51,7 +48,6 @@ // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg // cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg @@ -68,19 +64,22 @@ // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg -// RDY_dm_dmi_read_addr O 1 -// dm_dmi_read_data O 32 -// RDY_dm_dmi_read_data O 1 -// RDY_dm_dmi_write O 1 -// RDY_dm_ndm_reset_req_get_get O 1 reg +// RDY_dmi_read_addr O 1 +// dmi_read_data O 32 +// RDY_dmi_read_data O 1 +// RDY_dmi_write O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg // tv_verifier_info_get_get O 608 reg // RDY_tv_verifier_info_get_get O 1 reg +// RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused -// set_htif_addrs_tohost_addr I 64 reg -// set_htif_addrs_fromhost_addr I 64 reg +// start_tohost_addr I 64 +// start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -119,26 +118,24 @@ // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 -// dm_dmi_read_addr_dm_addr I 7 -// dm_dmi_write_dm_addr I 7 -// dm_dmi_write_dm_word I 32 +// nmi_req_set_not_clear I 1 unused +// dmi_read_addr_dm_addr I 7 +// dmi_write_dm_addr I 7 +// dmi_write_dm_word I 32 +// ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 -// EN_set_htif_addrs I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// EN_dm_dmi_read_addr I 1 -// EN_dm_dmi_write I 1 -// EN_dm_ndm_reset_req_get_get I 1 -// EN_dm_dmi_read_data I 1 +// EN_start I 1 +// EN_dmi_read_addr I 1 +// EN_dmi_write I 1 +// EN_ndm_reset_client_response_put I 1 +// EN_dmi_read_data I 1 +// EN_ndm_reset_client_request_get I 1 // EN_tv_verifier_info_get_get I 1 // // Combinational paths from inputs to outputs: // (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data -// (dm_dmi_read_addr_dm_addr, -// EN_dm_dmi_read_addr, -// EN_dm_dmi_read_data) -> dm_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -155,7 +152,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkCoreW(CLK, +module mkCoreW(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -163,16 +161,10 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, - set_htif_addrs_tohost_addr, - set_htif_addrs_fromhost_addr, - EN_set_htif_addrs, - RDY_set_htif_addrs, - - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start, cpu_imem_master_awvalid, @@ -200,8 +192,6 @@ module mkCoreW(CLK, cpu_imem_master_wvalid, - cpu_imem_master_wid, - cpu_imem_master_wdata, cpu_imem_master_wstrb, @@ -274,8 +264,6 @@ module mkCoreW(CLK, cpu_dmem_master_wvalid, - cpu_dmem_master_wid, - cpu_dmem_master_wdata, cpu_dmem_master_wstrb, @@ -354,27 +342,33 @@ module mkCoreW(CLK, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, + nmi_req_set_not_clear, - dm_dmi_read_addr_dm_addr, - EN_dm_dmi_read_addr, - RDY_dm_dmi_read_addr, + dmi_read_addr_dm_addr, + EN_dmi_read_addr, + RDY_dmi_read_addr, - EN_dm_dmi_read_data, - dm_dmi_read_data, - RDY_dm_dmi_read_data, + EN_dmi_read_data, + dmi_read_data, + RDY_dmi_read_data, - dm_dmi_write_dm_addr, - dm_dmi_write_dm_word, - EN_dm_dmi_write, - RDY_dm_dmi_write, + dmi_write_dm_addr, + dmi_write_dm_word, + EN_dmi_write, + RDY_dmi_write, - EN_dm_ndm_reset_req_get_get, - RDY_dm_ndm_reset_req_get_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put, EN_tv_verifier_info_get_get, tv_verifier_info_get_get, RDY_tv_verifier_info_get_get); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -384,19 +378,11 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // action method set_htif_addrs - input [63 : 0] set_htif_addrs_tohost_addr; - input [63 : 0] set_htif_addrs_fromhost_addr; - input EN_set_htif_addrs; - output RDY_set_htif_addrs; - - // action method cpu_reset_server_request_put - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // action method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; @@ -439,9 +425,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; @@ -553,9 +536,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid output cpu_dmem_master_wvalid; - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - // value method cpu_dmem_master_m_wdata output [63 : 0] cpu_dmem_master_wdata; @@ -674,28 +654,34 @@ module mkCoreW(CLK, // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; + // action method nmi_req + input nmi_req_set_not_clear; - // action method dm_dmi_read_addr - input [6 : 0] dm_dmi_read_addr_dm_addr; - input EN_dm_dmi_read_addr; - output RDY_dm_dmi_read_addr; + // action method dmi_read_addr + input [6 : 0] dmi_read_addr_dm_addr; + input EN_dmi_read_addr; + output RDY_dmi_read_addr; - // actionvalue method dm_dmi_read_data - input EN_dm_dmi_read_data; - output [31 : 0] dm_dmi_read_data; - output RDY_dm_dmi_read_data; + // actionvalue method dmi_read_data + input EN_dmi_read_data; + output [31 : 0] dmi_read_data; + output RDY_dmi_read_data; - // action method dm_dmi_write - input [6 : 0] dm_dmi_write_dm_addr; - input [31 : 0] dm_dmi_write_dm_word; - input EN_dm_dmi_write; - output RDY_dm_dmi_write; + // action method dmi_write + input [6 : 0] dmi_write_dm_addr; + input [31 : 0] dmi_write_dm_word; + input EN_dmi_write; + output RDY_dmi_write; - // action method dm_ndm_reset_req_get_get - input EN_dm_ndm_reset_req_get_get; - output RDY_dm_ndm_reset_req_get_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // actionvalue method tv_verifier_info_get_get input EN_tv_verifier_info_get_get; @@ -710,7 +696,7 @@ module mkCoreW(CLK, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; - wire [31 : 0] dm_dmi_read_data; + wire [31 : 0] dmi_read_data; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, @@ -725,7 +711,6 @@ module mkCoreW(CLK, cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, - cpu_dmem_master_wid, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, @@ -733,8 +718,7 @@ module mkCoreW(CLK, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; + cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, @@ -747,14 +731,13 @@ module mkCoreW(CLK, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_dm_dmi_read_addr, - RDY_dm_dmi_read_data, - RDY_dm_dmi_write, - RDY_dm_ndm_reset_req_get_get, - RDY_set_htif_addrs, + wire RDY_dmi_read_addr, + RDY_dmi_read_data, + RDY_dmi_write, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_set_verbosity, + RDY_start, RDY_tv_verifier_info_get_get, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, @@ -771,13 +754,19 @@ module mkCoreW(CLK, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, - cpu_imem_master_wvalid; + cpu_imem_master_wvalid, + ndm_reset_client_request_get; // register rg_fromhost_addr reg [63 : 0] rg_fromhost_addr; wire [63 : 0] rg_fromhost_addr$D_IN; wire rg_fromhost_addr$EN; + // register rg_hart0_reset_delay + reg [7 : 0] rg_hart0_reset_delay; + wire [7 : 0] rg_hart0_reset_delay$D_IN; + wire rg_hart0_reset_delay$EN; + // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; @@ -809,8 +798,7 @@ module mkCoreW(CLK, debug_module$master_awqos, debug_module$master_awregion, debug_module$master_bid, - debug_module$master_rid, - debug_module$master_wid; + debug_module$master_rid; wire [2 : 0] debug_module$master_arprot, debug_module$master_arsize, debug_module$master_awprot, @@ -822,7 +810,6 @@ module mkCoreW(CLK, wire debug_module$EN_dmi_read_addr, debug_module$EN_dmi_read_data, debug_module$EN_dmi_write, - debug_module$EN_get_ndm_reset_req_get, debug_module$EN_hart0_client_run_halt_request_get, debug_module$EN_hart0_client_run_halt_response_put, debug_module$EN_hart0_csr_mem_client_request_get, @@ -830,23 +817,29 @@ module mkCoreW(CLK, debug_module$EN_hart0_fpr_mem_client_request_get, debug_module$EN_hart0_fpr_mem_client_response_put, debug_module$EN_hart0_get_other_req_get, - debug_module$EN_hart0_get_reset_req_get, debug_module$EN_hart0_gpr_mem_client_request_get, debug_module$EN_hart0_gpr_mem_client_response_put, + debug_module$EN_hart0_reset_client_request_get, + debug_module$EN_hart0_reset_client_response_put, + debug_module$EN_ndm_reset_client_request_get, + debug_module$EN_ndm_reset_client_response_put, debug_module$RDY_dmi_read_addr, debug_module$RDY_dmi_read_data, debug_module$RDY_dmi_write, - debug_module$RDY_get_ndm_reset_req_get, debug_module$RDY_hart0_client_run_halt_request_get, debug_module$RDY_hart0_client_run_halt_response_put, debug_module$RDY_hart0_csr_mem_client_request_get, debug_module$RDY_hart0_csr_mem_client_response_put, debug_module$RDY_hart0_get_other_req_get, - debug_module$RDY_hart0_get_reset_req_get, debug_module$RDY_hart0_gpr_mem_client_request_get, debug_module$RDY_hart0_gpr_mem_client_response_put, + debug_module$RDY_hart0_reset_client_request_get, + debug_module$RDY_hart0_reset_client_response_put, + debug_module$RDY_ndm_reset_client_request_get, + debug_module$RDY_ndm_reset_client_response_put, debug_module$hart0_client_run_halt_request_get, debug_module$hart0_client_run_halt_response_put, + debug_module$hart0_reset_client_response_put, debug_module$master_arlock, debug_module$master_arready, debug_module$master_arvalid, @@ -860,7 +853,9 @@ module mkCoreW(CLK, debug_module$master_rvalid, debug_module$master_wlast, debug_module$master_wready, - debug_module$master_wvalid; + debug_module$master_wvalid, + debug_module$ndm_reset_client_request_get, + debug_module$ndm_reset_client_response_put; // ports of submodule dm_csr_tap wire [426 : 0] dm_csr_tap$trace_data_out_get; @@ -895,6 +890,9 @@ module mkCoreW(CLK, dm_gpr_tap_ifc$RDY_server_response_get, dm_gpr_tap_ifc$RDY_trace_data_out_get; + // ports of submodule dm_hart0_reset_controller + wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST; + // ports of submodule dm_mem_tap wire [426 : 0] dm_mem_tap$trace_data_out_get; wire [63 : 0] dm_mem_tap$master_araddr, @@ -921,7 +919,6 @@ module mkCoreW(CLK, dm_mem_tap$master_awregion, dm_mem_tap$master_bid, dm_mem_tap$master_rid, - dm_mem_tap$master_wid, dm_mem_tap$slave_arcache, dm_mem_tap$slave_arid, dm_mem_tap$slave_arqos, @@ -931,8 +928,7 @@ module mkCoreW(CLK, dm_mem_tap$slave_awqos, dm_mem_tap$slave_awregion, dm_mem_tap$slave_bid, - dm_mem_tap$slave_rid, - dm_mem_tap$slave_wid; + dm_mem_tap$slave_rid; wire [2 : 0] dm_mem_tap$master_arprot, dm_mem_tap$master_arsize, dm_mem_tap$master_awprot, @@ -980,29 +976,6 @@ module mkCoreW(CLK, dm_mem_tap$slave_wready, dm_mem_tap$slave_wvalid; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_requestor - wire f_reset_requestor$CLR, - f_reset_requestor$DEQ, - f_reset_requestor$D_IN, - f_reset_requestor$D_OUT, - f_reset_requestor$EMPTY_N, - f_reset_requestor$ENQ, - f_reset_requestor$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, fabric_2x3$v_from_masters_0_awaddr, @@ -1050,7 +1023,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, @@ -1061,7 +1033,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_1_awregion, fabric_2x3$v_from_masters_1_bid, fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_from_masters_1_wid, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, @@ -1072,7 +1043,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, @@ -1083,7 +1053,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, @@ -1093,8 +1062,7 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; + fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, @@ -1137,7 +1105,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, @@ -1209,6 +1176,9 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_wready, fabric_2x3$v_to_slaves_2_wvalid; + // ports of submodule hart0_reset + wire hart0_reset$RST_OUT; + // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, @@ -1229,7 +1199,6 @@ module mkCoreW(CLK, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, - plic$axi4_slave_wid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1244,8 +1213,6 @@ module mkCoreW(CLK, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, @@ -1320,7 +1287,6 @@ module mkCoreW(CLK, proc$debug_module_mem_server_awregion, proc$debug_module_mem_server_bid, proc$debug_module_mem_server_rid, - proc$debug_module_mem_server_wid, proc$hart0_put_other_req_put, proc$master0_arcache, proc$master0_arid, @@ -1332,7 +1298,6 @@ module mkCoreW(CLK, proc$master0_awregion, proc$master0_bid, proc$master0_rid, - proc$master0_wid, proc$master1_arcache, proc$master1_arid, proc$master1_arqos, @@ -1343,7 +1308,6 @@ module mkCoreW(CLK, proc$master1_awregion, proc$master1_bid, proc$master1_rid, - proc$master1_wid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1378,8 +1342,6 @@ module mkCoreW(CLK, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, - proc$EN_hart0_server_reset_request_put, - proc$EN_hart0_server_reset_response_get, proc$EN_set_verbosity, proc$EN_start, proc$EN_v_to_TV_0_get, @@ -1390,12 +1352,9 @@ module mkCoreW(CLK, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, - proc$RDY_hart0_server_reset_request_put, - proc$RDY_hart0_server_reset_response_get, proc$RDY_start, proc$RDY_v_to_TV_0_get, proc$RDY_v_to_TV_1_get, - proc$debug_external_interrupt_req_set_not_clear, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, proc$debug_module_mem_server_arvalid, @@ -1462,7 +1421,6 @@ module mkCoreW(CLK, tv_encode$EN_v_cpu_in_1_put, tv_encode$RDY_dm_in_put, tv_encode$RDY_out_get, - tv_encode$RDY_reset, tv_encode$RDY_v_cpu_in_0_put, tv_encode$RDY_v_cpu_in_1_put; @@ -1514,9 +1472,8 @@ module mkCoreW(CLK, CAN_FIRE_RL_mkConnectionGetPut_2, CAN_FIRE_RL_mkConnectionGetPut_3, CAN_FIRE_RL_mkConnectionGetPut_4, - CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, + CAN_FIRE_RL_rl_dm_hart0_reset, + CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_merge_dm_csr_trace_data, CAN_FIRE_RL_rl_merge_dm_gpr_trace_data, CAN_FIRE_RL_rl_merge_dm_mem_trace_data, @@ -1531,7 +1488,6 @@ module mkCoreW(CLK, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_rd_data_channel_4, CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_non_maskable_interrupt, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, @@ -1575,15 +1531,14 @@ module mkCoreW(CLK, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_debug_external_interrupt_req, - CAN_FIRE_dm_dmi_read_addr, - CAN_FIRE_dm_dmi_read_data, - CAN_FIRE_dm_dmi_write, - CAN_FIRE_dm_ndm_reset_req_get_get, - CAN_FIRE_set_htif_addrs, + CAN_FIRE_dmi_read_addr, + CAN_FIRE_dmi_read_data, + CAN_FIRE_dmi_write, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, + CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, + CAN_FIRE_start, CAN_FIRE_tv_verifier_info_get_get, WILL_FIRE_RL_ClientServerRequest, WILL_FIRE_RL_ClientServerRequest_1, @@ -1600,9 +1555,8 @@ module mkCoreW(CLK, WILL_FIRE_RL_mkConnectionGetPut_2, WILL_FIRE_RL_mkConnectionGetPut_3, WILL_FIRE_RL_mkConnectionGetPut_4, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, + WILL_FIRE_RL_rl_dm_hart0_reset, + WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_merge_dm_csr_trace_data, WILL_FIRE_RL_rl_merge_dm_gpr_trace_data, WILL_FIRE_RL_rl_merge_dm_mem_trace_data, @@ -1617,7 +1571,6 @@ module mkCoreW(CLK, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_rd_data_channel_4, WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_non_maskable_interrupt, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, @@ -1661,64 +1614,54 @@ module mkCoreW(CLK, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_debug_external_interrupt_req, - WILL_FIRE_dm_dmi_read_addr, - WILL_FIRE_dm_dmi_read_data, - WILL_FIRE_dm_dmi_write, - WILL_FIRE_dm_ndm_reset_req_get_get, - WILL_FIRE_set_htif_addrs, + WILL_FIRE_dmi_read_addr, + WILL_FIRE_dmi_read_data, + WILL_FIRE_dmi_write, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, + WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, + WILL_FIRE_start, WILL_FIRE_tv_verifier_info_get_get; + // inputs to muxes for submodule ports + wire [7 : 0] MUX_rg_hart0_reset_delay$write_1__VAL_1; + wire MUX_proc$start_1__SEL_1; + // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h7205; - reg [31 : 0] v__h7403; - reg [31 : 0] v__h7674; - reg [31 : 0] v__h7199; - reg [31 : 0] v__h7397; - reg [31 : 0] v__h7668; + reg [31 : 0] v__h6860; + reg [31 : 0] v__h7003; + reg [31 : 0] v__h15013; + reg [31 : 0] v__h6854; + reg [31 : 0] v__h6997; + reg [31 : 0] v__h15007; // synopsys translate_on // remaining internal signals - reg [63 : 0] x__h5725, x__h6650; + reg [63 : 0] x__h5570, x__h6495; reg [11 : 0] CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1, - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5; - reg [4 : 0] CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6; + reg [4 : 0] CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5, CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10, - x1_avValue_rd__h5432, - x1_avValue_rd__h6363; + x1_avValue_rd__h5277, + x1_avValue_rd__h6208; reg [3 : 0] CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2, CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7; + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7, + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8; reg [1 : 0] CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4, - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8; - wire tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113; + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // action method set_htif_addrs - assign RDY_set_htif_addrs = 1'd1 ; - assign CAN_FIRE_set_htif_addrs = 1'd1 ; - assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // action method cpu_reset_server_response_get - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; + // action method start + assign RDY_start = proc$RDY_start ; + assign CAN_FIRE_start = proc$RDY_start ; + assign WILL_FIRE_start = EN_start ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = proc$master0_awvalid ; @@ -1760,9 +1703,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = proc$master0_wvalid ; - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = proc$master0_wid ; - // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = proc$master0_wdata ; @@ -1867,9 +1807,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - // value method cpu_dmem_master_m_wdata assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; @@ -1998,32 +1935,43 @@ module mkCoreW(CLK, assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method nmi_req + assign CAN_FIRE_nmi_req = 1'd1 ; + assign WILL_FIRE_nmi_req = 1'd1 ; - // action method dm_dmi_read_addr - assign RDY_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign CAN_FIRE_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign WILL_FIRE_dm_dmi_read_addr = EN_dm_dmi_read_addr ; + // action method dmi_read_addr + assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ; - // actionvalue method dm_dmi_read_data - assign dm_dmi_read_data = debug_module$dmi_read_data ; - assign RDY_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign CAN_FIRE_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign WILL_FIRE_dm_dmi_read_data = EN_dm_dmi_read_data ; + // actionvalue method dmi_read_data + assign dmi_read_data = debug_module$dmi_read_data ; + assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ; - // action method dm_dmi_write - assign RDY_dm_dmi_write = debug_module$RDY_dmi_write ; - assign CAN_FIRE_dm_dmi_write = debug_module$RDY_dmi_write ; - assign WILL_FIRE_dm_dmi_write = EN_dm_dmi_write ; + // action method dmi_write + assign RDY_dmi_write = debug_module$RDY_dmi_write ; + assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ; + assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method dm_ndm_reset_req_get_get - assign RDY_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_dm_ndm_reset_req_get_get = EN_dm_ndm_reset_req_get_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + debug_module$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // actionvalue method tv_verifier_info_get_get assign tv_verifier_info_get_get = tv_encode$out_get ; @@ -2033,7 +1981,7 @@ module mkCoreW(CLK, // submodule debug_module mkDebug_Module debug_module(.CLK(CLK), - .RST_N(RST_N), + .RST_N(RST_N_dm_power_on_reset), .dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr), .dmi_write_dm_addr(debug_module$dmi_write_dm_addr), .dmi_write_dm_word(debug_module$dmi_write_dm_word), @@ -2041,6 +1989,7 @@ module mkCoreW(CLK, .hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put), .hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put), .hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put), + .hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put), .master_arready(debug_module$master_arready), .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), @@ -2052,10 +2001,12 @@ module mkCoreW(CLK, .master_rresp(debug_module$master_rresp), .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), + .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), .EN_dmi_read_data(debug_module$EN_dmi_read_data), .EN_dmi_write(debug_module$EN_dmi_write), - .EN_hart0_get_reset_req_get(debug_module$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get), @@ -2065,12 +2016,15 @@ module mkCoreW(CLK, .EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put), .EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get), .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), - .EN_get_ndm_reset_req_get(debug_module$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), .RDY_dmi_write(debug_module$RDY_dmi_write), - .RDY_hart0_get_reset_req_get(debug_module$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(), + .RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put), @@ -2085,7 +2039,9 @@ module mkCoreW(CLK, .hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put), - .RDY_get_ndm_reset_req_get(debug_module$RDY_get_ndm_reset_req_get), + .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), .master_awvalid(debug_module$master_awvalid), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), @@ -2098,7 +2054,6 @@ module mkCoreW(CLK, .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), .master_wvalid(debug_module$master_wvalid), - .master_wid(debug_module$master_wid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), @@ -2154,6 +2109,15 @@ module mkCoreW(CLK, .trace_data_out_get(dm_gpr_tap_ifc$trace_data_out_get), .RDY_trace_data_out_get(dm_gpr_tap_ifc$RDY_trace_data_out_get)); + // submodule dm_hart0_reset_controller + MakeResetA #(.RSTDELAY(32'd10), + .init(1'd1)) dm_hart0_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(dm_hart0_reset_controller$OUT_RST)); + // submodule dm_mem_tap mkDM_Mem_Tap dm_mem_tap(.CLK(CLK), .RST_N(RST_N), @@ -2193,7 +2157,6 @@ module mkCoreW(CLK, .slave_bready(dm_mem_tap$slave_bready), .slave_rready(dm_mem_tap$slave_rready), .slave_wdata(dm_mem_tap$slave_wdata), - .slave_wid(dm_mem_tap$slave_wid), .slave_wlast(dm_mem_tap$slave_wlast), .slave_wstrb(dm_mem_tap$slave_wstrb), .slave_wvalid(dm_mem_tap$slave_wvalid), @@ -2221,7 +2184,6 @@ module mkCoreW(CLK, .master_awqos(dm_mem_tap$master_awqos), .master_awregion(dm_mem_tap$master_awregion), .master_wvalid(dm_mem_tap$master_wvalid), - .master_wid(dm_mem_tap$master_wid), .master_wdata(dm_mem_tap$master_wdata), .master_wstrb(dm_mem_tap$master_wstrb), .master_wlast(dm_mem_tap$master_wlast), @@ -2241,35 +2203,6 @@ module mkCoreW(CLK, .trace_data_out_get(dm_mem_tap$trace_data_out_get), .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_requestor - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_requestor(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_requestor$D_IN), - .ENQ(f_reset_requestor$ENQ), - .DEQ(f_reset_requestor$DEQ), - .CLR(f_reset_requestor$CLR), - .D_OUT(f_reset_requestor$D_OUT), - .FULL_N(f_reset_requestor$FULL_N), - .EMPTY_N(f_reset_requestor$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), .RST_N(RST_N), @@ -2299,7 +2232,6 @@ module mkCoreW(CLK, .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), @@ -2328,7 +2260,6 @@ module mkCoreW(CLK, .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), @@ -2367,7 +2298,7 @@ module mkCoreW(CLK, .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), + .RDY_reset(), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), @@ -2403,7 +2334,6 @@ module mkCoreW(CLK, .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), @@ -2432,7 +2362,6 @@ module mkCoreW(CLK, .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), @@ -2461,7 +2390,6 @@ module mkCoreW(CLK, .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), @@ -2479,6 +2407,11 @@ module mkCoreW(CLK, .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); + // submodule hart0_reset + ResetEither hart0_reset(.A_RST(RST_N), + .B_RST(dm_hart0_reset_controller$OUT_RST), + .RST_OUT(hart0_reset$RST_OUT)); + // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), @@ -2507,7 +2440,6 @@ module mkCoreW(CLK, .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), @@ -2537,8 +2469,8 @@ module mkCoreW(CLK, .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), + .RDY_server_reset_request_put(), + .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), @@ -2556,8 +2488,7 @@ module mkCoreW(CLK, // submodule proc mkProc proc(.CLK(CLK), - .RST_N(RST_N), - .debug_external_interrupt_req_set_not_clear(proc$debug_external_interrupt_req_set_not_clear), + .RST_N(hart0_reset$RST_OUT), .debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr), .debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst), .debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache), @@ -2583,7 +2514,6 @@ module mkCoreW(CLK, .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), - .debug_module_mem_server_wid(proc$debug_module_mem_server_wid), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), @@ -2621,8 +2551,6 @@ module mkCoreW(CLK, .start_fromhostAddr(proc$start_fromhostAddr), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), - .EN_hart0_server_reset_request_put(proc$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(proc$EN_hart0_server_reset_response_get), .EN_start(proc$EN_start), .EN_set_verbosity(proc$EN_set_verbosity), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), @@ -2636,8 +2564,6 @@ module mkCoreW(CLK, .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), .EN_v_to_TV_0_get(proc$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(proc$EN_v_to_TV_1_get), - .RDY_hart0_server_reset_request_put(proc$RDY_hart0_server_reset_request_put), - .RDY_hart0_server_reset_response_get(proc$RDY_hart0_server_reset_response_get), .RDY_start(proc$RDY_start), .master0_awvalid(proc$master0_awvalid), .master0_awid(proc$master0_awid), @@ -2651,7 +2577,6 @@ module mkCoreW(CLK, .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), .master0_wvalid(proc$master0_wvalid), - .master0_wid(proc$master0_wid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), @@ -2680,7 +2605,6 @@ module mkCoreW(CLK, .master1_awqos(proc$master1_awqos), .master1_awregion(proc$master1_awregion), .master1_wvalid(proc$master1_wvalid), - .master1_wid(proc$master1_wid), .master1_wdata(proc$master1_wdata), .master1_wstrb(proc$master1_wstrb), .master1_wlast(proc$master1_wlast), @@ -2784,7 +2708,7 @@ module mkCoreW(CLK, .EN_v_cpu_in_1_put(tv_encode$EN_v_cpu_in_1_put), .EN_dm_in_put(tv_encode$EN_dm_in_put), .EN_out_get(tv_encode$EN_out_get), - .RDY_reset(tv_encode$RDY_reset), + .RDY_reset(), .RDY_v_cpu_in_0_put(tv_encode$RDY_v_cpu_in_0_put), .RDY_v_cpu_in_1_put(tv_encode$RDY_v_cpu_in_1_put), .RDY_dm_in_put(tv_encode$RDY_dm_in_put), @@ -2835,16 +2759,31 @@ module mkCoreW(CLK, .FULL_N(v_td2_to_td_1_f_out$FULL_N), .EMPTY_N(v_td2_to_td_1_f_out$EMPTY_N)); + // rule RL_rl_dm_hart0_reset + assign CAN_FIRE_RL_rl_dm_hart0_reset = + debug_module$RDY_hart0_reset_client_request_get && + rg_hart0_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ; + + // rule RL_rl_dm_hart0_reset_wait + assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = + (rg_hart0_reset_delay != 8'd1 || + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && + rg_hart0_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = + CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; + // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - debug_module$RDY_hart0_client_run_halt_request_get && - proc$RDY_hart0_run_halt_server_request_put ; + proc$RDY_hart0_run_halt_server_request_put && + debug_module$RDY_hart0_client_run_halt_request_get ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - debug_module$RDY_hart0_client_run_halt_response_put && - proc$RDY_hart0_run_halt_server_response_get ; + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2886,6 +2825,10 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; + // rule RL_rl_wr_response_channel + assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; + // rule RL_rl_rd_addr_channel assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; @@ -2896,22 +2839,22 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2924,22 +2867,22 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -3042,55 +2985,20 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_from_dm_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode$RDY_reset && - debug_module$RDY_hart0_get_reset_req_get && - proc$RDY_hart0_server_reset_request_put && - f_reset_requestor$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start && - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && proc$RDY_start && - proc$RDY_hart0_server_reset_response_get && - f_reset_requestor$EMPTY_N && - (!f_reset_requestor$D_OUT || f_reset_rsps$FULL_N) ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; - // rule RL_rl_relay_non_maskable_interrupt - assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - // rule RL_v_td2_to_td_0_rl_xform assign CAN_FIRE_RL_v_td2_to_td_0_rl_xform = v_td2_to_td_0_f_in$EMPTY_N && v_td2_to_td_0_f_out$FULL_N ; @@ -3103,18 +3011,34 @@ module mkCoreW(CLK, assign WILL_FIRE_RL_v_td2_to_td_1_rl_xform = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; + // inputs to muxes for submodule ports + assign MUX_proc$start_1__SEL_1 = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 ; + assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = + rg_hart0_reset_delay - 8'd1 ; + // register rg_fromhost_addr - assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; - assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + assign rg_fromhost_addr$D_IN = start_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_start ; + + // register rg_hart0_reset_delay + assign rg_hart0_reset_delay$D_IN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait ? + MUX_rg_hart0_reset_delay$write_1__VAL_1 : + 8'd210 ; + assign rg_hart0_reset_delay$EN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait || + WILL_FIRE_RL_rl_dm_hart0_reset ; // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_htif_addrs ; + assign rg_tohost_addr$D_IN = start_tohost_addr ; + assign rg_tohost_addr$EN = EN_start ; // submodule debug_module - assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; - assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; - assign debug_module$dmi_write_dm_word = dm_dmi_write_dm_word ; + assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ; + assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ; + assign debug_module$dmi_write_dm_word = dmi_write_dm_word ; assign debug_module$hart0_client_run_halt_response_put = proc$hart0_run_halt_server_response_get ; assign debug_module$hart0_csr_mem_client_response_put = @@ -3122,6 +3046,7 @@ module mkCoreW(CLK, assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ; assign debug_module$hart0_gpr_mem_client_response_put = dm_gpr_tap_ifc$server_response_get ; + assign debug_module$hart0_reset_client_response_put = 1'd1 ; assign debug_module$master_arready = dm_mem_tap$slave_arready ; assign debug_module$master_awready = dm_mem_tap$slave_awready ; assign debug_module$master_bid = dm_mem_tap$slave_bid ; @@ -3133,11 +3058,15 @@ module mkCoreW(CLK, assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; assign debug_module$master_wready = dm_mem_tap$slave_wready ; - assign debug_module$EN_dmi_read_addr = EN_dm_dmi_read_addr ; - assign debug_module$EN_dmi_read_data = EN_dm_dmi_read_data ; - assign debug_module$EN_dmi_write = EN_dm_dmi_write ; - assign debug_module$EN_hart0_get_reset_req_get = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; + assign debug_module$ndm_reset_client_response_put = + ndm_reset_client_response_put ; + assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; + assign debug_module$EN_dmi_read_data = EN_dmi_read_data ; + assign debug_module$EN_dmi_write = EN_dmi_write ; + assign debug_module$EN_hart0_reset_client_request_get = + CAN_FIRE_RL_rl_dm_hart0_reset ; + assign debug_module$EN_hart0_reset_client_response_put = + MUX_proc$start_1__SEL_1 ; assign debug_module$EN_hart0_client_run_halt_request_get = CAN_FIRE_RL_ClientServerRequest ; assign debug_module$EN_hart0_client_run_halt_response_put = @@ -3154,7 +3083,10 @@ module mkCoreW(CLK, CAN_FIRE_RL_ClientServerRequest_3 ; assign debug_module$EN_hart0_csr_mem_client_response_put = CAN_FIRE_RL_ClientServerResponse_3 ; - assign debug_module$EN_get_ndm_reset_req_get = EN_dm_ndm_reset_req_get_get ; + assign debug_module$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign debug_module$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule dm_csr_tap assign dm_csr_tap$client_response_put = @@ -3188,6 +3120,9 @@ module mkCoreW(CLK, assign dm_gpr_tap_ifc$EN_trace_data_out_get = CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ; + // submodule dm_hart0_reset_controller + assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; + // submodule dm_mem_tap assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; @@ -3225,36 +3160,12 @@ module mkCoreW(CLK, assign dm_mem_tap$slave_bready = debug_module$master_bready ; assign dm_mem_tap$slave_rready = debug_module$master_rready ; assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; - assign dm_mem_tap$slave_wid = debug_module$master_wid ; assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; assign dm_mem_tap$EN_trace_data_out_get = WILL_FIRE_RL_rl_merge_dm_mem_trace_data ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_requestor - assign f_reset_requestor$D_IN = - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; - assign f_reset_requestor$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign f_reset_requestor$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign f_reset_requestor$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_complete && - f_reset_requestor$D_OUT ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ; @@ -3282,7 +3193,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ; assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ; assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ; - assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ; assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ; @@ -3311,7 +3221,6 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wid = dm_mem_tap$master_wid ; assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; @@ -3353,9 +3262,7 @@ module mkCoreW(CLK, proc$debug_module_mem_server_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = proc$debug_module_mem_server_wready ; - assign fabric_2x3$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign fabric_2x3$EN_reset = 1'b0 ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule plic @@ -3384,7 +3291,6 @@ module mkCoreW(CLK, assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; @@ -3425,16 +3331,11 @@ module mkCoreW(CLK, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$EN_server_reset_request_put = 1'b0 ; + assign plic$EN_server_reset_response_get = 1'b0 ; + assign plic$EN_set_addr_map = EN_start ; // submodule proc - assign proc$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; assign proc$debug_module_mem_server_araddr = fabric_2x3$v_to_slaves_2_araddr ; assign proc$debug_module_mem_server_arburst = @@ -3478,7 +3379,6 @@ module mkCoreW(CLK, assign proc$debug_module_mem_server_rready = fabric_2x3$v_to_slaves_2_rready ; assign proc$debug_module_mem_server_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign proc$debug_module_mem_server_wid = fabric_2x3$v_to_slaves_2_wid ; assign proc$debug_module_mem_server_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign proc$debug_module_mem_server_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign proc$debug_module_mem_server_wvalid = @@ -3519,15 +3419,17 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_fromhostAddr = + MUX_proc$start_1__SEL_1 ? + rg_fromhost_addr : + start_fromhost_addr ; assign proc$start_startpc = 64'h0000000070000000 ; - assign proc$start_tohostAddr = rg_tohost_addr ; - assign proc$EN_hart0_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign proc$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign proc$start_tohostAddr = + MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; + assign proc$EN_start = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 || + EN_start ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; @@ -3574,9 +3476,7 @@ module mkCoreW(CLK, end assign tv_encode$v_cpu_in_0_put = v_td2_to_td_0_f_out$D_OUT ; assign tv_encode$v_cpu_in_1_put = v_td2_to_td_1_f_out$D_OUT ; - assign tv_encode$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign tv_encode$EN_reset = 1'b0 ; assign tv_encode$EN_v_cpu_in_0_put = CAN_FIRE_RL_mkConnectionGetPut_2 ; assign tv_encode$EN_v_cpu_in_1_put = CAN_FIRE_RL_mkConnectionGetPut_4 ; assign tv_encode$EN_dm_in_put = @@ -3608,12 +3508,12 @@ module mkCoreW(CLK, // submodule v_td2_to_td_0_f_out assign v_td2_to_td_0_f_out$D_IN = { v_td2_to_td_0_f_in$D_OUT[319:256], - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5, v_td2_to_td_0_f_in$D_OUT[255:192], v_td2_to_td_0_f_in$D_OUT[161:160] == 2'b11, v_td2_to_td_0_f_in$D_OUT[191:160], - x1_avValue_rd__h5432, - x__h5725, + x1_avValue_rd__h5277, + x__h5570, 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; assign v_td2_to_td_0_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_0_rl_xform ; assign v_td2_to_td_0_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_2 ; @@ -3623,17 +3523,17 @@ module mkCoreW(CLK, assign v_td2_to_td_1_f_in$D_IN = { proc$v_to_TV_1_get[319:154], proc$v_to_TV_1_get[154] ? - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 : + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 : 12'hAAA, proc$v_to_TV_1_get[141], proc$v_to_TV_1_get[141] ? { proc$v_to_TV_1_get[140], proc$v_to_TV_1_get[140] ? - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 : - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 } : + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 : + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 } : 5'h0A, proc$v_to_TV_1_get[135:72], - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8, + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9, proc$v_to_TV_1_get[69:0] } ; assign v_td2_to_td_1_f_in$ENQ = CAN_FIRE_RL_mkConnectionGetPut_3 ; assign v_td2_to_td_1_f_in$DEQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; @@ -3646,44 +3546,40 @@ module mkCoreW(CLK, v_td2_to_td_1_f_in$D_OUT[255:192], v_td2_to_td_1_f_in$D_OUT[161:160] == 2'b11, v_td2_to_td_1_f_in$D_OUT[191:160], - x1_avValue_rd__h6363, - x__h6650, + x1_avValue_rd__h6208, + x__h6495, 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; assign v_td2_to_td_1_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; assign v_td2_to_td_1_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_4 ; assign v_td2_to_td_1_f_out$CLR = 1'b0 ; // remaining internal signals - assign tv_encode_RDY_reset__07_AND_proc_RDY_hart0_ser_ETC___d113 = - tv_encode$RDY_reset && proc$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N && - f_reset_requestor$FULL_N ; always@(v_td2_to_td_0_f_in$D_OUT) begin case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h5432 = 5'd0; - default: x1_avValue_rd__h5432 = 5'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h5277 = 5'd0; + default: x1_avValue_rd__h5277 = 5'd0; endcase end always@(v_td2_to_td_0_f_in$D_OUT) begin case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h5725 = 64'd0; - default: x__h5725 = 64'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x__h5570 = 64'd0; + default: x__h5570 = 64'd0; endcase end always@(v_td2_to_td_1_f_in$D_OUT) begin case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h6363 = 5'd0; - default: x1_avValue_rd__h6363 = 5'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h6208 = 5'd0; + default: x1_avValue_rd__h6208 = 5'd0; endcase end always@(v_td2_to_td_1_f_in$D_OUT) begin case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h6650 = 64'd0; - default: x__h6650 = 64'd0; + 5'd3, 5'd8, 5'd9, 5'd11: x__h6495 = 64'd0; + default: x__h6495 = 64'd0; endcase end always@(proc$v_to_TV_0_get) @@ -3774,6 +3670,18 @@ module mkCoreW(CLK, default: CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4 = 2'd2; endcase end + always@(v_td2_to_td_0_f_in$D_OUT) + begin + case (v_td2_to_td_0_f_in$D_OUT[159:155]) + 5'd2, 5'd6, 5'd7: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd13; + 5'd3, 5'd8, 5'd9, 5'd11: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd6; + 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: + CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd5; + default: CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q5 = 5'd6; + endcase + end always@(proc$v_to_TV_1_get) begin case (proc$v_to_TV_1_get[153:142]) @@ -3817,9 +3725,9 @@ module mkCoreW(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = + CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 = proc$v_to_TV_1_get[153:142]; - default: CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = + default: CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q6 = 12'd2303; endcase end @@ -3827,9 +3735,9 @@ module mkCoreW(CLK, begin case (proc$v_to_TV_1_get[139:136]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = 4'd15; + default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = 4'd15; endcase end always@(proc$v_to_TV_1_get) @@ -3848,30 +3756,18 @@ module mkCoreW(CLK, 4'd11, 4'd12, 4'd13: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = + CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 = proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = 4'd15; + default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q8 = 4'd15; endcase end always@(proc$v_to_TV_1_get) begin case (proc$v_to_TV_1_get[71:70]) 2'd0, 2'd1: - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = + CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9 = proc$v_to_TV_1_get[71:70]; - default: CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = 2'd2; - endcase - end - always@(v_td2_to_td_0_f_in$D_OUT) - begin - case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd2, 5'd6, 5'd7: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd13; - 5'd3, 5'd8, 5'd9, 5'd11: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; - 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd5; - default: CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; + default: CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q9 = 2'd2; endcase end always@(v_td2_to_td_1_f_in$D_OUT) @@ -3894,12 +3790,16 @@ module mkCoreW(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; end else begin if (rg_fromhost_addr$EN) rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_hart0_reset_delay$EN) + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY + rg_hart0_reset_delay$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; end @@ -3911,6 +3811,7 @@ module mkCoreW(CLK, initial begin rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_hart0_reset_delay = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS @@ -3923,36 +3824,55 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h7205 = $stime; - #0; - end - v__h7199 = v__h7205 / 32'd10; + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + begin + v__h6860 = $stime; + #0; + end + v__h6854 = v__h6860 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h7199); + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", + v__h6854, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - begin - v__h7403 = $stime; - #0; - end - v__h7397 = v__h7403 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + begin + v__h7003 = $stime; + #0; + end + v__h6997 = v__h7003 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h7397); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h6997, + 64'h0000000070000000, + rg_tohost_addr, + rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h7674 = $stime; - #0; - end - v__h7668 = v__h7674 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + begin + v__h15013 = $stime; + #0; + end + v__h15007 = v__h15013 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h7668); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)", + v__h15007, + 64'h0000000070000000, + start_tohost_addr, + start_fromhost_addr); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v index c78345f..b6bd69d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -306,27 +306,27 @@ module mkDM_Abstract_Commands(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2815; - reg [31 : 0] v__h3054; - reg [31 : 0] v__h3179; - reg [31 : 0] v__h3506; - reg [31 : 0] v__h3623; - reg [31 : 0] v__h3336; - reg [31 : 0] v__h4114; - reg [31 : 0] v__h2809; - reg [31 : 0] v__h3048; - reg [31 : 0] v__h3173; - reg [31 : 0] v__h3330; - reg [31 : 0] v__h3500; - reg [31 : 0] v__h3617; - reg [31 : 0] v__h4108; + reg [31 : 0] v__h2853; + reg [31 : 0] v__h3092; + reg [31 : 0] v__h3217; + reg [31 : 0] v__h3544; + reg [31 : 0] v__h3661; + reg [31 : 0] v__h3374; + reg [31 : 0] v__h4152; + reg [31 : 0] v__h2847; + reg [31 : 0] v__h3086; + reg [31 : 0] v__h3211; + reg [31 : 0] v__h3368; + reg [31 : 0] v__h3538; + reg [31 : 0] v__h3655; + reg [31 : 0] v__h4146; // synopsys translate_on // remaining internal signals - wire [63 : 0] req_data__h860; - wire [31 : 0] virt_rg_abstractcs__h706, virt_rg_command__h770; - wire [15 : 0] regno__h2639; - wire [12 : 0] x__h1321, x__h1746; + wire [63 : 0] req_data__h896; + wire [31 : 0] virt_rg_abstractcs__h742, virt_rg_command__h806; + wire [15 : 0] regno__h2677; + wire [12 : 0] x__h1357, x__h1782; wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61, @@ -352,12 +352,12 @@ module mkDM_Abstract_Commands(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_data1 or - rg_data0 or virt_rg_abstractcs__h706 or virt_rg_command__h770) + rg_data0 or virt_rg_abstractcs__h742 or virt_rg_command__h806) begin case (av_read_dm_addr) 7'h04: av_read = rg_data0; - 7'h16: av_read = virt_rg_abstractcs__h706; - 7'h17: av_read = virt_rg_command__h770; + 7'h16: av_read = virt_rg_abstractcs__h742; + 7'h17: av_read = virt_rg_command__h806; default: av_read = rg_data1; endcase end @@ -416,7 +416,7 @@ module mkDM_Abstract_Commands(CLK, EN_hart0_csr_mem_client_response_put ; // submodule f_hart0_csr_reqs - FIFO1 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_reqs$D_IN), .ENQ(f_hart0_csr_reqs$ENQ), @@ -427,7 +427,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_reqs$EMPTY_N)); // submodule f_hart0_csr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_rsps$D_IN), .ENQ(f_hart0_csr_rsps$ENQ), @@ -438,7 +438,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_rsps$EMPTY_N)); // submodule f_hart0_fpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_reqs$D_IN), .ENQ(f_hart0_fpr_reqs$ENQ), @@ -449,7 +449,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_reqs$EMPTY_N)); // submodule f_hart0_fpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_rsps$D_IN), .ENQ(f_hart0_fpr_rsps$ENQ), @@ -460,7 +460,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_rsps$EMPTY_N)); // submodule f_hart0_gpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_reqs$D_IN), .ENQ(f_hart0_gpr_reqs$ENQ), @@ -471,7 +471,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N)); // submodule f_hart0_gpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_rsps$D_IN), .ENQ(f_hart0_gpr_rsps$ENQ), @@ -611,19 +611,19 @@ module mkDM_Abstract_Commands(CLK, EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h05 ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_1 = - { 1'd1, rg_command_access_reg_regno[11:0], req_data__h860 } ; + { 1'd1, rg_command_access_reg_regno[11:0], req_data__h896 } ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 = { 1'd0, rg_command_access_reg_regno[11:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1746[4:0], req_data__h860 } ; + { 1'd1, x__h1782[4:0], req_data__h896 } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1746[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1782[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1321[4:0], req_data__h860 } ; + { 1'd1, x__h1357[4:0], req_data__h896 } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1321[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1357[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 = f_hart0_fpr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ; always@(write_dm_addr or rg_abstractcs_busy or write_dm_word) @@ -722,10 +722,10 @@ module mkDM_Abstract_Commands(CLK, assign rg_abstractcs_cmderr$EN = EN_write && write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 || - WILL_FIRE_RL_rl_gpr_read_finish || - WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_csr_read_finish || WILL_FIRE_RL_rl_csr_write_finish || + WILL_FIRE_RL_rl_gpr_read_finish || + WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_fpr_read_finish || WILL_FIRE_RL_rl_fpr_write_finish || EN_reset || @@ -897,8 +897,8 @@ module mkDM_Abstract_Commands(CLK, assign f_hart0_gpr_rsps$CLR = EN_reset ; // remaining internal signals - assign regno__h2639 = { 3'd0, rg_command_access_reg_regno } ; - assign req_data__h860 = { rg_data1, rg_data0 } ; + assign regno__h2677 = { 3'd0, rg_command_access_reg_regno } ; + assign req_data__h896 = { rg_data1, rg_data0 } ; assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38 = rg_abstractcs_busy && rg_start_reg_access && rg_command_access_reg_write && @@ -938,10 +938,10 @@ module mkDM_Abstract_Commands(CLK, rg_command_access_reg_regno < 13'h1000 ; assign rg_command_access_reg_regno_ULT_0x1020___d57 = rg_command_access_reg_regno < 13'h1020 ; - assign virt_rg_abstractcs__h706 = - { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd0 } ; - assign virt_rg_command__h770 = - { 15'd17, rg_command_access_reg_write, regno__h2639 } ; + assign virt_rg_abstractcs__h742 = + { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd2 } ; + assign virt_rg_command__h806 = + { 15'd17, rg_command_access_reg_write, regno__h2677 } ; assign write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 = write_dm_addr == 7'h16 && (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) || @@ -975,8 +975,8 @@ module mkDM_Abstract_Commands(CLK, write_dm_word[22:20] != 3'd4 && write_dm_word[22:20] != 3'd5 && write_dm_word[22:20] != 3'd6 ; - assign x__h1321 = rg_command_access_reg_regno - 13'h1000 ; - assign x__h1746 = rg_command_access_reg_regno - 13'h1020 ; + assign x__h1357 = rg_command_access_reg_regno - 13'h1000 ; + assign x__h1782 = rg_command_access_reg_regno - 13'h1020 ; // handling of inlined registers @@ -1031,14 +1031,14 @@ module mkDM_Abstract_Commands(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) begin - v__h2815 = $stime; + v__h2853 = $stime; #0; end - v__h2809 = v__h2815 / 32'd10; + v__h2847 = v__h2853 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR", - v__h2809, + v__h2847, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) @@ -1048,16 +1048,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr == 7'h17 && rg_abstractcs_busy) begin - v__h3054 = $stime; + v__h3092 = $stime; #0; end - v__h3048 = v__h3054 / 32'd10; + v__h3086 = v__h3092 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3048, + v__h3086, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1068,15 +1068,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) begin - v__h3179 = $stime; + v__h3217 = $stime; #0; end - v__h3173 = v__h3179 / 32'd10; + v__h3211 = v__h3217 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3173, + v__h3211, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1094,15 +1094,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) begin - v__h3506 = $stime; + v__h3544 = $stime; #0; end - v__h3500 = v__h3506 / 32'd10; + v__h3538 = v__h3544 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3500, + v__h3538, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1112,15 +1112,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) begin - v__h3623 = $stime; + v__h3661 = $stime; #0; end - v__h3617 = v__h3623 / 32'd10; + v__h3655 = v__h3661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3617, + v__h3655, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1130,15 +1130,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) begin - v__h3336 = $stime; + v__h3374 = $stime; #0; end - v__h3330 = v__h3336 / 32'd10; + v__h3368 = v__h3374 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3330, + v__h3368, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1201,17 +1201,17 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr != 7'h04 && write_dm_addr != 7'h05) begin - v__h4114 = $stime; + v__h4152 = $stime; #0; end - v__h4108 = v__h4114 / 32'd10; + v__h4146 = v__h4152 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 && write_dm_addr != 7'h17 && write_dm_addr != 7'h04 && write_dm_addr != 7'h05) - $write("%0d: DM_Abstract_Commands.write: [", v__h4108); + $write("%0d: DM_Abstract_Commands.write: [", v__h4146); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol"); diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v index ddcbcb2..c048133 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v @@ -29,7 +29,6 @@ // master_awqos O 4 reg // master_awregion O 4 reg // master_wvalid O 1 reg -// master_wid O 4 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg @@ -62,7 +61,6 @@ // slave_awqos I 4 reg // slave_awregion I 4 reg // slave_wvalid I 1 -// slave_wid I 4 reg // slave_wdata I 64 reg // slave_wstrb I 8 reg // slave_wlast I 1 reg @@ -127,7 +125,6 @@ module mkDM_Mem_Tap(CLK, slave_awready, slave_wvalid, - slave_wid, slave_wdata, slave_wstrb, slave_wlast, @@ -194,8 +191,6 @@ module mkDM_Mem_Tap(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -266,7 +261,6 @@ module mkDM_Mem_Tap(CLK, // action method slave_m_wvalid input slave_wvalid; - input [3 : 0] slave_wid; input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; @@ -365,9 +359,6 @@ module mkDM_Mem_Tap(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -455,7 +446,6 @@ module mkDM_Mem_Tap(CLK, master_awid, master_awqos, master_awregion, - master_wid, slave_bid, slave_rid; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; @@ -509,7 +499,7 @@ module mkDM_Mem_Tap(CLK, master_xactor_f_wr_addr$FULL_N; // ports of submodule master_xactor_f_wr_data - wire [76 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; + wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; wire master_xactor_f_wr_data$CLR, master_xactor_f_wr_data$DEQ, master_xactor_f_wr_data$EMPTY_N, @@ -549,7 +539,7 @@ module mkDM_Mem_Tap(CLK, slave_xactor_f_wr_addr$FULL_N; // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; wire slave_xactor_f_wr_data$CLR, slave_xactor_f_wr_data$DEQ, slave_xactor_f_wr_data$EMPTY_N, @@ -597,7 +587,7 @@ module mkDM_Mem_Tap(CLK, WILL_FIRE_trace_data_out_get; // remaining internal signals - wire [63 : 0] stval___1__h1532, x__h1527, y_avValue_fst__h1438; + wire [63 : 0] stval___1__h1524, x__h1519, y_avValue_fst__h1430; // action method slave_m_awvalid assign CAN_FIRE_slave_m_awvalid = 1'd1 ; @@ -692,9 +682,6 @@ module mkDM_Mem_Tap(CLK, // value method master_m_wvalid assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; - // value method master_m_wid - assign master_wid = master_xactor_f_wr_data$D_OUT[76:73] ; - // value method master_m_wdata assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; @@ -813,7 +800,7 @@ module mkDM_Mem_Tap(CLK, .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); // submodule master_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(master_xactor_f_wr_data$D_IN), @@ -869,7 +856,7 @@ module mkDM_Mem_Tap(CLK, .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), + FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(slave_xactor_f_wr_data$D_IN), .ENQ(slave_xactor_f_wr_data$ENQ), @@ -920,7 +907,7 @@ module mkDM_Mem_Tap(CLK, // submodule f_trace_data assign f_trace_data$D_IN = { 171'h12AAAAAAAAAAAAAAA955555554A0000000000000002, - x__h1527, + x__h1519, slave_xactor_f_wr_addr$D_OUT[92:29], 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign f_trace_data$ENQ = CAN_FIRE_RL_write_reqs ; @@ -1006,7 +993,7 @@ module mkDM_Mem_Tap(CLK, // submodule slave_xactor_f_wr_data assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; + { slave_wdata, slave_wstrb, slave_wlast } ; assign slave_xactor_f_wr_data$ENQ = slave_wvalid && slave_xactor_f_wr_data$FULL_N ; assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_write_reqs ; @@ -1020,12 +1007,12 @@ module mkDM_Mem_Tap(CLK, assign slave_xactor_f_wr_resp$CLR = 1'b0 ; // remaining internal signals - assign stval___1__h1532 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; - assign x__h1527 = + assign stval___1__h1524 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; + assign x__h1519 = (slave_xactor_f_wr_data$D_OUT[8:1] == 8'h0F) ? - stval___1__h1532 : - y_avValue_fst__h1438 ; - assign y_avValue_fst__h1438 = + stval___1__h1524 : + y_avValue_fst__h1430 ; + assign y_avValue_fst__h1430 = { 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ; endmodule // mkDM_Mem_Tap diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 2c47720..4ba0a0f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -12,27 +12,35 @@ // av_read O 32 // RDY_av_read O 1 const // RDY_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg // hart0_get_other_req_get O 4 reg // RDY_hart0_get_other_req_get O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 // write_dm_addr I 7 // write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg +// ndm_reset_client_response_put I 1 reg // EN_reset I 1 // EN_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_av_read I 1 unused +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: // av_read_dm_addr -> av_read @@ -71,8 +79,13 @@ module mkDM_Run_Control(CLK, EN_write, RDY_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -86,8 +99,13 @@ module mkDM_Run_Control(CLK, hart0_get_other_req_get, RDY_hart0_get_other_req_get, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get); + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put); input CLK; input RST_N; @@ -111,9 +129,15 @@ module mkDM_Run_Control(CLK, input EN_write; output RDY_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -130,24 +154,34 @@ module mkDM_Run_Control(CLK, output [3 : 0] hart0_get_other_req_get; output RDY_hart0_get_other_req_get; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // signals for module outputs reg [31 : 0] av_read; wire [3 : 0] hart0_get_other_req_get; wire RDY_av_read, RDY_dmactive, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_reset, RDY_write, dmactive, - hart0_client_run_halt_request_get; + hart0_client_run_halt_request_get, + hart0_reset_client_request_get, + ndm_reset_client_request_get; // register rg_dmcontrol_dmactive reg rg_dmcontrol_dmactive; @@ -170,6 +204,14 @@ module mkDM_Run_Control(CLK, reg rg_dmstatus_allresumeack$D_IN; wire rg_dmstatus_allresumeack$EN; + // register rg_dmstatus_allunavail + reg rg_dmstatus_allunavail; + wire rg_dmstatus_allunavail$D_IN, rg_dmstatus_allunavail$EN; + + // register rg_hart0_hasreset + reg rg_hart0_hasreset; + wire rg_hart0_hasreset$D_IN, rg_hart0_hasreset$EN; + // register rg_hart0_running reg rg_hart0_running; reg rg_hart0_running$D_IN; @@ -191,10 +233,21 @@ module mkDM_Run_Control(CLK, // ports of submodule f_hart0_reset_reqs wire f_hart0_reset_reqs$CLR, f_hart0_reset_reqs$DEQ, + f_hart0_reset_reqs$D_IN, + f_hart0_reset_reqs$D_OUT, f_hart0_reset_reqs$EMPTY_N, f_hart0_reset_reqs$ENQ, f_hart0_reset_reqs$FULL_N; + // ports of submodule f_hart0_reset_rsps + wire f_hart0_reset_rsps$CLR, + f_hart0_reset_rsps$DEQ, + f_hart0_reset_rsps$D_IN, + f_hart0_reset_rsps$D_OUT, + f_hart0_reset_rsps$EMPTY_N, + f_hart0_reset_rsps$ENQ, + f_hart0_reset_rsps$FULL_N; + // ports of submodule f_hart0_run_halt_reqs wire f_hart0_run_halt_reqs$CLR, f_hart0_run_halt_reqs$DEQ, @@ -216,42 +269,89 @@ module mkDM_Run_Control(CLK, // ports of submodule f_ndm_reset_reqs wire f_ndm_reset_reqs$CLR, f_ndm_reset_reqs$DEQ, + f_ndm_reset_reqs$D_IN, + f_ndm_reset_reqs$D_OUT, f_ndm_reset_reqs$EMPTY_N, f_ndm_reset_reqs$ENQ, f_ndm_reset_reqs$FULL_N; + // ports of submodule f_ndm_reset_rsps + wire f_ndm_reset_rsps$CLR, + f_ndm_reset_rsps$DEQ, + f_ndm_reset_rsps$D_IN, + f_ndm_reset_rsps$D_OUT, + f_ndm_reset_rsps$EMPTY_N, + f_ndm_reset_rsps$ENQ, + f_ndm_reset_rsps$FULL_N; + // rule scheduling signals - wire CAN_FIRE_RL_rl_hart0_run_rsp, + wire CAN_FIRE_RL_rl_hart0_reset_rsp, + CAN_FIRE_RL_rl_hart0_run_rsp, + CAN_FIRE_RL_rl_ndm_reset_rsp, CAN_FIRE_av_read, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, CAN_FIRE_reset, CAN_FIRE_write, + WILL_FIRE_RL_rl_hart0_reset_rsp, WILL_FIRE_RL_rl_hart0_run_rsp, + WILL_FIRE_RL_rl_ndm_reset_rsp, WILL_FIRE_av_read, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, WILL_FIRE_reset, WILL_FIRE_write; // inputs to muxes for submodule ports wire MUX_rg_dmstatus_allresumeack$write_1__SEL_2, MUX_rg_dmstatus_allresumeack$write_1__SEL_3, - MUX_rg_hart0_running$write_1__SEL_3, + MUX_rg_dmstatus_allunavail$write_1__SEL_3, + MUX_rg_hart0_hasreset$write_1__SEL_3, MUX_rg_verbosity$write_1__SEL_2; + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h2225; + reg [31 : 0] v__h2768; + reg [31 : 0] v__h2874; + reg [31 : 0] v__h2989; + reg [31 : 0] v__h3109; + reg [31 : 0] v__h3149; + reg [31 : 0] v__h2186; + reg [31 : 0] v__h1178; + reg [31 : 0] v__h1172; + reg [31 : 0] v__h2180; + reg [31 : 0] v__h2219; + reg [31 : 0] v__h2762; + reg [31 : 0] v__h2868; + reg [31 : 0] v__h2983; + reg [31 : 0] v__h3103; + reg [31 : 0] v__h3143; + // synopsys translate_on + // remaining internal signals - wire [31 : 0] haltsum__h505, - virt_rg_dmcontrol__h670, - virt_rg_dmstatus__h543; - wire write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72, - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77; + wire [31 : 0] haltsum__h699, + virt_rg_dmcontrol__h930, + virt_rg_dmstatus__h805; + wire NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93, + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53, + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57; // value method dmactive assign dmactive = rg_dmcontrol_dmactive ; @@ -265,12 +365,12 @@ module mkDM_Run_Control(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_verbosity or - virt_rg_dmcontrol__h670 or virt_rg_dmstatus__h543 or haltsum__h505) + virt_rg_dmcontrol__h930 or virt_rg_dmstatus__h805 or haltsum__h699) begin case (av_read_dm_addr) - 7'h10: av_read = virt_rg_dmcontrol__h670; - 7'h11: av_read = virt_rg_dmstatus__h543; - 7'h13, 7'h40: av_read = haltsum__h505; + 7'h10: av_read = virt_rg_dmcontrol__h930; + 7'h11: av_read = virt_rg_dmstatus__h805; + 7'h13, 7'h40: av_read = haltsum__h699; default: av_read = { 28'd0, rg_verbosity }; endcase end @@ -280,19 +380,27 @@ module mkDM_Run_Control(CLK, // action method write assign RDY_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && - f_hart0_other_reqs$FULL_N ; - assign CAN_FIRE_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && + (rg_dmstatus_allunavail || + f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && + f_hart0_run_halt_reqs$FULL_N) && f_hart0_other_reqs$FULL_N ; + assign CAN_FIRE_write = RDY_write ; assign WILL_FIRE_write = EN_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign CAN_FIRE_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = f_hart0_reset_reqs$D_OUT ; + assign RDY_hart0_reset_client_request_get = f_hart0_reset_reqs$EMPTY_N ; + assign CAN_FIRE_hart0_reset_client_request_get = + f_hart0_reset_reqs$EMPTY_N ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = f_hart0_reset_rsps$FULL_N ; + assign CAN_FIRE_hart0_reset_client_response_put = + f_hart0_reset_rsps$FULL_N ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = f_hart0_run_halt_reqs$D_OUT ; @@ -317,10 +425,18 @@ module mkDM_Run_Control(CLK, assign CAN_FIRE_hart0_get_other_req_get = f_hart0_other_reqs$EMPTY_N ; assign WILL_FIRE_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign CAN_FIRE_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = f_ndm_reset_reqs$D_OUT ; + assign RDY_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign CAN_FIRE_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign CAN_FIRE_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule f_hart0_other_reqs FIFO2 #(.width(32'd4), .guarded(32'd1)) f_hart0_other_reqs(.RST(RST_N), @@ -334,13 +450,26 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_other_reqs$EMPTY_N)); // submodule f_hart0_reset_reqs - FIFO20 #(.guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_hart0_reset_reqs$ENQ), - .DEQ(f_hart0_reset_reqs$DEQ), - .CLR(f_hart0_reset_reqs$CLR), - .FULL_N(f_hart0_reset_reqs$FULL_N), - .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_reqs$D_IN), + .ENQ(f_hart0_reset_reqs$ENQ), + .DEQ(f_hart0_reset_reqs$DEQ), + .CLR(f_hart0_reset_reqs$CLR), + .D_OUT(f_hart0_reset_reqs$D_OUT), + .FULL_N(f_hart0_reset_reqs$FULL_N), + .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + + // submodule f_hart0_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_rsps$D_IN), + .ENQ(f_hart0_reset_rsps$ENQ), + .DEQ(f_hart0_reset_rsps$DEQ), + .CLR(f_hart0_reset_rsps$CLR), + .D_OUT(f_hart0_reset_rsps$D_OUT), + .FULL_N(f_hart0_reset_rsps$FULL_N), + .EMPTY_N(f_hart0_reset_rsps$EMPTY_N)); // submodule f_hart0_run_halt_reqs FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_run_halt_reqs(.RST(RST_N), @@ -365,27 +494,52 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_run_halt_rsps$EMPTY_N)); // submodule f_ndm_reset_reqs - FIFO20 #(.guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_ndm_reset_reqs$ENQ), - .DEQ(f_ndm_reset_reqs$DEQ), - .CLR(f_ndm_reset_reqs$CLR), - .FULL_N(f_ndm_reset_reqs$FULL_N), - .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_reqs$D_IN), + .ENQ(f_ndm_reset_reqs$ENQ), + .DEQ(f_ndm_reset_reqs$DEQ), + .CLR(f_ndm_reset_reqs$CLR), + .D_OUT(f_ndm_reset_reqs$D_OUT), + .FULL_N(f_ndm_reset_reqs$FULL_N), + .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + + // submodule f_ndm_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_rsps$D_IN), + .ENQ(f_ndm_reset_rsps$ENQ), + .DEQ(f_ndm_reset_rsps$DEQ), + .CLR(f_ndm_reset_rsps$CLR), + .D_OUT(f_ndm_reset_rsps$D_OUT), + .FULL_N(f_ndm_reset_rsps$FULL_N), + .EMPTY_N(f_ndm_reset_rsps$EMPTY_N)); + + // rule RL_rl_hart0_reset_rsp + assign CAN_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + + // rule RL_rl_ndm_reset_rsp + assign CAN_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; // rule RL_rl_hart0_run_rsp - assign CAN_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; - assign WILL_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; + assign CAN_FIRE_RL_rl_hart0_run_rsp = + f_hart0_run_halt_rsps$EMPTY_N && !f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_run_rsp = CAN_FIRE_RL_rl_hart0_run_rsp ; // inputs to muxes for submodule ports assign MUX_rg_dmstatus_allresumeack$write_1__SEL_2 = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT ; + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT ; assign MUX_rg_dmstatus_allresumeack$write_1__SEL_3 = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 ; - assign MUX_rg_hart0_running$write_1__SEL_3 = EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) ; + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 ; + assign MUX_rg_dmstatus_allunavail$write_1__SEL_3 = + EN_write && + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 ; + assign MUX_rg_hart0_hasreset$write_1__SEL_3 = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 ; assign MUX_rg_verbosity$write_1__SEL_2 = EN_write && write_dm_addr == 7'h60 ; @@ -422,26 +576,47 @@ module mkDM_Run_Control(CLK, default: rg_dmstatus_allresumeack$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_dmstatus_allresumeack$EN = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT || + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT || + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 || + EN_reset ; + + // register rg_dmstatus_allunavail + assign rg_dmstatus_allunavail$D_IN = + !EN_reset && !f_ndm_reset_rsps$EMPTY_N ; + assign rg_dmstatus_allunavail$EN = EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 || + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 || + f_ndm_reset_rsps$EMPTY_N || + EN_reset ; + + // register rg_hart0_hasreset + assign rg_hart0_hasreset$D_IN = !EN_reset && !f_hart0_reset_rsps$EMPTY_N ; + assign rg_hart0_hasreset$EN = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_hart0_running always@(EN_reset or - f_hart0_run_halt_rsps$EMPTY_N or - f_hart0_run_halt_rsps$D_OUT or MUX_rg_hart0_running$write_1__SEL_3) + WILL_FIRE_RL_rl_hart0_run_rsp or + f_hart0_run_halt_rsps$D_OUT or + f_ndm_reset_rsps$EMPTY_N or + f_ndm_reset_rsps$D_OUT or + f_hart0_reset_rsps$EMPTY_N or f_hart0_reset_rsps$D_OUT) case (1'b1) EN_reset: rg_hart0_running$D_IN = 1'd1; - f_hart0_run_halt_rsps$EMPTY_N: + WILL_FIRE_RL_rl_hart0_run_rsp: rg_hart0_running$D_IN = f_hart0_run_halt_rsps$D_OUT; - MUX_rg_hart0_running$write_1__SEL_3: rg_hart0_running$D_IN = 1'd1; + f_ndm_reset_rsps$EMPTY_N: rg_hart0_running$D_IN = f_ndm_reset_rsps$D_OUT; + f_hart0_reset_rsps$EMPTY_N: + rg_hart0_running$D_IN = f_hart0_reset_rsps$D_OUT; default: rg_hart0_running$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_hart0_running$EN = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) || - f_hart0_run_halt_rsps$EMPTY_N || + f_ndm_reset_rsps$EMPTY_N || WILL_FIRE_RL_rl_hart0_run_rsp || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_verbosity @@ -455,66 +630,123 @@ module mkDM_Run_Control(CLK, assign f_hart0_other_reqs$CLR = 1'b0 ; // submodule f_hart0_reset_reqs - assign f_hart0_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - write_dm_word[29] ; - assign f_hart0_reset_reqs$DEQ = EN_hart0_get_reset_req_get ; + assign f_hart0_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_hart0_reset_reqs$ENQ = MUX_rg_hart0_hasreset$write_1__SEL_3 ; + assign f_hart0_reset_reqs$DEQ = EN_hart0_reset_client_request_get ; assign f_hart0_reset_reqs$CLR = EN_reset ; + // submodule f_hart0_reset_rsps + assign f_hart0_reset_rsps$D_IN = hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$ENQ = EN_hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$DEQ = f_hart0_reset_rsps$EMPTY_N ; + assign f_hart0_reset_rsps$CLR = EN_reset ; + // submodule f_hart0_run_halt_reqs assign f_hart0_run_halt_reqs$D_IN = write_dm_word[30] && !rg_hart0_running ; assign f_hart0_run_halt_reqs$ENQ = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 ; + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 ; assign f_hart0_run_halt_reqs$DEQ = EN_hart0_client_run_halt_request_get ; assign f_hart0_run_halt_reqs$CLR = EN_reset ; // submodule f_hart0_run_halt_rsps assign f_hart0_run_halt_rsps$D_IN = hart0_client_run_halt_response_put ; assign f_hart0_run_halt_rsps$ENQ = EN_hart0_client_run_halt_response_put ; - assign f_hart0_run_halt_rsps$DEQ = f_hart0_run_halt_rsps$EMPTY_N ; + assign f_hart0_run_halt_rsps$DEQ = CAN_FIRE_RL_rl_hart0_run_rsp ; assign f_hart0_run_halt_rsps$CLR = EN_reset ; // submodule f_ndm_reset_reqs - assign f_ndm_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] ; - assign f_ndm_reset_reqs$DEQ = EN_get_ndm_reset_req_get ; + assign f_ndm_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_ndm_reset_reqs$ENQ = MUX_rg_dmstatus_allunavail$write_1__SEL_3 ; + assign f_ndm_reset_reqs$DEQ = EN_ndm_reset_client_request_get ; assign f_ndm_reset_reqs$CLR = EN_reset ; + // submodule f_ndm_reset_rsps + assign f_ndm_reset_rsps$D_IN = ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$ENQ = EN_ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$DEQ = f_ndm_reset_rsps$EMPTY_N ; + assign f_ndm_reset_rsps$CLR = EN_reset ; + // remaining internal signals - assign haltsum__h505 = { 31'h0, !rg_hart0_running } ; - assign virt_rg_dmcontrol__h670 = + assign NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 = + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + (!write_dm_word[31] || !write_dm_word[30]) && + (write_dm_word[30] && !rg_hart0_running || + write_dm_word[31] && rg_hart0_running) ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[31] && + write_dm_word[30] && + !rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[30] && + write_dm_word[31] && + rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + write_dm_word[29] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[26] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[25:16] != 10'd0 ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[31] && + write_dm_word[30] ; + assign haltsum__h699 = { 31'h0, !rg_hart0_running } ; + assign virt_rg_dmcontrol__h930 = { 2'b0, rg_dmcontrol_hartreset, 27'd0, rg_dmcontrol_ndmreset, rg_dmcontrol_dmactive } ; - assign virt_rg_dmstatus__h543 = - { 14'b0, + assign virt_rg_dmstatus__h805 = + { 12'd0, + rg_hart0_hasreset, + rg_hart0_hasreset, rg_dmstatus_allresumeack, rg_dmstatus_allresumeack, - 4'd0, + 2'd0, + rg_dmstatus_allunavail, + rg_dmstatus_allunavail, rg_hart0_running, rg_hart0_running, !rg_hart0_running, !rg_hart0_running, 8'd130 } ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 = + assign write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 = write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && + !write_dm_word[1] ; + assign write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57 = + write_dm_word[0] && !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && !write_dm_word[1] && - !write_dm_word[29] && - (!write_dm_word[31] || !write_dm_word[30]) && - (write_dm_word[30] && !rg_hart0_running || - write_dm_word[31] && rg_hart0_running) ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 = - write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[31] && - write_dm_word[30] && - !rg_hart0_running ; + write_dm_word[29] ; // handling of inlined registers @@ -523,12 +755,16 @@ module mkDM_Run_Control(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (rg_dmcontrol_dmactive$EN) rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_dmactive$D_IN; + if (rg_dmstatus_allunavail$EN) + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY + rg_dmstatus_allunavail$D_IN; end if (rg_dmcontrol_haltreq$EN) rg_dmcontrol_haltreq <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_haltreq$D_IN; @@ -541,6 +777,8 @@ module mkDM_Run_Control(CLK, if (rg_dmstatus_allresumeack$EN) rg_dmstatus_allresumeack <= `BSV_ASSIGNMENT_DELAY rg_dmstatus_allresumeack$D_IN; + if (rg_hart0_hasreset$EN) + rg_hart0_hasreset <= `BSV_ASSIGNMENT_DELAY rg_hart0_hasreset$D_IN; if (rg_hart0_running$EN) rg_hart0_running <= `BSV_ASSIGNMENT_DELAY rg_hart0_running$D_IN; if (rg_verbosity$EN) @@ -557,6 +795,8 @@ module mkDM_Run_Control(CLK, rg_dmcontrol_hartreset = 1'h0; rg_dmcontrol_ndmreset = 1'h0; rg_dmstatus_allresumeack = 1'h0; + rg_dmstatus_allunavail = 1'h0; + rg_hart0_hasreset = 1'h0; rg_hart0_running = 1'h0; rg_verbosity = 4'hA; end @@ -571,75 +811,117 @@ module mkDM_Run_Control(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1]) - $display("DM_Run_Control.write: dmcontrol 0x%08h: ndmreset=1: resetting platform", + rg_dmstatus_allunavail) + begin + v__h2225 = $stime; + #0; + end + v__h2219 = v__h2225 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + rg_dmstatus_allunavail) + $display("%0d: %m.dmcontrol_write 0x%0h: ndm reset in progress; ignoring this write", + v__h2219, write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - write_dm_word); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" WARNING: %m.dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display(" Both ndmreset (bit 1) and hartreset (bit 29) are asserted"); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" Both ndmreset [1] and hartreset [29] are asserted"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) $display(" ndmreset has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[26]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: 'hasel' is not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + begin + v__h2768 = $stime; + #0; + end + v__h2762 = v__h2768 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hasel is not supported", + v__h2762, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[25:16] != 10'd0) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: hartsel 0x%0h not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + begin + v__h2874 = $stime; + #0; + end + v__h2868 = v__h2874 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hartsel 0x%0h not supported", + v__h2868, write_dm_word, write_dm_word[25:16]); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: haltreq=1 and resumereq=1", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + begin + v__h2989 = $stime; + #0; + end + v__h2983 = v__h2989 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: haltreq=1 and resumereq=1", + v__h2983, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) $display(" This behavior is 'undefined' in the spec; ignoring"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77) - $display("DM_Run_Control.write: hart0 resume request"); + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + begin + v__h3109 = $stime; + #0; + end + v__h3103 = v__h3109 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[30] && - write_dm_word[31] && - rg_hart0_running) - $display("DM_Run_Control.write: hart0 halt request"); + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + $display("%0d: %m.dmcontrol_write: hart0 resume request", v__h3103); + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + begin + v__h3149 = $stime; + #0; + end + v__h3143 = v__h3149 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + $display("%0d: %m.dmcontrol_write: hart0 halt request", v__h3143); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) - $display("DM_Run_Control.write: dmcontrol 0x%08h (dmactive=0): resetting Debug Module", + begin + v__h2186 = $stime; + #0; + end + v__h2180 = v__h2186 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) + $display("%0d: %m.dmcontrol_write 0x%08h (dmactive=0): resetting Debug Module", + v__h2180, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[1]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -652,7 +934,7 @@ module mkDM_Run_Control(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -663,11 +945,21 @@ module mkDM_Run_Control(CLK, write_dm_word[29]) $display(" dmactive has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 running"); + if (f_ndm_reset_rsps$EMPTY_N) + begin + v__h1178 = $stime; + #0; + end + v__h1172 = v__h1178 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && !f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 halted"); + if (f_ndm_reset_rsps$EMPTY_N) + $write("%0d: %m.rl_ndm_reset_rsp: hart running = ", v__h1172); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && f_ndm_reset_rsps$D_OUT) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && !f_ndm_reset_rsps$D_OUT) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) if (f_ndm_reset_rsps$EMPTY_N) $write("\n"); end // synopsys translate_on endmodule // mkDM_Run_Control diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v index 8a04bd0..6b4f0c3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v @@ -10,7 +10,7 @@ // av_read O 32 // RDY_av_read O 1 // RDY_write O 1 -// master_awvalid O 1 +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -21,13 +21,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -38,7 +37,7 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 @@ -60,9 +59,7 @@ // EN_av_read I 1 // // Combinational paths from inputs to outputs: -// (master_awready, master_wready, master_arready) -> RDY_write -// master_arready -> RDY_av_read -// (master_arready, av_read_dm_addr) -> av_read +// av_read_dm_addr -> av_read // // @@ -121,8 +118,6 @@ module mkDM_System_Bus(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -228,9 +223,6 @@ module mkDM_System_Bus(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -312,8 +304,7 @@ module mkDM_System_Bus(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_av_read, @@ -328,66 +319,6 @@ module mkDM_System_Bus(CLK, master_wlast, master_wvalid; - // inlined wires - wire master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - wire [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - wire [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - // register rg_sb_state reg [1 : 0] rg_sb_state; wire [1 : 0] rg_sb_state$D_IN; @@ -440,6 +371,46 @@ module mkDM_System_Bus(CLK, reg [31 : 0] rg_sbdata0$D_IN; wire rg_sbdata0$EN; + // ports of submodule master_xactor_f_rd_addr + wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT; + wire master_xactor_f_rd_addr$CLR, + master_xactor_f_rd_addr$DEQ, + master_xactor_f_rd_addr$EMPTY_N, + master_xactor_f_rd_addr$ENQ, + master_xactor_f_rd_addr$FULL_N; + + // ports of submodule master_xactor_f_rd_data + wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT; + wire master_xactor_f_rd_data$CLR, + master_xactor_f_rd_data$DEQ, + master_xactor_f_rd_data$EMPTY_N, + master_xactor_f_rd_data$ENQ, + master_xactor_f_rd_data$FULL_N; + + // ports of submodule master_xactor_f_wr_addr + wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT; + wire master_xactor_f_wr_addr$CLR, + master_xactor_f_wr_addr$DEQ, + master_xactor_f_wr_addr$EMPTY_N, + master_xactor_f_wr_addr$ENQ, + master_xactor_f_wr_addr$FULL_N; + + // ports of submodule master_xactor_f_wr_data + wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; + wire master_xactor_f_wr_data$CLR, + master_xactor_f_wr_data$DEQ, + master_xactor_f_wr_data$EMPTY_N, + master_xactor_f_wr_data$ENQ, + master_xactor_f_wr_data$FULL_N; + + // ports of submodule master_xactor_f_wr_resp + wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT; + wire master_xactor_f_wr_resp$CLR, + master_xactor_f_wr_resp$DEQ, + master_xactor_f_wr_resp$EMPTY_N, + master_xactor_f_wr_resp$ENQ, + master_xactor_f_wr_resp$FULL_N; + // rule scheduling signals wire CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, @@ -466,9 +437,9 @@ module mkDM_System_Bus(CLK, reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2, MUX_rg_sbaddress1$write_1__VAL_2; reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4; - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, + wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1, + MUX_master_xactor_f_rd_addr$enq_1__VAL_2; + wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1, MUX_rg_sbaddress0$write_1__SEL_2, MUX_rg_sbaddress0$write_1__SEL_3, MUX_rg_sbaddress1$write_1__SEL_2, @@ -485,45 +456,45 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79, - wrd_wdata__h5118; - reg [7 : 0] wrd_wstrb__h5119; - reg [2 : 0] x__h3284, x__h4989; - wire [63 : 0] _theResult___fst__h5027, - addr64__h4331, - result__h1836, - result__h1866, - result__h1893, - result__h1920, - result__h1947, - result__h1974, - result__h2001, - result__h2028, - result__h2073, - result__h2100, - result__h2127, - result__h2154, - result__h2195, - result__h2222, + wrd_wdata__h4397; + reg [7 : 0] wrd_wstrb__h4398; + reg [2 : 0] x__h2654, x__h4302; + wire [63 : 0] _theResult___fst__h4340, + addr64__h3701, + result__h1250, + result__h1280, + result__h1307, + result__h1334, + result__h1361, + result__h1388, + result__h1415, + result__h1442, + result__h1487, + result__h1514, + result__h1541, + result__h1568, + result__h1609, + result__h1636, rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104, - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300, - sbaddress__h1228, - word64__h4971; - wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311, - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302, - v__h2728, - v__h2862; - wire [7 : 0] strobe64__h5026, strobe64__h5029, strobe64__h5032; - wire [5 : 0] shift_bits__h4974; + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299, + sbaddress__h638, + word64__h4284; + wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310, + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301, + v__h2132, + v__h2266; + wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345; + wire [5 : 0] shift_bits__h4287; wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317, + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316, rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95, - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279, - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327; + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278, + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326; // action method reset assign RDY_reset = 1'd1 ; @@ -532,13 +503,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h2728 or rg_sbaddress0 or rg_sbaddress1 or v__h2862) + v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266) begin case (av_read_dm_addr) - 7'h38: av_read = v__h2728; + 7'h38: av_read = v__h2132; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h2862; + 7'h3C: av_read = v__h2266; default: av_read = 32'd0; endcase end @@ -546,7 +517,7 @@ module mkDM_System_Bus(CLK, rg_sb_state == 2'd0 && (rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadondata || - !master_xactor_crg_rd_addr_full$port2__read) ; + master_xactor_f_rd_addr$FULL_N) ; assign CAN_FIRE_av_read = RDY_av_read ; assign WILL_FIRE_av_read = EN_av_read ; @@ -556,64 +527,61 @@ module mkDM_System_Bus(CLK, (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadonaddr || - !master_xactor_crg_rd_addr_full$port2__read) && + master_xactor_f_rd_addr$FULL_N) && (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; + master_xactor_f_wr_addr$FULL_N && + master_xactor_f_wr_data$FULL_N) ; assign WILL_FIRE_write = EN_write ; // value method master_m_awvalid - assign master_awvalid = master_xactor_crg_wr_addr_full ; + assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ; // value method master_m_awid - assign master_awid = master_xactor_rg_wr_addr[96:93] ; + assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ; // value method master_m_awaddr - assign master_awaddr = master_xactor_rg_wr_addr[92:29] ; + assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ; // value method master_m_awlen - assign master_awlen = master_xactor_rg_wr_addr[28:21] ; + assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ; // value method master_m_awsize - assign master_awsize = master_xactor_rg_wr_addr[20:18] ; + assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ; // value method master_m_awburst - assign master_awburst = master_xactor_rg_wr_addr[17:16] ; + assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ; // value method master_m_awlock - assign master_awlock = master_xactor_rg_wr_addr[15] ; + assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ; // value method master_m_awcache - assign master_awcache = master_xactor_rg_wr_addr[14:11] ; + assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ; // value method master_m_awprot - assign master_awprot = master_xactor_rg_wr_addr[10:8] ; + assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ; // value method master_m_awqos - assign master_awqos = master_xactor_rg_wr_addr[7:4] ; + assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ; // value method master_m_awregion - assign master_awregion = master_xactor_rg_wr_addr[3:0] ; + assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ; // action method master_m_awready assign CAN_FIRE_master_m_awready = 1'd1 ; assign WILL_FIRE_master_m_awready = 1'd1 ; // value method master_m_wvalid - assign master_wvalid = master_xactor_crg_wr_data_full ; - - // value method master_m_wid - assign master_wid = master_xactor_rg_wr_data[76:73] ; + assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; // value method master_m_wdata - assign master_wdata = master_xactor_rg_wr_data[72:9] ; + assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; // value method master_m_wstrb - assign master_wstrb = master_xactor_rg_wr_data[8:1] ; + assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ; // value method master_m_wlast - assign master_wlast = master_xactor_rg_wr_data[0] ; + assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ; // action method master_m_wready assign CAN_FIRE_master_m_wready = 1'd1 ; @@ -624,40 +592,40 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_bvalid = 1'd1 ; // value method master_m_bready - assign master_bready = 1'b1 ; + assign master_bready = master_xactor_f_wr_resp$FULL_N ; // value method master_m_arvalid - assign master_arvalid = master_xactor_crg_rd_addr_full ; + assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ; // value method master_m_arid - assign master_arid = master_xactor_rg_rd_addr[96:93] ; + assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ; // value method master_m_araddr - assign master_araddr = master_xactor_rg_rd_addr[92:29] ; + assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ; // value method master_m_arlen - assign master_arlen = master_xactor_rg_rd_addr[28:21] ; + assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ; // value method master_m_arsize - assign master_arsize = master_xactor_rg_rd_addr[20:18] ; + assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ; // value method master_m_arburst - assign master_arburst = master_xactor_rg_rd_addr[17:16] ; + assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ; // value method master_m_arlock - assign master_arlock = master_xactor_rg_rd_addr[15] ; + assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ; // value method master_m_arcache - assign master_arcache = master_xactor_rg_rd_addr[14:11] ; + assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ; // value method master_m_arprot - assign master_arprot = master_xactor_rg_rd_addr[10:8] ; + assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ; // value method master_m_arqos - assign master_arqos = master_xactor_rg_rd_addr[7:4] ; + assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ; // value method master_m_arregion - assign master_arregion = master_xactor_rg_rd_addr[3:0] ; + assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ; // action method master_m_arready assign CAN_FIRE_master_m_arready = 1'd1 ; @@ -668,20 +636,79 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_rvalid = 1'd1 ; // value method master_m_rready - assign master_rready = !master_xactor_crg_rd_data_full$port2__read ; + assign master_rready = master_xactor_f_rd_data$FULL_N ; + + // submodule master_xactor_f_rd_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_addr$D_IN), + .ENQ(master_xactor_f_rd_addr$ENQ), + .DEQ(master_xactor_f_rd_addr$DEQ), + .CLR(master_xactor_f_rd_addr$CLR), + .D_OUT(master_xactor_f_rd_addr$D_OUT), + .FULL_N(master_xactor_f_rd_addr$FULL_N), + .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N)); + + // submodule master_xactor_f_rd_data + FIFO2 #(.width(32'd71), + .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_data$D_IN), + .ENQ(master_xactor_f_rd_data$ENQ), + .DEQ(master_xactor_f_rd_data$DEQ), + .CLR(master_xactor_f_rd_data$CLR), + .D_OUT(master_xactor_f_rd_data$D_OUT), + .FULL_N(master_xactor_f_rd_data$FULL_N), + .EMPTY_N(master_xactor_f_rd_data$EMPTY_N)); + + // submodule master_xactor_f_wr_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_addr$D_IN), + .ENQ(master_xactor_f_wr_addr$ENQ), + .DEQ(master_xactor_f_wr_addr$DEQ), + .CLR(master_xactor_f_wr_addr$CLR), + .D_OUT(master_xactor_f_wr_addr$D_OUT), + .FULL_N(master_xactor_f_wr_addr$FULL_N), + .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); + + // submodule master_xactor_f_wr_data + FIFO2 #(.width(32'd73), + .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_data$D_IN), + .ENQ(master_xactor_f_wr_data$ENQ), + .DEQ(master_xactor_f_wr_data$DEQ), + .CLR(master_xactor_f_wr_data$CLR), + .D_OUT(master_xactor_f_wr_data$D_OUT), + .FULL_N(master_xactor_f_wr_data$FULL_N), + .EMPTY_N(master_xactor_f_wr_data$EMPTY_N)); + + // submodule master_xactor_f_wr_resp + FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_resp$D_IN), + .ENQ(master_xactor_f_wr_resp$ENQ), + .DEQ(master_xactor_f_wr_resp$DEQ), + .CLR(master_xactor_f_wr_resp$CLR), + .D_OUT(master_xactor_f_wr_resp$D_OUT), + .FULL_N(master_xactor_f_wr_resp$FULL_N), + .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N)); // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = - master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 && + master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 && rg_sbcs_sberror == 3'd0 ; assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ; // rule RL_rl_sb_write_response - assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; - assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; + assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; + assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; // inputs to muxes for submodule ports - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = + assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ; assign MUX_rg_sbaddress0$write_1__SEL_2 = @@ -699,50 +726,50 @@ module mkDM_System_Bus(CLK, ((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 || + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 || write_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_1 = - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 ; + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_3 = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 ; + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_4 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ; assign MUX_rg_sbdata0$write_1__SEL_3 = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, sbaddress__h1228, 8'd0, x__h3284, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, addr64__h4331, 8'd0, x__h3284, 18'd65536 } ; + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 = + { 4'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 = + { 4'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311) + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress0$write_1__VAL_2 = - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311; + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310; default: MUX_rg_sbaddress0$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0]; endcase end always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302) + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress1$write_1__VAL_2 = - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302; + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301; default: MUX_rg_sbaddress1$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32]; endcase @@ -755,100 +782,6 @@ module mkDM_System_Bus(CLK, endcase end - // inlined wires - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full && master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full && master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full && master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_rl_sb_read_finish && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - master_rvalid && !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - assign master_xactor_rg_wr_addr$D_IN = - { 4'd0, sbaddress__h1228, 8'd0, x__h4989, 18'd65536 } ; - assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_data - assign master_xactor_rg_wr_data$D_IN = - { 4'd0, wrd_wdata__h5118, wrd_wstrb__h5119, 1'd1 } ; - assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_rg_wr_resp$EN = master_bvalid ; - // register rg_sb_state assign rg_sb_state$D_IN = (EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ; @@ -856,7 +789,7 @@ module mkDM_System_Bus(CLK, EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 || + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; @@ -904,27 +837,27 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - sbaddress__h1228 : - addr64__h4331 ; + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + sbaddress__h638 : + addr64__h3701 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; // register rg_sbcs_sbaccess assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ; assign rg_sbcs_sbaccess$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbautoincrement assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ; assign rg_sbcs_sbautoincrement$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbbusyerror @@ -941,7 +874,7 @@ module mkDM_System_Bus(CLK, assign rg_sbcs_sbbusyerror$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 || EN_reset ; // register rg_sbcs_sberror @@ -960,25 +893,25 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbcs_sberror$EN = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 || - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 || + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 || + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 || EN_reset ; // register rg_sbcs_sbreadonaddr assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ; assign rg_sbcs_sbreadonaddr$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbreadondata assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ; assign rg_sbcs_sbreadondata$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbdata0 @@ -996,42 +929,93 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbdata0$EN = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 || + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; + // submodule master_xactor_f_rd_addr + assign master_xactor_f_rd_addr$D_IN = + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + MUX_master_xactor_f_rd_addr$enq_1__VAL_1 : + MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ; + assign master_xactor_f_rd_addr$ENQ = + EN_av_read && av_read_dm_addr == 7'h3C && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || + EN_write && write_dm_addr == 7'h39 && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; + assign master_xactor_f_rd_addr$DEQ = + master_xactor_f_rd_addr$EMPTY_N && master_arready ; + assign master_xactor_f_rd_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_rd_data + assign master_xactor_f_rd_data$D_IN = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_f_rd_data$ENQ = + master_rvalid && master_xactor_f_rd_data$FULL_N ; + assign master_xactor_f_rd_data$DEQ = + master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 && + rg_sbcs_sberror == 3'd0 ; + assign master_xactor_f_rd_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_addr + assign master_xactor_f_wr_addr$D_IN = + { 4'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ; + assign master_xactor_f_wr_addr$ENQ = + EN_write && + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign master_xactor_f_wr_addr$DEQ = + master_xactor_f_wr_addr$EMPTY_N && master_awready ; + assign master_xactor_f_wr_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_data + assign master_xactor_f_wr_data$D_IN = + { wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ; + assign master_xactor_f_wr_data$ENQ = + EN_write && + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign master_xactor_f_wr_data$DEQ = + master_xactor_f_wr_data$EMPTY_N && master_wready ; + assign master_xactor_f_wr_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_resp + assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ; + assign master_xactor_f_wr_resp$ENQ = + master_bvalid && master_xactor_f_wr_resp$FULL_N ; + assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ; + assign master_xactor_f_wr_resp$CLR = 1'b0 ; + // remaining internal signals - assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311 = + assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 = rg_sbcs_sbreadonaddr ? (rg_sbcs_sbautoincrement ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[31:0] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] : write_dm_word) : write_dm_word ; - assign IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302 = + assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 = (write_dm_addr == 7'h39) ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[63:32] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] : write_dm_word ; - assign _theResult___fst__h5027 = word64__h4971 << shift_bits__h4974 ; - assign addr64__h4331 = { rg_sbaddress1, write_dm_word } ; - assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; + assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ; + assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ; + assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ; + assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ; + assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ; + assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ; + assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ; + assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ; + assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ; + assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ; + assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ; + assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ; + assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ; + assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ; + assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ; + assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ; assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadondata ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 = + assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; @@ -1040,21 +1024,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbautoincrement ; assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 = - sbaddress__h1228 + + sbaddress__h638 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300 = - addr64__h4331 + + assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 = + addr64__h3701 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 = + assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h4974 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h5026 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h5029 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h5032 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h2728 = + assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h2132 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1064,71 +1048,71 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h2862 = + assign v__h2266 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h4971 = { 32'd0, write_dm_word } ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 = + assign word64__h4284 = { 32'd0, write_dm_word } ; + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && write_dm_word[19:17] != 3'd4 && write_dm_word[19:17] != 3'd3 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 = - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 = + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || (write_dm_addr == 7'h39 || write_dm_addr == 7'h3A || write_dm_addr == 7'h3C) && rg_sb_state != 2'd0 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && rg_sbcs_sbbusyerror && !write_dm_word[22] ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && (write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ; - assign write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 = + assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 = write_dm_addr == 7'h3C && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 ; always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: x__h3284 = rg_sbcs_sbaccess; - default: x__h3284 = 3'b011; + 3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess; + default: x__h2654 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2, 3'd3: x__h4989 = rg_sbcs_sbaccess; - default: x__h4989 = 3'b111; + 3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess; + default: x__h4302 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h5026 or strobe64__h5029 or strobe64__h5032) + strobe64__h4339 or strobe64__h4342 or strobe64__h4345) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h5119 = strobe64__h5026; - 3'd1: wrd_wstrb__h5119 = strobe64__h5029; - 3'd2: wrd_wstrb__h5119 = strobe64__h5032; - 3'd3: wrd_wstrb__h5119 = 8'b11111111; - default: wrd_wstrb__h5119 = 8'd0; + 3'd0: wrd_wstrb__h4398 = strobe64__h4339; + 3'd1: wrd_wstrb__h4398 = strobe64__h4342; + 3'd2: wrd_wstrb__h4398 = strobe64__h4345; + 3'd3: wrd_wstrb__h4398 = 8'b11111111; + default: wrd_wstrb__h4398 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h4971 or _theResult___fst__h5027) + always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h5118 = _theResult___fst__h5027; - default: wrd_wdata__h5118 = word64__h4971; + 3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340; + default: wrd_wdata__h4397 = word64__h4284; endcase end always@(rg_sbcs_sbaccess) @@ -1143,68 +1127,68 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h1836 or - result__h1866 or - result__h1893 or - result__h1920 or - result__h1947 or result__h1974 or result__h2001 or result__h2028) + result__h1250 or + result__h1280 or + result__h1307 or + result__h1334 or + result__h1361 or result__h1388 or result__h1415 or result__h1442) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1836; + result__h1250; 3'h1: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1866; + result__h1280; 3'h2: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1893; + result__h1307; 3'h3: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1920; + result__h1334; 3'h4: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1947; + result__h1361; 3'h5: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1974; + result__h1388; 3'h6: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2001; + result__h1415; 3'h7: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2028; + result__h1442; endcase end always@(rg_sbaddress_reading or - result__h2073 or result__h2100 or result__h2127 or result__h2154) + result__h1487 or result__h1514 or result__h1541 or result__h1568) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2073; + result__h1487; 3'h2: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2100; + result__h1514; 3'h4: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2127; + result__h1541; 3'h6: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2154; + result__h1568; default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h2195 or result__h2222) + always@(rg_sbaddress_reading or result__h1609 or result__h1636) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2195; + result__h1609; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2222; + result__h1636; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0; endcase end @@ -1212,7 +1196,7 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or - rg_sbaddress_reading or master_xactor_rg_rd_data) + rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT) begin case (rg_sbcs_sbaccess) 3'd0: @@ -1227,7 +1211,7 @@ module mkDM_System_Bus(CLK, 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = (rg_sbaddress_reading[2:0] == 3'h0) ? - master_xactor_rg_rd_data[66:3] : + master_xactor_f_rd_data$D_OUT[66:3] : 64'd0; default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = 64'd0; @@ -1240,51 +1224,16 @@ module mkDM_System_Bus(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0; end else begin - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_sbaddress0$EN) + if (rg_sbaddress0$EN) rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN; if (rg_sbaddress1$EN) rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN; end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN; if (rg_sbaddress_reading$EN) rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN; @@ -1309,16 +1258,6 @@ module mkDM_System_Bus(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; rg_sb_state = 2'h2; rg_sbaddress0 = 32'hAAAAAAAA; rg_sbaddress1 = 32'hAAAAAAAA; @@ -1484,24 +1423,24 @@ module mkDM_System_Bus(CLK, $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" ERROR: existing sbbusyerror (%0d) is not being cleared.", rg_sbcs_sbbusyerror); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" ERROR: sbaccess "); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && @@ -1517,7 +1456,7 @@ module mkDM_System_Bus(CLK, $write("DM_SBACCESS_128_BIT"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h38 && @@ -1658,61 +1597,61 @@ module mkDM_System_Bus(CLK, $write("] <= 0x%08h; addr not supported", write_dm_word, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(" rdr = "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[70:67]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[66:3]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[2:1]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + master_xactor_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + !master_xactor_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index bcb67ff..66dbc3c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -10,7 +10,9 @@ // dmi_read_data O 32 // RDY_dmi_read_data O 1 // RDY_dmi_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg @@ -25,8 +27,10 @@ // hart0_csr_mem_client_request_get O 77 reg // RDY_hart0_csr_mem_client_request_get O 1 reg // RDY_hart0_csr_mem_client_response_put O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg -// master_awvalid O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -37,13 +41,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -54,16 +57,18 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // dmi_read_addr_dm_addr I 7 // dmi_write_dm_addr I 7 // dmi_write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg // hart0_gpr_mem_client_response_put I 65 reg // hart0_fpr_mem_client_response_put I 65 reg // hart0_csr_mem_client_response_put I 65 reg +// ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 // master_bvalid I 1 @@ -77,28 +82,24 @@ // master_rlast I 1 reg // EN_dmi_read_addr I 1 // EN_dmi_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 // EN_hart0_gpr_mem_client_response_put I 1 // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_dmi_read_data I 1 +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 // EN_hart0_gpr_mem_client_request_get I 1 // EN_hart0_fpr_mem_client_request_get I 1 // EN_hart0_csr_mem_client_request_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr) -> RDY_dmi_read_data -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr, -// EN_dmi_read_data) -> dmi_read_data -// (master_awready, master_wready, master_arready) -> RDY_dmi_write +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -131,8 +132,13 @@ module mkDebug_Module(CLK, EN_dmi_write, RDY_dmi_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -170,8 +176,13 @@ module mkDebug_Module(CLK, EN_hart0_csr_mem_client_response_put, RDY_hart0_csr_mem_client_response_put, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put, master_awvalid, @@ -199,8 +210,6 @@ module mkDebug_Module(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -265,9 +274,15 @@ module mkDebug_Module(CLK, input EN_dmi_write; output RDY_dmi_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -314,9 +329,15 @@ module mkDebug_Module(CLK, input EN_hart0_csr_mem_client_response_put; output RDY_hart0_csr_mem_client_response_put; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // value method master_m_awvalid output master_awvalid; @@ -359,9 +380,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -447,14 +465,12 @@ module mkDebug_Module(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_dmi_read_addr, RDY_dmi_read_data, RDY_dmi_write, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_csr_mem_client_request_get, @@ -462,10 +478,14 @@ module mkDebug_Module(CLK, RDY_hart0_fpr_mem_client_request_get, RDY_hart0_fpr_mem_client_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, RDY_hart0_gpr_mem_client_request_get, RDY_hart0_gpr_mem_client_response_put, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, hart0_client_run_halt_request_get, + hart0_reset_client_request_get, master_arlock, master_arvalid, master_awlock, @@ -473,7 +493,8 @@ module mkDebug_Module(CLK, master_bready, master_rready, master_wlast, - master_wvalid; + master_wvalid, + ndm_reset_client_request_get; // inlined wires wire [7 : 0] f_read_addr_rv$port0__write_1, @@ -517,22 +538,30 @@ module mkDebug_Module(CLK, wire [6 : 0] dm_run_control$av_read_dm_addr, dm_run_control$write_dm_addr; wire [3 : 0] dm_run_control$hart0_get_other_req_get; wire dm_run_control$EN_av_read, - dm_run_control$EN_get_ndm_reset_req_get, dm_run_control$EN_hart0_client_run_halt_request_get, dm_run_control$EN_hart0_client_run_halt_response_put, dm_run_control$EN_hart0_get_other_req_get, - dm_run_control$EN_hart0_get_reset_req_get, + dm_run_control$EN_hart0_reset_client_request_get, + dm_run_control$EN_hart0_reset_client_response_put, + dm_run_control$EN_ndm_reset_client_request_get, + dm_run_control$EN_ndm_reset_client_response_put, dm_run_control$EN_reset, dm_run_control$EN_write, - dm_run_control$RDY_get_ndm_reset_req_get, dm_run_control$RDY_hart0_client_run_halt_request_get, dm_run_control$RDY_hart0_client_run_halt_response_put, dm_run_control$RDY_hart0_get_other_req_get, - dm_run_control$RDY_hart0_get_reset_req_get, + dm_run_control$RDY_hart0_reset_client_request_get, + dm_run_control$RDY_hart0_reset_client_response_put, + dm_run_control$RDY_ndm_reset_client_request_get, + dm_run_control$RDY_ndm_reset_client_response_put, dm_run_control$RDY_write, dm_run_control$dmactive, dm_run_control$hart0_client_run_halt_request_get, - dm_run_control$hart0_client_run_halt_response_put; + dm_run_control$hart0_client_run_halt_response_put, + dm_run_control$hart0_reset_client_request_get, + dm_run_control$hart0_reset_client_response_put, + dm_run_control$ndm_reset_client_request_get, + dm_run_control$ndm_reset_client_response_put; // ports of submodule dm_system_bus wire [63 : 0] dm_system_bus$master_araddr, @@ -553,8 +582,7 @@ module mkDebug_Module(CLK, dm_system_bus$master_awqos, dm_system_bus$master_awregion, dm_system_bus$master_bid, - dm_system_bus$master_rid, - dm_system_bus$master_wid; + dm_system_bus$master_rid; wire [2 : 0] dm_system_bus$master_arprot, dm_system_bus$master_arsize, dm_system_bus$master_awprot, @@ -588,7 +616,6 @@ module mkDebug_Module(CLK, CAN_FIRE_dmi_read_addr, CAN_FIRE_dmi_read_data, CAN_FIRE_dmi_write, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_csr_mem_client_request_get, @@ -596,19 +623,21 @@ module mkDebug_Module(CLK, CAN_FIRE_hart0_fpr_mem_client_request_get, CAN_FIRE_hart0_fpr_mem_client_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, CAN_FIRE_hart0_gpr_mem_client_request_get, CAN_FIRE_hart0_gpr_mem_client_response_put, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, CAN_FIRE_master_m_arready, CAN_FIRE_master_m_awready, CAN_FIRE_master_m_bvalid, CAN_FIRE_master_m_rvalid, CAN_FIRE_master_m_wready, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, WILL_FIRE_RL_rl_reset, WILL_FIRE_dmi_read_addr, WILL_FIRE_dmi_read_data, WILL_FIRE_dmi_write, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_csr_mem_client_request_get, @@ -616,19 +645,22 @@ module mkDebug_Module(CLK, WILL_FIRE_hart0_fpr_mem_client_request_get, WILL_FIRE_hart0_fpr_mem_client_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, WILL_FIRE_hart0_gpr_mem_client_request_get, WILL_FIRE_hart0_gpr_mem_client_response_put, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, WILL_FIRE_master_m_arready, WILL_FIRE_master_m_awready, WILL_FIRE_master_m_bvalid, WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready; + WILL_FIRE_master_m_wready, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h887; - reg [31 : 0] v__h881; + reg [31 : 0] v__h911; + reg [31 : 0] v__h905; // synopsys translate_on // action method dmi_read_addr @@ -705,12 +737,23 @@ module mkDebug_Module(CLK, dm_run_control$RDY_write && dm_system_bus$RDY_write ; assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign CAN_FIRE_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = + dm_run_control$hart0_reset_client_request_get ; + assign RDY_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign CAN_FIRE_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign CAN_FIRE_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = @@ -792,12 +835,23 @@ module mkDebug_Module(CLK, assign WILL_FIRE_hart0_csr_mem_client_response_put = EN_hart0_csr_mem_client_response_put ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + dm_run_control$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // value method master_m_awvalid assign master_awvalid = dm_system_bus$master_awvalid ; @@ -839,9 +893,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid assign master_wvalid = dm_system_bus$master_wvalid ; - // value method master_m_wid - assign master_wid = dm_system_bus$master_wid ; - // value method master_m_wdata assign master_wdata = dm_system_bus$master_wdata ; @@ -943,29 +994,37 @@ module mkDebug_Module(CLK, .RST_N(RST_N), .av_read_dm_addr(dm_run_control$av_read_dm_addr), .hart0_client_run_halt_response_put(dm_run_control$hart0_client_run_halt_response_put), + .hart0_reset_client_response_put(dm_run_control$hart0_reset_client_response_put), + .ndm_reset_client_response_put(dm_run_control$ndm_reset_client_response_put), .write_dm_addr(dm_run_control$write_dm_addr), .write_dm_word(dm_run_control$write_dm_word), .EN_reset(dm_run_control$EN_reset), .EN_av_read(dm_run_control$EN_av_read), .EN_write(dm_run_control$EN_write), - .EN_hart0_get_reset_req_get(dm_run_control$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(dm_run_control$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(dm_run_control$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(dm_run_control$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(dm_run_control$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(dm_run_control$EN_hart0_get_other_req_get), - .EN_get_ndm_reset_req_get(dm_run_control$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(dm_run_control$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(dm_run_control$EN_ndm_reset_client_response_put), .dmactive(dm_run_control$dmactive), .RDY_dmactive(), .RDY_reset(), .av_read(dm_run_control$av_read), .RDY_av_read(), .RDY_write(dm_run_control$RDY_write), - .RDY_hart0_get_reset_req_get(dm_run_control$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(dm_run_control$hart0_reset_client_request_get), + .RDY_hart0_reset_client_request_get(dm_run_control$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(dm_run_control$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(dm_run_control$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(dm_run_control$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(dm_run_control$RDY_hart0_client_run_halt_response_put), .hart0_get_other_req_get(dm_run_control$hart0_get_other_req_get), .RDY_hart0_get_other_req_get(dm_run_control$RDY_hart0_get_other_req_get), - .RDY_get_ndm_reset_req_get(dm_run_control$RDY_get_ndm_reset_req_get)); + .ndm_reset_client_request_get(dm_run_control$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(dm_run_control$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(dm_run_control$RDY_ndm_reset_client_response_put)); // submodule dm_system_bus mkDM_System_Bus dm_system_bus(.CLK(CLK), @@ -1003,7 +1062,6 @@ module mkDebug_Module(CLK, .master_awqos(dm_system_bus$master_awqos), .master_awregion(dm_system_bus$master_awregion), .master_wvalid(dm_system_bus$master_wvalid), - .master_wid(dm_system_bus$master_wid), .master_wdata(dm_system_bus$master_wdata), .master_wstrb(dm_system_bus$master_wstrb), .master_wlast(dm_system_bus$master_wlast), @@ -1100,6 +1158,10 @@ module mkDebug_Module(CLK, assign dm_run_control$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; assign dm_run_control$hart0_client_run_halt_response_put = hart0_client_run_halt_response_put ; + assign dm_run_control$hart0_reset_client_response_put = + hart0_reset_client_response_put ; + assign dm_run_control$ndm_reset_client_response_put = + ndm_reset_client_response_put ; assign dm_run_control$write_dm_addr = dmi_write_dm_addr ; assign dm_run_control$write_dm_word = dmi_write_dm_word ; assign dm_run_control$EN_reset = WILL_FIRE_RL_rl_reset ; @@ -1128,15 +1190,20 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h40 || dmi_write_dm_addr == 7'h5F || dmi_write_dm_addr == 7'h60) ; - assign dm_run_control$EN_hart0_get_reset_req_get = - EN_hart0_get_reset_req_get ; + assign dm_run_control$EN_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + assign dm_run_control$EN_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; assign dm_run_control$EN_hart0_client_run_halt_request_get = EN_hart0_client_run_halt_request_get ; assign dm_run_control$EN_hart0_client_run_halt_response_put = EN_hart0_client_run_halt_response_put ; assign dm_run_control$EN_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - assign dm_run_control$EN_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + assign dm_run_control$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign dm_run_control$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule dm_system_bus assign dm_system_bus$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; @@ -1208,12 +1275,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h887 = $stime; + v__h911 = $stime; #0; end - v__h881 = v__h887 / 32'd10; + v__h905 = v__h911 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h881); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h905); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v index fdb8f0f..8a1a6a7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric_2x3(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric_2x3(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric_2x3(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric_2x3(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,34 +1175,57 @@ module mkFabric_2x3(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1237,7 +1233,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1245,7 +1241,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1270,52 +1266,61 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1366,7 +1371,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1411,7 +1416,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1456,7 +1461,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1501,7 +1506,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1546,7 +1551,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1602,6 +1607,8 @@ module mkFabric_2x3(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_reset, CAN_FIRE_set_verbosity, CAN_FIRE_v_from_masters_0_m_arvalid, @@ -1658,6 +1665,8 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_reset, WILL_FIRE_set_verbosity, WILL_FIRE_v_from_masters_0_m_arvalid, @@ -1687,91 +1696,152 @@ module mkFabric_2x3(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8376; - reg [31 : 0] v__h8854; - reg [31 : 0] v__h9332; - reg [31 : 0] v__h9903; - reg [31 : 0] v__h10365; - reg [31 : 0] v__h10827; - reg [31 : 0] v__h12052; - reg [31 : 0] v__h12404; - reg [31 : 0] v__h12756; - reg [31 : 0] v__h13171; - reg [31 : 0] v__h13499; - reg [31 : 0] v__h13827; - reg [31 : 0] v__h14823; - reg [31 : 0] v__h15116; - reg [31 : 0] v__h15409; - reg [31 : 0] v__h15715; - reg [31 : 0] v__h15982; - reg [31 : 0] v__h16249; - reg [31 : 0] v__h16556; - reg [31 : 0] v__h16823; - reg [31 : 0] v__h17170; - reg [31 : 0] v__h17493; - reg [31 : 0] v__h17816; - reg [31 : 0] v__h18143; - reg [31 : 0] v__h18429; - reg [31 : 0] v__h18715; - reg [31 : 0] v__h19040; - reg [31 : 0] v__h19314; - reg [31 : 0] v__h5509; - reg [31 : 0] v__h5503; - reg [31 : 0] v__h8370; - reg [31 : 0] v__h8848; - reg [31 : 0] v__h9326; - reg [31 : 0] v__h9897; - reg [31 : 0] v__h10359; - reg [31 : 0] v__h10821; - reg [31 : 0] v__h12046; - reg [31 : 0] v__h12398; - reg [31 : 0] v__h12750; - reg [31 : 0] v__h13165; - reg [31 : 0] v__h13493; - reg [31 : 0] v__h13821; - reg [31 : 0] v__h14817; - reg [31 : 0] v__h15110; - reg [31 : 0] v__h15403; - reg [31 : 0] v__h15709; - reg [31 : 0] v__h15976; - reg [31 : 0] v__h16243; - reg [31 : 0] v__h16550; - reg [31 : 0] v__h16817; - reg [31 : 0] v__h17164; - reg [31 : 0] v__h17487; - reg [31 : 0] v__h17810; - reg [31 : 0] v__h18137; - reg [31 : 0] v__h18423; - reg [31 : 0] v__h18709; - reg [31 : 0] v__h19034; - reg [31 : 0] v__h19308; + reg [31 : 0] v__h8785; + reg [31 : 0] v__h9160; + reg [31 : 0] v__h9535; + reg [31 : 0] v__h9980; + reg [31 : 0] v__h10349; + reg [31 : 0] v__h10718; + reg [31 : 0] v__h11990; + reg [31 : 0] v__h12433; + reg [31 : 0] v__h12808; + reg [31 : 0] v__h13100; + reg [31 : 0] v__h13392; + reg [31 : 0] v__h13695; + reg [31 : 0] v__h13961; + reg [31 : 0] v__h14227; + reg [31 : 0] v__h14491; + reg [31 : 0] v__h14717; + reg [31 : 0] v__h15146; + reg [31 : 0] v__h15502; + reg [31 : 0] v__h15858; + reg [31 : 0] v__h16275; + reg [31 : 0] v__h16607; + reg [31 : 0] v__h16939; + reg [31 : 0] v__h17955; + reg [31 : 0] v__h18206; + reg [31 : 0] v__h18581; + reg [31 : 0] v__h18822; + reg [31 : 0] v__h19197; + reg [31 : 0] v__h19438; + reg [31 : 0] v__h19800; + reg [31 : 0] v__h20051; + reg [31 : 0] v__h20381; + reg [31 : 0] v__h20622; + reg [31 : 0] v__h20952; + reg [31 : 0] v__h21193; + reg [31 : 0] v__h21706; + reg [31 : 0] v__h22107; + reg [31 : 0] v__h5833; + reg [31 : 0] v__h5827; + reg [31 : 0] v__h8779; + reg [31 : 0] v__h9154; + reg [31 : 0] v__h9529; + reg [31 : 0] v__h9974; + reg [31 : 0] v__h10343; + reg [31 : 0] v__h10712; + reg [31 : 0] v__h11984; + reg [31 : 0] v__h12427; + reg [31 : 0] v__h12802; + reg [31 : 0] v__h13094; + reg [31 : 0] v__h13386; + reg [31 : 0] v__h13689; + reg [31 : 0] v__h13955; + reg [31 : 0] v__h14221; + reg [31 : 0] v__h14485; + reg [31 : 0] v__h14711; + reg [31 : 0] v__h15140; + reg [31 : 0] v__h15496; + reg [31 : 0] v__h15852; + reg [31 : 0] v__h16269; + reg [31 : 0] v__h16601; + reg [31 : 0] v__h16933; + reg [31 : 0] v__h17949; + reg [31 : 0] v__h18200; + reg [31 : 0] v__h18575; + reg [31 : 0] v__h18816; + reg [31 : 0] v__h19191; + reg [31 : 0] v__h19432; + reg [31 : 0] v__h19794; + reg [31 : 0] v__h20045; + reg [31 : 0] v__h20375; + reg [31 : 0] v__h20616; + reg [31 : 0] v__h20946; + reg [31 : 0] v__h21187; + reg [31 : 0] v__h21700; + reg [31 : 0] v__h22101; // synopsys translate_on // remaining internal signals - wire NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11895, + x__h12338, + x__h18092, + x__h18718, + x__h19334, + x__h21638, + x__h22039; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + x1_avValue_rresp__h18070, + x1_avValue_rresp__h18696, + x1_avValue_rresp__h19312; + wire _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538, + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -1962,10 +2032,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2094,10 +2160,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2226,10 +2288,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2307,58 +2365,36 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2372,7 +2408,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2386,7 +2422,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2427,58 +2463,58 @@ module mkFabric_2x3(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2492,7 +2528,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2506,7 +2542,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2584,7 +2620,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2644,7 +2680,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2704,7 +2740,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2764,7 +2800,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2824,7 +2860,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2896,58 +2932,54 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2955,15 +2987,14 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2971,100 +3002,37 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; @@ -3075,7 +3043,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; @@ -3086,7 +3054,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; @@ -3097,7 +3065,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && + fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; @@ -3108,7 +3076,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && + fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; @@ -3119,7 +3087,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && + fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; @@ -3128,8 +3096,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && + fabric_v_f_wr_err_info_0$EMPTY_N && fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; @@ -3138,40 +3105,123 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && + fabric_v_f_wr_err_info_1$EMPTY_N && fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_v_f_rd_sjs_0$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_1 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_2 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_3 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_4 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_5 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3180,9 +3230,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3191,9 +3241,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3202,9 +3252,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3213,8 +3263,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3223,8 +3272,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3234,14 +3282,75 @@ module mkFabric_2x3(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + 8'd0 : + x__h18092 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + 8'd0 : + x__h18718 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + 8'd0 : + x__h19334 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? + 8'd0 : + x__h11895 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ? + 8'd0 : + x__h12338 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3251,67 +3360,156 @@ module mkFabric_2x3(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ? + 8'd0 : + x__h21638 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ? + 8'd0 : + x__h22039 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3334,10 +3532,14 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3360,41 +3562,89 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_0$DEQ = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_1$DEQ = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3405,9 +3655,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3418,9 +3666,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3504,24 +3750,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3562,17 +3808,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3635,24 +3878,24 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3693,17 +3936,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3785,12 +4025,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3849,12 +4091,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -3913,12 +4157,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -3941,56 +4187,155 @@ module mkFabric_2x3(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 = - fabric_cfg_verbosity > 4'd1 ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 = + assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + x1_avValue_rresp__h18070 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + x1_avValue_rresp__h18696 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + x1_avValue_rresp__h19312 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < + soc_map$m_plic_addr_lim ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 = + soc_map$m_mem0_controller_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h18070 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18696 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19312 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11895 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12338 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h18092 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18718 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19334 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21638 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h22039 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -4000,6 +4345,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -4008,6 +4360,27 @@ module mkFabric_2x3(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4018,6 +4391,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4030,2581 +4410,3009 @@ module mkFabric_2x3(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8376 = $stime; + v__h8785 = $stime; #0; end - v__h8370 = v__h8376 / 32'd10; + v__h8779 = v__h8785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8370, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8779, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8854 = $stime; + v__h9160 = $stime; #0; end - v__h8848 = v__h8854 / 32'd10; + v__h9154 = v__h9160 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8848, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9154, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h9332 = $stime; + v__h9535 = $stime; #0; end - v__h9326 = v__h9332 / 32'd10; + v__h9529 = v__h9535 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9326, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9529, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9980 = $stime; + #0; + end + v__h9974 = v__h9980 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9974, + $signed(32'd1), + $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10349 = $stime; + #0; + end + v__h10343 = v__h10349 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10343, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10718 = $stime; + #0; + end + v__h10712 = v__h10718 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10712, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h11990 = $stime; + #0; + end + v__h11984 = v__h11990 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h11984, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9903 = $stime; + v__h12433 = $stime; #0; end - v__h9897 = v__h9903 / 32'd10; + v__h12427 = v__h12433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9897, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12427, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10365 = $stime; - #0; - end - v__h10359 = v__h10365 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10359, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10827 = $stime; - #0; - end - v__h10821 = v__h10827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12052 = $stime; - #0; - end - v__h12046 = v__h12052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12046, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12404 = $stime; - #0; - end - v__h12398 = v__h12404 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12398, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12756 = $stime; - #0; - end - v__h12750 = v__h12756 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12750, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13171 = $stime; - #0; - end - v__h13165 = v__h13171 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13165, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13499 = $stime; - #0; - end - v__h13493 = v__h13499 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13493, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13827 = $stime; - #0; - end - v__h13821 = v__h13827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h14823 = $stime; + v__h12808 = $stime; #0; end - v__h14817 = v__h14823 / 32'd10; + v__h12802 = v__h12808 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h14817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12802, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15116 = $stime; + v__h13100 = $stime; #0; end - v__h15110 = v__h15116 / 32'd10; + v__h13094 = v__h13100 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15110, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13094, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15409 = $stime; + v__h13392 = $stime; #0; end - v__h15403 = v__h15409 / 32'd10; + v__h13386 = v__h13392 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15403, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13386, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15715 = $stime; + v__h13695 = $stime; #0; end - v__h15709 = v__h15715 / 32'd10; + v__h13689 = v__h13695 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15709, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13689, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15982 = $stime; + v__h13961 = $stime; #0; end - v__h15976 = v__h15982 / 32'd10; + v__h13955 = v__h13961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15976, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13955, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16249 = $stime; + v__h14227 = $stime; #0; end - v__h16243 = v__h16249 / 32'd10; + v__h14221 = v__h14227 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16243, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14221, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16556 = $stime; + v__h14491 = $stime; #0; end - v__h16550 = v__h16556 / 32'd10; + v__h14485 = v__h14491 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16550, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14485, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16823 = $stime; + v__h14717 = $stime; #0; end - v__h16817 = v__h16823 / 32'd10; + v__h14711 = v__h14717 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14711, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15146 = $stime; + #0; + end + v__h15140 = v__h15146 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15140, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15502 = $stime; + #0; + end + v__h15496 = v__h15502 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15496, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15858 = $stime; + #0; + end + v__h15852 = v__h15858 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15852, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16275 = $stime; + #0; + end + v__h16269 = v__h16275 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16269, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16607 = $stime; + #0; + end + v__h16601 = v__h16607 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16601, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16939 = $stime; + #0; + end + v__h16933 = v__h16939 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16933, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17170 = $stime; + v__h17955 = $stime; #0; end - v__h17164 = v__h17170 / 32'd10; + v__h17949 = v__h17955 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17164, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h17949, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18206 = $stime; + #0; + end + v__h18200 = v__h18206 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18200, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17493 = $stime; + v__h18581 = $stime; #0; end - v__h17487 = v__h17493 / 32'd10; + v__h18575 = v__h18581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17487, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18575, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h18822 = $stime; + #0; + end + v__h18816 = v__h18822 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18816, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h17816 = $stime; + v__h19197 = $stime; #0; end - v__h17810 = v__h17816 / 32'd10; + v__h19191 = v__h19197 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17810, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19191, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19438 = $stime; + #0; + end + v__h19432 = v__h19438 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19432, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18143 = $stime; + v__h19800 = $stime; #0; end - v__h18137 = v__h18143 / 32'd10; + v__h19794 = v__h19800 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18137, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19794, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20051 = $stime; + #0; + end + v__h20045 = v__h20051 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20045, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18429 = $stime; + v__h20381 = $stime; #0; end - v__h18423 = v__h18429 / 32'd10; + v__h20375 = v__h20381 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18423, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20375, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20622 = $stime; + #0; + end + v__h20616 = v__h20622 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20616, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18715 = $stime; + v__h20952 = $stime; #0; end - v__h18709 = v__h18715 / 32'd10; + v__h20946 = v__h20952 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18709, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20946, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21193 = $stime; + #0; + end + v__h21187 = v__h21193 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21187, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19040 = $stime; + v__h21706 = $stime; #0; end - v__h19034 = v__h19040 / 32'd10; + v__h21700 = v__h21706 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19034, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21700, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19314 = $stime; + v__h22107 = $stime; #0; end - v__h19308 = v__h19314 / 32'd10; + v__h22101 = v__h22107 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19308, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h22101, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5509 = $stime; + v__h5833 = $stime; #0; end - v__h5503 = v__h5509 / 32'd10; + v__h5827 = v__h5833 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5503); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5827); end // synopsys translate_on endmodule // mkFabric_2x3 diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index 1de88dc..4f4586d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1611,23 +1611,23 @@ module mkLLCache(CLK, MUX_cache_toMInfoQ$enq_1__SEL_1; // remaining internal signals - reg [63 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247, + reg [63 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q74, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q75, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q76, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q77, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q79, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q82, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q83, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q84, @@ -1650,7 +1650,7 @@ module mkLLCache(CLK, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q103, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q104, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q105, - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248, + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q259, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q226, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q227, @@ -1677,7 +1677,7 @@ module mkLLCache(CLK, CASE_cache_pipelinefirst_BIT_577_0_cache_cRqM_ETC__q97, CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q237, CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q273, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q258, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q260, IF_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2505, @@ -1738,7 +1738,6 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62, @@ -1749,9 +1748,10 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68, CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8, - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72, + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q112, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q113, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q116, @@ -1817,14 +1817,14 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q94, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q95, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q96, - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251, + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249, CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q271, CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q270, CASE_cache_rsLdToDmaQ_deqP_0_NOT_cache_rsLdToD_ETC__q267, CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q268, CASE_cache_rsStToDmaQ_deqP_0_NOT_cache_rsStToD_ETC__q3, CASE_cache_rsStToDmaQ_deqP_0_cache_rsStToDmaQ__ETC__q4, - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252, + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250, CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q272, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q262, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q106, @@ -1889,8 +1889,8 @@ module mkLLCache(CLK, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q219, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q222, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q223, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254, SEL_ARR_NOT_cache_toCQ_data_0_534_BIT_583_535__ETC___d3541, SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706, x__h231129, @@ -3772,7 +3772,7 @@ module mkLLCache(CLK, SEL_ARR_cache_rqFromDmaQ_data_0_367_BIT_580_81_ETC___d2044, _1_CONCAT_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_ETC___d2062 } ; assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2 = - { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + { !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882, SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2164 } ; assign MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1 = @@ -5778,7 +5778,7 @@ module mkLLCache(CLK, cache_cRqMshr$pipelineResp_getAddrSucc, 1'd0 } ; assign IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_ETC___d1884 = - (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + (!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882) ? 2'd3 : 2'd1 ; @@ -6680,131 +6680,131 @@ module mkLLCache(CLK, perfReqQ_enqReq_lat_0$wget[4] : perfReqQ_enqReq_rl[4] ; assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 = - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 || - !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1822 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1824 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1826 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1828 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1830 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1832 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1834 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1836 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1838 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1840 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1842 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1844 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1846 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1848 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1850 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1852 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1854 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1856 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1858 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1860 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1862 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1864 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1866 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1868 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1870 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1872 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 || - NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 ; - assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882 = + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1874 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 = !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 || !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 || + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1876 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 || + NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1878 ; + assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1882 = + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 || + !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 || NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_367_BI_ETC___d1880 ; assign NOT_SEL_ARR_NOT_cache_rsFromCQ_data_0_171_BIT__ETC___d2229 = - { !CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251, + { !CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249, SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2223, x__h255367 } ; assign NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3038 = @@ -7010,8 +7010,8 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81 } ; assign SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2164 = { SEL_ARR_cache_rqFromDmaQ_data_0_367_BITS_516_T_ETC___d2155, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 } ; + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 } ; assign SEL_ARR_cache_rqFromDmaQ_data_0_367_BIT_580_81_ETC___d1894 = { CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q94, @@ -7138,21 +7138,21 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205 = - { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 } ; + { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2214 = { SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2205, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q78, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q79 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2223 = { SEL_ARR_cache_rsFromCQ_data_0_171_BITS_512_TO__ETC___d2214, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 } ; + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 } ; assign SEL_ARR_cache_rsFromCQ_data_0_171_BITS_579_TO__ETC___d2230 = - { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253, - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254, + { CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251, + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252, NOT_SEL_ARR_NOT_cache_rsFromCQ_data_0_171_BIT__ETC___d2229 } ; assign SEL_ARR_cache_rsFromMQ_data_0_234_BITS_516_TO__ETC___d2267 = { CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q82, @@ -7190,7 +7190,7 @@ module mkLLCache(CLK, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q105 } ; assign SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3607 = { SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3602, - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248, + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246, SEL_ARR_cache_toCQ_data_0_534_BITS_66_TO_3_543_ETC___d3546 } ; assign SEL_ARR_cache_toCQ_data_0_534_BITS_582_TO_519__ETC___d3615 = { CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q259, @@ -7198,7 +7198,7 @@ module mkLLCache(CLK, SEL_ARR_cache_toCQ_data_0_534_BIT_516_565_cach_ETC___d3614 } ; assign SEL_ARR_cache_toCQ_data_0_534_BIT_516_565_cach_ETC___d3614 = { x__h384525, - !CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252, + !CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250, SEL_ARR_cache_toCQ_data_0_534_BITS_514_TO_451__ETC___d3607, x__h386046 } ; assign SEL_ARR_cache_toMQ_data_0_699_BITS_511_TO_448__ETC___d4031 = @@ -7341,8 +7341,8 @@ module mkLLCache(CLK, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q223 } ; assign SEL_ARR_cache_toMQ_data_0_699_BIT_575_726_cach_ETC___d4013 = { SEL_ARR_cache_toMQ_data_0_699_BIT_575_726_cach_ETC___d4004, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244, - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 } ; + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253, + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 } ; assign _0_CONCAT_IF_cache_pipeline_first__533_BITS_521_ETC___d2993 = { 1'd0, cache_pipeline_first__533_BITS_521_TO_520_551__ETC___d2552 ? @@ -7756,6 +7756,14 @@ module mkLLCache(CLK, cache_rsStToDmaQ_data_1[2:0]; endcase end + always@(cache_rqFromCQ_deqP or + cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) + begin + case (cache_rqFromCQ_deqP) + 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; + 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; + endcase + end always@(cache_cRqRetryIndexQ_deqP or cache_cRqRetryIndexQ_data_0 or cache_cRqRetryIndexQ_data_1 or @@ -7792,14 +7800,6 @@ module mkLLCache(CLK, 4'd15: x__h230768 = cache_cRqRetryIndexQ_data_15; endcase end - always@(cache_rqFromCQ_deqP or - cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) - begin - case (cache_rqFromCQ_deqP) - 1'd0: x__h237718 = cache_rqFromCQ_data_0[3:1]; - 1'd1: x__h237718 = cache_rqFromCQ_data_1[3:1]; - endcase - end always@(cache_rqFromCQ_deqP or cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) begin @@ -7860,783 +7860,15 @@ module mkLLCache(CLK, 1'd1: x__h255367 = cache_rsFromCQ_data_1[0]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = - !cache_rqFromDmaQ_data_0[578]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 = - !cache_rqFromDmaQ_data_1[578]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = - !cache_rqFromDmaQ_data_0[579]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 = - !cache_rqFromDmaQ_data_1[579]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = - !cache_rqFromDmaQ_data_0[580]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 = - !cache_rqFromDmaQ_data_1[580]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = - !cache_rqFromDmaQ_data_0[576]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 = - !cache_rqFromDmaQ_data_1[576]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = - !cache_rqFromDmaQ_data_0[577]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = - !cache_rqFromDmaQ_data_1[577]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = - !cache_rqFromDmaQ_data_0[574]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = - !cache_rqFromDmaQ_data_1[574]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = - !cache_rqFromDmaQ_data_0[575]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = - !cache_rqFromDmaQ_data_1[575]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = - !cache_rqFromDmaQ_data_0[572]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = - !cache_rqFromDmaQ_data_1[572]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = - !cache_rqFromDmaQ_data_0[573]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = - !cache_rqFromDmaQ_data_1[573]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = - !cache_rqFromDmaQ_data_0[570]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = - !cache_rqFromDmaQ_data_1[570]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = - !cache_rqFromDmaQ_data_0[571]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = - !cache_rqFromDmaQ_data_1[571]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = - !cache_rqFromDmaQ_data_0[568]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = - !cache_rqFromDmaQ_data_1[568]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = - !cache_rqFromDmaQ_data_0[569]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = - !cache_rqFromDmaQ_data_1[569]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = - !cache_rqFromDmaQ_data_0[566]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = - !cache_rqFromDmaQ_data_1[566]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = - !cache_rqFromDmaQ_data_0[567]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = - !cache_rqFromDmaQ_data_1[567]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = - !cache_rqFromDmaQ_data_0[564]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = - !cache_rqFromDmaQ_data_1[564]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = - !cache_rqFromDmaQ_data_0[565]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = - !cache_rqFromDmaQ_data_1[565]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = - !cache_rqFromDmaQ_data_0[562]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = - !cache_rqFromDmaQ_data_1[562]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = - !cache_rqFromDmaQ_data_0[563]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = - !cache_rqFromDmaQ_data_1[563]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = - !cache_rqFromDmaQ_data_0[560]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = - !cache_rqFromDmaQ_data_1[560]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = - !cache_rqFromDmaQ_data_0[561]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = - !cache_rqFromDmaQ_data_1[561]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = - !cache_rqFromDmaQ_data_0[558]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = - !cache_rqFromDmaQ_data_1[558]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = - !cache_rqFromDmaQ_data_0[559]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = - !cache_rqFromDmaQ_data_1[559]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = - !cache_rqFromDmaQ_data_0[556]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = - !cache_rqFromDmaQ_data_1[556]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = - !cache_rqFromDmaQ_data_0[557]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = - !cache_rqFromDmaQ_data_1[557]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = - !cache_rqFromDmaQ_data_0[554]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = - !cache_rqFromDmaQ_data_1[554]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = - !cache_rqFromDmaQ_data_0[555]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = - !cache_rqFromDmaQ_data_1[555]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = - !cache_rqFromDmaQ_data_0[552]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = - !cache_rqFromDmaQ_data_1[552]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = - !cache_rqFromDmaQ_data_0[553]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = - !cache_rqFromDmaQ_data_1[553]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = - !cache_rqFromDmaQ_data_0[550]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = - !cache_rqFromDmaQ_data_1[550]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = - !cache_rqFromDmaQ_data_0[551]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = - !cache_rqFromDmaQ_data_1[551]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = - !cache_rqFromDmaQ_data_0[548]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = - !cache_rqFromDmaQ_data_1[548]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = - !cache_rqFromDmaQ_data_0[549]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = - !cache_rqFromDmaQ_data_1[549]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = - !cache_rqFromDmaQ_data_0[546]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = - !cache_rqFromDmaQ_data_1[546]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = - !cache_rqFromDmaQ_data_0[547]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = - !cache_rqFromDmaQ_data_1[547]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = - !cache_rqFromDmaQ_data_0[544]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = - !cache_rqFromDmaQ_data_1[544]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = - !cache_rqFromDmaQ_data_0[545]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = - !cache_rqFromDmaQ_data_1[545]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = - !cache_rqFromDmaQ_data_0[542]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = - !cache_rqFromDmaQ_data_1[542]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = - !cache_rqFromDmaQ_data_0[543]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = - !cache_rqFromDmaQ_data_1[543]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = - !cache_rqFromDmaQ_data_0[540]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = - !cache_rqFromDmaQ_data_1[540]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = - !cache_rqFromDmaQ_data_0[541]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = - !cache_rqFromDmaQ_data_1[541]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = - !cache_rqFromDmaQ_data_0[538]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = - !cache_rqFromDmaQ_data_1[538]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = - !cache_rqFromDmaQ_data_0[539]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = - !cache_rqFromDmaQ_data_1[539]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = - !cache_rqFromDmaQ_data_0[536]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = - !cache_rqFromDmaQ_data_1[536]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = - !cache_rqFromDmaQ_data_0[537]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = - !cache_rqFromDmaQ_data_1[537]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = - !cache_rqFromDmaQ_data_0[534]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = - !cache_rqFromDmaQ_data_1[534]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = - !cache_rqFromDmaQ_data_0[535]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = - !cache_rqFromDmaQ_data_1[535]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = - !cache_rqFromDmaQ_data_0[532]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = - !cache_rqFromDmaQ_data_1[532]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = - !cache_rqFromDmaQ_data_0[533]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = - !cache_rqFromDmaQ_data_1[533]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = - !cache_rqFromDmaQ_data_0[530]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = - !cache_rqFromDmaQ_data_1[530]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = - !cache_rqFromDmaQ_data_0[531]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = - !cache_rqFromDmaQ_data_1[531]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = - !cache_rqFromDmaQ_data_0[528]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = - !cache_rqFromDmaQ_data_1[528]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = - !cache_rqFromDmaQ_data_0[529]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = - !cache_rqFromDmaQ_data_1[529]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = - !cache_rqFromDmaQ_data_0[526]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = - !cache_rqFromDmaQ_data_1[526]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = - !cache_rqFromDmaQ_data_0[527]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = - !cache_rqFromDmaQ_data_1[527]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = - !cache_rqFromDmaQ_data_0[524]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = - !cache_rqFromDmaQ_data_1[524]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = - !cache_rqFromDmaQ_data_0[525]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = - !cache_rqFromDmaQ_data_1[525]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = - !cache_rqFromDmaQ_data_0[522]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = - !cache_rqFromDmaQ_data_1[522]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = - !cache_rqFromDmaQ_data_0[523]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = - !cache_rqFromDmaQ_data_1[523]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = - !cache_rqFromDmaQ_data_0[520]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = - !cache_rqFromDmaQ_data_1[520]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = - !cache_rqFromDmaQ_data_0[521]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = - !cache_rqFromDmaQ_data_1[521]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = - !cache_rqFromDmaQ_data_0[518]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = - !cache_rqFromDmaQ_data_1[518]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = - !cache_rqFromDmaQ_data_0[519]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = - !cache_rqFromDmaQ_data_1[519]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = - !cache_rqFromDmaQ_data_0[517]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = - !cache_rqFromDmaQ_data_1[517]; - endcase - end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = cache_rsFromCQ_data_0[512:449]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q6 = cache_rsFromCQ_data_1[512:449]; endcase end @@ -8645,10 +7877,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = cache_rsFromCQ_data_0[448:385]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q7 = cache_rsFromCQ_data_1[448:385]; endcase end @@ -8657,10 +7889,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = cache_rsFromCQ_data_0[384:321]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q8 = cache_rsFromCQ_data_1[384:321]; endcase end @@ -8669,13 +7901,781 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = cache_rsFromCQ_data_0[320:257]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q73 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q9 = cache_rsFromCQ_data_1[320:257]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + !cache_rqFromDmaQ_data_0[578]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 = + !cache_rqFromDmaQ_data_1[578]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + !cache_rqFromDmaQ_data_0[579]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 = + !cache_rqFromDmaQ_data_1[579]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + !cache_rqFromDmaQ_data_0[580]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 = + !cache_rqFromDmaQ_data_1[580]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + !cache_rqFromDmaQ_data_0[576]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 = + !cache_rqFromDmaQ_data_1[576]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + !cache_rqFromDmaQ_data_0[577]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 = + !cache_rqFromDmaQ_data_1[577]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + !cache_rqFromDmaQ_data_0[574]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 = + !cache_rqFromDmaQ_data_1[574]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + !cache_rqFromDmaQ_data_0[575]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 = + !cache_rqFromDmaQ_data_1[575]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + !cache_rqFromDmaQ_data_0[572]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 = + !cache_rqFromDmaQ_data_1[572]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + !cache_rqFromDmaQ_data_0[573]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 = + !cache_rqFromDmaQ_data_1[573]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + !cache_rqFromDmaQ_data_0[570]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 = + !cache_rqFromDmaQ_data_1[570]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + !cache_rqFromDmaQ_data_0[571]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 = + !cache_rqFromDmaQ_data_1[571]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + !cache_rqFromDmaQ_data_0[568]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 = + !cache_rqFromDmaQ_data_1[568]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + !cache_rqFromDmaQ_data_0[569]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 = + !cache_rqFromDmaQ_data_1[569]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + !cache_rqFromDmaQ_data_0[566]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 = + !cache_rqFromDmaQ_data_1[566]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + !cache_rqFromDmaQ_data_0[567]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 = + !cache_rqFromDmaQ_data_1[567]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + !cache_rqFromDmaQ_data_0[564]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 = + !cache_rqFromDmaQ_data_1[564]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + !cache_rqFromDmaQ_data_0[565]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 = + !cache_rqFromDmaQ_data_1[565]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + !cache_rqFromDmaQ_data_0[562]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 = + !cache_rqFromDmaQ_data_1[562]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + !cache_rqFromDmaQ_data_0[563]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 = + !cache_rqFromDmaQ_data_1[563]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + !cache_rqFromDmaQ_data_0[560]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 = + !cache_rqFromDmaQ_data_1[560]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + !cache_rqFromDmaQ_data_0[561]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 = + !cache_rqFromDmaQ_data_1[561]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + !cache_rqFromDmaQ_data_0[558]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 = + !cache_rqFromDmaQ_data_1[558]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + !cache_rqFromDmaQ_data_0[559]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 = + !cache_rqFromDmaQ_data_1[559]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + !cache_rqFromDmaQ_data_0[556]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 = + !cache_rqFromDmaQ_data_1[556]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + !cache_rqFromDmaQ_data_0[557]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 = + !cache_rqFromDmaQ_data_1[557]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + !cache_rqFromDmaQ_data_0[554]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 = + !cache_rqFromDmaQ_data_1[554]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + !cache_rqFromDmaQ_data_0[555]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 = + !cache_rqFromDmaQ_data_1[555]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + !cache_rqFromDmaQ_data_0[552]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 = + !cache_rqFromDmaQ_data_1[552]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + !cache_rqFromDmaQ_data_0[553]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 = + !cache_rqFromDmaQ_data_1[553]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + !cache_rqFromDmaQ_data_0[550]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 = + !cache_rqFromDmaQ_data_1[550]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + !cache_rqFromDmaQ_data_0[551]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 = + !cache_rqFromDmaQ_data_1[551]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + !cache_rqFromDmaQ_data_0[548]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 = + !cache_rqFromDmaQ_data_1[548]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + !cache_rqFromDmaQ_data_0[549]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 = + !cache_rqFromDmaQ_data_1[549]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + !cache_rqFromDmaQ_data_0[546]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 = + !cache_rqFromDmaQ_data_1[546]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + !cache_rqFromDmaQ_data_0[547]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 = + !cache_rqFromDmaQ_data_1[547]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + !cache_rqFromDmaQ_data_0[544]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 = + !cache_rqFromDmaQ_data_1[544]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + !cache_rqFromDmaQ_data_0[545]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 = + !cache_rqFromDmaQ_data_1[545]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + !cache_rqFromDmaQ_data_0[542]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 = + !cache_rqFromDmaQ_data_1[542]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + !cache_rqFromDmaQ_data_0[543]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 = + !cache_rqFromDmaQ_data_1[543]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + !cache_rqFromDmaQ_data_0[540]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 = + !cache_rqFromDmaQ_data_1[540]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + !cache_rqFromDmaQ_data_0[541]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 = + !cache_rqFromDmaQ_data_1[541]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + !cache_rqFromDmaQ_data_0[538]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 = + !cache_rqFromDmaQ_data_1[538]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + !cache_rqFromDmaQ_data_0[539]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 = + !cache_rqFromDmaQ_data_1[539]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + !cache_rqFromDmaQ_data_0[536]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 = + !cache_rqFromDmaQ_data_1[536]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + !cache_rqFromDmaQ_data_0[537]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 = + !cache_rqFromDmaQ_data_1[537]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + !cache_rqFromDmaQ_data_0[534]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 = + !cache_rqFromDmaQ_data_1[534]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + !cache_rqFromDmaQ_data_0[535]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 = + !cache_rqFromDmaQ_data_1[535]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + !cache_rqFromDmaQ_data_0[532]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 = + !cache_rqFromDmaQ_data_1[532]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + !cache_rqFromDmaQ_data_0[533]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 = + !cache_rqFromDmaQ_data_1[533]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + !cache_rqFromDmaQ_data_0[530]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 = + !cache_rqFromDmaQ_data_1[530]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + !cache_rqFromDmaQ_data_0[531]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 = + !cache_rqFromDmaQ_data_1[531]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + !cache_rqFromDmaQ_data_0[528]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 = + !cache_rqFromDmaQ_data_1[528]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + !cache_rqFromDmaQ_data_0[529]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 = + !cache_rqFromDmaQ_data_1[529]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + !cache_rqFromDmaQ_data_0[526]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 = + !cache_rqFromDmaQ_data_1[526]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + !cache_rqFromDmaQ_data_0[527]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 = + !cache_rqFromDmaQ_data_1[527]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + !cache_rqFromDmaQ_data_0[524]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 = + !cache_rqFromDmaQ_data_1[524]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + !cache_rqFromDmaQ_data_0[525]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 = + !cache_rqFromDmaQ_data_1[525]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + !cache_rqFromDmaQ_data_0[522]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 = + !cache_rqFromDmaQ_data_1[522]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + !cache_rqFromDmaQ_data_0[523]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 = + !cache_rqFromDmaQ_data_1[523]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + !cache_rqFromDmaQ_data_0[520]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q69 = + !cache_rqFromDmaQ_data_1[520]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + !cache_rqFromDmaQ_data_0[521]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q70 = + !cache_rqFromDmaQ_data_1[521]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + !cache_rqFromDmaQ_data_0[518]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q71 = + !cache_rqFromDmaQ_data_1[518]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + !cache_rqFromDmaQ_data_0[519]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q72 = + !cache_rqFromDmaQ_data_1[519]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + !cache_rqFromDmaQ_data_0[517]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q73 = + !cache_rqFromDmaQ_data_1[517]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -9003,6 +9003,17 @@ module mkLLCache(CLK, !cache_toCQ_data_1[583]; endcase end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = + !cache_toMQ_data_0[640]; + 1'd1: + SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = + !cache_toMQ_data_1[640]; + endcase + end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) @@ -9070,17 +9081,6 @@ module mkLLCache(CLK, endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = - !cache_toMQ_data_0[640]; - 1'd1: - SEL_ARR_NOT_cache_toMQ_data_0_699_BIT_640_700__ETC___d3706 = - !cache_toMQ_data_1[640]; - endcase - end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) 1'd0: @@ -10679,37 +10679,15 @@ module mkLLCache(CLK, cache_rsLdToDmaQ_data_1[260:197]; endcase end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244 = - cache_toMQ_data_0[513]; - 1'd1: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q244 = - cache_toMQ_data_1[513]; - endcase - end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 = - cache_toMQ_data_0[512]; - 1'd1: - CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q245 = - cache_toMQ_data_1[512]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244 = cache_rqFromDmaQ_data_0[132:69]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q246 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q244 = cache_rqFromDmaQ_data_1[132:69]; endcase end @@ -10718,10 +10696,10 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 = cache_rqFromDmaQ_data_0[68:5]; 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q247 = + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q245 = cache_rqFromDmaQ_data_1[68:5]; endcase end @@ -10729,10 +10707,10 @@ module mkLLCache(CLK, begin case (cache_toCQ_deqP) 1'd0: - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 = + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246 = cache_toCQ_data_0[130:67]; 1'd1: - CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 = + CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q246 = cache_toCQ_data_1[130:67]; endcase end @@ -10741,10 +10719,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247 = cache_rsFromCQ_data_0[128:65]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q249 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q247 = cache_rsFromCQ_data_1[128:65]; endcase end @@ -10753,10 +10731,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 = cache_rsFromCQ_data_0[64:1]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q250 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q248 = cache_rsFromCQ_data_1[64:1]; endcase end @@ -10833,10 +10811,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251 = + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249 = !cache_rsFromCQ_data_0[513]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q251 = + CASE_cache_rsFromCQ_deqP_0_NOT_cache_rsFromCQ__ETC__q249 = !cache_rsFromCQ_data_1[513]; endcase end @@ -10844,10 +10822,10 @@ module mkLLCache(CLK, begin case (cache_toCQ_deqP) 1'd0: - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252 = + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250 = !cache_toCQ_data_0[515]; 1'd1: - CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q252 = + CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q250 = !cache_toCQ_data_1[515]; endcase end @@ -10856,10 +10834,10 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251 = cache_rsFromCQ_data_0[579:516]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q253 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q251 = cache_rsFromCQ_data_1[579:516]; endcase end @@ -10868,14 +10846,36 @@ module mkLLCache(CLK, begin case (cache_rsFromCQ_deqP) 1'd0: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252 = cache_rsFromCQ_data_0[515:514]; 1'd1: - CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q254 = + CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q252 = cache_rsFromCQ_data_1[515:514]; endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253 = + cache_toMQ_data_0[513]; + 1'd1: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q253 = + cache_toMQ_data_1[513]; + endcase + end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 = + cache_toMQ_data_0[512]; + 1'd1: + CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q254 = + cache_toMQ_data_1[512]; + endcase + end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) 1'd0: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index a3e2152..2bc3b30 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1376,12 +1376,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_511_EQ_0_512_THEN_m__ETC___d3768; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5; reg [47 : 0] y_avValue_info_tag__h195314; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_IF_m_pipe_enq2Mat_lat_0_whas__77_TH_ETC___d3401; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3212, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310; @@ -3943,11 +3943,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5, IF_send_r_BITS_583_TO_582_511_EQ_0_512_THEN_m__ETC___d3789 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5911,7 +5911,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -9970,38 +9970,25 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10516,75 +10503,6 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3399; endcase end - always@(way__h173542 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308) - begin - case (way__h173542) - 4'd0: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218; - 4'd1: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224; - 4'd2: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230; - 4'd3: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236; - 4'd4: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242; - 4'd5: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248; - 4'd6: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254; - 4'd7: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260; - 4'd8: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266; - 4'd9: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272; - 4'd10: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278; - 4'd11: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284; - 4'd12: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290; - 4'd13: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296; - 4'd14: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302; - 4'd15: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; - endcase - end always@(way__h173542 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or @@ -10654,6 +10572,75 @@ module mkLLPipeline(CLK, IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; endcase end + always@(way__h173542 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308) + begin + case (way__h173542) + 4'd0: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218; + 4'd1: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224; + 4'd2: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3230; + 4'd3: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3236; + 4'd4: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3242; + 4'd5: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3248; + 4'd6: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3254; + 4'd7: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3260; + 4'd8: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3266; + 4'd9: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3272; + 4'd10: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3278; + 4'd11: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3284; + 4'd12: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3290; + 4'd13: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3296; + 4'd14: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3302; + 4'd15: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3310 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; + endcase + end always@(way__h173542 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3406 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3411 or @@ -10723,6 +10710,19 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3481; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q5 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end // handling of inlined registers diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index 1344419..dc42889 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -25072,75 +25072,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or @@ -25210,6 +25141,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11057 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25376,6 +25376,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -25528,75 +25597,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[65]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11112 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11110; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25680,6 +25680,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11114 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11115 or @@ -25832,75 +25901,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[63]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11132; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11133; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11134; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11135; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11136; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11137; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11138; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11139; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11140; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11141; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11142; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11143; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11144; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11145; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11146; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11149 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25984,75 +25984,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[62]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or @@ -26122,6 +26053,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11186 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26288,75 +26288,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[60]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -26426,6 +26357,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11223 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26592,75 +26592,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[58]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or @@ -26730,6 +26661,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11240; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11243; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11244; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11245; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11246; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11247; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11248; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11249; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11250; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11251; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11252; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11253; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11254; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11255; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11256; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11257; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11260 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11258; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -26896,75 +26896,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[56]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11262 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11263 or @@ -27034,6 +26965,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11277; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11280; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11281; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11282; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11283; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11284; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11285; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11286; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11287; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11288; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11289; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11290; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11291; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11292; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11293; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11294; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11297 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11295; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27200,75 +27200,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[54]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11299 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11300 or @@ -27338,6 +27269,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11334 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -27808,75 +27808,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[50]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or @@ -27946,6 +27877,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11388; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11391; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11392; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11393; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11394; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11395; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11396; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11397; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11398; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11399; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11400; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11401; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11402; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11403; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11404; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11405; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11408 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11406; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -28112,75 +28112,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[48]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11410 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11411 or @@ -28250,6 +28181,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11430; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11431; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11432; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11433; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11434; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11435; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11436; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11437; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11438; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11439; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11440; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11441; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11442; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11445 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -29024,75 +29024,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[42]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11521 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11522 or @@ -29162,6 +29093,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11536; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11539; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11540; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11541; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11542; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11543; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11544; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11545; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11546; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11547; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11548; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11549; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11550; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11551; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11552; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11553; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d11556 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34535,6 +34535,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34671,73 +34738,6 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end - always@(transfer_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_1_whas_THEN_m_reqVec_ETC___d10602 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getSlot_n or m_slotVec_0_dummy2_0_read__2303_AND_m_slotVec__ETC___d12503 or m_slotVec_1_dummy2_0_read__2308_AND_m_slotVec__ETC___d12504 or @@ -35083,6 +35083,75 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2378_AND_m_slotVec_ETC___d12418; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; + endcase + end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2568_AND_m_dat_ETC___d12573 or m_dataValidVec_1_dummy2_0_read__2574_AND_m_dat_ETC___d12579 or @@ -35221,75 +35290,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or @@ -35360,72 +35360,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11058; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11059; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11060; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11023; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11061; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11024; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11062; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11025; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11063; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11026; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11064; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11027; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11065; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11028; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11066; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11029; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11067; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11030; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11068; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11031; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11069; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11032; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11070; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11033; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11071; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11034; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11072; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11035; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11036; endcase end always@(sendRsToDmaC_getRq_n or @@ -35842,75 +35842,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -35980,6 +35911,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11203; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11206; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11207; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11208; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11209; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11210; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11211; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11212; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11213; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11214; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11215; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11216; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11217; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11218; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11219; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11220; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13044 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11221; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11225 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11226 or @@ -36257,72 +36257,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; endcase end always@(sendRsToDmaC_getRq_n or @@ -36394,75 +36394,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11319; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11320; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11321; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11322; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11323; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11324; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11325; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11326; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11327; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11328; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11329; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11330; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11331; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or @@ -36532,6 +36463,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11356; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11357; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11358; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11359; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11360; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11361; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11362; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11363; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11364; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11365; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11366; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11367; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11368; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13056 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11369; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11373 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11374 or @@ -36739,6 +36739,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11425; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11428 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11429 or @@ -36877,75 +36946,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13064 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or @@ -37222,75 +37222,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or @@ -37360,6 +37291,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11560; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11561; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11562; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11563; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11564; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11565; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11566; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11567; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11568; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11569; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11570; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11571; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11572; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13073 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11573; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11595 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11596 or @@ -37843,75 +37843,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or @@ -37981,6 +37912,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11739; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11743; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11744; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11745; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11746; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11747; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11748; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11749; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11750; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11751; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11752; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11753; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11754; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11755; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11756; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11757; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13088 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11758; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11761 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11762 or @@ -38257,6 +38257,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11832; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11835 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11836 or @@ -38326,6 +38395,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or @@ -38395,75 +38533,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11856; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11857; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11858; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11859; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11860; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11861; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11862; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11863; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11864; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11865; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11866; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11867; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11868; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13097 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -38740,6 +38809,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11961; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11965 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11966 or @@ -38878,75 +39016,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or @@ -39223,144 +39292,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109; - endcase - end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12131; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12132; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12133; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12134; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12135; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12136; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12137; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12138; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12139; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12140; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12141; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12142; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12143; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12144; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12145; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or @@ -39430,6 +39361,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12096; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12097; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12098; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12099; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12100; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12101; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12102; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12103; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12104; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12105; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12106; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12107; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12108; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13116 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12109; + endcase + end always@(sendRsToDmaC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -39702,6 +39702,75 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10964; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; + endcase + end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or @@ -39840,75 +39909,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12811; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12672; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12679; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12686; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12693; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12700; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12707; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12714; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12721; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12728; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12735; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12742; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12749; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12756; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12763; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12770; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12779 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12777; - endcase - end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12781 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12783 or @@ -40185,7 +40185,7 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12846; endcase end - always@(sendToM_getData_n or + always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or @@ -40203,54 +40203,54 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) begin - case (sendToM_getData_n) + case (sendRsToDmaC_getData_n) 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; endcase end @@ -40323,75 +40323,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12880; endcase end - always@(sendRsToDmaC_getData_n or - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) - begin - case (sendRsToDmaC_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d13146 = - IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40461,6 +40392,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12949; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885 or + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887 or + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889 or + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891 or + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893 or + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895 or + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897 or + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899 or + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901 or + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903 or + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905 or + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907 or + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909 or + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911 or + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913 or + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12885; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12887; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_2_dummy2_0_read__2680_AND_m_dataV_ETC___d12889; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_3_dummy2_0_read__2687_AND_m_dataV_ETC___d12891; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_4_dummy2_0_read__2694_AND_m_dataV_ETC___d12893; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_5_dummy2_0_read__2701_AND_m_dataV_ETC___d12895; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_6_dummy2_0_read__2708_AND_m_dataV_ETC___d12897; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_7_dummy2_0_read__2715_AND_m_dataV_ETC___d12899; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_8_dummy2_0_read__2722_AND_m_dataV_ETC___d12901; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_9_dummy2_0_read__2729_AND_m_dataV_ETC___d12903; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_10_dummy2_0_read__2736_AND_m_data_ETC___d12905; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_11_dummy2_0_read__2743_AND_m_data_ETC___d12907; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_12_dummy2_0_read__2750_AND_m_data_ETC___d12909; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_13_dummy2_0_read__2757_AND_m_data_ETC___d12911; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_14_dummy2_0_read__2764_AND_m_data_ETC___d12913; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2666_AND_ETC___d12917 = + IF_m_dataVec_15_dummy2_0_read__2771_AND_m_data_ETC___d12915; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2666_AND_m_dataV_ETC___d12919 or IF_m_dataVec_1_dummy2_0_read__2673_AND_m_dataV_ETC___d12921 or @@ -40668,6 +40668,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11018; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11021 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11022 or @@ -40806,75 +40875,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11073; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11040; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11041; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11042; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11043; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11044; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11045; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11046; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11047; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11048; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11049; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11050; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11051; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11052; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11053; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11054; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13178 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11055; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11077 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11078 or @@ -41151,75 +41151,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11147; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11169 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11170 or @@ -41289,6 +41220,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11184; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11151; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11152; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11153; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11154; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11155; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11156; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11157; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11158; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11159; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11160; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11161; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11162; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11163; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11164; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11165; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13187 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11166; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11188 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11189 or @@ -41772,75 +41772,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11314; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11317 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11318 or @@ -41910,6 +41841,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11332; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11336; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11337; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11338; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11339; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11340; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11341; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11342; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11343; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11344; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11345; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11346; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11347; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11348; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11349; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11350; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13202 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11351; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11354 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11355 or @@ -42187,72 +42187,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; endcase end always@(sendRqToC_getRq_n or @@ -42324,75 +42324,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11443; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11447; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11448; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11449; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11450; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11451; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11452; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11453; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11454; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11455; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11456; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11457; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11458; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11459; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11460; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11461; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13211 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11462; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11465 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11466 or @@ -42462,6 +42393,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11480; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11484; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11485; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11486; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11487; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11488; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11489; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11490; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11491; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11492; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11493; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11494; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11495; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11496; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11497; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11498; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13214 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11499; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11502 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11503 or @@ -42669,6 +42669,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11554; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11558 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11559 or @@ -42807,75 +42876,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11610; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11576; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11577; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11578; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11579; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11580; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11581; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11582; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11583; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11584; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11585; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11586; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11587; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11588; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11589; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11590; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11591; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11613 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11614 or @@ -43152,75 +43152,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11684; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11706 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11707 or @@ -43290,6 +43221,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11721; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11687; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11688; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11689; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11690; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11691; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11692; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11693; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11694; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11695; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11696; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11697; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11698; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11699; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11700; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11701; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13230 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11702; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11724 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11725 or @@ -43773,75 +43773,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11850; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11854 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11855 or @@ -43911,6 +43842,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11869; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11872; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11873; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11874; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11875; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11876; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11877; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11878; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11879; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11880; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11881; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11882; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11883; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11884; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11885; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11886; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13245 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11887; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11891 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11892 or @@ -44188,72 +44188,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) begin case (sendRqToC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; endcase end always@(sendRqToC_getRq_n or @@ -44325,75 +44325,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11980; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d11983; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d11984; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d11985; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d11986; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d11987; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d11988; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d11989; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d11990; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d11991; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d11992; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d11993; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d11994; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d11995; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d11996; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d11997; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d11998; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12002 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12003 or @@ -44463,6 +44394,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12017; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12020; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12021; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12022; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12023; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12024; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12025; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12026; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12027; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12028; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12029; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12030; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12031; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12032; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12033; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12034; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13257 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12035; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12039 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12040 or @@ -44670,6 +44670,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12091; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12094 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12095 or @@ -44808,75 +44877,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12146; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12113; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12114; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12115; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12116; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12117; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12118; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12119; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12120; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12121; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12122; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12123; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12124; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12125; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12126; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12127; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13265 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12128; - endcase - end always@(sendRqToC_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0849_2187_OR_NOT_ETC___d12191 or NOT_m_reqVec_1_dummy2_0_read__0854_2192_OR_NOT_ETC___d12196 or @@ -46328,122 +46328,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[62]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[62]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[62]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[62]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[62]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[62]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[62]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[62]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[62]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[62]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[62]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[62]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[62]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[62]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[62]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[62]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46560,6 +46444,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[63]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[62]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[62]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[62]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[62]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[62]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[62]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[62]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[62]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[62]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[62]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[62]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[62]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[62]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[62]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[62]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14088 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[62]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47024,6 +47024,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[58]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[56]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[56]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[56]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[56]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[56]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[56]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[56]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[56]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[56]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[56]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[56]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[56]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[56]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[56]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[56]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[56]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47256,122 +47372,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[55]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[56]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[56]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[56]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[56]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[56]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[56]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[56]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[56]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[56]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[56]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[56]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[56]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[56]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[56]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[56]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14199 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[56]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47836,6 +47836,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[51]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[49]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[49]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[49]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[49]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[49]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[49]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[49]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[49]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[49]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[49]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[49]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[49]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[49]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[49]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[49]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[49]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48068,122 +48184,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[48]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[49]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[49]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[49]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[49]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[49]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[49]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[49]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[49]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[49]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[49]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[49]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[49]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[49]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[49]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[49]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14329 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[49]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48648,122 +48648,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[44]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[43]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[43]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[43]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[43]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[43]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[43]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[43]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[43]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[43]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[43]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[43]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[43]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[43]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[43]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[43]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[43]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48880,6 +48764,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[42]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[43]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[43]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[43]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[43]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[43]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[43]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[43]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[43]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[43]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[43]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[43]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[43]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[43]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[43]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[43]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14440 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[43]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49692,122 +49692,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[33]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[33]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[33]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[33]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[33]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[33]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[33]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[33]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[33]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[33]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[33]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[33]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[33]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[33]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[33]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[33]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49924,6 +49808,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[34]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[33]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[33]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[33]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[33]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[33]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[33]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[33]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[33]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[33]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[33]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[33]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[33]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[33]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[33]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[33]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14625 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[33]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50388,6 +50388,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[29]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[27]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[27]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[27]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[27]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[27]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[27]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[27]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[27]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[27]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[27]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[27]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[27]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[27]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[27]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[27]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[27]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50620,122 +50736,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[26]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[27]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[27]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[27]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[27]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[27]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[27]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[27]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[27]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[27]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[27]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[27]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[27]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[27]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[27]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[27]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14736 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[27]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51200,6 +51200,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[22]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[20]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[20]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[20]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[20]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[20]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[20]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[20]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[20]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[20]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[20]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[20]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[20]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[20]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[20]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[20]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[20]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51432,122 +51548,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[19]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[20]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[20]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[20]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[20]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[20]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[20]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[20]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[20]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[20]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[20]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[20]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[20]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[20]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[20]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[20]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14865 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[20]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52012,122 +52012,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[15]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[14]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[14]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[14]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[14]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[14]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[14]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[14]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[14]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[14]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[14]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[14]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[14]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[14]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[14]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[14]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[14]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52244,6 +52128,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[13]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[14]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[14]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[14]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[14]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[14]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[14]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[14]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[14]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[14]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[14]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[14]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[14]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[14]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[14]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[14]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0850_AND_m_r_ETC___d14976 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[14]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53007,6 +53007,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -53139,73 +53206,6 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15184 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getAddrSucc_n or m_addrSuccValidVec_0_dummy2_1$Q_OUT or m_addrSuccValidVec_0_dummy2_2$Q_OUT or @@ -53872,6 +53872,73 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end + always@(sendRqToC_getSlot_n or + m_slotVec_0_rl or + m_slotVec_1_rl or + m_slotVec_2_rl or + m_slotVec_3_rl or + m_slotVec_4_rl or + m_slotVec_5_rl or + m_slotVec_6_rl or + m_slotVec_7_rl or + m_slotVec_8_rl or + m_slotVec_9_rl or + m_slotVec_10_rl or + m_slotVec_11_rl or + m_slotVec_12_rl or + m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) + begin + case (sendRqToC_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_0_rl[1:0]; + 4'd1: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_1_rl[1:0]; + 4'd2: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_2_rl[1:0]; + 4'd3: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_3_rl[1:0]; + 4'd4: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_4_rl[1:0]; + 4'd5: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_5_rl[1:0]; + 4'd6: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_6_rl[1:0]; + 4'd7: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_7_rl[1:0]; + 4'd8: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_8_rl[1:0]; + 4'd9: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_9_rl[1:0]; + 4'd10: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_10_rl[1:0]; + 4'd11: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_11_rl[1:0]; + 4'd12: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_12_rl[1:0]; + 4'd13: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_13_rl[1:0]; + 4'd14: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_14_rl[1:0]; + 4'd15: + SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = + m_slotVec_15_rl[1:0]; + endcase + end always@(sendToM_getSlot_n or m_slotVec_0_rl or m_slotVec_1_rl or @@ -54006,73 +54073,6 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_rl[5:4]; endcase end - always@(sendRqToC_getSlot_n or - m_slotVec_0_rl or - m_slotVec_1_rl or - m_slotVec_2_rl or - m_slotVec_3_rl or - m_slotVec_4_rl or - m_slotVec_5_rl or - m_slotVec_6_rl or - m_slotVec_7_rl or - m_slotVec_8_rl or - m_slotVec_9_rl or - m_slotVec_10_rl or - m_slotVec_11_rl or - m_slotVec_12_rl or - m_slotVec_13_rl or m_slotVec_14_rl or m_slotVec_15_rl) - begin - case (sendRqToC_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_0_rl[1:0]; - 4'd1: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_1_rl[1:0]; - 4'd2: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_2_rl[1:0]; - 4'd3: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_3_rl[1:0]; - 4'd4: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_4_rl[1:0]; - 4'd5: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_5_rl[1:0]; - 4'd6: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_6_rl[1:0]; - 4'd7: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_7_rl[1:0]; - 4'd8: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_8_rl[1:0]; - 4'd9: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_9_rl[1:0]; - 4'd10: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_10_rl[1:0]; - 4'd11: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_11_rl[1:0]; - 4'd12: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_12_rl[1:0]; - 4'd13: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_13_rl[1:0]; - 4'd14: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_14_rl[1:0]; - 4'd15: - SEL_ARR_m_slotVec_0_rl_914_BITS_1_TO_0_984_m_s_ETC___d13395 = - m_slotVec_15_rl[1:0]; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or @@ -54515,75 +54515,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152 or - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153 or - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154 or - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155 or - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156 or - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157 or - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158 or - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159 or - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160 or - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161 or - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162 or - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163 or - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164 or - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = - m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12168 or m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12169 or @@ -54653,6 +54584,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12183; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150 or + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151 or + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152 or + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153 or + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154 or + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155 or + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156 or + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157 or + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158 or + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159 or + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160 or + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161 or + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162 or + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163 or + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164 or + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_0__ETC___d12150; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_1__ETC___d12151; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_2_dummy2_0_read__0859_AND_m_reqVec_2__ETC___d12152; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_3_dummy2_0_read__0864_AND_m_reqVec_3__ETC___d12153; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_4_dummy2_0_read__0869_AND_m_reqVec_4__ETC___d12154; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_5_dummy2_0_read__0874_AND_m_reqVec_5__ETC___d12155; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_6_dummy2_0_read__0879_AND_m_reqVec_6__ETC___d12156; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_7_dummy2_0_read__0884_AND_m_reqVec_7__ETC___d12157; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_8_dummy2_0_read__0889_AND_m_reqVec_8__ETC___d12158; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_9_dummy2_0_read__0894_AND_m_reqVec_9__ETC___d12159; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_10_dummy2_0_read__0899_AND_m_reqVec_1_ETC___d12160; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_11_dummy2_0_read__0904_AND_m_reqVec_1_ETC___d12161; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_12_dummy2_0_read__0909_AND_m_reqVec_1_ETC___d12162; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_13_dummy2_0_read__0914_AND_m_reqVec_1_ETC___d12163; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_14_dummy2_0_read__0919_AND_m_reqVec_1_ETC___d12164; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0849_AND_m_r_ETC___d13268 = + m_reqVec_15_dummy2_0_read__0924_AND_m_reqVec_1_ETC___d12165; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -55786,74 +55786,6 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899271; endcase end - always@(sendRsToDmaC_getRq_n or - n__read_addr__h897906 or - n__read_addr__h897997 or - n__read_addr__h898088 or - n__read_addr__h898179 or - n__read_addr__h898270 or - n__read_addr__h898361 or - n__read_addr__h898452 or - n__read_addr__h898543 or - n__read_addr__h898634 or - n__read_addr__h898725 or - n__read_addr__h898816 or - n__read_addr__h898907 or - n__read_addr__h898998 or - n__read_addr__h899089 or - n__read_addr__h899180 or n__read_addr__h899271) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897906; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h897997; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898088; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898179; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898270; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898361; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898452; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898543; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898634; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898725; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898816; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898907; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h898998; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899089; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899180; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = - n__read_addr__h899271; - endcase - end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -55923,6 +55855,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end + always@(sendRsToDmaC_getRq_n or + n__read_addr__h897906 or + n__read_addr__h897997 or + n__read_addr__h898088 or + n__read_addr__h898179 or + n__read_addr__h898270 or + n__read_addr__h898361 or + n__read_addr__h898452 or + n__read_addr__h898543 or + n__read_addr__h898634 or + n__read_addr__h898725 or + n__read_addr__h898816 or + n__read_addr__h898907 or + n__read_addr__h898998 or + n__read_addr__h899089 or + n__read_addr__h899180 or n__read_addr__h899271) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897906; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h897997; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898088; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898179; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898270; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898361; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898452; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898543; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898634; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898725; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898816; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898907; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h898998; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899089; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899180; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_0_read__0849_AND__ETC___d13023 = + n__read_addr__h899271; + endcase + end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0849_AND_m_reqVec_ETC___d10931 or IF_m_reqVec_1_dummy2_0_read__0854_AND_m_reqVec_ETC___d10932 or @@ -56129,6 +56129,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0924_AND_m_reqVe_ETC___d10946; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995883 or + n__read_addr__h995985 or + n__read_addr__h996087 or + n__read_addr__h996189 or + n__read_addr__h996291 or + n__read_addr__h996393 or + n__read_addr__h996495 or + n__read_addr__h996597 or + n__read_addr__h996699 or + n__read_addr__h996801 or + n__read_addr__h996903 or + n__read_addr__h997005 or + n__read_addr__h997107 or + n__read_addr__h997209 or + n__read_addr__h997311 or n__read_addr__h997413) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995883; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h995985; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996087; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996189; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996291; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996393; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996495; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996597; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996699; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996801; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h996903; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997005; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997107; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997209; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997311; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = + n__read_addr__h997413; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -56261,74 +56329,6 @@ module mkLastLvCRqMshr(CLK, 2'd0; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995883 or - n__read_addr__h995985 or - n__read_addr__h996087 or - n__read_addr__h996189 or - n__read_addr__h996291 or - n__read_addr__h996393 or - n__read_addr__h996495 or - n__read_addr__h996597 or - n__read_addr__h996699 or - n__read_addr__h996801 or - n__read_addr__h996903 or - n__read_addr__h997005 or - n__read_addr__h997107 or - n__read_addr__h997209 or - n__read_addr__h997311 or n__read_addr__h997413) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995883; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h995985; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996087; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996189; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996291; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996393; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996495; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996597; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996699; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996801; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h996903; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997005; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997107; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997209; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997311; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0850_AND__ETC___d13869 = - n__read_addr__h997413; - endcase - end always@(sendRqToC_setSlot_s) begin case (sendRqToC_setSlot_s[7:6]) @@ -56770,123 +56770,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3267; endcase end - always@(pipelineResp_getSlot_n or - m_slotVec_0_dummy2_1$Q_OUT or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930 or - m_slotVec_1_dummy2_1$Q_OUT or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017 or - m_slotVec_2_dummy2_1$Q_OUT or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103 or - m_slotVec_3_dummy2_1$Q_OUT or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189 or - m_slotVec_4_dummy2_1$Q_OUT or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275 or - m_slotVec_5_dummy2_1$Q_OUT or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361 or - m_slotVec_6_dummy2_1$Q_OUT or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447 or - m_slotVec_7_dummy2_1$Q_OUT or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533 or - m_slotVec_8_dummy2_1$Q_OUT or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619 or - m_slotVec_9_dummy2_1$Q_OUT or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705 or - m_slotVec_10_dummy2_1$Q_OUT or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791 or - m_slotVec_11_dummy2_1$Q_OUT or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877 or - m_slotVec_12_dummy2_1$Q_OUT or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963 or - m_slotVec_13_dummy2_1$Q_OUT or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049 or - m_slotVec_14_dummy2_1$Q_OUT or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135 or - m_slotVec_15_dummy2_1$Q_OUT or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221) - begin - case (pipelineResp_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_0_dummy2_1$Q_OUT && m_slotVec_0_dummy2_2$Q_OUT && - IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930; - 4'd1: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_1_dummy2_1$Q_OUT && m_slotVec_1_dummy2_2$Q_OUT && - IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017; - 4'd2: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_2_dummy2_1$Q_OUT && m_slotVec_2_dummy2_2$Q_OUT && - IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103; - 4'd3: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_3_dummy2_1$Q_OUT && m_slotVec_3_dummy2_2$Q_OUT && - IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189; - 4'd4: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_4_dummy2_1$Q_OUT && m_slotVec_4_dummy2_2$Q_OUT && - IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275; - 4'd5: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_5_dummy2_1$Q_OUT && m_slotVec_5_dummy2_2$Q_OUT && - IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361; - 4'd6: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_6_dummy2_1$Q_OUT && m_slotVec_6_dummy2_2$Q_OUT && - IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447; - 4'd7: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_7_dummy2_1$Q_OUT && m_slotVec_7_dummy2_2$Q_OUT && - IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533; - 4'd8: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_8_dummy2_1$Q_OUT && m_slotVec_8_dummy2_2$Q_OUT && - IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619; - 4'd9: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_9_dummy2_1$Q_OUT && m_slotVec_9_dummy2_2$Q_OUT && - IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705; - 4'd10: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_10_dummy2_1$Q_OUT && m_slotVec_10_dummy2_2$Q_OUT && - IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791; - 4'd11: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_11_dummy2_1$Q_OUT && m_slotVec_11_dummy2_2$Q_OUT && - IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877; - 4'd12: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_12_dummy2_1$Q_OUT && m_slotVec_12_dummy2_2$Q_OUT && - IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963; - 4'd13: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_13_dummy2_1$Q_OUT && m_slotVec_13_dummy2_2$Q_OUT && - IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049; - 4'd14: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_14_dummy2_1$Q_OUT && m_slotVec_14_dummy2_2$Q_OUT && - IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135; - 4'd15: - SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = - m_slotVec_15_dummy2_1$Q_OUT && m_slotVec_15_dummy2_2$Q_OUT && - IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221; - endcase - end always@(pipelineResp_getSlot_n or m_slotVec_0_dummy2_1$Q_OUT or m_slotVec_0_dummy2_2$Q_OUT or @@ -57004,6 +56887,123 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3260; endcase end + always@(pipelineResp_getSlot_n or + m_slotVec_0_dummy2_1$Q_OUT or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930 or + m_slotVec_1_dummy2_1$Q_OUT or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017 or + m_slotVec_2_dummy2_1$Q_OUT or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103 or + m_slotVec_3_dummy2_1$Q_OUT or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189 or + m_slotVec_4_dummy2_1$Q_OUT or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275 or + m_slotVec_5_dummy2_1$Q_OUT or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361 or + m_slotVec_6_dummy2_1$Q_OUT or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447 or + m_slotVec_7_dummy2_1$Q_OUT or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533 or + m_slotVec_8_dummy2_1$Q_OUT or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619 or + m_slotVec_9_dummy2_1$Q_OUT or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705 or + m_slotVec_10_dummy2_1$Q_OUT or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791 or + m_slotVec_11_dummy2_1$Q_OUT or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877 or + m_slotVec_12_dummy2_1$Q_OUT or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963 or + m_slotVec_13_dummy2_1$Q_OUT or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049 or + m_slotVec_14_dummy2_1$Q_OUT or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135 or + m_slotVec_15_dummy2_1$Q_OUT or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221) + begin + case (pipelineResp_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_0_dummy2_1$Q_OUT && m_slotVec_0_dummy2_2$Q_OUT && + IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1930; + 4'd1: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_1_dummy2_1$Q_OUT && m_slotVec_1_dummy2_2$Q_OUT && + IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2017; + 4'd2: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_2_dummy2_1$Q_OUT && m_slotVec_2_dummy2_2$Q_OUT && + IF_m_slotVec_2_lat_0_whas__084_THEN_m_slotVec__ETC___d2103; + 4'd3: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_3_dummy2_1$Q_OUT && m_slotVec_3_dummy2_2$Q_OUT && + IF_m_slotVec_3_lat_0_whas__170_THEN_m_slotVec__ETC___d2189; + 4'd4: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_4_dummy2_1$Q_OUT && m_slotVec_4_dummy2_2$Q_OUT && + IF_m_slotVec_4_lat_0_whas__256_THEN_m_slotVec__ETC___d2275; + 4'd5: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_5_dummy2_1$Q_OUT && m_slotVec_5_dummy2_2$Q_OUT && + IF_m_slotVec_5_lat_0_whas__342_THEN_m_slotVec__ETC___d2361; + 4'd6: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_6_dummy2_1$Q_OUT && m_slotVec_6_dummy2_2$Q_OUT && + IF_m_slotVec_6_lat_0_whas__428_THEN_m_slotVec__ETC___d2447; + 4'd7: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_7_dummy2_1$Q_OUT && m_slotVec_7_dummy2_2$Q_OUT && + IF_m_slotVec_7_lat_0_whas__514_THEN_m_slotVec__ETC___d2533; + 4'd8: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_8_dummy2_1$Q_OUT && m_slotVec_8_dummy2_2$Q_OUT && + IF_m_slotVec_8_lat_0_whas__600_THEN_m_slotVec__ETC___d2619; + 4'd9: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_9_dummy2_1$Q_OUT && m_slotVec_9_dummy2_2$Q_OUT && + IF_m_slotVec_9_lat_0_whas__686_THEN_m_slotVec__ETC___d2705; + 4'd10: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_10_dummy2_1$Q_OUT && m_slotVec_10_dummy2_2$Q_OUT && + IF_m_slotVec_10_lat_0_whas__772_THEN_m_slotVec_ETC___d2791; + 4'd11: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_11_dummy2_1$Q_OUT && m_slotVec_11_dummy2_2$Q_OUT && + IF_m_slotVec_11_lat_0_whas__858_THEN_m_slotVec_ETC___d2877; + 4'd12: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_12_dummy2_1$Q_OUT && m_slotVec_12_dummy2_2$Q_OUT && + IF_m_slotVec_12_lat_0_whas__944_THEN_m_slotVec_ETC___d2963; + 4'd13: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_13_dummy2_1$Q_OUT && m_slotVec_13_dummy2_2$Q_OUT && + IF_m_slotVec_13_lat_0_whas__030_THEN_m_slotVec_ETC___d3049; + 4'd14: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_14_dummy2_1$Q_OUT && m_slotVec_14_dummy2_2$Q_OUT && + IF_m_slotVec_14_lat_0_whas__116_THEN_m_slotVec_ETC___d3135; + 4'd15: + SEL_ARR_m_slotVec_0_dummy2_1_read__2304_AND_m__ETC___d15296 = + m_slotVec_15_dummy2_1$Q_OUT && m_slotVec_15_dummy2_2$Q_OUT && + IF_m_slotVec_15_lat_0_whas__202_THEN_m_slotVec_ETC___d3221; + endcase + end always@(pipelineResp_getSlot_n or IF_m_slotVec_0_lat_0_whas__911_THEN_m_slotVec__ETC___d1957 or IF_m_slotVec_1_lat_0_whas__998_THEN_m_slotVec__ETC___d2043 or diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index b7af2b7..e58a869 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -18,7 +18,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -47,7 +46,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 reg -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -64,12 +62,12 @@ // master1_arqos O 4 reg // master1_arregion O 4 reg // master1_rready O 1 reg +// jtag_tdo O 1 // tv_verifier_info_tx_tvalid O 1 reg // tv_verifier_info_tx_tdata O 608 reg // tv_verifier_info_tx_tstrb O 76 reg // tv_verifier_info_tx_tkeep O 76 reg // tv_verifier_info_tx_tlast O 1 reg -// jtag_tdo O 1 // CLK_jtag_tclk_out O 1 clock // CLK_GATE_jtag_tclk_out O 1 const // CLK I 1 clock @@ -97,11 +95,11 @@ // master1_rresp I 2 reg // master1_rlast I 1 reg // cpu_external_interrupt_req I 16 -// debug_external_interrupt_req_set_not_clear I 1 -// tv_verifier_info_tx_tready I 1 +// debug_external_interrupt_req_set_not_clear I 1 unused // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 +// tv_verifier_info_tx_tready I 1 // // Combinational paths from inputs to outputs: // (master0_awready, master0_wready) -> master0_bready @@ -150,8 +148,6 @@ module mkP3_Core(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -224,8 +220,6 @@ module mkP3_Core(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -276,6 +270,14 @@ module mkP3_Core(CLK, debug_external_interrupt_req_set_not_clear, + jtag_tdi, + + jtag_tms, + + jtag_tclk, + + jtag_tdo, + tv_verifier_info_tx_tvalid, tv_verifier_info_tx_tdata, @@ -288,14 +290,6 @@ module mkP3_Core(CLK, tv_verifier_info_tx_tready, - jtag_tdi, - - jtag_tms, - - jtag_tclk, - - jtag_tdo, - CLK_jtag_tclk_out, CLK_GATE_jtag_tclk_out); input CLK; @@ -342,9 +336,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -456,9 +447,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -535,6 +523,18 @@ module mkP3_Core(CLK, // action method debug_external_interrupt_req input debug_external_interrupt_req_set_not_clear; + // action method jtag_tdi + input jtag_tdi; + + // action method jtag_tms + input jtag_tms; + + // action method jtag_tclk + input jtag_tclk; + + // value method jtag_tdo + output jtag_tdo; + // value method tv_verifier_info_tx_m_tvalid output tv_verifier_info_tx_tvalid; @@ -559,18 +559,6 @@ module mkP3_Core(CLK, // action method tv_verifier_info_tx_m_tready input tv_verifier_info_tx_tready; - // action method jtag_tdi - input jtag_tdi; - - // action method jtag_tms - input jtag_tms; - - // action method jtag_tclk - input jtag_tclk; - - // value method jtag_tdo - output jtag_tdo; - // oscillator and gates for output clock CLK_jtag_tclk_out output CLK_jtag_tclk_out; output CLK_GATE_jtag_tclk_out; @@ -598,7 +586,6 @@ module mkP3_Core(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -606,8 +593,7 @@ module mkP3_Core(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -661,9 +647,10 @@ module mkP3_Core(CLK, reg [33 : 0] bus_dmi_rsp_fifof_q_1$D_IN; wire bus_dmi_rsp_fifof_q_1$EN; - // register rg_once - reg rg_once; - wire rg_once$D_IN, rg_once$EN; + // register rg_ndm_reset_delay + reg [7 : 0] rg_ndm_reset_delay; + wire [7 : 0] rg_ndm_reset_delay$D_IN; + wire rg_ndm_reset_delay$EN; // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; @@ -683,17 +670,17 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, - corew$set_htif_addrs_fromhost_addr, - corew$set_htif_addrs_tohost_addr, - corew$set_verbosity_logdelay; - wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; + corew$set_verbosity_logdelay, + corew$start_fromhost_addr, + corew$start_tohost_addr; + wire [31 : 0] corew$dmi_read_data, corew$dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, corew$cpu_dmem_master_wstrb, corew$cpu_imem_master_arlen, corew$cpu_imem_master_awlen, corew$cpu_imem_master_wstrb; - wire [6 : 0] corew$dm_dmi_read_addr_dm_addr, corew$dm_dmi_write_dm_addr; + wire [6 : 0] corew$dmi_read_addr_dm_addr, corew$dmi_write_dm_addr; wire [3 : 0] corew$cpu_dmem_master_arcache, corew$cpu_dmem_master_arid, corew$cpu_dmem_master_arqos, @@ -704,7 +691,6 @@ module mkP3_Core(CLK, corew$cpu_dmem_master_awregion, corew$cpu_dmem_master_bid, corew$cpu_dmem_master_rid, - corew$cpu_dmem_master_wid, corew$cpu_imem_master_arcache, corew$cpu_imem_master_arid, corew$cpu_imem_master_arqos, @@ -715,7 +701,6 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awregion, corew$cpu_imem_master_bid, corew$cpu_imem_master_rid, - corew$cpu_imem_master_wid, corew$set_verbosity_verbosity; wire [2 : 0] corew$cpu_dmem_master_arprot, corew$cpu_dmem_master_arsize, @@ -733,21 +718,19 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awburst, corew$cpu_imem_master_bresp, corew$cpu_imem_master_rresp; - wire corew$EN_cpu_reset_server_request_put, - corew$EN_cpu_reset_server_response_get, - corew$EN_dm_dmi_read_addr, - corew$EN_dm_dmi_read_data, - corew$EN_dm_dmi_write, - corew$EN_dm_ndm_reset_req_get_get, - corew$EN_set_htif_addrs, + wire corew$EN_dmi_read_addr, + corew$EN_dmi_read_data, + corew$EN_dmi_write, + corew$EN_ndm_reset_client_request_get, + corew$EN_ndm_reset_client_response_put, corew$EN_set_verbosity, + corew$EN_start, corew$EN_tv_verifier_info_get_get, - corew$RDY_cpu_reset_server_request_put, - corew$RDY_cpu_reset_server_response_get, - corew$RDY_dm_dmi_read_addr, - corew$RDY_dm_dmi_read_data, - corew$RDY_dm_dmi_write, - corew$RDY_dm_ndm_reset_req_get_get, + corew$RDY_dmi_read_addr, + corew$RDY_dmi_read_data, + corew$RDY_dmi_write, + corew$RDY_ndm_reset_client_request_get, + corew$RDY_ndm_reset_client_response_put, corew$RDY_tv_verifier_info_get_get, corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, @@ -793,7 +776,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$debug_external_interrupt_req_set_not_clear; + corew$ndm_reset_client_response_put, + corew$nmi_req_set_not_clear; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -809,6 +793,12 @@ module mkP3_Core(CLK, jtagtap$jtag_tdo, jtagtap$jtag_tms; + // ports of submodule ndm_reset + wire ndm_reset$RST_OUT; + + // ports of submodule ndm_reset_controller + wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -834,13 +824,13 @@ module mkP3_Core(CLK, CAN_FIRE_RL_mkConnectionVtoAf_6, CAN_FIRE_RL_mkConnectionVtoAf_7, CAN_FIRE_RL_mkConnectionVtoAf_8, + CAN_FIRE_RL_rl_always, CAN_FIRE_RL_rl_dmi_req, CAN_FIRE_RL_rl_dmi_req_cpu, CAN_FIRE_RL_rl_dmi_rsp, CAN_FIRE_RL_rl_dmi_rsp_cpu, - CAN_FIRE_RL_rl_ndmreset, - CAN_FIRE_RL_rl_once, - CAN_FIRE_RL_rl_reset_response, + CAN_FIRE_RL_rl_ndm_reset, + CAN_FIRE_RL_rl_ndm_reset_wait, CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_interrupt_reqs, CAN_FIRE_jtag_tclk, @@ -872,13 +862,13 @@ module mkP3_Core(CLK, WILL_FIRE_RL_mkConnectionVtoAf_6, WILL_FIRE_RL_mkConnectionVtoAf_7, WILL_FIRE_RL_mkConnectionVtoAf_8, + WILL_FIRE_RL_rl_always, WILL_FIRE_RL_rl_dmi_req, WILL_FIRE_RL_rl_dmi_req_cpu, WILL_FIRE_RL_rl_dmi_rsp, WILL_FIRE_RL_rl_dmi_rsp_cpu, - WILL_FIRE_RL_rl_ndmreset, - WILL_FIRE_RL_rl_once, - WILL_FIRE_RL_rl_reset_response, + WILL_FIRE_RL_rl_ndm_reset, + WILL_FIRE_RL_rl_ndm_reset_wait, WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_interrupt_reqs, WILL_FIRE_jtag_tclk, @@ -899,9 +889,10 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2, - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; + wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2; wire MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2, @@ -909,9 +900,17 @@ module mkP3_Core(CLK, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1; + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h1278; + reg [31 : 0] v__h1389; + reg [31 : 0] v__h1272; + reg [31 : 0] v__h1383; + // synopsys translate_on + // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28; - wire IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37; + wire IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87, _dfoo1, _dfoo3; @@ -959,9 +958,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid assign master0_wvalid = corew$cpu_imem_master_wvalid ; - // value method master0_m_wid - assign master0_wid = corew$cpu_imem_master_wid ; - // value method master0_m_wdata assign master0_wdata = corew$cpu_imem_master_wdata ; @@ -1066,9 +1062,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid assign master1_wvalid = corew$cpu_dmem_master_wvalid ; - // value method master1_m_wid - assign master1_wid = corew$cpu_dmem_master_wid ; - // value method master1_m_wdata assign master1_wdata = corew$cpu_dmem_master_wdata ; @@ -1141,6 +1134,21 @@ module mkP3_Core(CLK, assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method jtag_tdi + assign CAN_FIRE_jtag_tdi = 1'd1 ; + assign WILL_FIRE_jtag_tdi = 1'd1 ; + + // action method jtag_tms + assign CAN_FIRE_jtag_tms = 1'd1 ; + assign WILL_FIRE_jtag_tms = 1'd1 ; + + // action method jtag_tclk + assign CAN_FIRE_jtag_tclk = 1'd1 ; + assign WILL_FIRE_jtag_tclk = 1'd1 ; + + // value method jtag_tdo + assign jtag_tdo = jtagtap$jtag_tdo ; + // value method tv_verifier_info_tx_m_tvalid assign tv_verifier_info_tx_tvalid = tv_xactor$axi_out_tvalid ; @@ -1160,21 +1168,6 @@ module mkP3_Core(CLK, assign CAN_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; assign WILL_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - // action method jtag_tdi - assign CAN_FIRE_jtag_tdi = 1'd1 ; - assign WILL_FIRE_jtag_tdi = 1'd1 ; - - // action method jtag_tms - assign CAN_FIRE_jtag_tms = 1'd1 ; - assign WILL_FIRE_jtag_tms = 1'd1 ; - - // action method jtag_tclk - assign CAN_FIRE_jtag_tclk = 1'd1 ; - assign WILL_FIRE_jtag_tclk = 1'd1 ; - - // value method jtag_tdo - assign jtag_tdo = jtagtap$jtag_tdo ; - // submodule bus_dmi_req_fifof FIFO2 #(.width(32'd41), .guarded(32'd1)) bus_dmi_req_fifof(.RST(RST_N), .CLK(CLK), @@ -1187,8 +1180,9 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.CLK(CLK), - .RST_N(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + .CLK(CLK), + .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), @@ -1227,27 +1221,25 @@ module mkP3_Core(CLK, .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), - .debug_external_interrupt_req_set_not_clear(corew$debug_external_interrupt_req_set_not_clear), - .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), - .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), - .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), - .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), - .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), + .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), + .dmi_write_dm_addr(corew$dmi_write_dm_addr), + .dmi_write_dm_word(corew$dmi_write_dm_word), + .ndm_reset_client_response_put(corew$ndm_reset_client_response_put), + .nmi_req_set_not_clear(corew$nmi_req_set_not_clear), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), + .start_fromhost_addr(corew$start_fromhost_addr), + .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), - .EN_set_htif_addrs(corew$EN_set_htif_addrs), - .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), - .EN_dm_dmi_read_addr(corew$EN_dm_dmi_read_addr), - .EN_dm_dmi_read_data(corew$EN_dm_dmi_read_data), - .EN_dm_dmi_write(corew$EN_dm_dmi_write), - .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), + .EN_start(corew$EN_start), + .EN_dmi_read_addr(corew$EN_dmi_read_addr), + .EN_dmi_read_data(corew$EN_dmi_read_data), + .EN_dmi_write(corew$EN_dmi_write), + .EN_ndm_reset_client_request_get(corew$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(corew$EN_ndm_reset_client_response_put), .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), .RDY_set_verbosity(), - .RDY_set_htif_addrs(), - .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), - .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), + .RDY_start(), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), .cpu_imem_master_awid(corew$cpu_imem_master_awid), .cpu_imem_master_awaddr(corew$cpu_imem_master_awaddr), @@ -1260,7 +1252,6 @@ module mkP3_Core(CLK, .cpu_imem_master_awqos(corew$cpu_imem_master_awqos), .cpu_imem_master_awregion(corew$cpu_imem_master_awregion), .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), - .cpu_imem_master_wid(corew$cpu_imem_master_wid), .cpu_imem_master_wdata(corew$cpu_imem_master_wdata), .cpu_imem_master_wstrb(corew$cpu_imem_master_wstrb), .cpu_imem_master_wlast(corew$cpu_imem_master_wlast), @@ -1289,7 +1280,6 @@ module mkP3_Core(CLK, .cpu_dmem_master_awqos(corew$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(corew$cpu_dmem_master_awregion), .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(corew$cpu_dmem_master_wid), .cpu_dmem_master_wdata(corew$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(corew$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(corew$cpu_dmem_master_wlast), @@ -1306,11 +1296,13 @@ module mkP3_Core(CLK, .cpu_dmem_master_arqos(corew$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(corew$cpu_dmem_master_arregion), .cpu_dmem_master_rready(corew$cpu_dmem_master_rready), - .RDY_dm_dmi_read_addr(corew$RDY_dm_dmi_read_addr), - .dm_dmi_read_data(corew$dm_dmi_read_data), - .RDY_dm_dmi_read_data(corew$RDY_dm_dmi_read_data), - .RDY_dm_dmi_write(corew$RDY_dm_dmi_write), - .RDY_dm_ndm_reset_req_get_get(corew$RDY_dm_ndm_reset_req_get_get), + .RDY_dmi_read_addr(corew$RDY_dmi_read_addr), + .dmi_read_data(corew$dmi_read_data), + .RDY_dmi_read_data(corew$RDY_dmi_read_data), + .RDY_dmi_write(corew$RDY_dmi_write), + .ndm_reset_client_request_get(), + .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), .RDY_tv_verifier_info_get_get(corew$RDY_tv_verifier_info_get_get)); @@ -1333,6 +1325,19 @@ module mkP3_Core(CLK, .CLK_jtag_tclk_out(jtagtap$CLK_jtag_tclk_out), .CLK_GATE_jtag_tclk_out()); + // submodule ndm_reset + ResetEither ndm_reset(.A_RST(RST_N), + .B_RST(ndm_reset_controller$OUT_RST), + .RST_OUT(ndm_reset$RST_OUT)); + + // submodule ndm_reset_controller + MakeResetA #(.RSTDELAY(32'd10), .init(1'd1)) ndm_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(ndm_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1346,21 +1351,15 @@ module mkP3_Core(CLK, .axi_out_tkeep(tv_xactor$axi_out_tkeep), .axi_out_tlast(tv_xactor$axi_out_tlast)); - // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = - corew$RDY_cpu_reset_server_request_put && !rg_once ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; + // rule RL_rl_always + assign CAN_FIRE_RL_rl_always = 1'd1 ; + assign WILL_FIRE_RL_rl_always = 1'd1 ; - // rule RL_rl_reset_response - assign CAN_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - assign WILL_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - - // rule RL_rl_ndmreset - assign CAN_FIRE_RL_rl_ndmreset = - corew$RDY_dm_ndm_reset_req_get_get && rg_once ; - assign WILL_FIRE_RL_rl_ndmreset = CAN_FIRE_RL_rl_ndmreset ; + // rule RL_rl_ndm_reset + assign CAN_FIRE_RL_rl_ndm_reset = + corew$RDY_ndm_reset_client_request_get && + rg_ndm_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset = CAN_FIRE_RL_rl_ndm_reset ; // rule RL_mkConnectionVtoAf assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; @@ -1409,15 +1408,22 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 ; + IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu assign CAN_FIRE_RL_rl_dmi_rsp_cpu = - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_read_data ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_read_data ; assign WILL_FIRE_RL_rl_dmi_rsp_cpu = CAN_FIRE_RL_rl_dmi_rsp_cpu && !WILL_FIRE_RL_rl_dmi_req_cpu ; + // rule RL_rl_ndm_reset_wait + assign CAN_FIRE_RL_rl_ndm_reset_wait = + (rg_ndm_reset_delay != 8'd1 || + corew$RDY_ndm_reset_client_response_put) && + rg_ndm_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; + // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = corew$RDY_tv_verifier_info_get_get && tv_xactor$RDY_tv_in_put ; @@ -1458,37 +1464,38 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = - (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : - bus_dmi_rsp_fifof_q_1 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ? MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 : MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 = + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = + (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : + bus_dmi_rsp_fifof_q_1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 = (bus_dmi_rsp_fifof_cntr_r == 2'd2) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : 34'd0 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 = { 32'hAAAAAAAA, (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2) ? 2'd0 : 2'd2 } ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 = - { corew$dm_dmi_read_data, 2'd0 } ; + { corew$dmi_read_data, 2'd0 } ; + assign MUX_rg_ndm_reset_delay$write_1__VAL_1 = rg_ndm_reset_delay - 8'd1 ; // inlined wires assign bus_dmi_rsp_fifof_enqueueing$whas = @@ -1503,7 +1510,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 : + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1530,25 +1537,25 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_0$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register bus_dmi_rsp_fifof_q_1 always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr) begin case (1'b1) // synopsys parallel_case MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1; + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1; MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2; + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2; WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr: bus_dmi_rsp_fifof_q_1$D_IN = 34'd0; default: bus_dmi_rsp_fifof_q_1$D_IN = @@ -1556,14 +1563,18 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_1$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; - // register rg_once - assign rg_once$D_IN = !WILL_FIRE_RL_rl_ndmreset ; - assign rg_once$EN = WILL_FIRE_RL_rl_ndmreset || WILL_FIRE_RL_rl_once ; + // register rg_ndm_reset_delay + assign rg_ndm_reset_delay$D_IN = + WILL_FIRE_RL_rl_ndm_reset_wait ? + MUX_rg_ndm_reset_delay$write_1__VAL_1 : + 8'd110 ; + assign rg_ndm_reset_delay$EN = + WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; @@ -1626,28 +1637,27 @@ module mkP3_Core(CLK, assign corew$cpu_imem_master_rresp = master0_rresp ; assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; - assign corew$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; - assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; - assign corew$set_htif_addrs_tohost_addr = 64'h0 ; + assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; + assign corew$start_fromhost_addr = 64'h0 ; + assign corew$start_tohost_addr = 64'h0 ; assign corew$EN_set_verbosity = 1'b0 ; - assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; - assign corew$EN_cpu_reset_server_response_get = - corew$RDY_cpu_reset_server_response_get ; - assign corew$EN_dm_dmi_read_addr = + assign corew$EN_start = 1'b0 ; + assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; - assign corew$EN_dm_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; - assign corew$EN_dm_dmi_write = + assign corew$EN_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; + assign corew$EN_dmi_write = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ; - assign corew$EN_dm_ndm_reset_req_get_get = CAN_FIRE_RL_rl_ndmreset ; + assign corew$EN_ndm_reset_client_request_get = CAN_FIRE_RL_rl_ndm_reset ; + assign corew$EN_ndm_reset_client_response_put = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; // submodule jtagtap @@ -1659,26 +1669,29 @@ module mkP3_Core(CLK, assign jtagtap$jtag_tdi = jtag_tdi ; assign jtagtap$jtag_tms = jtag_tms ; + // submodule ndm_reset_controller + assign ndm_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule tv_xactor assign tv_xactor$axi_out_tready = tv_verifier_info_tx_tready ; assign tv_xactor$tv_in_put = corew$tv_verifier_info_get_get ; assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 = + assign IF_bus_dmi_req_fifof_first__6_BITS_1_TO_0_7_EQ_ETC___d87 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? - corew$RDY_dm_dmi_read_addr : + corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || bus_dmi_rsp_fifof_cntr_r != 2'd2) && (bus_dmi_req_fifof$D_OUT[1:0] != 2'd2 || - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_write) ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 = + bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_9_MINUS_1___d37 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1690,7 +1703,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_once <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -1703,7 +1716,8 @@ module mkP3_Core(CLK, if (bus_dmi_rsp_fifof_q_1$EN) bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY bus_dmi_rsp_fifof_q_1$D_IN; - if (rg_once$EN) rg_once <= `BSV_ASSIGNMENT_DELAY rg_once$D_IN; + if (rg_ndm_reset_delay$EN) + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end end @@ -1715,9 +1729,41 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_once = 1'h0; + rg_ndm_reset_delay = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + begin + v__h1278 = $stime; + #0; + end + v__h1272 = v__h1278 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1272, + $signed(32'd10)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1389 = $stime; + #0; + end + v__h1383 = v__h1389 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1383); + end + // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index a4e336f..0e742fc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -41,7 +41,6 @@ // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg // axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg @@ -133,7 +132,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awready, axi4_slave_wvalid, - axi4_slave_wid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, @@ -253,7 +251,6 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_m_wvalid input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; @@ -814,7 +811,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_wr_addr$FULL_N; // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; wire m_slave_xactor_f_wr_data$CLR, m_slave_xactor_f_wr_data$DEQ, m_slave_xactor_f_wr_data$EMPTY_N, @@ -1015,22 +1012,22 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75671; - reg [31 : 0] v__h75866; - reg [31 : 0] v__h76061; - reg [31 : 0] v__h76256; - reg [31 : 0] v__h76451; - reg [31 : 0] v__h76646; - reg [31 : 0] v__h76841; - reg [31 : 0] v__h77036; - reg [31 : 0] v__h77231; - reg [31 : 0] v__h77426; - reg [31 : 0] v__h77621; - reg [31 : 0] v__h77816; - reg [31 : 0] v__h78011; - reg [31 : 0] v__h78206; - reg [31 : 0] v__h78401; - reg [31 : 0] v__h78596; + reg [31 : 0] v__h75656; + reg [31 : 0] v__h75851; + reg [31 : 0] v__h76046; + reg [31 : 0] v__h76241; + reg [31 : 0] v__h76436; + reg [31 : 0] v__h76631; + reg [31 : 0] v__h76826; + reg [31 : 0] v__h77021; + reg [31 : 0] v__h77216; + reg [31 : 0] v__h77411; + reg [31 : 0] v__h77606; + reg [31 : 0] v__h77801; + reg [31 : 0] v__h77996; + reg [31 : 0] v__h78191; + reg [31 : 0] v__h78386; + reg [31 : 0] v__h78581; reg [31 : 0] v__h6142; reg [31 : 0] v__h13078; reg [31 : 0] v__h13263; @@ -1042,19 +1039,19 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h24054; reg [31 : 0] v__h26248; reg [31 : 0] v__h26461; - reg [31 : 0] v__h26738; - reg [31 : 0] v__h26966; - reg [31 : 0] v__h27863; - reg [31 : 0] v__h28046; - reg [31 : 0] v__h67028; - reg [31 : 0] v__h67316; - reg [31 : 0] v__h67845; - reg [31 : 0] v__h67931; - reg [31 : 0] v__h68130; - reg [31 : 0] v__h68351; - reg [31 : 0] v__h74688; - reg [31 : 0] v__h74798; - reg [31 : 0] v__h74911; + reg [31 : 0] v__h26735; + reg [31 : 0] v__h26959; + reg [31 : 0] v__h27854; + reg [31 : 0] v__h28037; + reg [31 : 0] v__h67019; + reg [31 : 0] v__h67307; + reg [31 : 0] v__h67836; + reg [31 : 0] v__h67922; + reg [31 : 0] v__h68121; + reg [31 : 0] v__h68340; + reg [31 : 0] v__h74675; + reg [31 : 0] v__h74785; + reg [31 : 0] v__h74898; reg [31 : 0] v__h6136; reg [31 : 0] v__h13072; reg [31 : 0] v__h13257; @@ -1066,42 +1063,42 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h25967; reg [31 : 0] v__h26242; reg [31 : 0] v__h26455; - reg [31 : 0] v__h26732; - reg [31 : 0] v__h26960; - reg [31 : 0] v__h27857; - reg [31 : 0] v__h28040; - reg [31 : 0] v__h67022; - reg [31 : 0] v__h67310; - reg [31 : 0] v__h67839; - reg [31 : 0] v__h67925; - reg [31 : 0] v__h68124; - reg [31 : 0] v__h68345; - reg [31 : 0] v__h74682; - reg [31 : 0] v__h74792; - reg [31 : 0] v__h74905; - reg [31 : 0] v__h75665; - reg [31 : 0] v__h75860; - reg [31 : 0] v__h76055; - reg [31 : 0] v__h76250; - reg [31 : 0] v__h76445; - reg [31 : 0] v__h76640; - reg [31 : 0] v__h76835; - reg [31 : 0] v__h77030; - reg [31 : 0] v__h77225; - reg [31 : 0] v__h77420; - reg [31 : 0] v__h77615; - reg [31 : 0] v__h77810; - reg [31 : 0] v__h78005; - reg [31 : 0] v__h78200; - reg [31 : 0] v__h78395; - reg [31 : 0] v__h78590; + reg [31 : 0] v__h26729; + reg [31 : 0] v__h26953; + reg [31 : 0] v__h27848; + reg [31 : 0] v__h28031; + reg [31 : 0] v__h67013; + reg [31 : 0] v__h67301; + reg [31 : 0] v__h67830; + reg [31 : 0] v__h67916; + reg [31 : 0] v__h68115; + reg [31 : 0] v__h68334; + reg [31 : 0] v__h74669; + reg [31 : 0] v__h74779; + reg [31 : 0] v__h74892; + reg [31 : 0] v__h75650; + reg [31 : 0] v__h75845; + reg [31 : 0] v__h76040; + reg [31 : 0] v__h76235; + reg [31 : 0] v__h76430; + reg [31 : 0] v__h76625; + reg [31 : 0] v__h76820; + reg [31 : 0] v__h77015; + reg [31 : 0] v__h77210; + reg [31 : 0] v__h77405; + reg [31 : 0] v__h77600; + reg [31 : 0] v__h77795; + reg [31 : 0] v__h77990; + reg [31 : 0] v__h78185; + reg [31 : 0] v__h78380; + reg [31 : 0] v__h78575; // synopsys translate_on // remaining internal signals reg [63 : 0] y_avValue_fst__h26146; - reg [4 : 0] x__h24009, x__h67485; + reg [4 : 0] x__h24009, x__h67476; reg [2 : 0] x__h13491, x__h23830; - reg [1 : 0] v__h67105, y_avValue_snd__h26147; + reg [1 : 0] v__h67096, y_avValue_snd__h26147; reg CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, @@ -1150,7 +1147,7 @@ module mkPLIC_16_2_7(CLK, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, @@ -1248,7 +1245,7 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; wire [63 : 0] addr_offset__h13214, - addr_offset__h26927, + addr_offset__h26920, rdata___1__h26402, rdata__h26200, v__h13420, @@ -1269,9 +1266,9 @@ module mkPLIC_16_2_7(CLK, y_avValue_fst__h26192; wire [31 : 0] v_ie__h18145, v_ip__h13672, - wdata32__h26928, + wdata32__h26921, x__h23671, - x__h67108; + x__h67099; wire [9 : 0] source_id__h15663, source_id__h15770, source_id__h15843, @@ -1334,121 +1331,121 @@ module mkPLIC_16_2_7(CLK, source_id__h23227, source_id__h23335, source_id__h23443, - source_id__h29473, - source_id__h30683, - source_id__h31893, - source_id__h33103, - source_id__h34313, - source_id__h35523, - source_id__h36733, - source_id__h37943, - source_id__h39153, - source_id__h40363, - source_id__h41573, - source_id__h42783, - source_id__h43993, - source_id__h45203, - source_id__h46413, - source_id__h47623, - source_id__h48833, - source_id__h50043, - source_id__h51253, - source_id__h52463, - source_id__h53673, - source_id__h54883, - source_id__h56093, - source_id__h57303, - source_id__h58513, - source_id__h59723, - source_id__h60933, - source_id__h62143, - source_id__h63353, - source_id__h64563, - source_id__h65773, - source_id__h67434, + source_id__h29464, + source_id__h30674, + source_id__h31884, + source_id__h33094, + source_id__h34304, + source_id__h35514, + source_id__h36724, + source_id__h37934, + source_id__h39144, + source_id__h40354, + source_id__h41564, + source_id__h42774, + source_id__h43984, + source_id__h45194, + source_id__h46404, + source_id__h47614, + source_id__h48824, + source_id__h50034, + source_id__h51244, + source_id__h52454, + source_id__h53664, + source_id__h54874, + source_id__h56084, + source_id__h57294, + source_id__h58504, + source_id__h59714, + source_id__h60924, + source_id__h62134, + source_id__h63344, + source_id__h64554, + source_id__h65764, + source_id__h67425, source_id_base__h13628, - source_id_base__h28146; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, + source_id_base__h28137; + wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71311, - b__h73316, + b__h71298, + b__h73303, max_id__h23957; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, + wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71310, - a__h73315; + a__h71297, + a__h73302; wire [1 : 0] rresp__h26201, - v__h26932, - v__h27092, - v__h27105, - v__h27940, - v__h27959, - v__h28123, - v__h28142, - v__h67142, - v__h67430, - v__h67474, + v__h26925, + v__h27083, + v__h27096, + v__h27931, + v__h27950, + v__h28114, + v__h28133, + v__h67133, + v__h67421, + v__h67465, y_avValue_snd__h26093, y_avValue_snd__h26114, y_avValue_snd__h26126, @@ -1460,8 +1457,8 @@ module mkPLIC_16_2_7(CLK, y_avValue_snd__h26193; wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, NOT_m_cfg_verbosity_read_ULE_1_5___d16, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, @@ -1469,62 +1466,62 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320, - NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328, - NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336, - NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344, - NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352, - NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360, - NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256, - NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264, - NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272, - NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280, - NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288, - NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296, - NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304, - NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, + NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240, + NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318, + NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326, + NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334, + NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342, + NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350, + NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358, + NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247, + NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254, + NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262, + NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270, + NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278, + NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286, + NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294, + NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302, + NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310, _dfoo1, _dfoo10, _dfoo100, @@ -3098,83 +3095,83 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; @@ -3321,10 +3318,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71310 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h71297 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73315 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h73302 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3381,7 +3378,7 @@ module mkPLIC_16_2_7(CLK, .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(m_slave_xactor_f_wr_data$D_IN), @@ -3442,181 +3439,181 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3686,174 +3683,174 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1988 ; // register m_cfg_verbosity @@ -3879,8 +3876,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 @@ -3894,8 +3891,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3906,8 +3903,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3918,8 +3915,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3931,8 +3928,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3944,8 +3941,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3957,8 +3954,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3970,8 +3967,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3983,8 +3980,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3996,8 +3993,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4009,8 +4006,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4021,8 +4018,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4033,8 +4030,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4045,8 +4042,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4057,8 +4054,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4069,8 +4066,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4081,8 +4078,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4093,8 +4090,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4105,8 +4102,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 @@ -4312,192 +4309,192 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4829,10 +4826,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_data assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; assign m_slave_xactor_f_wr_data$ENQ = axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; @@ -4840,7 +4834,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_resp assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26932 } ; + { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26925 } ; assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_f_wr_resp$DEQ = axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; @@ -4863,54 +4857,54 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67108 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67108 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26927[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : + ((x__h67099 == 32'h00200000) ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : + x__h67099 != 32'h00200004 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + addr_offset__h26920[11:2] == 10'd0 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? m_vrg_source_prio_10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? m_vrg_source_prio_11 : @@ -4921,38 +4915,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? 5'd10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? m_vrg_source_prio_12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? m_vrg_source_prio_13 : @@ -4963,50 +4957,50 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? 5'd12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? m_vrg_source_prio_14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? 5'd15 : (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? 5'd14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : @@ -5015,39 +5009,39 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? m_vrg_source_prio_2 : IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? @@ -5065,38 +5059,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? m_vrg_source_prio_4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? m_vrg_source_prio_5 : @@ -5107,38 +5101,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? 5'd4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? m_vrg_source_prio_6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? m_vrg_source_prio_7 : @@ -5149,38 +5143,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? 5'd6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? m_vrg_source_prio_8 : IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? m_vrg_source_prio_9 : @@ -5237,10792 +5231,10792 @@ module mkPLIC_16_2_7(CLK, x__h23671 == 32'h00200004 && m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && x__h24009 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30683 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h30674 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31893 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h31884 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33103 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h33094 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34313 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h34304 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35523 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h35514 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36733 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h36724 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37943 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h37934 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39153 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h39144 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40363 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h40354 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41573 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h41564 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42783 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h42774 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43993 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h43984 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45203 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h45194 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46413 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h46404 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47623 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h47614 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48833 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h48824 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50043 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h50034 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51253 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h51244 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52463 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h52454 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53673 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h53664 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54883 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h54874 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56093 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h56084 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57303 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h57294 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58513 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h58504 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59723 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h59714 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60933 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h60924 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62143 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h62134 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63353 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h63344 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64563 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h64554 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65773 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h65764 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29473 <= 10'd16 ; - assign NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242 = + source_id__h29464 <= 10'd16 ; + assign NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240 = !m_vrg_source_busy_0 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_0 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320 = + assign NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328 = + assign NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336 = + assign NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344 = + assign NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352 = + assign NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360 = + assign NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249 = + assign NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256 = + assign NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264 = + assign NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272 = + assign NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280 = + assign NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288 = + assign NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296 = + assign NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304 = + assign NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_8_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312 = + assign NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_9_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo10 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo100 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo883 ; assign _dfoo102 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo963 ; assign _dfoo11 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo110 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo983 ; assign _dfoo112 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo120 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo130 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1233 ; assign _dfoo137 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1253 ; assign _dfoo139 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo140 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1273 ; assign _dfoo141 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1363 ; assign _dfoo15 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo150 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1373 ; assign _dfoo151 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1393 ; assign _dfoo153 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1413 ; assign _dfoo155 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo160 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1513 ; assign _dfoo165 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1533 ; assign _dfoo167 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1553 ; assign _dfoo169 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1563 ; assign _dfoo17 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo170 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1633 ; assign _dfoo177 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1653 ; assign _dfoo179 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo180 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1673 ; assign _dfoo181 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1693 ; assign _dfoo183 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo190 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1773 ; assign _dfoo191 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1793 ; assign _dfoo193 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1813 ; assign _dfoo195 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1833 ; assign _dfoo197 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo20 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo200 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1963 ; assign _dfoo21 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo210 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo220 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo230 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo240 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo250 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo260 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo270 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo137 ; assign _dfoo274 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo139 ; assign _dfoo276 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo141 ; assign _dfoo278 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo143 ; assign _dfoo28 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo280 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo145 ; assign _dfoo282 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo147 ; assign _dfoo284 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo149 ; assign _dfoo286 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo151 ; assign _dfoo288 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo153 ; assign _dfoo29 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo290 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo155 ; assign _dfoo292 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo157 ; assign _dfoo294 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo159 ; assign _dfoo296 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo161 ; assign _dfoo298 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo163 ; assign _dfoo3 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo30 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo300 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo165 ; assign _dfoo302 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo167 ; assign _dfoo304 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo169 ; assign _dfoo306 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo171 ; assign _dfoo308 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo173 ; assign _dfoo31 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo310 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo175 ; assign _dfoo312 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo177 ; assign _dfoo314 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo179 ; assign _dfoo316 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo181 ; assign _dfoo318 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo183 ; assign _dfoo32 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo320 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo185 ; assign _dfoo322 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo187 ; assign _dfoo324 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo189 ; assign _dfoo326 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo191 ; assign _dfoo328 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo193 ; assign _dfoo33 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo330 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo195 ; assign _dfoo332 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo197 ; assign _dfoo334 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo199 ; assign _dfoo336 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo201 ; assign _dfoo338 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo203 ; assign _dfoo34 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo340 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo350 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo360 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo370 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo380 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo390 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo40 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo400 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo273 ; assign _dfoo41 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo410 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo275 ; assign _dfoo412 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo277 ; assign _dfoo414 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo279 ; assign _dfoo416 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo281 ; assign _dfoo418 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo283 ; assign _dfoo42 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo420 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo285 ; assign _dfoo422 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo287 ; assign _dfoo424 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo289 ; assign _dfoo426 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo291 ; assign _dfoo428 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo293 ; assign _dfoo43 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo430 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo295 ; assign _dfoo432 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo297 ; assign _dfoo434 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo299 ; assign _dfoo436 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo301 ; assign _dfoo438 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo303 ; assign _dfoo44 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo440 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo305 ; assign _dfoo442 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo307 ; assign _dfoo444 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo309 ; assign _dfoo446 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo311 ; assign _dfoo448 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo313 ; assign _dfoo45 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo450 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo315 ; assign _dfoo452 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo317 ; assign _dfoo454 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo319 ; assign _dfoo456 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo321 ; assign _dfoo458 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo323 ; assign _dfoo46 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo460 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo325 ; assign _dfoo462 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo327 ; assign _dfoo464 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo329 ; assign _dfoo466 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo331 ; assign _dfoo468 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo333 ; assign _dfoo47 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo470 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo335 ; assign _dfoo472 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo337 ; assign _dfoo474 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo339 ; assign _dfoo476 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo480 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo490 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo50 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo500 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo510 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo520 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo530 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo540 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo409 ; assign _dfoo546 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo411 ; assign _dfoo548 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo413 ; assign _dfoo55 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo550 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo415 ; assign _dfoo552 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo417 ; assign _dfoo554 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo419 ; assign _dfoo556 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo421 ; assign _dfoo558 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo423 ; assign _dfoo56 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo560 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo425 ; assign _dfoo562 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo427 ; assign _dfoo564 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo429 ; assign _dfoo566 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo431 ; assign _dfoo568 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo433 ; assign _dfoo57 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo570 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo435 ; assign _dfoo572 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo437 ; assign _dfoo574 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo439 ; assign _dfoo576 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo441 ; assign _dfoo578 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo443 ; assign _dfoo58 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo580 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo445 ; assign _dfoo582 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo447 ; assign _dfoo584 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo449 ; assign _dfoo586 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo451 ; assign _dfoo588 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo453 ; assign _dfoo59 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo590 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo455 ; assign _dfoo592 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo457 ; assign _dfoo594 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo459 ; assign _dfoo596 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo461 ; assign _dfoo598 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo463 ; assign _dfoo6 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo60 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo600 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo465 ; assign _dfoo602 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo467 ; assign _dfoo604 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo469 ; assign _dfoo606 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo471 ; assign _dfoo608 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo473 ; assign _dfoo61 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo610 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo475 ; assign _dfoo612 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo620 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo630 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo640 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo650 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo660 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo670 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo680 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo545 ; assign _dfoo682 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo547 ; assign _dfoo684 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo549 ; assign _dfoo686 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo551 ; assign _dfoo688 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo553 ; assign _dfoo690 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo555 ; assign _dfoo692 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo557 ; assign _dfoo694 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo559 ; assign _dfoo696 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo561 ; assign _dfoo698 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo563 ; assign _dfoo7 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo70 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo565 ; assign _dfoo702 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo567 ; assign _dfoo704 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo569 ; assign _dfoo706 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo571 ; assign _dfoo708 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo573 ; assign _dfoo710 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo575 ; assign _dfoo712 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo577 ; assign _dfoo714 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo579 ; assign _dfoo716 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo581 ; assign _dfoo718 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo583 ; assign _dfoo72 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo585 ; assign _dfoo722 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo587 ; assign _dfoo724 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo589 ; assign _dfoo726 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo591 ; assign _dfoo728 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo593 ; assign _dfoo730 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo595 ; assign _dfoo732 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo597 ; assign _dfoo734 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo599 ; assign _dfoo736 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo601 ; assign _dfoo738 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo603 ; assign _dfoo74 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo605 ; assign _dfoo742 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo607 ; assign _dfoo744 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo609 ; assign _dfoo746 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo611 ; assign _dfoo748 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo80 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo681 ; assign _dfoo818 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo683 ; assign _dfoo82 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo685 ; assign _dfoo822 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo687 ; assign _dfoo824 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo689 ; assign _dfoo826 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo691 ; assign _dfoo828 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo693 ; assign _dfoo830 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo695 ; assign _dfoo832 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo697 ; assign _dfoo834 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo699 ; assign _dfoo836 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo701 ; assign _dfoo838 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo703 ; assign _dfoo84 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo705 ; assign _dfoo842 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo707 ; assign _dfoo844 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo709 ; assign _dfoo846 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo711 ; assign _dfoo848 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo713 ; assign _dfoo850 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo715 ; assign _dfoo852 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo717 ; assign _dfoo854 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo719 ; assign _dfoo856 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo721 ; assign _dfoo858 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo723 ; assign _dfoo86 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo725 ; assign _dfoo862 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo727 ; assign _dfoo864 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo729 ; assign _dfoo866 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo731 ; assign _dfoo868 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo733 ; assign _dfoo870 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo735 ; assign _dfoo872 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo737 ; assign _dfoo874 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo739 ; assign _dfoo876 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo741 ; assign _dfoo878 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo743 ; assign _dfoo88 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo745 ; assign _dfoo882 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo747 ; assign _dfoo884 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo90 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo817 ; assign _dfoo954 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo819 ; assign _dfoo956 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo821 ; assign _dfoo958 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo823 ; assign _dfoo96 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo825 ; assign _dfoo962 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo827 ; assign _dfoo964 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo829 ; assign _dfoo966 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo831 ; assign _dfoo968 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo833 ; assign _dfoo970 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo835 ; assign _dfoo972 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo837 ; assign _dfoo974 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo839 ; assign _dfoo976 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo841 ; assign _dfoo978 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo843 ; assign _dfoo98 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo845 ; assign _dfoo982 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo847 ; assign _dfoo984 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo849 ; assign _dfoo986 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo851 ; assign _dfoo988 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo853 ; assign _dfoo990 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo855 ; assign _dfoo992 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo857 ; assign _dfoo994 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo859 ; assign _dfoo996 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo861 ; assign _dfoo998 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo863 ; - assign a__h71310 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign a__h71297 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73315 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; + assign a__h73302 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; assign addr_offset__h13214 = m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26927 = + assign addr_offset__h26920 = m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71311 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign b__h71298 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73316 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; + assign b__h73303 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = addr_offset__h13214 < 64'h0000000000003000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = @@ -16044,181 +16038,181 @@ module mkPLIC_16_2_7(CLK, addr_offset__h13214 < 64'h0000000000002000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = source_id_base__h13628 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26927[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26927[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26927[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = + addr_offset__h26920[16:12] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = + addr_offset__h26920[16:12] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = + addr_offset__h26920[16:12] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26927 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26927[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26927[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26927[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26927[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26927[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26927[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26927[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26927[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26927[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26927[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26927[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26927[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26927[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26927[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26927[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26927[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26927[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = + addr_offset__h26920 < 64'h0000000000001000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = + addr_offset__h26920[11:2] <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = + addr_offset__h26920[11:2] == 10'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = + addr_offset__h26920[11:2] == 10'd2 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = + addr_offset__h26920[11:2] == 10'd3 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = + addr_offset__h26920[11:2] == 10'd4 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = + addr_offset__h26920[11:2] == 10'd5 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = + addr_offset__h26920[11:2] == 10'd6 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = + addr_offset__h26920[11:2] == 10'd7 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = + addr_offset__h26920[11:2] == 10'd8 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = + addr_offset__h26920[11:2] == 10'd9 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = + addr_offset__h26920[11:2] == 10'd10 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = + addr_offset__h26920[11:2] == 10'd11 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = + addr_offset__h26920[11:2] == 10'd12 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = + addr_offset__h26920[11:2] == 10'd13 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = + addr_offset__h26920[11:2] == 10'd14 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = + addr_offset__h26920[11:2] == 10'd15 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = + addr_offset__h26920[11:2] == 10'd16 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26927 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28146 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = + addr_offset__h26920 < 64'h0000000000002000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = + source_id_base__h28137 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = + addr_offset__h26920 < 64'h0000000000003000 ; assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26927 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26927[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26927[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26927[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = + addr_offset__h26920[11:7] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = + addr_offset__h26920[11:7] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = + addr_offset__h26920[11:7] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && m_vvrg_ie_1_10 ; assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && m_vvrg_ie_1_11 ; assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && m_vvrg_ie_1_12 ; assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && m_vvrg_ie_1_13 ; assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = m_vrg_source_ip_13 && @@ -16233,45 +16227,45 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && m_vvrg_ie_1_14 ; assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && m_vvrg_ie_1_15 ; assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && m_vvrg_ie_1_16 ; assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = m_vrg_source_ip_16 && @@ -16285,90 +16279,90 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && m_vvrg_ie_1_2 ; assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && m_vvrg_ie_1_3 ; assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && m_vvrg_ie_1_4 ; assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && m_vvrg_ie_1_5 ; assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && m_vvrg_ie_1_6 ; assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && m_vvrg_ie_1_7 ; assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = m_vrg_source_ip_7 && @@ -16383,30 +16377,30 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && m_vvrg_ie_1_8 ; assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && m_vvrg_ie_1_9 ; assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = m_vrg_source_ip_9 && @@ -16493,40 +16487,40 @@ module mkPLIC_16_2_7(CLK, assign source_id__h23227 = 10'd3 + source_id_base__h13628 ; assign source_id__h23335 = 10'd2 + source_id_base__h13628 ; assign source_id__h23443 = 10'd1 + source_id_base__h13628 ; - assign source_id__h29473 = { addr_offset__h26927[4:0], 5'd1 } ; - assign source_id__h30683 = { addr_offset__h26927[4:0], 5'd2 } ; - assign source_id__h31893 = { addr_offset__h26927[4:0], 5'd3 } ; - assign source_id__h33103 = { addr_offset__h26927[4:0], 5'd4 } ; - assign source_id__h34313 = { addr_offset__h26927[4:0], 5'd5 } ; - assign source_id__h35523 = { addr_offset__h26927[4:0], 5'd6 } ; - assign source_id__h36733 = { addr_offset__h26927[4:0], 5'd7 } ; - assign source_id__h37943 = { addr_offset__h26927[4:0], 5'd8 } ; - assign source_id__h39153 = { addr_offset__h26927[4:0], 5'd9 } ; - assign source_id__h40363 = { addr_offset__h26927[4:0], 5'd10 } ; - assign source_id__h41573 = { addr_offset__h26927[4:0], 5'd11 } ; - assign source_id__h42783 = { addr_offset__h26927[4:0], 5'd12 } ; - assign source_id__h43993 = { addr_offset__h26927[4:0], 5'd13 } ; - assign source_id__h45203 = { addr_offset__h26927[4:0], 5'd14 } ; - assign source_id__h46413 = { addr_offset__h26927[4:0], 5'd15 } ; - assign source_id__h47623 = { addr_offset__h26927[4:0], 5'd16 } ; - assign source_id__h48833 = { addr_offset__h26927[4:0], 5'd17 } ; - assign source_id__h50043 = { addr_offset__h26927[4:0], 5'd18 } ; - assign source_id__h51253 = { addr_offset__h26927[4:0], 5'd19 } ; - assign source_id__h52463 = { addr_offset__h26927[4:0], 5'd20 } ; - assign source_id__h53673 = { addr_offset__h26927[4:0], 5'd21 } ; - assign source_id__h54883 = { addr_offset__h26927[4:0], 5'd22 } ; - assign source_id__h56093 = { addr_offset__h26927[4:0], 5'd23 } ; - assign source_id__h57303 = { addr_offset__h26927[4:0], 5'd24 } ; - assign source_id__h58513 = { addr_offset__h26927[4:0], 5'd25 } ; - assign source_id__h59723 = { addr_offset__h26927[4:0], 5'd26 } ; - assign source_id__h60933 = { addr_offset__h26927[4:0], 5'd27 } ; - assign source_id__h62143 = { addr_offset__h26927[4:0], 5'd28 } ; - assign source_id__h63353 = { addr_offset__h26927[4:0], 5'd29 } ; - assign source_id__h64563 = { addr_offset__h26927[4:0], 5'd30 } ; - assign source_id__h65773 = { addr_offset__h26927[4:0], 5'd31 } ; - assign source_id__h67434 = { 5'd0, x__h67485 } ; + assign source_id__h29464 = { addr_offset__h26920[4:0], 5'd1 } ; + assign source_id__h30674 = { addr_offset__h26920[4:0], 5'd2 } ; + assign source_id__h31884 = { addr_offset__h26920[4:0], 5'd3 } ; + assign source_id__h33094 = { addr_offset__h26920[4:0], 5'd4 } ; + assign source_id__h34304 = { addr_offset__h26920[4:0], 5'd5 } ; + assign source_id__h35514 = { addr_offset__h26920[4:0], 5'd6 } ; + assign source_id__h36724 = { addr_offset__h26920[4:0], 5'd7 } ; + assign source_id__h37934 = { addr_offset__h26920[4:0], 5'd8 } ; + assign source_id__h39144 = { addr_offset__h26920[4:0], 5'd9 } ; + assign source_id__h40354 = { addr_offset__h26920[4:0], 5'd10 } ; + assign source_id__h41564 = { addr_offset__h26920[4:0], 5'd11 } ; + assign source_id__h42774 = { addr_offset__h26920[4:0], 5'd12 } ; + assign source_id__h43984 = { addr_offset__h26920[4:0], 5'd13 } ; + assign source_id__h45194 = { addr_offset__h26920[4:0], 5'd14 } ; + assign source_id__h46404 = { addr_offset__h26920[4:0], 5'd15 } ; + assign source_id__h47614 = { addr_offset__h26920[4:0], 5'd16 } ; + assign source_id__h48824 = { addr_offset__h26920[4:0], 5'd17 } ; + assign source_id__h50034 = { addr_offset__h26920[4:0], 5'd18 } ; + assign source_id__h51244 = { addr_offset__h26920[4:0], 5'd19 } ; + assign source_id__h52454 = { addr_offset__h26920[4:0], 5'd20 } ; + assign source_id__h53664 = { addr_offset__h26920[4:0], 5'd21 } ; + assign source_id__h54874 = { addr_offset__h26920[4:0], 5'd22 } ; + assign source_id__h56084 = { addr_offset__h26920[4:0], 5'd23 } ; + assign source_id__h57294 = { addr_offset__h26920[4:0], 5'd24 } ; + assign source_id__h58504 = { addr_offset__h26920[4:0], 5'd25 } ; + assign source_id__h59714 = { addr_offset__h26920[4:0], 5'd26 } ; + assign source_id__h60924 = { addr_offset__h26920[4:0], 5'd27 } ; + assign source_id__h62134 = { addr_offset__h26920[4:0], 5'd28 } ; + assign source_id__h63344 = { addr_offset__h26920[4:0], 5'd29 } ; + assign source_id__h64554 = { addr_offset__h26920[4:0], 5'd30 } ; + assign source_id__h65764 = { addr_offset__h26920[4:0], 5'd31 } ; + assign source_id__h67425 = { 5'd0, x__h67476 } ; assign source_id_base__h13628 = { addr_offset__h13214[4:0], 5'h0 } ; - assign source_id_base__h28146 = { addr_offset__h26927[4:0], 5'h0 } ; + assign source_id_base__h28137 = { addr_offset__h26920[4:0], 5'h0 } ; assign v__h13420 = { 61'd0, x__h13491 } ; assign v__h13669 = { 32'd0, v_ip__h13672 } ; assign v__h18142 = { 32'd0, v_ie__h18145 } ; @@ -16536,48 +16530,48 @@ module mkPLIC_16_2_7(CLK, v__h25472 : 64'd0 ; assign v__h25472 = { 59'd0, max_id__h23957 } ; - assign v__h26932 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? + assign v__h26925 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? 2'b11 : - v__h27092 ; - assign v__h27092 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27105 : - v__h27940 ; - assign v__h27105 = - (addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? + v__h27083 ; + assign v__h27083 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + v__h27096 : + v__h27931 ; + assign v__h27096 = + (addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? 2'b0 : 2'b10 ; - assign v__h27940 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27959 : - v__h28123 ; - assign v__h27959 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? + assign v__h27931 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? + v__h27950 : + v__h28114 ; + assign v__h27950 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? 2'b0 : 2'b10 ; - assign v__h28123 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign v__h28114 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? + v__h28133 : + v__h67096 ; + assign v__h28133 = + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28142 : - v__h67105 ; - assign v__h28142 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? 2'b0 : 2'b10 ; - assign v__h67142 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? + assign v__h67133 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? 2'b0 : 2'b10 ; - assign v__h67430 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67474 : + assign v__h67421 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? + v__h67465 : 2'b10 ; - assign v__h67474 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? + assign v__h67465 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? 2'b0 : 2'b10 ; assign v_ie__h18145 = @@ -16710,8 +16704,8 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26928 = - (addr_offset__h26927[2:0] == 3'd4) ? + assign wdata32__h26921 = + (addr_offset__h26920[2:0] == 3'd4) ? m_slave_xactor_f_wr_data$D_OUT[72:41] : m_slave_xactor_f_wr_data$D_OUT[40:9] ; assign x__h23671 = @@ -16720,8 +16714,8 @@ module mkPLIC_16_2_7(CLK, (addr_offset__h13214[2:0] == 3'd4) ? rdata___1__h26402 : rdata__h26200 ; - assign x__h67108 = - { addr_offset__h26927[31:16], 4'd0, addr_offset__h26927[11:0] } ; + assign x__h67099 = + { addr_offset__h26920[31:16], 4'd0, addr_offset__h26920[11:0] } ; assign y_avValue_fst__h26092 = (x__h24009 == 5'd0) ? v__h25453 : 64'd0 ; assign y_avValue_fst__h26113 = m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? @@ -16853,13 +16847,13 @@ module mkPLIC_16_2_7(CLK, default: x__h24009 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h26927 or + always@(addr_offset__h26920 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26927[16:12]) - 5'd0: x__h67485 = m_vrg_servicing_source_0; - 5'd1: x__h67485 = m_vrg_servicing_source_1; - default: x__h67485 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h26920[16:12]) + 5'd0: x__h67476 = m_vrg_servicing_source_0; + 5'd1: x__h67476 = m_vrg_servicing_source_1; + default: x__h67476 = 5'b01010 /* unspecified value */ ; endcase end always@(source_id__h16208 or @@ -24574,7 +24568,7 @@ module mkPLIC_16_2_7(CLK, default: y_avValue_fst__h26146 = 64'd0; endcase end - always@(source_id__h67434 or + always@(source_id__h67425 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24592,68 +24586,68 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h67434) + case (source_id__h67425) 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_0; 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_1; 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_2; 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_3; 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_4; 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_5; 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_6; 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_7; 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_8; 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_9; 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_10; 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_11; 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_12; 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_13; 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_14; 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_15; 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h67108 or v__h67142 or v__h67430) + always@(x__h67099 or v__h67133 or v__h67421) begin - case (x__h67108) - 32'h00200000: v__h67105 = v__h67142; - 32'h00200004: v__h67105 = v__h67430; - default: v__h67105 = 2'b10; + case (x__h67099) + 32'h00200000: v__h67096 = v__h67133; + 32'h00200004: v__h67096 = v__h67421; + default: v__h67096 = 2'b10; endcase end @@ -25240,9 +25234,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71310, + a__h71297, m_vrg_target_threshold_0, - b__h71311, + b__h71298, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25283,216 +25277,216 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73315, + a__h73302, m_vrg_target_threshold_1, - b__h73316, + b__h73303, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) begin - v__h75671 = $stime; + v__h75656 = $stime; #0; end - v__h75665 = v__h75671 / 32'd10; + v__h75650 = v__h75656 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75665, + v__h75650, $signed(32'd0), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) begin - v__h75866 = $stime; + v__h75851 = $stime; #0; end - v__h75860 = v__h75866 / 32'd10; + v__h75845 = v__h75851 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75860, + v__h75845, $signed(32'd1), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) begin - v__h76061 = $stime; + v__h76046 = $stime; #0; end - v__h76055 = v__h76061 / 32'd10; + v__h76040 = v__h76046 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76055, + v__h76040, $signed(32'd2), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) begin - v__h76256 = $stime; + v__h76241 = $stime; #0; end - v__h76250 = v__h76256 / 32'd10; + v__h76235 = v__h76241 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76250, + v__h76235, $signed(32'd3), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) begin - v__h76451 = $stime; + v__h76436 = $stime; #0; end - v__h76445 = v__h76451 / 32'd10; + v__h76430 = v__h76436 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76445, + v__h76430, $signed(32'd4), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) begin - v__h76646 = $stime; + v__h76631 = $stime; #0; end - v__h76640 = v__h76646 / 32'd10; + v__h76625 = v__h76631 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76640, + v__h76625, $signed(32'd5), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) begin - v__h76841 = $stime; + v__h76826 = $stime; #0; end - v__h76835 = v__h76841 / 32'd10; + v__h76820 = v__h76826 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76835, + v__h76820, $signed(32'd6), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) begin - v__h77036 = $stime; + v__h77021 = $stime; #0; end - v__h77030 = v__h77036 / 32'd10; + v__h77015 = v__h77021 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77030, + v__h77015, $signed(32'd7), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) begin - v__h77231 = $stime; + v__h77216 = $stime; #0; end - v__h77225 = v__h77231 / 32'd10; + v__h77210 = v__h77216 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77225, + v__h77210, $signed(32'd8), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) begin - v__h77426 = $stime; + v__h77411 = $stime; #0; end - v__h77420 = v__h77426 / 32'd10; + v__h77405 = v__h77411 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77420, + v__h77405, $signed(32'd9), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) begin - v__h77621 = $stime; + v__h77606 = $stime; #0; end - v__h77615 = v__h77621 / 32'd10; + v__h77600 = v__h77606 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77615, + v__h77600, $signed(32'd10), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) begin - v__h77816 = $stime; + v__h77801 = $stime; #0; end - v__h77810 = v__h77816 / 32'd10; + v__h77795 = v__h77801 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77810, + v__h77795, $signed(32'd11), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) begin - v__h78011 = $stime; + v__h77996 = $stime; #0; end - v__h78005 = v__h78011 / 32'd10; + v__h77990 = v__h77996 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78005, + v__h77990, $signed(32'd12), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) begin - v__h78206 = $stime; + v__h78191 = $stime; #0; end - v__h78200 = v__h78206 / 32'd10; + v__h78185 = v__h78191 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78200, + v__h78185, $signed(32'd13), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) begin - v__h78401 = $stime; + v__h78386 = $stime; #0; end - v__h78395 = v__h78401 / 32'd10; + v__h78380 = v__h78386 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78395, + v__h78380, $signed(32'd14), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) begin - v__h78596 = $stime; + v__h78581 = $stime; #0; end - v__h78590 = v__h78596 / 32'd10; + v__h78575 = v__h78581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78590, + v__h78575, $signed(32'd15), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) @@ -26127,14 +26121,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h26738 = $stime; + v__h26735 = $stime; #0; end - v__h26732 = v__h26738 / 32'd10; + v__h26729 = v__h26735 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26732); + $display("%0d: PLIC.rl_process_wr_req", v__h26729); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26238,15 +26232,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26287,485 +26273,467 @@ module mkPLIC_16_2_7(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) begin - v__h26966 = $stime; + v__h26959 = $stime; #0; end - v__h26960 = v__h26966 / 32'd10; + v__h26953 = v__h26959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26960); + v__h26953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) begin - v__h27863 = $stime; + v__h27854 = $stime; #0; end - v__h27857 = v__h27863 / 32'd10; + v__h27848 = v__h27854 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27857, - addr_offset__h26927[11:2], - wdata32__h26928); + v__h27848, + addr_offset__h26920[11:2], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) begin - v__h28046 = $stime; + v__h28037 = $stime; #0; end - v__h28040 = v__h28046 / 32'd10; + v__h28031 = v__h28037 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28040, - source_id_base__h28146); + v__h28031, + source_id_base__h28137); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) begin - v__h67028 = $stime; + v__h67019 = $stime; #0; end - v__h67022 = v__h67028 / 32'd10; + v__h67013 = v__h67019 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67022, - addr_offset__h26927[11:7], - source_id_base__h28146, - wdata32__h26928); + v__h67013, + addr_offset__h26920[11:7], + source_id_base__h28137, + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) begin - v__h67316 = $stime; + v__h67307 = $stime; #0; end - v__h67310 = v__h67316 / 32'd10; + v__h67301 = v__h67307 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67310, - addr_offset__h26927[16:12], - wdata32__h26928); + v__h67301, + addr_offset__h26920[16:12], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) begin - v__h67845 = $stime; + v__h67836 = $stime; #0; end - v__h67839 = v__h67845 / 32'd10; + v__h67830 = v__h67836 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67839, - addr_offset__h26927[16:12], - source_id__h67434); + v__h67830, + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) begin - v__h67931 = $stime; + v__h67922 = $stime; #0; end - v__h67925 = v__h67931 / 32'd10; + v__h67916 = v__h67922 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67925); + v__h67916); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Completion message from target %0d to source %0d", - addr_offset__h26927[16:12], - source_id__h67434); + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) begin - v__h68130 = $stime; + v__h68121 = $stime; #0; end - v__h68124 = v__h68130 / 32'd10; + v__h68115 = v__h68121 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68124); + v__h68115); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h68351 = $stime; + v__h68340 = $stime; #0; end - v__h68345 = v__h68351 / 32'd10; + v__h68334 = v__h68340 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68345); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68334); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26869,15 +26837,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26935,7 +26895,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26932); + $write("'h%h", v__h26925); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26951,38 +26911,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74688 = $stime; + v__h74675 = $stime; #0; end - v__h74682 = v__h74688 / 32'd10; + v__h74669 = v__h74675 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74682, + v__h74669, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74798 = $stime; + v__h74785 = $stime; #0; end - v__h74792 = v__h74798 / 32'd10; + v__h74779 = v__h74785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74792, + v__h74779, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74911 = $stime; + v__h74898 = $stime; #0; end - v__h74905 = v__h74911 / 32'd10; + v__h74892 = v__h74898 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74905, + v__h74892, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 6809f3b..5b384c7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -6,8 +6,6 @@ // // Ports: // Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg // RDY_start O 1 // master0_awvalid O 1 // master0_awid O 4 reg @@ -21,7 +19,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -50,7 +47,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -125,7 +121,6 @@ // master1_rlast I 1 reg // m_external_interrupt_req_set_not_clear I 1 // s_external_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 // debug_module_mem_server_awvalid I 1 @@ -140,7 +135,6 @@ // debug_module_mem_server_awqos I 4 reg // debug_module_mem_server_awregion I 4 reg // debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_wid I 4 reg // debug_module_mem_server_wdata I 64 reg // debug_module_mem_server_wstrb I 8 reg // debug_module_mem_server_wlast I 1 reg @@ -162,8 +156,6 @@ // hart0_fpr_mem_server_request_put I 70 reg // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 -// EN_hart0_server_reset_request_put I 1 -// EN_hart0_server_reset_response_get I 1 // EN_start I 1 // EN_set_verbosity I 1 // EN_hart0_run_halt_server_request_put I 1 @@ -200,12 +192,6 @@ module mkProc(CLK, RST_N, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - start_startpc, start_tohostAddr, start_fromhostAddr, @@ -238,8 +224,6 @@ module mkProc(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -312,8 +296,6 @@ module mkProc(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -364,8 +346,6 @@ module mkProc(CLK, s_external_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, - non_maskable_interrupt_req_set_not_clear, set_verbosity_verbosity, @@ -387,7 +367,6 @@ module mkProc(CLK, debug_module_mem_server_awready, debug_module_mem_server_wvalid, - debug_module_mem_server_wid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, @@ -474,14 +453,6 @@ module mkProc(CLK, input CLK; input RST_N; - // action method hart0_server_reset_request_put - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // action method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - // action method start input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; @@ -530,9 +501,6 @@ module mkProc(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -644,9 +612,6 @@ module mkProc(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -723,9 +688,6 @@ module mkProc(CLK, // action method s_external_interrupt_req input s_external_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; - // action method non_maskable_interrupt_req input non_maskable_interrupt_req_set_not_clear; @@ -752,7 +714,6 @@ module mkProc(CLK, // action method debug_module_mem_server_m_wvalid input debug_module_mem_server_wvalid; - input [3 : 0] debug_module_mem_server_wid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; @@ -893,7 +854,6 @@ module mkProc(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -901,8 +861,7 @@ module mkProc(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -926,8 +885,6 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, - RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, RDY_set_verbosity, RDY_start, RDY_v_to_TV_0_get, @@ -966,11 +923,9 @@ module mkProc(CLK, wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read; wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, @@ -1074,8 +1029,8 @@ module mkProc(CLK, wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN; // register llc_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire llc_axi4_adapter_master_xactor_rg_wr_data$EN; // register llc_axi4_adapter_master_xactor_rg_wr_resp @@ -1122,6 +1077,26 @@ module mkProc(CLK, reg llc_mem_server_propDstIdx_0_rl; wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN; + // register llc_mem_server_rg_cacheline_cache_addr + reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr; + wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN; + wire llc_mem_server_rg_cacheline_cache_addr$EN; + + // register llc_mem_server_rg_cacheline_cache_data + reg [511 : 0] llc_mem_server_rg_cacheline_cache_data; + wire [511 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN; + wire llc_mem_server_rg_cacheline_cache_data$EN; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay; + wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN; + + // register llc_mem_server_rg_cacheline_cache_state + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state; + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN; + wire llc_mem_server_rg_cacheline_cache_state$EN; + // register mmioPlatform_amoResp reg [63 : 0] mmioPlatform_amoResp; wire [63 : 0] mmioPlatform_amoResp$D_IN; @@ -1322,8 +1297,8 @@ module mkProc(CLK, wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_resp @@ -1435,7 +1410,6 @@ module mkProc(CLK, core_0$EN_recvDoStats, core_0$EN_renameDebug_renameErr_get, core_0$EN_sendDoStats, - core_0$EN_setDEIP, core_0$EN_setMEIP, core_0$EN_setSEIP, core_0$EN_tlbToMem_memReq_deq, @@ -1489,7 +1463,6 @@ module mkProc(CLK, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, core_0$sendDoStats, - core_0$setDEIP_v, core_0$setMEIP_v, core_0$setSEIP_v; @@ -1509,20 +1482,6 @@ module mkProc(CLK, enqDst_1_0_dummy2_1$EN, enqDst_1_0_dummy2_1$Q_OUT; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule llc reg [644 : 0] llc$dma_memReq_enq_x; wire [640 : 0] llc$to_mem_toM_first; @@ -1603,7 +1562,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N; // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_data - wire [76 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, + wire [72 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT; wire llc_mem_server_axi4_slave_xactor_f_wr_data$CLR, llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ, @@ -1631,13 +1590,10 @@ module mkProc(CLK, llc_mem_server_enqDst_0_dummy2_1$Q_OUT; // ports of submodule llc_mem_server_f_dword_in_line - wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN, - llc_mem_server_f_dword_in_line$D_OUT; + wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN; wire llc_mem_server_f_dword_in_line$CLR, llc_mem_server_f_dword_in_line$DEQ, - llc_mem_server_f_dword_in_line$EMPTY_N, - llc_mem_server_f_dword_in_line$ENQ, - llc_mem_server_f_dword_in_line$FULL_N; + llc_mem_server_f_dword_in_line$ENQ; // ports of submodule llc_mem_server_propDstData_0_dummy2_0 wire llc_mem_server_propDstData_0_dummy2_0$D_IN, @@ -1843,11 +1799,17 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, CAN_FIRE_RL_llc_mem_server_propDstData_0_canon, CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader, CAN_FIRE_RL_llc_mem_server_sendStRespToTlb, CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC, CAN_FIRE_RL_llc_mem_server_srcPropose, @@ -1901,7 +1863,6 @@ module mkProc(CLK, CAN_FIRE_RL_rl_dummy7, CAN_FIRE_RL_rl_dummy8, CAN_FIRE_RL_rl_dummy9, - CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_terminate, CAN_FIRE_RL_rl_tohost, CAN_FIRE_RL_sendPRq, @@ -1912,7 +1873,6 @@ module mkProc(CLK, CAN_FIRE_RL_srcPropose_1, CAN_FIRE_RL_srcPropose_2, CAN_FIRE_RL_srcPropose_3, - CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_debug_module_mem_server_m_arvalid, CAN_FIRE_debug_module_mem_server_m_awvalid, CAN_FIRE_debug_module_mem_server_m_bready, @@ -1927,8 +1887,6 @@ module mkProc(CLK, CAN_FIRE_hart0_put_other_req_put, CAN_FIRE_hart0_run_halt_server_request_put, CAN_FIRE_hart0_run_halt_server_response_get, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_master0_m_arready, CAN_FIRE_master0_m_awready, @@ -1962,11 +1920,17 @@ module mkProc(CLK, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, WILL_FIRE_RL_llc_mem_server_propDstData_0_canon, WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader, WILL_FIRE_RL_llc_mem_server_sendStRespToTlb, WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC, WILL_FIRE_RL_llc_mem_server_srcPropose, @@ -2020,7 +1984,6 @@ module mkProc(CLK, WILL_FIRE_RL_rl_dummy7, WILL_FIRE_RL_rl_dummy8, WILL_FIRE_RL_rl_dummy9, - WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_terminate, WILL_FIRE_RL_rl_tohost, WILL_FIRE_RL_sendPRq, @@ -2031,7 +1994,6 @@ module mkProc(CLK, WILL_FIRE_RL_srcPropose_1, WILL_FIRE_RL_srcPropose_2, WILL_FIRE_RL_srcPropose_3, - WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_debug_module_mem_server_m_arvalid, WILL_FIRE_debug_module_mem_server_m_awvalid, WILL_FIRE_debug_module_mem_server_m_bready, @@ -2046,8 +2008,6 @@ module mkProc(CLK, WILL_FIRE_hart0_put_other_req_put, WILL_FIRE_hart0_run_halt_server_request_put, WILL_FIRE_hart0_run_halt_server_response_get, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_master0_m_arready, WILL_FIRE_master0_m_awready, @@ -2071,9 +2031,11 @@ module mkProc(CLK, MUX_mmioPlatform_state$write_1__VAL_4; wire [644 : 0] MUX_llc$dma_memReq_enq_1__VAL_1, MUX_llc$dma_memReq_enq_1__VAL_2, - MUX_llc$dma_memReq_enq_1__VAL_3; + MUX_llc$dma_memReq_enq_1__VAL_3, + MUX_llc$dma_memReq_enq_1__VAL_4; wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + wire [511 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3, @@ -2097,6 +2059,7 @@ module mkProc(CLK, wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4; + wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2; wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1; wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1, MUX_mmioPlatform_state$write_1__VAL_2, @@ -2111,7 +2074,8 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, MUX_llc$dma_memReq_enq_1__SEL_1, - MUX_llc$dma_memReq_enq_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, MUX_mmioPlatform_amoResp$write_1__SEL_1, MUX_mmioPlatform_amoResp$write_1__SEL_2, MUX_mmioPlatform_curReq$write_1__SEL_1, @@ -2127,318 +2091,312 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h151720; - reg [31 : 0] v__h4189; - reg [31 : 0] v__h4362; - reg [31 : 0] v__h4626; - reg [31 : 0] v__h6665; - reg [31 : 0] v__h2465; - reg [31 : 0] v__h6966; - reg [31 : 0] v__h7459; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h93935; - reg [31 : 0] v__h93980; - reg [31 : 0] v__h93890; - reg [31 : 0] v__h104972; - reg [31 : 0] v__h104927; - reg [31 : 0] v__h123524; - reg [31 : 0] v__h123691; - reg [31 : 0] v__h125794; - reg [31 : 0] v__h143140; - reg [31 : 0] v__h122905; - reg [31 : 0] v__h149835; - reg [31 : 0] v__h150343; - reg [31 : 0] v__h2459; - reg [31 : 0] v__h4183; - reg [31 : 0] v__h4356; - reg [31 : 0] v__h4620; - reg [31 : 0] v__h6659; - reg [31 : 0] v__h6960; - reg [31 : 0] v__h7453; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h93884; - reg [31 : 0] v__h93929; - reg [31 : 0] v__h93974; - reg [31 : 0] v__h104921; - reg [31 : 0] v__h104966; - reg [31 : 0] v__h122899; - reg [31 : 0] v__h123518; - reg [31 : 0] v__h123685; - reg [31 : 0] v__h125788; - reg [31 : 0] v__h143134; - reg [31 : 0] v__h149829; - reg [31 : 0] v__h150337; - reg [31 : 0] v__h151714; + reg [31 : 0] v__h160987; + reg [31 : 0] v__h160523; + reg [31 : 0] v__h4001; + reg [31 : 0] v__h4174; + reg [31 : 0] v__h4438; + reg [31 : 0] v__h6475; + reg [31 : 0] v__h2277; + reg [31 : 0] v__h6775; + reg [31 : 0] v__h7268; + reg [31 : 0] v__h7431; + reg [31 : 0] v__h99152; + reg [31 : 0] v__h99950; + reg [31 : 0] v__h100099; + reg [31 : 0] v__h132480; + reg [31 : 0] v__h132647; + reg [31 : 0] v__h134750; + reg [31 : 0] v__h152094; + reg [31 : 0] v__h131861; + reg [31 : 0] v__h158788; + reg [31 : 0] v__h159296; + reg [31 : 0] v__h2271; + reg [31 : 0] v__h3995; + reg [31 : 0] v__h4168; + reg [31 : 0] v__h4432; + reg [31 : 0] v__h6469; + reg [31 : 0] v__h6769; + reg [31 : 0] v__h7262; + reg [31 : 0] v__h7425; + reg [31 : 0] v__h99146; + reg [31 : 0] v__h99944; + reg [31 : 0] v__h100093; + reg [31 : 0] v__h131855; + reg [31 : 0] v__h132474; + reg [31 : 0] v__h132641; + reg [31 : 0] v__h134744; + reg [31 : 0] v__h152088; + reg [31 : 0] v__h158782; + reg [31 : 0] v__h159290; + reg [31 : 0] v__h160517; + reg [31 : 0] v__h160981; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34, - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909, - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844, - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846, - data64__h136964, - ld_data__h121022, - rd_data_rdata__h119471, - w1__h45347, - w1__h45352, - w2__h45348, - w2__h45354, - x__h45343; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944; - reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5, - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1; - reg [7 : 0] strb8__h136965; - reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6, - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3; - reg [2 : 0] x__h59061; - reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22; + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34, + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908, + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875, + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843, + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845, + data64__h145920, + dword__h91077, + ld_data__h130082, + old_dword__h86767, + w1__h45156, + w1__h45161, + w2__h45157, + w2__h45163, + x__h45152; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943; + reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1, + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5; + reg [7 : 0] strb8__h145921; + reg [5 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441; + reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2, + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3, + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6, + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7; + reg [2 : 0] x__h58870; + reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4, + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8, + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20, - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319, - x__h59068, - x__h79786; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - new_cline__h123827; - wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394; - wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645; - wire [64 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - data__h29436, - failed_testnum__h151763, - line_addr__h104901, - mem_req_rd_addr_araddr__h123125, - mem_req_wr_addr_awaddr__h137049, - mmioPlatform_fromHostQ_data_0__h40137, - mmioPlatform_mtime__h34750, - mmioPlatform_reqData__h45939, - n__read_addr__h58929, - n__read_addr__h59014, - n__read_addr__h77548, - n__read_addr__h77627, - n__read_snd_addr__h92309, - newData__h29517, - newData__h32447, - op_result__h45955, - op_result__h46485, - op_result__h46490, - op_result__h46495, - op_result__h46500, - op_result__h46506, - op_result__h46513, - op_result__h46519, - req_addr__h94041, - result__h45398, - result__h45522, - result__h45550, - result__h45578, - result__h45606, - result__h45634, - result__h45662, - result__h45690, - result__h45718, - result__h45763, - result__h45791, - result__h45819, - result__h45847, - result__h45888, - result__h45916, - result__h46042, - result__h46069, - result__h46096, - result__h46123, - result__h46150, - result__h46177, - result__h46204, - result__h46231, - result__h46275, - result__h46302, - result__h46329, - result__h46356, - result__h46396, - result__h46423, - result__h46540, - result__h46606, - result__h46672, - result__h46738, - result__h46804, - result__h46870, - result__h46936, - result__h46998, - result__h47043, - result__h47109, - result__h47175, - result__h47233, - result__h47278, - w1___1__h45457, - w2___1__h45458, - x1_avValue_data__h37809, - x1_avValue_data__h42276, - x__h29628, - x__h32538, - x__h34898, - x__h38327, - x__h38338, - x__h40347, - x__h40358, - x__h47455; - wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671; - wire [31 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952, + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20, + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318, + x__h58877, + x__h79595; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410, + new_cline__h132783; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644; + wire [64 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192, + data__h29245, + failed_testnum__h160566, + line_addr__h100012, + line_addr__h99863, + mask__h86764, + mem_req_rd_addr_araddr__h132081, + mem_req_wr_addr_awaddr__h146005, + mmioPlatform_fromHostQ_data_0__h39946, + mmioPlatform_mtime__h34559, + mmioPlatform_reqData__h45748, + n__read_addr__h58738, + n__read_addr__h58823, + n__read_addr__h77357, + n__read_addr__h77436, + n__read_snd_addr__h121516, + newData__h29326, + newData__h32256, + new_dword__h86768, + op_result__h45764, + op_result__h46294, + op_result__h46299, + op_result__h46304, + op_result__h46309, + op_result__h46315, + op_result__h46322, + op_result__h46328, + result__h45207, + result__h45331, + result__h45359, + result__h45387, + result__h45415, + result__h45443, + result__h45471, + result__h45499, + result__h45527, + result__h45572, + result__h45600, + result__h45628, + result__h45656, + result__h45697, + result__h45725, + result__h45851, + result__h45878, + result__h45905, + result__h45932, + result__h45959, + result__h45986, + result__h46013, + result__h46040, + result__h46084, + result__h46111, + result__h46138, + result__h46165, + result__h46205, + result__h46232, + result__h46349, + result__h46415, + result__h46481, + result__h46547, + result__h46613, + result__h46679, + result__h46745, + result__h46807, + result__h46852, + result__h46918, + result__h46984, + result__h47042, + result__h47087, + w1___1__h45266, + w2___1__h45267, + x1_avValue_data__h37618, + x1_avValue_data__h42085, + x__h29437, + x__h32347, + x__h34707, + x__h38136, + x__h38147, + x__h40156, + x__h40167, + x__h47264, + x__h87930, + y__h87931, + y__h87932; + wire [47 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670; + wire [31 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665, + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h29229, - v__h29266, - w15347_BITS_31_TO_0__q15, - w25348_BITS_31_TO_0__q16, - x_data__h28019; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121; - wire [5 : 0] x__h123160, x__h137074; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120; - wire [3 : 0] b__h122832, b__h2359; - wire [2 : 0] n__read_id__h58933, n__read_id__h59018; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073, - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077, - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; - wire IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515, - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054, - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423, - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267, - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470, - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165, - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219, - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969, - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138, - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145, - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976, - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056, - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325, - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934, - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283, - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304, - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609, - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205, - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226, - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338, - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340, - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053, - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623, - mmioPlatform_cycle_12_ULT_99___d313, - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936, - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27644, - mmioPlatform_reqBE_BIT_4___h27604, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58934, - n__read_child__h59019, - n__read_child__h77551, - n__read_child__h77630, - n__read_snd_id__h92310, - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093, - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097, - x__h58747, - x__h72299, - x__h77370; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // action method hart0_server_reset_response_get - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; + v__h29038, + v__h29075, + w15156_BITS_31_TO_0__q15, + w25157_BITS_31_TO_0__q16, + x_data__h27828; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120; + wire [5 : 0] x__h132116, x__h146030; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119; + wire [3 : 0] b__h131788, b__h2171; + wire [2 : 0] n__read_id__h58742, n__read_id__h58827; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072, + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197, + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076, + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086; + wire IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514, + IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053, + IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422, + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266, + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617, + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164, + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460, + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218, + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968, + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137, + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144, + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975, + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055, + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324, + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933, + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282, + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303, + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608, + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204, + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225, + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337, + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339, + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052, + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477, + mmioPlatform_cycle_11_ULT_99___d312, + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935, + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295, + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576, + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321, + mmioPlatform_reqBE_BIT_0___h27453, + mmioPlatform_reqBE_BIT_4___h27413, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596, + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217, + n__read_child__h58743, + n__read_child__h58828, + n__read_child__h77360, + n__read_child__h77439, + n__read_snd_id__h121517, + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092, + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096, + x__h58556, + x__h72108, + x__h77179; // action method start - assign RDY_start = CAN_FIRE_start ; + assign RDY_start = mmioPlatform_state == 2'd0 ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -2482,9 +2440,6 @@ module mkProc(CLK, // value method master0_m_wvalid assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master0_m_wid - assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master0_m_wdata assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2591,9 +2546,6 @@ module mkProc(CLK, // value method master1_m_wvalid assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master1_m_wid - assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master1_m_wdata assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2668,10 +2620,6 @@ module mkProc(CLK, assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // action method non_maskable_interrupt_req assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ; assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ; @@ -2826,17 +2774,17 @@ module mkProc(CLK, assign v_to_TV_0_get = { core_0$v_to_TV_0_get[319:154], core_0$v_to_TV_0_get[154] ? - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 : + CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 : 12'hAAA, core_0$v_to_TV_0_get[141], core_0$v_to_TV_0_get[141] ? { core_0$v_to_TV_0_get[140], core_0$v_to_TV_0_get[140] ? - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 : - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 } : + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 : + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 } : 5'h0A, core_0$v_to_TV_0_get[135:72], - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, + CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4, core_0$v_to_TV_0_get[69:0] } ; assign RDY_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; assign CAN_FIRE_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; @@ -2846,17 +2794,17 @@ module mkProc(CLK, assign v_to_TV_1_get = { core_0$v_to_TV_1_get[319:154], core_0$v_to_TV_1_get[154] ? - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 : + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 : 12'hAAA, core_0$v_to_TV_1_get[141], core_0$v_to_TV_1_get[141] ? { core_0$v_to_TV_1_get[140], core_0$v_to_TV_1_get[140] ? - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 : - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 } : + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 : + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 } : 5'h0A, core_0$v_to_TV_1_get[135:72], - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8, core_0$v_to_TV_1_get[69:0] } ; assign RDY_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; assign CAN_FIRE_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; @@ -2880,7 +2828,6 @@ module mkProc(CLK, .mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x), .mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t), .recvDoStats_x(core_0$recvDoStats_x), - .setDEIP_v(core_0$setDEIP_v), .setMEIP_v(core_0$setMEIP_v), .setSEIP_v(core_0$setSEIP_v), .tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x), @@ -2915,7 +2862,6 @@ module mkProc(CLK, .EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get), .EN_setMEIP(core_0$EN_setMEIP), .EN_setSEIP(core_0$EN_setSEIP), - .EN_setDEIP(core_0$EN_setDEIP), .EN_hart0_run_halt_server_request_put(core_0$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(core_0$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(core_0$EN_hart0_gpr_mem_server_request_put), @@ -3006,7 +2952,6 @@ module mkProc(CLK, .RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get), .RDY_setMEIP(), .RDY_setSEIP(), - .RDY_setDEIP(), .RDY_hart0_run_halt_server_request_put(core_0$RDY_hart0_run_halt_server_request_put), .hart0_run_halt_server_response_get(core_0$hart0_run_halt_server_response_get), .RDY_hart0_run_halt_server_response_get(core_0$RDY_hart0_run_halt_server_response_get), @@ -3048,24 +2993,6 @@ module mkProc(CLK, .EN(enqDst_1_0_dummy2_1$EN), .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - // submodule llc mkLLCache llc(.CLK(CLK), .RST_N(RST_N), @@ -3189,7 +3116,7 @@ module mkProc(CLK, .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N)); // submodule llc_mem_server_axi4_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN), @@ -3234,9 +3161,9 @@ module mkProc(CLK, .ENQ(llc_mem_server_f_dword_in_line$ENQ), .DEQ(llc_mem_server_f_dword_in_line$DEQ), .CLR(llc_mem_server_f_dword_in_line$CLR), - .D_OUT(llc_mem_server_f_dword_in_line$D_OUT), - .FULL_N(llc_mem_server_f_dword_in_line$FULL_N), - .EMPTY_N(llc_mem_server_f_dword_in_line$EMPTY_N)); + .D_OUT(), + .FULL_N(), + .EMPTY_N()); // submodule llc_mem_server_propDstData_0_dummy2_0 RevertReg #(.width(32'd1), @@ -3511,16 +3438,16 @@ module mkProc(CLK, // rule RL_srcPropose assign CAN_FIRE_RL_srcPropose = - core_0$RDY_dCacheToParent_rqToP_first && core_0$RDY_dCacheToParent_rqToP_deq && + core_0$RDY_dCacheToParent_rqToP_first && (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT || !propDstIdx_0_rl) ; assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ; // rule RL_srcPropose_1 assign CAN_FIRE_RL_srcPropose_1 = - core_0$RDY_iCacheToParent_rqToP_first && core_0$RDY_iCacheToParent_rqToP_deq && + core_0$RDY_iCacheToParent_rqToP_first && (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT || !propDstIdx_1_rl) ; assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ; @@ -3532,13 +3459,13 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 ; + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 assign CAN_FIRE_RL_srcPropose_2 = - core_0$RDY_dCacheToParent_rsToP_first && core_0$RDY_dCacheToParent_rsToP_deq && + core_0$RDY_dCacheToParent_rsToP_first && (!propDstIdx_1_0_dummy2_0$Q_OUT || !propDstIdx_1_0_dummy2_1$Q_OUT || !propDstIdx_1_0_rl) ; @@ -3546,8 +3473,8 @@ module mkProc(CLK, // rule RL_srcPropose_3 assign CAN_FIRE_RL_srcPropose_3 = - core_0$RDY_iCacheToParent_rsToP_first && core_0$RDY_iCacheToParent_rsToP_deq && + core_0$RDY_iCacheToParent_rsToP_first && (!propDstIdx_1_1_dummy2_0$Q_OUT || !propDstIdx_1_1_dummy2_1$Q_OUT || !propDstIdx_1_1_rl) ; @@ -3560,7 +3487,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 ; + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3671,13 +3598,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2359 == 4'd0 ; + b__h2171 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2359 != 4'd0 && + b__h2171 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3701,23 +3628,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_12_ULT_99___d313 ; + mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_12_ULT_99___d313 ; + !mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 && + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3734,7 +3661,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 && + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3743,7 +3670,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 && + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3759,8 +3686,8 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMTimeCmpDone assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone = - core_0$RDY_mmioToPlatform_cRs_deq && core_0$RDY_mmioToPlatform_pRs_enq && + core_0$RDY_mmioToPlatform_cRs_deq && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone = @@ -3789,7 +3716,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40347 == 64'd0 || + x__h40156 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3807,7 +3734,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3815,14 +3742,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3832,22 +3759,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930 && + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3923,10 +3850,105 @@ module mkProc(CLK, assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ; assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ; + // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_st_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + !llc$dma_respSt_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd1 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + !llc$dma_respLd_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd2 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + // rule RL_llc_mem_server_srcPropose assign CAN_FIRE_RL_llc_mem_server_srcPropose = - core_0$RDY_tlbToMem_memReq_first && core_0$RDY_tlbToMem_memReq_deq && + core_0$RDY_tlbToMem_memReq_first && (!llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT || !llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT || !llc_mem_server_propDstIdx_0_rl) ; @@ -3941,64 +3963,20 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_wr - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b011 || - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] || - llc$RDY_dma_memReq_enq) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_rd - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b011 || - llc$RDY_dma_memReq_enq && - llc_mem_server_f_dword_in_line$FULL_N) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - // rule RL_llc_mem_server_sendTlbReqToLLC assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC = llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ; assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC = CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendLdRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - llc_mem_server_f_dword_in_line$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && - !llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = @@ -4008,14 +3986,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; - // rule RL_llc_mem_server_sendStRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && - llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && - !llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; - // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && @@ -4066,27 +4036,23 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h122832 == 4'd0 ; + b__h131788 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h122832 != 4'd0 && + b__h131788 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 ; + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4094,41 +4060,36 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || + (!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 ; - assign MUX_llc$dma_memReq_enq_1__SEL_2 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign MUX_mmioPlatform_amoResp$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,12 +4101,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || @@ -4175,20 +4136,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28019 } ; + x_data__h27828 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4202,35 +4163,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29436 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29245 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4239,91 +4200,44 @@ module mkProc(CLK, { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } : mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = - { req_addr__h94041, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, + { llc_mem_server_rg_cacheline_cache_addr, + 64'hFFFFFFFFFFFFFFFF, + llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h104901, + { line_addr__h99863, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = + { line_addr__h100012, + 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], 577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd1) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[127:64], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd0) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[63:0] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = + llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4248,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366))) ; + IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4261,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4276,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 or + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 or + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,75 +4309,75 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ? + (mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45343 } ; + x__h45152 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47455, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47264, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40347 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40156 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40347 != 64'd0 ; + x__h40156 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38327 == 64'd0 ; + x__h38136 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - x__h58747 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 && + x__h58556 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 } ; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - x__h77370 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 && + x__h77179 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 } ; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h92309, n__read_snd_id__h92310 } ; + { 1'd1, n__read_snd_addr__h121516, n__read_snd_id__h121517 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4512,15 +4426,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2359 - 4'd1 ; + b__h2171 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2359 ; - assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h2171 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4569,30 +4479,26 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h122832 - 4'd1 ; + b__h131788 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h122832 ; - assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h131788 ; // register cfg_verbosity assign cfg_verbosity$D_IN = EN_hart0_put_other_req_put ? hart0_put_other_req_put : set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ; + assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000, + IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + (NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4600,8 +4506,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 } ; + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230, + IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4610,7 +4516,7 @@ module mkProc(CLK, // register llc_axi4_adapter_ctr_wr_rsps_pending_crg assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register llc_axi4_adapter_master_xactor_crg_rd_addr_full @@ -4640,7 +4546,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h123125, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h132081, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4651,13 +4557,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h137049, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h146005, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h136964, strb8__h136965, 1'd1 } ; + { data64__h145920, strb8__h145921, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4669,7 +4575,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h123827 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h132783 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4700,10 +4606,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487, + IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4717,10 +4623,66 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; + // register llc_mem_server_rg_cacheline_cache_addr + assign llc_mem_server_rg_cacheline_cache_addr$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? + line_addr__h99863 : + line_addr__h100012 ; + assign llc_mem_server_rg_cacheline_cache_addr$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; + + // register llc_mem_server_rg_cacheline_cache_data + assign llc_mem_server_rg_cacheline_cache_data$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 : + llc$dma_respLd_first[516:5] ; + assign llc_mem_server_rg_cacheline_cache_data$EN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 10'd1023 : + MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ; + assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // register llc_mem_server_rg_cacheline_cache_state + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3; + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4; + default: llc_mem_server_rg_cacheline_cache_state$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign llc_mem_server_rg_cacheline_cache_state$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + // register mmioPlatform_amoResp assign mmioPlatform_amoResp$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ? @@ -4743,7 +4705,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4756,11 +4718,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 && + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4770,11 +4732,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4788,7 +4750,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_data_0$D_IN = mmioPlatform_fromHostQ_enqReq_rl[63:0] ; assign mmioPlatform_fromHostQ_data_0$EN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] ; @@ -4800,7 +4762,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_empty$D_IN = mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_fromHostQ_clearReq_rl || - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 ; + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 ; assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ; // register mmioPlatform_fromHostQ_enqReq_rl @@ -4809,8 +4771,8 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_full assign mmioPlatform_fromHostQ_full$D_IN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 ; + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 ; assign mmioPlatform_fromHostQ_full$EN = 1'd1 ; // register mmioPlatform_instSel @@ -4821,16 +4783,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 ; + mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32447 : + newData__h32256 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4839,7 +4801,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29517 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29326 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4849,9 +4811,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4953,9 +4915,9 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] : mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4965,7 +4927,7 @@ module mkProc(CLK, assign mmioPlatform_toHostQ_empty$D_IN = mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_toHostQ_clearReq_rl || - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 ; + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 ; assign mmioPlatform_toHostQ_empty$EN = 1'd1 ; // register mmioPlatform_toHostQ_enqReq_rl @@ -4974,8 +4936,8 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 ; + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 ; assign mmioPlatform_toHostQ_full$EN = 1'd1 ; // register mmioPlatform_waitLowerMSIPCRs @@ -4985,7 +4947,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4993,15 +4955,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5009,7 +4971,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full @@ -5060,8 +5022,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_master_xactor_rg_wr_data assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], + { mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64], 1'd1 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN = @@ -5083,28 +5044,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160, + { IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154, + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 } ; + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198, + { IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192, + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 } ; + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5117,36 +5078,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 ; + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5252,11 +5213,10 @@ module mkProc(CLK, end assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ; assign core_0$recvDoStats_x = core_0$sendDoStats ; - assign core_0$setDEIP_v = debug_external_interrupt_req_set_not_clear ; assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h121022, llc$dma_respLd_first[3] } ; + { ld_data__h130082, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5277,13 +5237,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 || + (!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5294,15 +5254,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 || + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5337,7 +5297,6 @@ module mkProc(CLK, core_0$RDY_renameDebug_renameErr_get ; assign core_0$EN_setMEIP = 1'd1 ; assign core_0$EN_setSEIP = 1'd1 ; - assign core_0$EN_setDEIP = 1'd1 ; assign core_0$EN_hart0_run_halt_server_request_put = EN_hart0_run_halt_server_request_put ; assign core_0$EN_hart0_run_halt_server_response_get = @@ -5360,7 +5319,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ; + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5369,37 +5328,31 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ; + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule llc always@(MUX_llc$dma_memReq_enq_1__SEL_1 or MUX_llc$dma_memReq_enq_1__VAL_1 or - MUX_llc$dma_memReq_enq_1__SEL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or MUX_llc$dma_memReq_enq_1__VAL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or + MUX_llc$dma_memReq_enq_1__VAL_3 or WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or - MUX_llc$dma_memReq_enq_1__VAL_3) + MUX_llc$dma_memReq_enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case MUX_llc$dma_memReq_enq_1__SEL_1: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1; - MUX_llc$dma_memReq_enq_1__SEL_2: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2; - WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3; + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4; default: llc$dma_memReq_enq_x = 645'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5407,17 +5360,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 } ; + { IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h123827, + { new_cline__h132783, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5426,26 +5379,18 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign llc$EN_dma_memReq_enq = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 || - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; assign llc$EN_dma_respLd_deq = WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; assign llc$EN_dma_respSt_deq = WILL_FIRE_RL_llc_mem_server_sendStRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign llc$EN_to_mem_toM_deq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_rg_rd_req_beat == 3'd7 || @@ -5496,14 +5441,14 @@ module mkProc(CLK, debug_module_mem_server_arvalid && llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, rd_data_rdata__h119471, 3'd1 } ; + { 4'd0, dword__h91077, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = debug_module_mem_server_rready && llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ; @@ -5525,26 +5470,25 @@ module mkProc(CLK, debug_module_mem_server_awvalid && llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_data assign llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN = - { debug_module_mem_server_wid, - debug_module_mem_server_wdata, + { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast } ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ = debug_module_mem_server_wvalid && llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp assign llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN = 6'd0 ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ = debug_module_mem_server_bready && llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ; @@ -5553,7 +5497,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5561,12 +5505,9 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_doEnq ; // submodule llc_mem_server_f_dword_in_line - assign llc_mem_server_f_dword_in_line$D_IN = - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32] ; - assign llc_mem_server_f_dword_in_line$ENQ = - MUX_llc$dma_memReq_enq_1__SEL_2 ; - assign llc_mem_server_f_dword_in_line$DEQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ; + assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ; assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ; // submodule llc_mem_server_propDstData_0_dummy2_0 @@ -5586,11 +5527,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5784,86 +5725,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), - .amoExec_current_data(x__h34898), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h29628)); + .amoExec_current_data(x__h34707), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h29437)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34750), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h32538)); + .amoExec_current_data(mmioPlatform_mtime__h34559), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h32347)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, + 2'd0 }), + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h39946), + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h38147)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27413 && + mmioPlatform_reqBE_BIT_0___h27453, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h40358)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, - 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40137), - .amoExec_in_data(mmioPlatform_reqData__h45939), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h38338)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = + .amoExec_in_data(mmioPlatform_reqData__h45748), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27413 && + !mmioPlatform_reqBE_BIT_0___h27453), + .amoExec(x__h40167)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37809 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + x1_avValue_data__h37618 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 = + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 = + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29517 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054 = - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ? + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 = + newData__h29326 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053 = + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 : + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323 = - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ? + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322 = + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 : + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_ETC___d1125 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_A_ETC___d1422 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 ; - assign IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366 = + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 ; + assign IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5871,89 +5812,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__95_THEN_enqDst_0_lat_0_ETC___d1000 = - NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 ? + assign IF_enqDst_0_lat_0_whas__94_THEN_enqDst_0_lat_0_ETC___d999 = + NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1231 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1230 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 = - NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 ? + assign IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 = + NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 = + assign IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1251, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1250, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - x__h72299 } ; - assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 = + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1260, + x__h72108 } ; + assign IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1269 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1241, + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1240, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, - IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269 } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__482_THE_ETC___d1487 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 ? + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1245, + IF_enqDst_1_0_lat_1_whas__222_THEN_enqDst_1_0__ETC___d1268 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538 = + { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd7) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[511:448], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd6) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[447:384], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd5) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[383:320], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd4) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[319:256] } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1543 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1538, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd3) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[255:192], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd2) ? + new_dword__h86768 : + llc_mem_server_rg_cacheline_cache_data[191:128] } ; + assign IF_llc_mem_server_enqDst_0_lat_0_whas__629_THE_ETC___d1634 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 = - ((mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + assign IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 = + ((mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5966,23 +5934,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5995,23 +5963,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6024,144 +5992,144 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d666, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d665, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d670, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 = + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 = + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d683 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40347 == 64'd0 : - x__h38327 == 64'd0, + x__h40156 == 64'd0 : + x__h38136 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42276 } ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = + x1_avValue_data__h42085 } ; + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = + assign IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 = mmioPlatform_waitLowerMSIPCRs ? - core_0$RDY_mmioToPlatform_cRs_first && - core_0$RDY_mmioToPlatform_cRs_deq : + core_0$RDY_mmioToPlatform_cRs_deq && + core_0$RDY_mmioToPlatform_cRs_first : (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_first) && + core_0$RDY_mmioToPlatform_cRs_deq) && (!mmioPlatform_waitUpperMSIPCRs || - core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d931 = + core_0$RDY_mmioToPlatform_cRs_first) ; + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d930 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__16__ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943) : mmioPlatform_fetchedInsts_0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 = + assign IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 = + assign IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 = + assign IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 = + assign IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077 = + assign IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087 = + assign IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 = + assign IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 = + assign IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145 = + assign IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976 = + assign IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 = + assign NOT_enqDst_0_dummy2_0_read__039_040_OR_NOT_enq_ETC___d1055 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 || - IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054) ; - assign NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 || + IF_NOT_propDstIdx_0_dummy2_1_read__018_019_OR__ETC___d1053) ; + assign NOT_enqDst_1_0_dummy2_0_read__308_309_OR_NOT_e_ETC___d1324 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__278_279_O_ETC___d1323) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__277_278_O_ETC___d1322) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__513_ETC___d1520 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__660_ETC___d1667 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__467_ETC___d1470 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d707 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__614_ETC___d1617 ; + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d706 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6172,7 +6140,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6183,7 +6151,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d720 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d719 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6195,7 +6163,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d730 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d729 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6207,7 +6175,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d921 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d920 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6217,7 +6185,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d934 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d933 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6227,44 +6195,44 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 = + assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 = !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_fromHostQ_clearReq_rl ; - assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 = + assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 = (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT || !mmioPlatform_fromHostQ_enqReq_rl[64]) && (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT && (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 = + assign NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || !core_0$mmioToPlatform_cRq_notEmpty || - core_0$RDY_mmioToPlatform_cRq_first && - core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = + core_0$RDY_mmioToPlatform_cRq_deq && + core_0$RDY_mmioToPlatform_cRq_first ; + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 = + assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_toHostQ_clearReq_rl ; - assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 = + assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 = (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT || (mmioPlatform_toHostQ_enqReq_lat_0$whas ? !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6273,101 +6241,109 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 = + assign NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340 = + assign NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 = + assign NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 = + assign NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 = - { CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 = - { CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - x__h79786 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360 = - { CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 = - { CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20, - x__h59061, - x__h59068 } ; - assign b__h122832 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__056_TH_ETC___d1120 = + { CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__325__ETC___d1417 = + { CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410, + x__h79595 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359 = + { CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1359, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1376, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1410 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__149_THE_ETC___d1393, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__056_AND_I_ETC___d1119 = + { CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20, + x__h58870, + x__h58877 } ; + assign b__h131788 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2359 = + assign b__h2171 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29436 = + assign data__h29245 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29229, 32'd0 } ; - assign failed_testnum__h151763 = + { v__h29038, 32'd0 } ; + assign failed_testnum__h160566 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h104901 = + assign line_addr__h100012 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1584 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign mem_req_rd_addr_araddr__h123125 = - { llc$to_mem_toM_first[68:11], x__h123160 } ; - assign mem_req_wr_addr_awaddr__h137049 = - { llc$to_mem_toM_first[639:582], x__h137074 } ; - assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 = + assign line_addr__h99863 = + { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], + 6'b0 } ; + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1555 = + line_addr__h100012 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1477 = + line_addr__h99863 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h86764 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'hFF : + 8'h0 } ; + assign mem_req_rd_addr_araddr__h132081 = + { llc$to_mem_toM_first[68:11], x__h132116 } ; + assign mem_req_wr_addr_awaddr__h146005 = + { llc$to_mem_toM_first[639:582], x__h146030 } ; + assign mmioPlatform_cycle_11_ULT_99___d312 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40137 = + assign mmioPlatform_fromHostQ_data_0__h39946 = mmioPlatform_fromHostQ_data_0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = + assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] || (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT || @@ -6376,275 +6352,273 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34750 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32447 ; - assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = + assign mmioPlatform_mtime__h34559 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 = + mmioPlatform_mtimecmp_0 <= newData__h32256 ; + assign mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27644 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27604 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h45939 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = + assign mmioPlatform_reqBE_BIT_0___h27453 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27413 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h45748 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (!IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (!mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 = + assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 || + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 || (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h58929 = + assign n__read_addr__h58738 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59014 = + assign n__read_addr__h58823 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77548 = + assign n__read_addr__h77357 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 : + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1154 : 64'd0 ; - assign n__read_addr__h77627 = + assign n__read_addr__h77436 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 : + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1192 : 64'd0 ; - assign n__read_child__h58934 = + assign n__read_child__h58743 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59019 = + assign n__read_child__h58828 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77551 = + assign n__read_child__h77360 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 ; - assign n__read_child__h77630 = + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1180 ; + assign n__read_child__h77439 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 ; - assign n__read_id__h58933 = + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1218 ; + assign n__read_id__h58742 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59018 = + assign n__read_id__h58827 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h92309 = + assign n__read_snd_addr__h121516 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h92310 = + assign n__read_snd_id__h121517 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h29517 = + assign newData__h29326 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29628 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32447 = + x__h29437 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 ; + assign newData__h32256 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32538 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h123827 = + x__h32347 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 ; + assign new_cline__h132783 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h45955 = - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 + - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ; - assign op_result__h46485 = w1__h45352 ^ w2__h45354 ; - assign op_result__h46490 = w1__h45352 & w2__h45354 ; - assign op_result__h46495 = w1__h45352 | w2__h45354 ; - assign op_result__h46500 = - (w1__h45352 < w2__h45354) ? w1__h45352 : w2__h45354 ; - assign op_result__h46506 = - (w1__h45352 <= w2__h45354) ? w2__h45354 : w1__h45352 ; - assign op_result__h46513 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + assign new_dword__h86768 = x__h87930 | y__h87931 ; + assign op_result__h45764 = + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 + + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ; + assign op_result__h46294 = w1__h45161 ^ w2__h45163 ; + assign op_result__h46299 = w1__h45161 & w2__h45163 ; + assign op_result__h46304 = w1__h45161 | w2__h45163 ; + assign op_result__h46309 = + (w1__h45161 < w2__h45163) ? w1__h45161 : w2__h45163 ; + assign op_result__h46315 = + (w1__h45161 <= w2__h45163) ? w2__h45163 : w1__h45161 ; + assign op_result__h46322 = + ((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^ 64'h8000000000000000)) ? - w1__h45352 : - w2__h45354 ; - assign op_result__h46519 = - ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ + w1__h45161 : + w2__h45163 ; + assign op_result__h46328 = + ((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ + (IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^ 64'h8000000000000000)) ? - w2__h45354 : - w1__h45352 ; - assign propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 = + w2__h45163 : + w1__h45161 ; + assign propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097 = + assign propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign req_addr__h94041 = - { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], - 6'b0 } ; - assign result__h45398 = + assign result__h45207 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0] } ; - assign result__h45522 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45550 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45578 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45606 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45634 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45662 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45690 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45718 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45763 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h45791 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h45819 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h45847 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h45888 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h45916 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46042 = + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0] } ; + assign result__h45331 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45359 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45387 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45415 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45443 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45471 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45499 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45527 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45572 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45600 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45628 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45656 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45697 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h45725 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h45851 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46069 = + assign result__h45878 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46096 = + assign result__h45905 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46123 = + assign result__h45932 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46150 = + assign result__h45959 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46177 = + assign result__h45986 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46204 = + assign result__h46013 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46231 = + assign result__h46040 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46275 = + assign result__h46084 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46302 = + assign result__h46111 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46329 = + assign result__h46138 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46356 = + assign result__h46165 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46396 = + assign result__h46205 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46423 = + assign result__h46232 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46540 = + assign result__h46349 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46606 = + assign result__h46415 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46672 = + assign result__h46481 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46738 = + assign result__h46547 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h46804 = + assign result__h46613 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h46870 = + assign result__h46679 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h46936 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], + assign result__h46745 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h46998 = + assign result__h46807 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0] } ; - assign result__h47043 = + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0] } ; + assign result__h46852 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47109 = + assign result__h46918 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47175 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], + assign result__h46984 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47233 = + assign result__h47042 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0] } ; - assign result__h47278 = - { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0], + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0] } ; + assign result__h47087 = + { IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29229 = mmioPlatform_waitUpperMSIPCRs ? v__h29266 : 32'd0 ; - assign v__h29266 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15347_BITS_31_TO_0__q15 = w1__h45347[31:0] ; - assign w1___1__h45457 = { 32'd0, w1__h45347[31:0] } ; - assign w25348_BITS_31_TO_0__q16 = w2__h45348[31:0] ; - assign w2___1__h45458 = { 32'd0, w2__h45348[31:0] } ; - assign x1_avValue_data__h37809 = + assign v__h29038 = mmioPlatform_waitUpperMSIPCRs ? v__h29075 : 32'd0 ; + assign v__h29075 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15156_BITS_31_TO_0__q15 = w1__h45156[31:0] ; + assign w1___1__h45266 = { 32'd0, w1__h45156[31:0] } ; + assign w25157_BITS_31_TO_0__q16 = w2__h45157[31:0] ; + assign w2___1__h45267 = { 32'd0, w2__h45157[31:0] } ; + assign x1_avValue_data__h37618 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42276 = + assign x1_avValue_data__h42085 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h123160 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h137074 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34898 = mmioPlatform_mtimecmp_0 ; - assign x__h38327 = + assign x__h132116 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h146030 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34707 = mmioPlatform_mtimecmp_0 ; + assign x__h38136 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38338 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 ; - assign x__h40347 = + x__h38147 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d675 ; + assign x__h40156 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40358 : + x__h40167 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6653,107 +6627,48 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47455 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58747 = - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? + assign x__h47264 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58556 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ; - assign x__h72299 = + NOT_propDstIdx_0_dummy2_1_read__018_019_OR_IF__ETC___d1052 ; + assign x__h72108 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 ; - assign x__h77370 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? + IF_enqDst_1_0_lat_0_whas__225_THEN_enqDst_1_0__ETC___d1266 ; + assign x__h77179 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ; - assign x_data__h28019 = { 31'd0, mmioPlatform_reqData[0] } ; - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - core_0$v_to_TV_1_get[153:142]; - default: CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - 12'd2303; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[71:70]) - 2'd0, 2'd1: - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = - core_0$v_to_TV_1_get[71:70]; - default: CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = 2'd2; - endcase - end + NOT_propDstIdx_1_0_dummy2_1_read__277_278_OR_I_ETC___d1321 ; + assign x__h87930 = old_dword__h86767 & y__h87932 ; + assign x_data__h27828 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h87931 = + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & + mask__h86764 ; + assign y__h87932 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'd0 : + 8'd255 } ; always@(core_0$v_to_TV_0_get) begin case (core_0$v_to_TV_0_get[153:142]) @@ -6797,9 +6712,9 @@ module mkProc(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = + CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 = core_0$v_to_TV_0_get[153:142]; - default: CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = + default: CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q1 = 12'd2303; endcase end @@ -6807,9 +6722,9 @@ module mkProc(CLK, begin case (core_0$v_to_TV_0_get[139:136]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 = core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = 4'd15; + default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q2 = 4'd15; endcase end always@(core_0$v_to_TV_0_get) @@ -6828,469 +6743,579 @@ module mkProc(CLK, 4'd11, 4'd12, 4'd13: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = + CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 = core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = 4'd15; + default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q3 = 4'd15; endcase end always@(core_0$v_to_TV_0_get) begin case (core_0$v_to_TV_0_get[71:70]) 2'd0, 2'd1: - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = + CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4 = core_0$v_to_TV_0_get[71:70]; - default: CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = 2'd2; + default: CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q4 = 2'd2; endcase end - always@(llc_mem_server_f_dword_in_line$D_OUT or llc$dma_respLd_first) + always@(core_0$v_to_TV_1_get) begin - case (llc_mem_server_f_dword_in_line$D_OUT) - 3'd0: rd_data_rdata__h119471 = llc$dma_respLd_first[68:5]; - 3'd1: rd_data_rdata__h119471 = llc$dma_respLd_first[132:69]; - 3'd2: rd_data_rdata__h119471 = llc$dma_respLd_first[196:133]; - 3'd3: rd_data_rdata__h119471 = llc$dma_respLd_first[260:197]; - 3'd4: rd_data_rdata__h119471 = llc$dma_respLd_first[324:261]; - 3'd5: rd_data_rdata__h119471 = llc$dma_respLd_first[388:325]; - 3'd6: rd_data_rdata__h119471 = llc$dma_respLd_first[452:389]; - 3'd7: rd_data_rdata__h119471 = llc$dma_respLd_first[516:453]; + case (core_0$v_to_TV_1_get[153:142]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 = + core_0$v_to_TV_1_get[153:142]; + default: CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q5 = + 12'd2303; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[139:136]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 = + core_0$v_to_TV_1_get[139:136]; + default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q6 = 4'd15; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[139:136]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 = + core_0$v_to_TV_1_get[139:136]; + default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q7 = 4'd15; + endcase + end + always@(core_0$v_to_TV_1_get) + begin + case (core_0$v_to_TV_1_get[71:70]) + 2'd0, 2'd1: + CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8 = + core_0$v_to_TV_1_get[71:70]; + default: CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q8 = 2'd2; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) + 3'd0: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h91077 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h121022 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h121022 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h121022 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h121022 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h121022 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h121022 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h121022 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h121022 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h130082 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h130082 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h130082 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h130082 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h130082 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h130082 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h130082 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h130082 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h136964 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h136964 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h136964 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h136964 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h136964 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h136964 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h136964 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h136964 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h145920 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h145920 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h145920 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h145920 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h145920 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h145920 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h145920 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h145920 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h136965 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h136965 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h136965 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h136965 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h136965 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h136965 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h136965 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h136965 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h145921 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h145921 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h145921 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h145921 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h145921 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h145921 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h145921 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h145921 = llc$to_mem_toM_first[575:568]; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) + 3'd0: old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: + old_dword__h86767 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h45763 or - result__h45791 or result__h45819 or result__h45847) + result__h45331 or + result__h45359 or + result__h45387 or + result__h45415 or + result__h45443 or + result__h45471 or result__h45499 or result__h45527) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45763; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45331; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45359; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45791; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45387; + 3'h3: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45415; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45819; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45443; + 3'h5: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45471; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45847; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45499; + 3'h7: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 = + result__h45527; + endcase + end + always@(mmioPlatform_curReq or + result__h45572 or + result__h45600 or result__h45628 or result__h45656) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45572; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45600; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45628; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = + result__h45656; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h45522 or - result__h45550 or - result__h45578 or - result__h45606 or - result__h45634 or - result__h45662 or result__h45690 or result__h45718) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45522; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45550; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45578; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45606; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45634; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45662; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45690; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45718; - endcase - end - always@(mmioPlatform_curReq or result__h45888 or result__h45916) + always@(mmioPlatform_curReq or result__h45697 or result__h45725) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h45888; + result__h45697; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h45916; + result__h45725; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; 2'b10: - w2__h45348 = + w2__h45157 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h45348 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + w2__h45157 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w2___1__h45458 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or + w2___1__h45267 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: w2__h45354 = w2___1__h45458; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; + 2'b10: w2__h45163 = w2___1__h45267; 2'b11: - w2__h45354 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + w2__h45163 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_curReq or - result__h46275 or - result__h46302 or result__h46329 or result__h46356) + result__h45851 or + result__h45878 or + result__h45905 or + result__h45932 or + result__h45959 or + result__h45986 or result__h46013 or result__h46040) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46275; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45851; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45878; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46302; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45905; + 3'h3: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45932; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46329; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45959; + 3'h5: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h45986; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46356; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h46013; + 3'h7: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 = + result__h46040; + endcase + end + always@(mmioPlatform_curReq or + result__h46084 or + result__h46111 or result__h46138 or result__h46165) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46084; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46111; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46138; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = + result__h46165; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h46042 or - result__h46069 or - result__h46096 or - result__h46123 or - result__h46150 or - result__h46177 or result__h46204 or result__h46231) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46042; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46069; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46096; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46123; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46150; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46177; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46204; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46231; - endcase - end - always@(mmioPlatform_curReq or result__h46396 or result__h46423) + always@(mmioPlatform_curReq or result__h46205 or result__h46232) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46396; + result__h46205; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46423; + result__h46232; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; 2'b10: - w1__h45347 = + w1__h45156 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h45347 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + w1__h45156 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w1___1__h45457 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or + w1___1__h45266 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: w1__h45352 = w1___1__h45457; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; + 2'b10: w1__h45161 = w1___1__h45266; 2'b11: - w1__h45352 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + w1__h45161 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w15347_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829 or + w15156_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d817; 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d829; 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - { {32{w15347_BITS_31_TO_0__q15[31]}}, - w15347_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + { {32{w15156_BITS_31_TO_0__q15[31]}}, + w15156_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d836; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w25348_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778 or + w25157_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d765; 2'b01: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d778; 2'b10: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - { {32{w25348_BITS_31_TO_0__q16[31]}}, - w25348_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + { {32{w25157_BITS_31_TO_0__q16[31]}}, + w25157_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46519 or - w2__h45354 or - op_result__h45955 or - op_result__h46485 or - op_result__h46490 or - op_result__h46495 or - op_result__h46513 or op_result__h46500 or op_result__h46506) + op_result__h46328 or + w2__h45163 or + op_result__h45764 or + op_result__h46294 or + op_result__h46299 or + op_result__h46304 or + op_result__h46322 or op_result__h46309 or op_result__h46315) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - w2__h45354; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + w2__h45163; 4'd1: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h45955; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h45764; 4'd2: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46485; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46294; 4'd3: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46490; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46299; 4'd4: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46495; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46304; 4'd5: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46513; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46322; 4'd7: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46500; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46309; 4'd8: - IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46506; - default: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46519; + IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46315; + default: IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 = + op_result__h46328; endcase end always@(mmioPlatform_curReq or - result__h46998 or - result__h47043 or result__h47109 or result__h47175) + result__h46807 or + result__h46852 or result__h46918 or result__h46984) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h46998; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46807; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47043; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46852; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47109; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46918; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47175; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = + result__h46984; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45398 or - result__h46540 or - result__h46606 or - result__h46672 or - result__h46738 or - result__h46804 or result__h46870 or result__h46936) + result__h45207 or + result__h46349 or + result__h46415 or + result__h46481 or + result__h46547 or + result__h46613 or result__h46679 or result__h46745) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h45398; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h45207; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46540; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46349; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46606; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46415; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46672; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46481; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46738; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46547; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46804; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46613; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46870; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46679; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46936; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 = + result__h46745; endcase end - always@(mmioPlatform_curReq or result__h47233 or result__h47278) + always@(mmioPlatform_curReq or result__h47042 or result__h47087) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47233; + result__h47042; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47278; + result__h47087; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785) begin case (mmioPlatform_reqSz) 2'b0: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d899; 2'b01: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d908; 2'b10: - x__h45343 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h45152 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h45343 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; + x__h45152 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_37_EQ_0x_ETC___d785; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7298,15 +7323,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d943 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 or + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7314,11 +7339,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520; + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 or + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7326,315 +7351,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586; + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969 or + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976) + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__66_THEN_propDstIdx_ETC___d969; + IF_propDstIdx_0_lat_0_whas__65_THEN_propDstIdx_ETC___d968; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 = + SEL_ARR_propDstIdx_0_dummy2_1_read__018_AND_IF_ETC___d1049 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__73_THEN_propDstIdx_ETC___d976; + IF_propDstIdx_1_lat_0_whas__72_THEN_propDstIdx_ETC___d975; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138 or + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145) + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__135_THEN_propDst_ETC___d1138; + IF_propDstIdx_1_0_lat_0_whas__134_THEN_propDst_ETC___d1137; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__277_AND__ETC___d1318 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145; + IF_propDstIdx_1_1_lat_0_whas__141_THEN_propDst_ETC___d1144; endcase end - always@(x__h58747 or n__read_id__h58933 or n__read_id__h59018) + always@(x__h58556 or n__read_id__h58742 or n__read_id__h58827) begin - case (x__h58747) - 1'd0: x__h59061 = n__read_id__h58933; - 1'd1: x__h59061 = n__read_id__h59018; + case (x__h58556) + 1'd0: x__h58870 = n__read_id__h58742; + 1'd1: x__h58870 = n__read_id__h58827; endcase end - always@(x__h58747 or n__read_child__h58934 or n__read_child__h59019) + always@(x__h58556 or n__read_child__h58743 or n__read_child__h58828) begin - case (x__h58747) - 1'd0: x__h59068 = n__read_child__h58934; - 1'd1: x__h59068 = n__read_child__h59019; + case (x__h58556) + 1'd0: x__h58877 = n__read_child__h58743; + 1'd1: x__h58877 = n__read_child__h58828; endcase end - always@(x__h58747 or - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 or - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097) + always@(x__h58556 or + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092 or + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20 = - propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093; + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20 = + propDstData_0_dummy2_1_read__056_AND_IF_propDs_ETC___d1092; 1'd1: - CASE_x8747_0_propDstData_0_dummy2_1_read__057__ETC__q20 = - propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097; + CASE_x8556_0_propDstData_0_dummy2_1_read__056__ETC__q20 = + propDstData_1_dummy2_1_read__061_AND_IF_propDs_ETC___d1096; endcase end - always@(x__h58747 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077) + always@(x__h58556 or + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072 or + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1072; 1'd1: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1076; endcase end - always@(x__h58747 or - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 or - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087) + always@(x__h58556 or + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082 or + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__056_THEN_IF_pr_ETC___d1082; 1'd1: - CASE_x8747_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; + CASE_x8556_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__061_THEN_IF_pr_ETC___d1086; endcase end - always@(x__h58747 or n__read_addr__h58929 or n__read_addr__h59014) + always@(x__h58556 or n__read_addr__h58738 or n__read_addr__h58823) begin - case (x__h58747) + case (x__h58556) 1'd0: - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23 = - n__read_addr__h58929; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23 = + n__read_addr__h58738; 1'd1: - CASE_x8747_0_n__read_addr8929_1_n__read_addr90_ETC__q23 = - n__read_addr__h59014; + CASE_x8556_0_n__read_addr8738_1_n__read_addr88_ETC__q23 = + n__read_addr__h58823; endcase end - always@(x__h77370 or n__read_child__h77551 or n__read_child__h77630) + always@(x__h77179 or n__read_child__h77360 or n__read_child__h77439) begin - case (x__h77370) - 1'd0: x__h79786 = n__read_child__h77551; - 1'd1: x__h79786 = n__read_child__h77630; + case (x__h77179) + 1'd0: x__h79595 = n__read_child__h77360; + 1'd1: x__h79595 = n__read_child__h77439; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77370 or + always@(x__h77179 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7370_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7179_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77370 or + always@(x__h77179 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 or + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198) + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 : + IF_propDstData_1_0_lat_0_whas__149_THEN_propDs_ETC___d1159 : 2'd0; 1'd1: - CASE_x7370_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7179_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 : + IF_propDstData_1_1_lat_0_whas__187_THEN_propDs_ETC___d1197 : 2'd0; endcase end - always@(x__h77370 or - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 or - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340) + always@(x__h77179 or + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337 or + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338; + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__325_336_OR__ETC___d1337; 1'd1: - CASE_x7370_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340; + CASE_x7179_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__327_338_OR__ETC___d1339; endcase end - always@(x__h77370 or n__read_addr__h77548 or n__read_addr__h77627) + always@(x__h77179 or n__read_addr__h77357 or n__read_addr__h77436) begin - case (x__h77370) + case (x__h77179) 1'd0: - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34 = - n__read_addr__h77548; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34 = + n__read_addr__h77357; 1'd1: - CASE_x7370_0_n__read_addr7548_1_n__read_addr76_ETC__q34 = - n__read_addr__h77627; + CASE_x7179_0_n__read_addr7357_1_n__read_addr74_ETC__q34 = + n__read_addr__h77436; endcase end @@ -7670,6 +7695,10 @@ module mkProc(CLK, llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1; + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + 10'd0; + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3; mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0; mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7767,6 +7796,15 @@ module mkProc(CLK, if (llc_mem_server_propDstIdx_0_rl$EN) llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY llc_mem_server_propDstIdx_0_rl$D_IN; + if (llc_mem_server_rg_cacheline_cache_addr$EN) + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_addr$D_IN; + if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN) + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + if (llc_mem_server_rg_cacheline_cache_state$EN) + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_state$D_IN; if (mmioPlatform_cycle$EN) mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN; if (mmioPlatform_fromHostAddr$EN) @@ -7879,6 +7917,9 @@ module mkProc(CLK, if (llc_axi4_adapter_rg_cline$EN) llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_cline$D_IN; + if (llc_mem_server_rg_cacheline_cache_data$EN) + llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_data$D_IN; if (mmioPlatform_amoResp$EN) mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN; if (mmioPlatform_curReq$EN) @@ -7947,7 +7988,7 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; llc_axi4_adapter_rg_cline = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7958,6 +7999,11 @@ module mkProc(CLK, llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA; llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl = 1'h0; + llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_data = + 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA; + llc_mem_server_rg_cacheline_cache_state = 3'h2; mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA; mmioPlatform_cycle = 7'h2A; @@ -8002,7 +8048,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = @@ -8028,7 +8074,15 @@ module mkProc(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", + begin + v__h160987 = $stime; + #0; + end + v__h160981 = v__h160987 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h160981, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8038,14 +8092,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h151720 = $stime; + v__h160523 = $stime; #0; end - v__h151714 = v__h151720 / 32'd10; + v__h160517 = v__h160523 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h151714, + v__h160517, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8055,7 +8109,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h151763); + $display("FAIL %0d", failed_testnum__h160566); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8063,14 +8117,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4189 = $stime; + v__h4001 = $stime; #0; end - v__h4183 = v__h4189 / 32'd10; + v__h3995 = v__h4001 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4183); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h3995); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8130,16 +8184,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4362 = $stime; + v__h4174 = $stime; #0; end - v__h4356 = v__h4362 / 32'd10; + v__h4168 = v__h4174 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4356); + v__h4168); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8243,15 +8297,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4626 = $stime; + v__h4438 = $stime; #0; end - v__h4620 = v__h4626 / 32'd10; + v__h4432 = v__h4438 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4620); + v__h4432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8420,14 +8474,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6665 = $stime; + v__h6475 = $stime; #0; end - v__h6659 = v__h6665 / 32'd10; + v__h6469 = v__h6475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6659); + $display("%0d: ERROR: CreditCounter: overflow", v__h6469); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8535,15 +8589,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8580,15 +8626,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2465 = $stime; + v__h2277 = $stime; #0; end - v__h2459 = v__h2465 / 32'd10; + v__h2271 = v__h2277 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2459); + v__h2271); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8853,14 +8899,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6966 = $stime; + v__h6775 = $stime; #0; end - v__h6960 = v__h6966 / 32'd10; + v__h6769 = v__h6775 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6960); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6769); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8897,15 +8943,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7459 = $stime; + v__h7268 = $stime; #0; end - v__h7453 = v__h7459 / 32'd10; + v__h7262 = v__h7268 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7453); + v__h7262); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -8945,14 +8991,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7622 = $stime; + v__h7431 = $stime; #0; end - v__h7616 = v__h7622 / 32'd10; + v__h7425 = v__h7431 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7616); + v__h7425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9136,1088 +9182,131 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) begin - v__h93935 = $stime; + v__h99152 = $stime; #0; end - v__h93929 = v__h93935 / 32'd10; + v__h99146 = v__h99152 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awsize is not code for 1,2,4,8", - v__h93929); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display("%0d: %m.fa_writeback line at %0h", + v__h99146, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) begin - v__h93980 = $stime; + v__h99950 = $stime; #0; end - v__h93974 = v__h93980 / 32'd10; + v__h99944 = v__h99950 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: wlast is 1", - v__h93974); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h99944, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(" "); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1623) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) begin - v__h93890 = $stime; + v__h100099 = $stime; #0; end - v__h93884 = v__h93890 / 32'd10; + v__h100093 = v__h100099 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awlen is not 0 (burst length is not 1)", - v__h93884); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display("%0d: %m.fa_writeback line at %0h", + v__h100093, + llc_mem_server_rg_cacheline_cache_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - begin - v__h104972 = $stime; - #0; - end - v__h104966 = v__h104972 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arsize is not code for 1,2,4,8", - v__h104966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - begin - v__h104927 = $stime; - #0; - end - v__h104921 = v__h104927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arlen is not 0 (burst length is not 1)", - v__h104921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("\n"); + if (WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss) + $display(" data %0128h", llc_mem_server_rg_cacheline_cache_data); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) begin - v__h123524 = $stime; + v__h132480 = $stime; #0; end - v__h123518 = v__h123524 / 32'd10; + v__h132474 = v__h132480 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h123518, + v__h132474, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h123691 = $stime; + v__h132647 = $stime; #0; end - v__h123685 = v__h123691 / 32'd10; + v__h132641 = v__h132647 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h123685); + v__h132641); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10279,135 +9368,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764 && + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h125794 = $stime; + v__h134750 = $stime; #0; end - v__h125788 = v__h125794 / 32'd10; + v__h134744 = v__h134750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h125788); + v__h134744); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11605,177 +10694,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h143140 = $stime; + v__h152094 = $stime; #0; end - v__h143134 = v__h143140 / 32'd10; + v__h152088 = v__h152094 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h143134); + $display("%0d: ERROR: CreditCounter: overflow", v__h152088); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", mem_req_wr_addr_awaddr__h137049); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", mem_req_wr_addr_awaddr__h146005); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("AXI4_Wr_Data { ", "wid: "); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", 4'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", data64__h145920); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", data64__h136964); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", strb8__h136965); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", strb8__h145921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h122905 = $stime; + v__h131861 = $stime; #0; end - v__h122899 = v__h122905 / 32'd10; + v__h131855 = v__h131861 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h122899, + v__h131855, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11846,159 +10927,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) - $write("'h%h", mem_req_rd_addr_araddr__h123125); + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) + $write("'h%h", mem_req_rd_addr_araddr__h132081); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) begin - v__h149835 = $stime; + v__h158788 = $stime; #0; end - v__h149829 = v__h149835 / 32'd10; + v__h158782 = v__h158788 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h149829, + v__h158782, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__747_U_ETC___d1764) + NOT_llc_axi4_adapter_cfg_verbosity_read__731_U_ETC___d1748) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h150343 = $stime; + v__h159296 = $stime; #0; end - v__h150337 = v__h150343 / 32'd10; + v__h159290 = v__h159296 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h150337); + v__h159290); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index 17acf2a..ec9efa4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -3633,9 +3633,9 @@ module mkReorderBufferSynth(CLK, MUX_m_valid_1_23_dummy2_1$write_1__SEL_1, MUX_m_valid_1_23_dummy2_1$write_1__SEL_2, MUX_m_valid_1_23_dummy_1_0$wset_1__VAL_1, + MUX_m_valid_1_24_dummy2_1$write_1__SEL_1, MUX_m_valid_1_24_dummy2_1$write_1__SEL_2, MUX_m_valid_1_24_dummy_1_0$wset_1__VAL_1, - MUX_m_valid_1_24_lat_1$wset_1__SEL_1, MUX_m_valid_1_25_dummy2_1$write_1__SEL_1, MUX_m_valid_1_25_dummy2_1$write_1__SEL_2, MUX_m_valid_1_25_dummy_1_0$wset_1__VAL_1, @@ -9238,12 +9238,12 @@ module mkReorderBufferSynth(CLK, assign MUX_m_valid_1_23_dummy2_1$write_1__SEL_2 = WILL_FIRE_RL_m_canon_enq && m_enqP_1 == 5'd23 && SEL_ARR_m_enqEn_0_whas__20_m_enqEn_1_whas__21__ETC___d1420 ; + assign MUX_m_valid_1_24_dummy2_1$write_1__SEL_1 = + EN_specUpdate_incorrectSpeculation && + (m_wrongSpecEn$wget[16] || m_row_1_24$dependsOn_wrongSpec) ; assign MUX_m_valid_1_24_dummy2_1$write_1__SEL_2 = WILL_FIRE_RL_m_canon_enq && m_enqP_1 == 5'd24 && SEL_ARR_m_enqEn_0_whas__20_m_enqEn_1_whas__21__ETC___d1420 ; - assign MUX_m_valid_1_24_lat_1$wset_1__SEL_1 = - EN_specUpdate_incorrectSpeculation && - (m_wrongSpecEn$wget[16] || m_row_1_24$dependsOn_wrongSpec) ; assign MUX_m_valid_1_25_dummy2_1$write_1__SEL_1 = EN_specUpdate_incorrectSpeculation && (m_wrongSpecEn$wget[16] || m_row_1_25$dependsOn_wrongSpec) ; @@ -10302,7 +10302,7 @@ module mkReorderBufferSynth(CLK, // register m_valid_1_24_rl assign m_valid_1_24_rl$D_IN = m_valid_1_24_lat_1$whas ? - !MUX_m_valid_1_24_lat_1$wset_1__SEL_1 : + !MUX_m_valid_1_24_dummy2_1$write_1__SEL_1 : !MUX_m_valid_1_24_dummy_1_0$wset_1__VAL_1 && m_valid_1_24_rl ; assign m_valid_1_24_rl$EN = 1'd1 ; diff --git a/src_Testbench/Fabrics/AXI4/AXI4_Deburster.bsv b/src_Testbench/Fabrics/AXI4/AXI4_Deburster.bsv new file mode 100644 index 0000000..b79654b --- /dev/null +++ b/src_Testbench/Fabrics/AXI4/AXI4_Deburster.bsv @@ -0,0 +1,322 @@ +// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved + +package AXI4_Deburster; + +// ================================================================ +// This package defines a AXI4-slave-to-AXI4-slave conversion module. +// The parameter interface is an AXI4-slave that carries no burst transactions. +// The output interface is an AXI4-slave that carries burst transactions. + +// ================================================================ +// Bluespec library imports + +import Vector :: *; +import FIFOF :: *; +import SpecialFIFOs :: *; +import ConfigReg :: *; + +// ---------------- +// BSV additional libs + +import Cur_Cycle :: *; + +// ================================================================ +// Project imports + +import Semi_FIFOF :: *; +import AXI4_Types :: *; + +// ================================================================ +// The interface for the fabric module + +interface AXI4_Deburster_IFC #(numeric type wd_id, + numeric type wd_addr, + numeric type wd_data, + numeric type wd_user); + method Action reset; + + // From master + interface AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) from_master; + + // To slave + interface AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user) to_slave; +endinterface + +// ================================================================ +// The Deburster module +// The function parameter is an address-decode function, which +// returns (True, slave-port-num) if address is mapped to slave-port-num +// (False, ?) if address is unmapped to any slave port + +module mkAXI4_Deburster (AXI4_Deburster_IFC #(wd_id, wd_addr, wd_data, wd_user)) + provisos (Add #(a__, 8, wd_addr)); + + // 0 quiet; 1: display start of burst; 2: display all traffic + Integer cfg_verbosity = 0; + + Reg #(Bool) rg_reset <- mkReg (True); + + // Transactor facing master + AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user) + xactor_from_master <- mkAXI4_Slave_Xactor; + + // Transactor facing slave + AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user) + xactor_to_slave <- mkAXI4_Master_Xactor; + + // On a write-transaction, this register is the W-channel burst beat count + // (0 => start of burst) + Reg #(AXI4_Len) rg_w_beat_count <- mkReg (0); + + // On a write-transaction, records awlen for slave + // Size of FIFO should cover slave latency + FIFOF #(AXI4_Len) f_w_awlen <- mkSizedFIFOF (4); + + // On a write-transaction, this register is the B-channel burst beat count + // which is the number of individual (non-burst) responses from the + // slave to be combined into a single burst response to the master. + // (0 => ready for next burst) + Reg #(AXI4_Len) rg_b_beat_count <- mkReg (0); + + // On a burst write-transaction, all the individual slave responses + // may not have the same 'resp' on the B channel. This register + // remembers the first 'non-okay' resp (if any), to be returned to + // the master in the burst response. + Reg #(AXI4_Resp) rg_b_resp <- mkReg (axi4_resp_okay); + + // On a read-transaction, records arlen for slave + // Size of FIFO should cover slave latency + FIFOF #(AXI4_Len) f_r_arlen <- mkSizedFIFOF (4); + + // On a read-transaction, this register is the AR-channel burst beat count + // (0 => start of next burst) + Reg #(AXI4_Len) rg_ar_beat_count <- mkReg (0); + + // On a read-transaction, this register is the R-channel burst beat count + // (0 => ready for next burst) + Reg #(AXI4_Len) rg_r_beat_count <- mkReg (0); + + // ---------------------------------------------------------------- + // Compute address for beat + + function Bit #(wd_addr) fv_addr_for_beat (Bit #(wd_addr) start_addr, + AXI4_Size axsize, + AXI4_Burst axburst, + AXI4_Len beat_count); + Bit #(wd_addr) addr = start_addr; + if (axburst == axburst_incr) + addr = start_addr + (zeroExtend (beat_count) << pack (axsize)); + else if (axburst == axburst_wrap) + addr = start_addr; // TODO: fixup + return addr; + endfunction + + // ---------------------------------------------------------------- + // RESET + + rule rl_reset (rg_reset); + $display ("%0d: %m::AXI4_Deburster.rl_reset", cur_cycle); + xactor_from_master.reset; + xactor_to_slave.reset; + + f_w_awlen.clear; + rg_w_beat_count <= 0; + rg_b_beat_count <= 0; + rg_b_resp <= axi4_resp_okay; + + f_r_arlen.clear; + rg_ar_beat_count <= 0; + rg_r_beat_count <= 0; + + rg_reset <= False; + endrule + + // ---------------------------------------------------------------- + // BEHAVIOR + + // ---------------- + // Wr requests (AW and W channels) + + rule rl_wr_xaction_master_to_slave; + AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a_in = xactor_from_master.o_wr_addr.first; + AXI4_Wr_Data #(wd_data, wd_user) d_in = xactor_from_master.o_wr_data.first; + + // Construct output AW item + let a_out = a_in; + a_out.awaddr = fv_addr_for_beat (a_in.awaddr, a_in.awsize, a_in.awburst, rg_w_beat_count); + a_out.awlen = 0; + a_out.awburst = axburst_fixed; // Not necessary when awlen=1, but slave may be finicky + + // Set WLAST to true since this is always last beat of outgoing xaction (awlen=1) + let d_out = d_in; + d_out.wlast = True; + + // Send to slave + xactor_to_slave.i_wr_addr.enq (a_out); + xactor_to_slave.i_wr_data.enq (d_out); + + xactor_from_master.o_wr_data.deq; + + // Remember burst length so that individual responses from slave + // can be combined into a single burst response to the master. + if (rg_w_beat_count == 0) + f_w_awlen.enq (a_in.awlen); + + if (rg_w_beat_count < a_in.awlen) + rg_w_beat_count <= rg_w_beat_count + 1; + else begin + // Last beat of incoming burst; done with AW item + xactor_from_master.o_wr_addr.deq; + rg_w_beat_count <= 0; + + // Simulation-only assertion-check (no action, just display assertion failure) + // Last incoming beat must have WLAST = 1 + if (! d_in.wlast) begin + $display ("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", cur_cycle); + $display (" WLAST not set on last data beat (awlen = %0d)", a_in.awlen); + $display (" ", fshow (d_in)); + end + end + + // Debugging + if (cfg_verbosity > 0) begin + $display ("%0d: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s, beat %0d", + cur_cycle, rg_w_beat_count); + if (rg_w_beat_count == 0) + $display (" a_in : ", fshow (a_in)); + if ((rg_w_beat_count == 0) || (cfg_verbosity > 1)) begin + $display (" d_in : ", fshow (d_in)); + $display (" a_out: ", fshow (a_out)); + $display (" d_out: ", fshow (d_out)); + end + end + endrule: rl_wr_xaction_master_to_slave + + // ---------------- + // Wr responses (B channel): consume responses from slave until the + // last response for a burst, then respond to master. Remember if + // any of them was not an 'okay' response. + + rule rl_wr_resp_slave_to_master; + AXI4_Wr_Resp #(wd_id, wd_user) b_in <- pop_o (xactor_to_slave.o_wr_resp); + + if (rg_b_beat_count < f_w_awlen.first) begin + // Remember first non-okay response (if any) of a burst in rg_b_resp + if ((rg_b_resp == axi4_resp_okay) && (b_in.bresp != axi4_resp_okay)) + rg_b_resp <= b_in.bresp; + + // not last beat of burst + rg_b_beat_count <= rg_b_beat_count + 1; + + if (cfg_verbosity > 1) begin + $display ("%0d: %m::AXI4_Deburster.rl_wr_resp_slave_to_master: m <- s, beat %0d", + cur_cycle, rg_b_beat_count); + $display (" Consuming and discarding beat %0d", rg_b_beat_count); + $display (" ", fshow (b_in)); + end + end + else begin + // Last beat of burst + let b_out = b_in; + if (rg_b_resp != axi4_resp_okay) + b_out.bresp = rg_b_resp; + xactor_from_master.i_wr_resp.enq (b_out); + + f_w_awlen.deq; + + // Get ready for next burst + rg_b_beat_count <= 0; + rg_b_resp <= axi4_resp_okay; + + if (cfg_verbosity > 1) begin + $display ("%0d: %m::AXI4_Deburster.rl_wr_resp_slave_to_master: m <- s, beat %0d", + cur_cycle, rg_b_beat_count); + $display (" b_in: ", fshow (b_in)); + $display (" b_out: ", fshow (b_out)); + end + end + endrule + + // ---------------- + // Rd requests (AR channel) + + rule rl_rd_xaction_master_to_slave; + AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a_in = xactor_from_master.o_rd_addr.first; + + // Compute forwarded request for each beat, and send + let a_out = a_in; + a_out.araddr = fv_addr_for_beat (a_in.araddr, a_in.arsize, a_in.arburst, rg_ar_beat_count); + a_out.arlen = 0; + a_out.arburst = axburst_fixed; // Not necessary when arlen=1, but slave may be finicky + xactor_to_slave.i_rd_addr.enq (a_out); + + // On first beat, set up the response count + if (rg_ar_beat_count == 0) + f_r_arlen.enq (a_in.arlen); + + if (rg_ar_beat_count < a_in.arlen) + rg_ar_beat_count <= rg_ar_beat_count + 1; + else begin + // Last beat sent; done with AR item + xactor_from_master.o_rd_addr.deq; + rg_ar_beat_count <= 0; + end + + // Debugging + if (cfg_verbosity > 0) begin + $display ("%0d: %m::AXI4_Deburster.rl_rd_xaction_master_to_slave: m -> s, beat %0d", + cur_cycle, rg_ar_beat_count); + if (rg_ar_beat_count == 0) + $display (" a_in: ", fshow (a_in)); + if ((rg_ar_beat_count == 0) || (cfg_verbosity > 1)) + $display (" a_out: ", fshow (a_out)); + end + endrule: rl_rd_xaction_master_to_slave + + // ---------------- + // Rd responses + + rule rl_rd_resp_slave_to_master; + AXI4_Rd_Data #(wd_id, wd_data, wd_user) r_in <- pop_o (xactor_to_slave.o_rd_data); + let arlen = f_r_arlen.first; + + let r_out = r_in; + if (rg_r_beat_count < arlen) begin + // not last beat of burst + r_out.rlast = False; + rg_r_beat_count <= rg_r_beat_count + 1; + end + else begin + // Last beat of burst + rg_r_beat_count <= 0; + r_out.rlast = True; // should be set already, but override if not + f_r_arlen.deq; + end + + xactor_from_master.i_rd_data.enq (r_out); + + // Debugging + if (cfg_verbosity > 0) begin + $display ("%0d: %m::AXI4_Deburster.rl_rd_resp_slave_to_master: m <- s, beat %0d", + cur_cycle, rg_r_beat_count); + if ((rg_r_beat_count == 0) || (cfg_verbosity > 1)) begin + $display (" r_in: ", fshow (r_in)); + $display (" r_out: ", fshow (r_out)); + end + end + endrule: rl_rd_resp_slave_to_master + + // ---------------------------------------------------------------- + // INTERFACE + + method Action reset () if (! rg_reset); + rg_reset <= True; + endmethod + + interface from_master = xactor_from_master.axi_side; + interface to_slave = xactor_to_slave .axi_side; +endmodule + +// ================================================================ + +endpackage: AXI4_Deburster diff --git a/src_Testbench/Fabrics/AXI4/AXI4_Fabric.bsv b/src_Testbench/Fabrics/AXI4/AXI4_Fabric.bsv index 27f7b14..52b950a 100644 --- a/src_Testbench/Fabrics/AXI4/AXI4_Fabric.bsv +++ b/src_Testbench/Fabrics/AXI4/AXI4_Fabric.bsv @@ -28,8 +28,8 @@ import AXI4_Types :: *; // ================================================================ // The interface for the fabric module -interface AXI4_Fabric_IFC #(numeric type num_masters, - numeric type num_slaves, +interface AXI4_Fabric_IFC #(numeric type tn_num_masters, + numeric type tn_num_slaves, numeric type wd_id, numeric type wd_addr, numeric type wd_data, @@ -38,194 +38,240 @@ interface AXI4_Fabric_IFC #(numeric type num_masters, method Action set_verbosity (Bit #(4) verbosity); // From masters - interface Vector #(num_masters, AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_from_masters; + interface Vector #(tn_num_masters, AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_from_masters; // To slaves - interface Vector #(num_slaves, AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_to_slaves; + interface Vector #(tn_num_slaves, AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_to_slaves; endinterface // ================================================================ // The Fabric module -// The function parameter is an address-decode function, which returns +// The function parameter is an address-decode function, which // returns (True, slave-port-num) if address is mapped to slave-port-num -// (False, ?) if address is unmapped to any port +// (False, ?) if address is unmapped to any slave port -module mkAXI4_Fabric #(function Tuple2 #(Bool, Bit #(TLog #(num_slaves))) +module mkAXI4_Fabric #(function Tuple2 #(Bool, Bit #(TLog #(tn_num_slaves))) fn_addr_to_slave_num (Bit #(wd_addr) addr)) - (AXI4_Fabric_IFC #(num_masters, num_slaves, wd_id, wd_addr, wd_data, wd_user)) + (AXI4_Fabric_IFC #(tn_num_masters, tn_num_slaves, wd_id, wd_addr, wd_data, wd_user)) - provisos (Log #(num_masters, log_nm), - Log #(num_slaves, log_ns), - Log #(TAdd #(num_masters, 1), log_nm_plus_1), - Log #(TAdd #(num_slaves, 1), log_ns_plus_1), - Add #(_dummy, TLog #(num_slaves), log_ns_plus_1)); + provisos (Log #(tn_num_masters, log_nm), + Log #(tn_num_slaves, log_ns), + Log #(TAdd #(tn_num_slaves, 1), log_ns_plus_1), + Add #(_dummy, TLog #(tn_num_slaves), log_ns_plus_1)); + Integer num_masters = valueOf (tn_num_masters); + Integer num_slaves = valueOf (tn_num_slaves); + + // 0: quiet; 1: show transactions Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0); Reg #(Bool) rg_reset <- mkReg (True); // Transactors facing masters - Vector #(num_masters, AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)) + Vector #(tn_num_masters, AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)) xactors_from_masters <- replicateM (mkAXI4_Slave_Xactor); // Transactors facing slaves - Vector #(num_slaves, AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)) + Vector #(tn_num_slaves, AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)) xactors_to_slaves <- replicateM (mkAXI4_Master_Xactor); - // FIFOs to keep track of which master originated a transaction, in - // order to route corresponding responses back to that master. - // Legal masters are 0..(num_masters-1) - // The value of 'num_masters' is used for decode errors (no such slave) + // ---------------------------------------------------------------- + // Book-keeping to keep track of which master originated a transaction, in + // order to route corresponding responses back to that master, etc. + // Legal slaves are 0..(num_slaves-1) + // The "illegal" value of 'num_slaves' is used for decode errors (no such slave) + // Size of SizedFIFOs is estimated: should cover round-trip latency to slave and back. - Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_wr_sjs <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_id))) v_f_wr_err_id <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_wr_err_user <- replicateM (mkSizedFIFOF (8)); - Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_wr_mis <- replicateM (mkSizedFIFOF (8)); + // ---------------- + // Write-transaction book-keeping - Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_rd_sjs <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_id))) v_f_rd_err_id <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_rd_err_user <- replicateM (mkSizedFIFOF (8)); - Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_rd_mis <- replicateM (mkSizedFIFOF (8)); + // On an mi->sj write-transaction, this fifo records sj for master mi + Vector #(tn_num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_wr_sjs <- replicateM (mkSizedFIFOF (8)); + + // On an mi->sj write-transaction, this fifo records mi for slave sj + Vector #(tn_num_slaves, FIFOF #(Bit #(log_nm))) v_f_wr_mis <- replicateM (mkSizedFIFOF (8)); + + // On an mi->sj write-transaction, this fifo records a task (sj, awlen) for W channel + Vector #(tn_num_masters, + FIFOF #(Tuple2 #(Bit #(log_ns_plus_1), + AXI4_Len))) v_f_wd_tasks <- replicateM (mkFIFOF); + // On an mi->sj write-transaction, this register is the W-channel burst beat_count + // (0 => ready for next burst) + Vector #(tn_num_masters, Reg #(AXI4_Len)) v_rg_wd_beat_count <- replicateM (mkReg (0)); + + // On a write-transaction to non-exisitent slave, record id and user for error response + Vector #(tn_num_masters, + FIFOF #(Tuple2 #(Bit #(wd_id), + Bit #(wd_user)))) v_f_wr_err_info <- replicateM (mkSizedFIFOF (8)); + + // ---------------- + // Read-transaction book-keeping + + // On an mi->sj read-transaction, records sj for master mi + Vector #(tn_num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_rd_sjs <- replicateM (mkSizedFIFOF (8)); + // On an mi->sj read-transaction, records (mi,arlen) for slave sj + Vector #(tn_num_slaves, + FIFOF #(Tuple2 #(Bit #(log_nm), + AXI4_Len))) v_f_rd_mis <- replicateM (mkSizedFIFOF (8)); + // On an mi->sj read-transaction, this register is the R-channel burst beat_count + // (0 => ready for next burst) + Vector #(tn_num_slaves, Reg #(AXI4_Len)) v_rg_r_beat_count <- replicateM (mkReg (0)); + + // On a read-transaction to non-exisitent slave, record id and user for error response + Vector #(tn_num_masters, + FIFOF #(Tuple3 #(AXI4_Len, + Bit #(wd_id), + Bit #(wd_user)))) v_f_rd_err_info <- replicateM (mkSizedFIFOF (8)); + + // On an mi->non-existent-slave read-transaction, + // this register is the R-channel burst beat_count + // (0 => ready for next burst) + Vector #(tn_num_masters, Reg #(AXI4_Len)) v_rg_r_err_beat_count <- replicateM (mkReg (0)); // ---------------------------------------------------------------- - // BEHAVIOR + // RESET rule rl_reset (rg_reset); - $display ("%0d: AXI4_Fabric.rl_reset", cur_cycle); - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) begin + $display ("%0d: %m.rl_reset", cur_cycle); + for (Integer mi = 0; mi < num_masters; mi = mi + 1) begin xactors_from_masters [mi].reset; v_f_wr_sjs [mi].clear; - v_f_wr_err_id [mi].clear; - v_f_wr_err_user [mi].clear; + v_f_wd_tasks [mi].clear; + v_rg_wd_beat_count [mi] <= 0; + + v_f_wr_err_info [mi].clear; v_f_rd_sjs [mi].clear; - v_f_rd_err_id [mi].clear; - v_f_rd_err_user [mi].clear; + + v_f_rd_err_info [mi].clear; end - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) begin + for (Integer sj = 0; sj < num_slaves; sj = sj + 1) begin xactors_to_slaves [sj].reset; v_f_wr_mis [sj].clear; v_f_rd_mis [sj].clear; + v_rg_r_beat_count [sj] <= 0; end rg_reset <= False; endrule // ---------------------------------------------------------------- - // Help functions for moving data from masters to slaves + // BEHAVIOR - Integer num_slaves_i = valueOf (num_slaves); + // ---------------------------------------------------------------- + // Predicates to check if master I has transaction for slave J - function Bool wr_move_from_mi_to_sj (Integer mi, Integer sj); + function Bool fv_mi_has_wr_for_sj (Integer mi, Integer sj); let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr; match { .legal, .slave_num } = fn_addr_to_slave_num (addr); return (legal - && ( (num_slaves_i == 1) + && ( (num_slaves == 1) || (slave_num == fromInteger (sj)))); endfunction - function Bool wr_illegal_sj (Integer mi); + function Bool fv_mi_has_wr_for_none (Integer mi); let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr; match { .legal, ._ } = fn_addr_to_slave_num (addr); return (! legal); endfunction - function Bool rd_move_from_mi_to_sj (Integer mi, Integer sj); + function Bool fv_mi_has_rd_for_sj (Integer mi, Integer sj); let addr = xactors_from_masters [mi].o_rd_addr.first.araddr; match { .legal, .slave_num } = fn_addr_to_slave_num (addr); return (legal - && ( (num_slaves_i == 1) + && ( (num_slaves == 1) || (slave_num == fromInteger (sj)))); endfunction - function Bool rd_illegal_sj (Integer mi); + function Bool fv_mi_has_rd_for_none (Integer mi); let addr = xactors_from_masters [mi].o_rd_addr.first.araddr; match { .legal, ._ } = fn_addr_to_slave_num (addr); return (! legal); endfunction - // ---------------- - // Wr requests from masters to slaves + // ================================================================ + // Wr requests (AW, W and B channels) - // Legal destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) + // Wr requests to legal slaves (AW channel) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + for (Integer sj = 0; sj < num_slaves; sj = sj + 1) - rule rl_wr_xaction_master_to_slave (wr_move_from_mi_to_sj (mi, sj)); + rule rl_wr_xaction_master_to_slave (fv_mi_has_wr_for_sj (mi, sj)); + // Move the AW transaction AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr); - AXI4_Wr_Data #(wd_id, wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data); - xactors_to_slaves [sj].i_wr_addr.enq (a); - xactors_to_slaves [sj].i_wr_data.enq (d); + // Enqueue a task for the W channel + v_f_wd_tasks [mi].enq (tuple2 (fromInteger (sj), a.awlen)); + + // Book-keeping v_f_wr_mis [sj].enq (fromInteger (mi)); v_f_wr_sjs [mi].enq (fromInteger (sj)); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (a)); - $display (" ", fshow (d)); + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + cur_cycle, mi, sj); + $display (" ", fshow (a)); end endrule - // Non-existent destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - rule rl_wr_xaction_no_such_slave (wr_illegal_sj (mi)); + // Wr requests to non-existent slave (AW channel) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + rule rl_wr_xaction_no_such_slave (fv_mi_has_wr_for_none (mi)); AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr); - AXI4_Wr_Data #(wd_id, wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data); + AXI4_Wr_Data #(wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data); - v_f_wr_sjs [mi].enq (fromInteger (valueOf (num_slaves))); - v_f_wr_err_id [mi].enq (a.awid); - v_f_wr_err_user [mi].enq (a.awuser); + // Special value 'num_slaves' (not a legal sj) means "no such slave" + v_f_wr_sjs [mi].enq (fromInteger (num_slaves)); + v_f_wr_err_info [mi].enq (tuple2 (a.awid, a.awuser)); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", cur_cycle, mi); + // Enqueue a task for the W channel (must consume the write-data burst) + v_f_wd_tasks [mi].enq (tuple2 (fromInteger (num_slaves), a.awlen)); + + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", + cur_cycle, mi); $display (" ", fshow (a)); end endrule - // ---------------- - // Rd requests from masters to slaves + // Wr data (W channel) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) - // Legal destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) + // Handle W channel burst + // Invariant: v_rg_wd_beat_count == 0 between bursts + // Note: awlen is encoded as 0..255 for burst lengths of 1..256 + rule rl_wr_xaction_master_to_slave_data (v_f_wd_tasks [mi].first matches {.sj, .awlen}); + AXI4_Wr_Data #(wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data); - rule rl_rd_xaction_master_to_slave (rd_move_from_mi_to_sj (mi, sj)); - AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); + // If sj is a legal slave, send it the data beat, else drop it. + if (sj < fromInteger (num_slaves)) + xactors_to_slaves [sj].i_wr_data.enq (d); - xactors_to_slaves [sj].i_rd_addr.enq (a); + if (v_rg_wd_beat_count [mi] == awlen) begin + // End of burst + v_f_wd_tasks [mi].deq; + v_rg_wd_beat_count [mi] <= 0; - v_f_rd_mis [sj].enq (fromInteger (mi)); - v_f_rd_sjs [mi].enq (fromInteger (sj)); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (a)); + // Simulation-only assertion-check (no action, just display assertion failure) + // Final beat must have WLAST = 1 + // Rely on slave (which should also see this error) to return error response + if (! (d.wlast)) begin + $display ("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + cur_cycle, mi, sj); + $display (" WLAST not set on final data beat (awlen = %0d)", awlen); + $display (" ", fshow (d)); end - endrule + end + else + v_rg_wd_beat_count [mi] <= v_rg_wd_beat_count [mi] + 1; + endrule - // Non-existent destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - rule rl_rd_xaction_no_such_slave (rd_illegal_sj (mi)); - AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); + // Wr responses from slaves to masters (B channel) - v_f_rd_sjs [mi].enq (fromInteger (valueOf (num_slaves))); - v_f_rd_err_id [mi].enq (a.arid); - v_f_rd_err_user [mi].enq (a.aruser); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", cur_cycle, mi); - $display (" ", fshow (a)); - end - endrule - - // ---------------- - // Wr responses from slaves to masters - - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + for (Integer sj = 0; sj < num_slaves; sj = sj + 1) rule rl_wr_resp_slave_to_master ( (v_f_wr_mis [sj].first == fromInteger (mi)) && (v_f_wr_sjs [mi].first == fromInteger (sj))); @@ -235,86 +281,149 @@ module mkAXI4_Fabric #(function Tuple2 #(Bool, Bit #(TLog #(num_slaves))) xactors_from_masters [mi].i_wr_resp.enq (b); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", cur_cycle, mi, sj); + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + cur_cycle, mi, sj); $display (" ", fshow (b)); end endrule - // ---------------- - // Wr error responses to masters + // Wr error responses to masters (B channel) // v_f_wr_sjs [mi].first has value num_slaves (illegal value) - // v_f_wr_err_id [mi].first contains the request's 'id' data - // v_f_wr_err_user [mi].first contains the request's 'user' data + // v_f_wr_err_info [mi].first contains request fields 'awid' and 'awuser' - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) - rule rl_wr_resp_err_to_master (v_f_wr_sjs [mi].first == fromInteger (valueOf (num_slaves))); + rule rl_wr_resp_err_to_master (v_f_wr_sjs [mi].first == fromInteger (num_slaves)); v_f_wr_sjs [mi].deq; - v_f_wr_err_id [mi].deq; - v_f_wr_err_user [mi].deq; + v_f_wr_err_info [mi].deq; - let b = AXI4_Wr_Resp {bid: v_f_wr_err_id [mi].first, + match { .awid, .awuser } = v_f_wr_err_info [mi].first; + + let b = AXI4_Wr_Resp {bid: awid, bresp: axi4_resp_decerr, - buser: v_f_wr_err_user [mi].first}; + buser: awuser}; xactors_from_masters [mi].i_wr_resp.enq (b); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: wr master [%0d] <- error", cur_cycle, mi); + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", cur_cycle, mi); $display (" ", fshow (b)); end endrule - // ---------------- - // Rd responses from slaves to masters + // ================================================================ + // Rd requests (AR and R channels) - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) + // Rd requests to legal slaves (AR channel) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + for (Integer sj = 0; sj < num_slaves; sj = sj + 1) - rule rl_rd_resp_slave_to_master ( (v_f_rd_mis [sj].first == fromInteger (mi)) - && (v_f_rd_sjs [mi].first == fromInteger (sj))); - v_f_rd_mis [sj].deq; - v_f_rd_sjs [mi].deq; - AXI4_Rd_Data #(wd_id, wd_data, wd_user) r <- pop_o (xactors_to_slaves [sj].o_rd_data); + rule rl_rd_xaction_master_to_slave (fv_mi_has_rd_for_sj (mi, sj)); + AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); - xactors_from_masters [mi].i_rd_data.enq (r); + xactors_to_slaves [sj].i_rd_addr.enq (a); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (r)); + v_f_rd_mis [sj].enq (tuple2 (fromInteger (mi), a.arlen)); + v_f_rd_sjs [mi].enq (fromInteger (sj)); + + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + cur_cycle, mi, sj); + $display (" ", fshow (a)); end endrule - // ---------------- - // Rd error responses to masters + // Rd requests to non-existent slave (AR channel) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + rule rl_rd_xaction_no_such_slave (fv_mi_has_rd_for_none (mi)); + AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); + + v_f_rd_sjs [mi].enq (fromInteger (num_slaves)); + v_f_rd_err_info [mi].enq (tuple3 (a.arlen, a.arid, a.aruser)); + + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", + cur_cycle, mi); + $display (" ", fshow (a)); + end + endrule + + // Rd responses from slaves to masters (R channel) + + for (Integer mi = 0; mi < num_masters; mi = mi + 1) + for (Integer sj = 0; sj < num_slaves; sj = sj + 1) + + rule rl_rd_resp_slave_to_master (v_f_rd_mis [sj].first matches { .mi2, .arlen } + &&& (mi2 == fromInteger (mi)) + &&& (v_f_rd_sjs [mi].first == fromInteger (sj))); + + AXI4_Rd_Data #(wd_id, wd_data, wd_user) r <- pop_o (xactors_to_slaves [sj].o_rd_data); + + if (v_rg_r_beat_count [sj] == arlen) begin + // Final beat of burst + v_f_rd_mis [sj].deq; + v_f_rd_sjs [mi].deq; + v_rg_r_beat_count [sj] <= 0; + + // Assertion-check + // Final beat must have RLAST = 1 + // If not, and if RRESP is OK, set RRESP to AXI4_RESP_SLVERR + if ((r.rresp == axi4_resp_okay) && (! (r.rlast))) begin + r.rresp = axi4_resp_slverr; + $display ("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + cur_cycle, mi, sj); + $display (" RLAST not set on final data beat (arlen = %0d)", arlen); + $display (" ", fshow (r)); + end + end + else + v_rg_r_beat_count [sj] <= v_rg_r_beat_count [sj] + 1; + + xactors_from_masters [mi].i_rd_data.enq (r); + + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + cur_cycle, mi, sj); + $display (" r: ", fshow (r)); + end + endrule + + // Rd error responses to masters (R channel) // v_f_rd_sjs [mi].first has value num_slaves (illegal value) - // v_f_rd_err_id [mi].first contains the request's 'id' data - // v_f_rd_err_user [mi].first contains the request's 'user' data + // v_f_rd_err_info [mi].first contains request fields: 'arlen', 'arid', 'aruser' - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) + for (Integer mi = 0; mi < num_masters; mi = mi + 1) - rule rl_rd_resp_err_to_master (v_f_rd_sjs [mi].first == fromInteger (valueOf (num_slaves))); - v_f_rd_sjs [mi].deq; - v_f_rd_err_id [mi].deq; - v_f_rd_err_user [mi].deq; + rule rl_rd_resp_err_to_master (v_f_rd_sjs [mi].first == fromInteger (num_slaves)); + match { .arlen, .arid, .aruser } = v_f_rd_err_info [mi].first; Bit #(wd_data) data = 0; - let r = AXI4_Rd_Data {rid: v_f_rd_err_id [mi].first, + let r = AXI4_Rd_Data {rid: arid, rdata: data, rresp: axi4_resp_decerr, - rlast: True, - ruser: v_f_rd_err_user [mi].first}; + rlast: (v_rg_r_err_beat_count [mi] == arlen), + ruser: aruser}; xactors_from_masters [mi].i_rd_data.enq (r); - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Fabric: rd master [%0d] <- error", cur_cycle, mi); - $display (" ", fshow (r)); + if (v_rg_r_err_beat_count [mi] == arlen) begin + // Last beat of burst + v_f_rd_sjs [mi].deq; + v_f_rd_err_info [mi].deq; + v_rg_r_err_beat_count [mi] <= 0; + end + else + v_rg_r_err_beat_count [mi] <= v_rg_r_err_beat_count [mi] + 1; + + if (cfg_verbosity > 0) begin + $display ("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + cur_cycle, mi); + $display (" r: ", fshow (r)); end endrule - // ---------------------------------------------------------------- + // ================================================================ // INTERFACE function AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) f1 (Integer j) diff --git a/src_Testbench/Fabrics/AXI4/AXI4_Mem_Model.bsv b/src_Testbench/Fabrics/AXI4/AXI4_Mem_Model.bsv new file mode 100644 index 0000000..0c681e4 --- /dev/null +++ b/src_Testbench/Fabrics/AXI4/AXI4_Mem_Model.bsv @@ -0,0 +1,211 @@ +// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved. +// Author: Rishiyur S. Nikhil + +package AXI4_Mem_Model; + +// ================================================================ +// A memory-model to be used as a slave on an AXI4 bus. +// Only partical functionality; will be gradually improved over time. +// Current status: +// Address and Data bus widths: 64b +// Bursts: 'fixed' and 'incr' only +// Size: Full 64-bit width reads/writes only +// Strobes: Not yet handled +// memory size: See 'mem_size_word64' definition below + +// ================================================================ +// Exports + +export AXI4_Mem_Model_IFC (..); +export mkAXI4_Mem_Model; + +// ================================================================ +// Bluespec library imports + +import RegFile :: *; +import FIFOF :: *; +import GetPut :: *; +import ClientServer :: *; + +// ---------------- +// BSV additional libs + +import Cur_Cycle :: *; +import GetPut_Aux :: *; +import Semi_FIFOF :: *; + +// ================================================================ +// Project imports + +import AXI4_Types :: *; + +// ================================================================ +// INTERFACE + +interface AXI4_Mem_Model_IFC #(numeric type wd_id, + numeric type wd_addr, + numeric type wd_data, + numeric type wd_user); + + method Action init (Bit #(wd_addr) addr_map_base, Bit #(wd_addr) addr_map_lim); + + interface AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) slave; + +endinterface + +// ================================================================ +// IMPLEMENTATION + +Integer mem_size_word64 = 'h100_0000; // 16M x 64b words = 128MiB + +function Bool fn_addr_ok (Bit #(64) base, Bit #(64) lim, Bit #(64) addr, AXI4_Size size); + let aligned = fn_addr_is_aligned (addr, size); + let in_range = ((base <= addr) && (addr < lim)); + return (aligned && in_range); +endfunction + +// ---------------- + +module mkAXI4_Mem_Model (AXI4_Mem_Model_IFC #(wd_id, wd_addr, wd_data, wd_user)) + provisos (NumAlias #(wd_addr, 64), + NumAlias #(wd_data, 64)); + + // 0 = quiet; 1 = show mem transactions + Integer verbosity = 1; + + Reg #(Bool) rg_initialized <- mkReg (False); + + Reg #(Bit #(wd_addr)) rg_addr_map_base <- mkRegU; + Reg #(Bit #(wd_addr)) rg_addr_map_lim <- mkRegU; + + AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user) xactor <- mkAXI4_Slave_Xactor; + + RegFile #(Bit #(wd_addr), Bit #(wd_data)) rf <- mkRegFile (0, fromInteger (mem_size_word64)); + + // ================================================================ + // Read requests + // TODO: does a bad addr return 'burst-len' err responses or just 1? + + Reg #(Bit #(8)) rg_rd_beat <- mkReg (0); + + // Recv request on RD_ADDR bus + // Send burst responses on RD_DATA bus + rule rl_read (rg_initialized); + let rd_addr = xactor.o_rd_addr.first; + let rf_index = ((rd_addr.araddr - rg_addr_map_base) >> 3); + if (rd_addr.arburst == axburst_incr) + rf_index = rf_index + zeroExtend (rg_rd_beat); + let last = (rg_rd_beat == rd_addr.arlen); + + let addr_ok = fn_addr_ok (rg_addr_map_base, rg_addr_map_lim, rd_addr.araddr, rd_addr.arsize); + + let data = (addr_ok ? rf.sub (rf_index) : 0); + + AXI4_Rd_Data #(wd_id, wd_data, wd_user) + rd_data = AXI4_Rd_Data {rid: rd_addr.arid, + rdata: data, + rresp: (addr_ok ? axi4_resp_okay : axi4_resp_slverr), + rlast: last, + ruser: rd_addr.aruser}; + xactor.i_rd_data.enq (rd_data); + + if (last) begin + xactor.o_rd_addr.deq; + rg_rd_beat <= 0; + end + else + rg_rd_beat <= rg_rd_beat + 1; + + if (verbosity != 0) begin + $write ("%0d: %m.rl_read: ", cur_cycle); + $write (fshow_Rd_Addr (rd_addr)); + $write (fshow_Rd_Data (rd_data)); + if (addr_ok) + $display (" beat %0d rf_index 0x%0h", rg_rd_beat, rf_index); + else + $display (" beat 0x%0h BAD ADDR", rg_rd_beat); + end + endrule + + // ================================================================ + // Write requests + + Reg #(Bit #(8)) rg_wr_beat <- mkReg (0); + + // Recv request on WR_ADDR bus and burst data on WR_DATA bus, + // send final response on WR_RESP bus + rule rl_write (rg_initialized); + let wr_addr = xactor.o_wr_addr.first; + let wr_data <- pop_o (xactor.o_wr_data); + let rf_index = ((wr_addr.awaddr - rg_addr_map_base) >> 3); + if (wr_addr.awburst == axburst_incr) + rf_index = rf_index + zeroExtend (rg_wr_beat); + let last = (rg_wr_beat == wr_addr.awlen); + + let addr_ok = fn_addr_ok (rg_addr_map_base, rg_addr_map_lim, wr_addr.awaddr, wr_addr.awsize); + + if (addr_ok) + rf.upd (rf_index, wr_data.wdata); + + if (verbosity != 0) begin + $write ("%0d: %m.rl_write: ", cur_cycle); + $write (fshow_Wr_Data (wr_data)); + $write (" ", fshow_Wr_Addr (wr_addr)); + if (addr_ok) + $display (" beat %0d rf_index %0h", rg_wr_beat, rf_index); + else + $display (" beat %0d BAD ADDR", rg_wr_beat); + end + + if (last) begin + AXI4_Wr_Resp #(wd_id, wd_user) wr_resp = ?; + wr_resp = AXI4_Wr_Resp {bid: wr_addr.awid, + bresp: (addr_ok ? axi4_resp_okay : axi4_resp_slverr), + buser: wr_addr.awuser}; + xactor.i_wr_resp.enq (wr_resp); + xactor.o_wr_addr.deq; + rg_wr_beat <= 0; + if (verbosity != 0) + $display (" ", fshow_Wr_Resp (wr_resp)); + end + else + rg_wr_beat <= rg_wr_beat + 1; + endrule + + // ================================================================ + // INTERFACE + + method Action init (Bit #(wd_addr) addr_map_base, Bit #(wd_addr) addr_map_lim); + if (addr_map_base [2:0] != 3'b0) + $display ("%0d: %m.init: ERROR: unaligned addr_map_base 0x%0h", cur_cycle, addr_map_base); + else if (addr_map_lim [2:0] != 3'b0) + $display ("%0d: %m.init: ERROR: unaligned addr_map_lim 0x%0h", cur_cycle, addr_map_lim); + else if (addr_map_lim <= addr_map_base) + $display ("%0d: %m.init: ERROR: addr_map_base 0x%0h > addr_map_lim 0x%0h", + cur_cycle, + addr_map_base, + addr_map_lim); + else if ((addr_map_lim - addr_map_base) > fromInteger (mem_size_word64 * 8)) + $display ("%0d: %m.init: ERROR: mem size (base 0x%0h, lim 0x%0h) > max (0x%0h)", + cur_cycle, + addr_map_base, + addr_map_lim, + fromInteger (mem_size_word64 * 8)); + else begin + xactor.reset; + rg_addr_map_base <= addr_map_base; + rg_addr_map_lim <= addr_map_lim; + rg_initialized <= True; + $display ("%0d: %m.init: addr_map_base 0x%0h, addr_map_lim 0x%0h", + cur_cycle, + addr_map_base, + addr_map_lim); + end + endmethod + + interface slave = xactor.axi_side; +endmodule + +// ================================================================ + +endpackage diff --git a/src_Testbench/Fabrics/AXI4/AXI4_Types.bsv b/src_Testbench/Fabrics/AXI4/AXI4_Types.bsv index bbd08cf..ef09633 100644 --- a/src_Testbench/Fabrics/AXI4/AXI4_Types.bsv +++ b/src_Testbench/Fabrics/AXI4/AXI4_Types.bsv @@ -118,6 +118,20 @@ AXI4_Resp axi4_resp_exokay = 2'b_01; AXI4_Resp axi4_resp_slverr = 2'b_10; AXI4_Resp axi4_resp_decerr = 2'b_11; +// ================================================================ +// Function to check address-alignment + +function Bool fn_addr_is_aligned (Bit #(wd_addr) addr, AXI4_Size size); + return ( (size == axsize_1) + || ((size == axsize_2) && (addr [0] == 1'b0)) + || ((size == axsize_4) && (addr [1:0] == 2'b0)) + || ((size == axsize_8) && (addr [2:0] == 3'b0)) + || ((size == axsize_16) && (addr [3:0] == 4'b0)) + || ((size == axsize_32) && (addr [4:0] == 5'b0)) + || ((size == axsize_64) && (addr [5:0] == 6'b0)) + || ((size == axsize_128) && (addr [6:0] == 7'b0))); +endfunction + // ================================================================ // These are the signal-level interfaces for an AXI4 master. // The (*..*) attributes ensure that when bsc compiles this to Verilog, @@ -150,7 +164,6 @@ interface AXI4_Master_IFC #(numeric type wd_id, // Wr Data channel (* always_ready, result="wvalid" *) method Bool m_wvalid; // out - (* always_ready, result="wid" *) method Bit #(wd_id) m_wid; // out (* always_ready, result="wdata" *) method Bit #(wd_data) m_wdata; // out (* always_ready, result="wstrb" *) method Bit #(TDiv #(wd_data, 8)) m_wstrb; // out (* always_ready, result="wlast" *) method Bool m_wlast; // out @@ -232,7 +245,6 @@ interface AXI4_Slave_IFC #(numeric type wd_id, // Wr Data channel (* always_ready, always_enabled, prefix = "" *) method Action m_wvalid ((* port="wvalid" *) Bool wvalid, // in - (* port="wid" *) Bit #(wd_id) wid, // in (* port="wdata" *) Bit #(wd_data) wdata, // in (* port="wstrb" *) Bit #(TDiv #(wd_data,8)) wstrb, // in (* port="wlast" *) Bool wlast, // in @@ -306,7 +318,6 @@ instance Connectable #(AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user), (* fire_when_enabled, no_implicit_conditions *) rule rl_wr_data_channel; axis.m_wvalid (axim.m_wvalid, - axim.m_wid, axim.m_wdata, axim.m_wstrb, axim.m_wlast, @@ -375,7 +386,6 @@ AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user) // Wr Data channel method Bool m_wvalid = False; // out - method Bit #(wd_id) m_wid = ?; // out method Bit #(wd_data) m_wdata = ?; // out method Bit #(TDiv #(wd_data, 8)) m_wstrb = ?; // out method Bool m_wlast = ?; // out @@ -446,7 +456,6 @@ AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) // Wr Data channel method Action m_wvalid (Bool wvalid, - Bit #(wd_id) wid, Bit #(wd_data) wdata, Bit #(TDiv #(wd_data, 8)) wstrb, Bool wlast, @@ -591,13 +600,11 @@ deriving (Bits, FShow); // Write Data channel typedef struct { - Bit #(wd_id) wid; Bit #(wd_data) wdata; Bit #(TDiv #(wd_data, 8)) wstrb; Bool wlast; Bit #(wd_user) wuser; - } AXI4_Wr_Data #(numeric type wd_id, - numeric type wd_data, + } AXI4_Wr_Data #(numeric type wd_data, numeric type wd_user) deriving (Bits, FShow); @@ -643,6 +650,88 @@ typedef struct { numeric type wd_user) deriving (Bits, FShow); +// ================================================================ +// The following are specialized 'fshow' functions for AXI4 bus +// payloads: the most common fields, and more compact. + +function Fmt fshow_AXI4_Size (AXI4_Size size); + Fmt result = ?; + if (size == axsize_1) result = $format ("sz1"); + else if (size == axsize_2) result = $format ("sz2"); + else if (size == axsize_4) result = $format ("sz4"); + else if (size == axsize_8) result = $format ("sz8"); + else if (size == axsize_16) result = $format ("sz16"); + else if (size == axsize_32) result = $format ("sz32"); + else if (size == axsize_64) result = $format ("sz64"); + else if (size == axsize_128) result = $format ("sz128"); + return result; +endfunction + +function Fmt fshow_AXI4_Burst (AXI4_Burst burst); + Fmt result = ?; + if (burst == axburst_fixed) result = $format ("fixed"); + else if (burst == axburst_incr) result = $format ("incr"); + else if (burst == axburst_wrap) result = $format ("wrap"); + else result = $format ("burst:%0d", burst); + return result; +endfunction + +function Fmt fshow_AXI4_Resp (AXI4_Resp resp); + Fmt result = ?; + if (resp == axi4_resp_okay) result = $format ("okay"); + else if (resp == axi4_resp_exokay) result = $format ("exokay"); + else if (resp == axi4_resp_slverr) result = $format ("slverr"); + else if (resp == axi4_resp_decerr) result = $format ("decerr"); + return result; +endfunction + +// ---------------- + +function Fmt fshow_Wr_Addr (AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) x); + Fmt result = ($format ("{awaddr:%0h,", x.awaddr) + + $format ("awlen:%0d", x.awlen) + + $format (",") + + fshow_AXI4_Size (x.awsize) + + $format (",") + + fshow_AXI4_Burst (x.awburst) + + $format ("}")); + return result; +endfunction + +function Fmt fshow_Wr_Data (AXI4_Wr_Data #(wd_data, wd_user) x); + let result = ($format ("{wdata:%0h,wstrb:%0h", x.wdata, x.wstrb) + + (x.wlast ? $format (",wlast") : $format (",..")) + + $format ("}")); + return result; +endfunction + +function Fmt fshow_Wr_Resp (AXI4_Wr_Resp #(wd_id, wd_user) x); + Fmt result = ($format ("{bresp:") + + fshow_AXI4_Resp (x.bresp) + + $format ("}")); + return result; +endfunction + +function Fmt fshow_Rd_Addr (AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) x); + Fmt result = ($format ("{araddr:%0h", x.araddr) + + $format (",arlen:%0d", x.arlen) + + $format (",") + + fshow_AXI4_Size (x.arsize) + + $format (",") + + fshow_AXI4_Burst (x.arburst) + + $format ("}")); + return result; +endfunction + +function Fmt fshow_Rd_Data (AXI4_Rd_Data #(wd_id, wd_data, wd_user) x); + Fmt result = ($format ("{rresp:") + + fshow_AXI4_Resp (x.rresp) + + $format (",rdata:%0h", x.rdata) + + (x.rlast ? $format (",rlast") : $format (",..")) + + $format ("}")); + return result; +endfunction + // ================================================================ // AXI4 buffer @@ -655,7 +744,7 @@ interface AXI4_Server_IFC #(numeric type wd_id, numeric type wd_user); interface FIFOF_I #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) i_wr_addr; - interface FIFOF_I #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) i_wr_data; + interface FIFOF_I #(AXI4_Wr_Data #(wd_data, wd_user)) i_wr_data; interface FIFOF_O #(AXI4_Wr_Resp #(wd_id, wd_user)) o_wr_resp; interface FIFOF_I #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) i_rd_addr; @@ -671,7 +760,7 @@ interface AXI4_Client_IFC #(numeric type wd_id, numeric type wd_user); interface FIFOF_O #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) o_wr_addr; - interface FIFOF_O #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) o_wr_data; + interface FIFOF_O #(AXI4_Wr_Data #(wd_data, wd_user)) o_wr_data; interface FIFOF_I #(AXI4_Wr_Resp #(wd_id, wd_user)) i_wr_resp; interface FIFOF_O #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) o_rd_addr; @@ -695,7 +784,7 @@ endinterface module mkAXI4_Buffer (AXI4_Buffer_IFC #(wd_id, wd_addr, wd_data, wd_user)); FIFOF #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) f_wr_addr <- mkFIFOF; - FIFOF #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) f_wr_data <- mkFIFOF; + FIFOF #(AXI4_Wr_Data #(wd_data, wd_user)) f_wr_data <- mkFIFOF; FIFOF #(AXI4_Wr_Resp #(wd_id, wd_user)) f_wr_resp <- mkFIFOF; FIFOF #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) f_rd_addr <- mkFIFOF; @@ -732,7 +821,7 @@ endmodule module mkAXI4_Buffer_2 (AXI4_Buffer_IFC #(wd_id, wd_addr, wd_data, wd_user)); FIFOF #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) f_wr_addr <- mkMaster_EdgeFIFOF; - FIFOF #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) f_wr_data <- mkMaster_EdgeFIFOF; + FIFOF #(AXI4_Wr_Data #(wd_data, wd_user)) f_wr_data <- mkMaster_EdgeFIFOF; FIFOF #(AXI4_Wr_Resp #(wd_id, wd_user)) f_wr_resp <- mkSlave_EdgeFIFOF; FIFOF #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) f_rd_addr <- mkMaster_EdgeFIFOF; @@ -780,7 +869,7 @@ interface AXI4_Master_Xactor_IFC #(numeric type wd_id, // FIFOF side interface FIFOF_I #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) i_wr_addr; - interface FIFOF_I #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) i_wr_data; + interface FIFOF_I #(AXI4_Wr_Data #(wd_data, wd_user)) i_wr_data; interface FIFOF_O #(AXI4_Wr_Resp #(wd_id, wd_user)) o_wr_resp; interface FIFOF_I #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) i_rd_addr; @@ -798,7 +887,7 @@ module mkAXI4_Master_Xactor (AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, w // These FIFOs are guarded on BSV side, unguarded on AXI side FIFOF #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (guarded, unguarded); - FIFOF #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) f_wr_data <- mkGFIFOF (guarded, unguarded); + FIFOF #(AXI4_Wr_Data #(wd_data, wd_user)) f_wr_data <- mkGFIFOF (guarded, unguarded); FIFOF #(AXI4_Wr_Resp #(wd_id, wd_user)) f_wr_resp <- mkGFIFOF (unguarded, guarded); FIFOF #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (guarded, unguarded); @@ -836,7 +925,6 @@ module mkAXI4_Master_Xactor (AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, w // Wr Data channel method Bool m_wvalid = f_wr_data.notEmpty; - method Bit #(wd_id) m_wid = f_wr_data.first.wid; method Bit #(wd_data) m_wdata = f_wr_data.first.wdata; method Bit #(TDiv #(wd_data, 8)) m_wstrb = f_wr_data.first.wstrb; method Bool m_wlast = f_wr_data.first.wlast; @@ -921,7 +1009,7 @@ module mkAXI4_Master_Xactor_2 (AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, Reg #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) rg_wr_addr <- mkRegU; Array #(Reg #(Bool)) crg_wr_data_full <- mkCReg (3, False); - Reg #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) rg_wr_data <- mkRegU; + Reg #(AXI4_Wr_Data #(wd_data, wd_user)) rg_wr_data <- mkRegU; Array #(Reg #(Bool)) crg_wr_resp_full <- mkCReg (3, False); Reg #(AXI4_Wr_Resp #(wd_id, wd_user)) rg_wr_resp <- mkRegU; @@ -975,7 +1063,6 @@ module mkAXI4_Master_Xactor_2 (AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, // Wr Data channel method Bool m_wvalid = crg_wr_data_full [port_deq]; - method Bit #(wd_id) m_wid = rg_wr_data.wid; method Bit #(wd_data) m_wdata = rg_wr_data.wdata; method Bit #(TDiv #(wd_data, 8)) m_wstrb = rg_wr_data.wstrb; method Bool m_wlast = rg_wr_data.wlast; @@ -1065,7 +1152,7 @@ interface AXI4_Slave_Xactor_IFC #(numeric type wd_id, // FIFOF side interface FIFOF_O #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) o_wr_addr; - interface FIFOF_O #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) o_wr_data; + interface FIFOF_O #(AXI4_Wr_Data #(wd_data, wd_user)) o_wr_data; interface FIFOF_I #(AXI4_Wr_Resp #(wd_id, wd_user)) i_wr_resp; interface FIFOF_O #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) o_rd_addr; @@ -1083,7 +1170,7 @@ module mkAXI4_Slave_Xactor (AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_ // These FIFOs are guarded on BSV side, unguarded on AXI side FIFOF #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded); - FIFOF #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) f_wr_data <- mkGFIFOF (unguarded, guarded); + FIFOF #(AXI4_Wr_Data #(wd_data, wd_user)) f_wr_data <- mkGFIFOF (unguarded, guarded); FIFOF #(AXI4_Wr_Resp #(wd_id, wd_user)) f_wr_resp <- mkGFIFOF (guarded, unguarded); FIFOF #(AXI4_Rd_Addr #(wd_id, wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded); @@ -1135,14 +1222,12 @@ module mkAXI4_Slave_Xactor (AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_ // Wr Data channel method Action m_wvalid (Bool wvalid, - Bit #(wd_id) wid, Bit #(wd_data) wdata, Bit #(TDiv #(wd_data, 8)) wstrb, Bool wlast, Bit #(wd_user) wuser); if (wvalid && f_wr_data.notFull) - f_wr_data.enq (AXI4_Wr_Data {wid: wid, - wdata: wdata, + f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast: wlast, wuser: wuser}); @@ -1229,7 +1314,7 @@ module mkAXI4_Slave_Xactor_2 (AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, w Reg #(AXI4_Wr_Addr #(wd_id, wd_addr, wd_user)) rg_wr_addr <- mkRegU; Array #(Reg #(Bool)) crg_wr_data_full <- mkCReg (3, False); - Reg #(AXI4_Wr_Data #(wd_id, wd_data, wd_user)) rg_wr_data <- mkRegU; + Reg #(AXI4_Wr_Data #(wd_data, wd_user)) rg_wr_data <- mkRegU; Array #(Reg #(Bool)) crg_wr_resp_full <- mkCReg (3, False); Reg #(AXI4_Wr_Resp #(wd_id, wd_user)) rg_wr_resp <- mkRegU; @@ -1295,15 +1380,13 @@ module mkAXI4_Slave_Xactor_2 (AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, w // Wr Data channel method Action m_wvalid (Bool wvalid, - Bit #(wd_id) wid, Bit #(wd_data) wdata, Bit #(TDiv #(wd_data, 8)) wstrb, Bool wlast, Bit #(wd_user) wuser); if (wvalid && (! crg_wr_data_full [port_enq])) begin crg_wr_data_full [port_enq] <= True; // enq - rg_wr_data <= AXI4_Wr_Data {wid: wid, - wdata: wdata, + rg_wr_data <= AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast: wlast, wuser: wuser}; diff --git a/src_Testbench/Fabrics/AXI4/Unit_Test/Makefile b/src_Testbench/Fabrics/AXI4/Unit_Test/Makefile new file mode 100644 index 0000000..2e0c495 --- /dev/null +++ b/src_Testbench/Fabrics/AXI4/Unit_Test/Makefile @@ -0,0 +1,73 @@ +### -*-Makefile-*- + +# Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved + +# Makefile for standalone Unit Tester for Deburster (Bluesim only) + +.PHONY: all +all: compile simulator + +# ================================================================ +# Search path for bsc for .bsv files + +BSV_ADDL_LIBS=../../../../src_Core/BSV_Additional_Libs + +BSC_PATH = -p ..:$(BSV_ADDL_LIBS):+ + +# ---------------- +# Top-level file and module + +TOPFILE = Unit_Test_Deburster.bsv +TOPMODULE = mkUnit_Test_Deburster + +# ================================================================ +# bsc compilation flags + +BSC_COMPILATION_FLAGS += \ + -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-show-timestamps -check-assert \ + -suppress-warnings G0020 \ + +RTS -K128M -RTS -show-range-conflict + +# ================================================================ +# Compile Bluesim intermediate files from BSV sources (needs Bluespec 'bsc' compiler) + +TMP_DIRS = -bdir build_dir -simdir build_dir -info-dir build_dir + +build_dir: + mkdir -p $@ + +.PHONY: compile +compile: build_dir + @echo "INFO: Re-compiling BSV sources" + bsc -u -elab -sim $(TMP_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) $(TOPFILE) + @echo "INFO: Re-compiled BSV sources" + +# ================================================================ +# Compile and link Bluesim intermediate files into a Bluesim executable + +SIM_EXE_FILE = exe_HW_sim + +BSC_C_FLAGS += \ + -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 \ + -Xl -v + +.PHONY: simulator +simulator: + @echo "INFO: linking bsc-compiled objects into Bluesim executable" + bsc -sim -parallel-sim-link 8 \ + $(TMP_DIRS) \ + -e $(TOPMODULE) -o ./$(SIM_EXE_FILE) \ + $(BSC_C_FLAGS) + @echo "INFO: linked bsc-compiled objects into Bluesim executable" + +# ================================================================ + +.PHONY: clean +clean: + rm -r -f *~ build_dir + +.PHONY: full_clean +full_clean: clean + rm -r -f $(SIM_EXE_FILE)* *.log *.vcd + +# ================================================================ diff --git a/src_Testbench/Fabrics/AXI4/Unit_Test/Unit_Test_Deburster.bsv b/src_Testbench/Fabrics/AXI4/Unit_Test/Unit_Test_Deburster.bsv new file mode 100644 index 0000000..2e8687c --- /dev/null +++ b/src_Testbench/Fabrics/AXI4/Unit_Test/Unit_Test_Deburster.bsv @@ -0,0 +1,289 @@ +// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved + +package Unit_Test_Deburster; + +// ================================================================ +// Standalone unit tester for AXI4_Deburster.bsv + +// ================================================================ +// Bluespec library imports + +import FIFOF :: *; +import Connectable :: *; + +// ---------------- +// BSV additional libs + +import Cur_Cycle :: *; + +// ================================================================ +// Project imports + +import Semi_FIFOF :: *; +import AXI4_Types :: *; +import AXI4_Deburster :: *; + +// ================================================================ +// Synthesized instance of Deburster + +typedef 4 Wd_Id; +typedef 32 Wd_Addr; +typedef 64 Wd_Data; +typedef 10 Wd_User; + +typedef AXI4_Deburster_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) AXI4_Deburster_IFC_Inst; + +(* synthesize *) +module mkAXI4_Deburster_Inst (AXI4_Deburster_IFC_Inst); + let m <- mkAXI4_Deburster; + return m; +endmodule + +// ================================================================ + +(* synthesize *) +module mkUnit_Test_Deburster (Empty); + AXI4_Deburster_IFC_Inst deburster <- mkAXI4_Deburster_Inst; + + AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master <- mkAXI4_Master_Xactor; + AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave <- mkAXI4_Slave_Xactor; + + mkConnection (master.axi_side, deburster.from_master); + mkConnection (deburster.to_slave, slave.axi_side); + + Reg #(Bit #(32)) rg_test <- mkReg (20); // Chooses which test to run + + FIFOF #(Bit #(8)) f_len <- mkFIFOF; + Reg #(Bit #(8)) rg_beat <- mkReg (0); + Reg #(Bit #(32)) rg_idle_count <- mkReg (0); + + // ================================================================ + // Help function to create AXI4 channel payloads + + function AXI4_Wr_Addr #(Wd_Id, Wd_Addr, Wd_User) + fv_mk_wr_addr (Bit #(Wd_Id) id, + Bit #(Wd_Addr) addr, + Bit #(8) len, + Bit #(2) burst, + Bit #(Wd_User) user); + return AXI4_Wr_Addr {awid: id, + awaddr: addr, + awlen: len, + awsize: axsize_8, + awburst: burst, + awlock: 0, + awcache: 0, + awprot: 0, + awqos: 0, + awregion: 0, + awuser: user}; + endfunction + + function AXI4_Wr_Data #(Wd_Data, Wd_User) + fv_mk_wr_data (Bit #(Wd_Data) data, + Bit #(Wd_User) user); + Bool last = (rg_beat == f_len.first - 1); + return AXI4_Wr_Data {wdata: data, + wstrb: 'hFF, + wlast: last, + wuser: user}; + endfunction + + function AXI4_Wr_Resp #(Wd_Id, Wd_User) + fv_mk_wr_resp (AXI4_Wr_Addr #(Wd_Id, Wd_Addr, Wd_User) wa); + return AXI4_Wr_Resp {bid: wa.awid, + bresp: axi4_resp_okay, + buser: wa.awuser}; + endfunction + + function AXI4_Rd_Addr #(Wd_Id, Wd_Addr, Wd_User) + fv_mk_rd_addr (Bit #(Wd_Id) id, + Bit #(Wd_Addr) addr, + Bit #(8) len, + Bit #(2) burst, + Bit #(Wd_User) user); + return AXI4_Rd_Addr {arid: id, + araddr: addr, + arlen: len, + arsize: axsize_8, + arburst: burst, + arlock: 0, + arcache: 0, + arprot: 0, + arqos: 0, + arregion: 0, + aruser: user}; + endfunction + + function AXI4_Rd_Data #(Wd_Id, Wd_Data, Wd_User) + fv_mk_rd_data (AXI4_Rd_Addr #(Wd_Id, Wd_Addr, Wd_User) ar); + return AXI4_Rd_Data {rid: ar.arid, + rdata: zeroExtend (ar.araddr + 'h10_000), + rresp: axi4_resp_okay, + rlast: True, + ruser: ar.aruser}; + endfunction + + // ================================================================ + // STIMULUS + + Bit #(Wd_Id) id1 = 1; + Bit #(Wd_User) user1 = 1; + + // ---------------- + // Write tests + + rule rl_wr_single (rg_test == 0); + Bit #(8) len = 1; + let wa = fv_mk_wr_addr (id1, 'h1000, (len - 1), axburst_fixed, user1); + master.i_wr_addr.enq (wa); + + f_len.enq (len); + rg_idle_count <= 0; + rg_test <= 100; + + $display ("%0d: master.rl_wr_single: ", cur_cycle); + $display (" ", fshow (wa)); + endrule + + rule rl_wr_burst_addr_0 (rg_test == 10); + Bit #(8) len = 2; + let wa = fv_mk_wr_addr (id1, 'h1000, (len - 1), axburst_incr, user1); + master.i_wr_addr.enq (wa); + + f_len.enq (len); + rg_idle_count <= 0; + rg_test <= 11; + + $display ("%0d: master.rl_wr_burst_addr_0: ", cur_cycle); + $display (" ", fshow (wa)); + endrule + + rule rl_wr_burst_addr_1 (rg_test == 11); + Bit #(8) len = 4; + let wa = fv_mk_wr_addr (id1, 'h2000, (len - 1), axburst_incr, user1); + master.i_wr_addr.enq (wa); + + f_len.enq (len); + rg_idle_count <= 0; + rg_test <= 100; + + $display ("%0d: master.rl_wr_burst_addr_1: ", cur_cycle); + $display (" ", fshow (wa)); + endrule + + rule rl_wr_data; + let data = 'h1_0000 + zeroExtend (rg_beat); + let wd = fv_mk_wr_data (data, user1); + master.i_wr_data.enq (wd); + rg_idle_count <= 0; + + if (rg_beat < f_len.first - 1) + rg_beat <= rg_beat + 1; + else begin + rg_beat <= 0; + f_len.deq; + + rg_test <= '1; + end + + $display ("%0d: master.rl_wr_data: ", cur_cycle); + $display (" ", fshow (wd)); + endrule + + // ---------------- + // Read tests + + rule rl_rd_single (rg_test == 2); + let ra = fv_mk_rd_addr (id1, 'h1000, 1, axburst_fixed, user1); + master.i_rd_addr.enq (ra); + rg_idle_count <= 0; + rg_test <= '1; + + $display ("%0d: master.rd_single: ", cur_cycle); + $display (" ", fshow (ra)); + endrule + + rule rl_rd_burst_addr_0 (rg_test == 20); + Bit #(8) len = 2; + let ra = fv_mk_rd_addr (id1, 'h1000, (len - 1), axburst_incr, user1); + master.i_rd_addr.enq (ra); + + rg_idle_count <= 0; + rg_test <= 21; + + $display ("%0d: master.rl_rd_burst_addr_0: ", cur_cycle); + $display (" ", fshow (ra)); + endrule + + rule rl_rd_burst_addr_1 (rg_test == 21); + Bit #(8) len = 4; + let ra = fv_mk_rd_addr (id1, 'h2000, (len - 1), axburst_incr, user1); + master.i_rd_addr.enq (ra); + + rg_idle_count <= 0; + rg_test <= 100; + + $display ("%0d: master.rl_rd_burst_addr_1: ", cur_cycle); + $display (" ", fshow (ra)); + endrule + + // ================================================================ + // Drain and display responses received by master + + rule rl_wr_resps; + let wr_resp <- pop_o (master.o_wr_resp); + $display ("%0d: master: ", cur_cycle); + $display (" ", fshow (wr_resp)); + rg_idle_count <= 0; + endrule + + rule rl_rd_resps; + let rd_resp <- pop_o (master.o_rd_data); + $display ("%0d: master: ", cur_cycle); + $display (" ", fshow (rd_resp)); + rg_idle_count <= 0; + endrule + + // ================================================================ + // Slave: return functional responses + // Note: we should not be receiving any bursts, since we're fronted by the Deburster. + + rule rl_slave_IP_model_writes; + $display ("%0d: %m.rl_slave_IP_model_writes: ", cur_cycle); + + let wa <- pop_o (slave.o_wr_addr); + let wd <- pop_o (slave.o_wr_data); + + let wr = fv_mk_wr_resp (wa); + slave.i_wr_resp.enq (wr); + $display (" ", fshow (wa)); + $display (" ", fshow (wd)); + $display (" ", fshow (wr)); + endrule + + rule rl_slave_IP_model_rd_addr; + let ra <- pop_o (slave.o_rd_addr); + slave.i_rd_data.enq (fv_mk_rd_data (ra)); + + $display ("%0d: slave: ", cur_cycle); + $display (" ", fshow (ra)); + endrule + + // ================================================================ + + rule rl_idle_quit; + if (rg_idle_count == 100) begin + $display ("%0d: UnitTest_Deburster: idle; quit", cur_cycle); + $finish (0); + end + else begin + rg_idle_count <= rg_idle_count + 1; + end + endrule + +endmodule + +// ================================================================ + +endpackage diff --git a/src_Testbench/SoC/Mem_Controller.bsv b/src_Testbench/SoC/Mem_Controller.bsv index ac6807d..06982cb 100644 --- a/src_Testbench/SoC/Mem_Controller.bsv +++ b/src_Testbench/SoC/Mem_Controller.bsv @@ -47,7 +47,9 @@ Bits_per_Raw_Mem_Word, Raw_Mem_Word, Mem_Controller_IFC (..), -mkMem_Controller; +mkMem_Controller, + +status_mem_controller_terminated; // ================================================================ // BSV library imports @@ -173,6 +175,11 @@ typedef enum {STATE_POWER_ON_RESET, } State deriving (Bits, Eq, FShow); +// ================================================================ +// Catch-all status + +Integer status_mem_controller_terminated = 1; + // ================================================================ // Interface @@ -189,6 +196,10 @@ interface Mem_Controller_IFC; // To raw memory (outside the SoC) interface MemoryClient #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) to_raw_mem; + // Catch-all status; return-value can identify the origin (0 = none) + (* always_ready *) + method Bit #(8) status; + // For ISA tests: watch memory writes to addr method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr); endinterface @@ -263,6 +274,9 @@ module mkMem_Controller (Mem_Controller_IFC); Reg #(Bool) rg_watch_tohost <- mkReg (False); Reg #(Fabric_Addr) rg_tohost_addr <- mkReg ('h_8000_1000); + // Catch-all status + Reg #(Bit #(8)) rg_status <- mkReg (0); + // ================================================================ // BEHAVIOR @@ -274,6 +288,7 @@ module mkMem_Controller (Mem_Controller_IFC); slave_xactor.reset; f_raw_mem_reqs.clear; f_raw_mem_rsps.clear; + rg_status <= 0; endaction endfunction @@ -535,7 +550,7 @@ module mkMem_Controller (Mem_Controller_IFC); $display ("PASS"); else $display ("FAIL %0d", exit_value); - $finish (truncate (exit_value)); + rg_status <= fromInteger (status_mem_controller_terminated); end endrule @@ -642,6 +657,11 @@ module mkMem_Controller (Mem_Controller_IFC); // To raw memory (outside the SoC) interface to_raw_mem = toGPClient (f_raw_mem_reqs, f_raw_mem_rsps); + // Catch-all status; return-value can identify the origin (0 = none) + method Bit #(8) status; + return rg_status; + endmethod + // For ISA tests: watch memory writes to addr method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr); rg_watch_tohost <= watch_tohost; diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index db0f1ab..0015cc0 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. +// Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved. package SoC_Top; @@ -21,6 +21,7 @@ import GetPut :: *; import ClientServer :: *; import Connectable :: *; import Memory :: *; +import Clocks :: *; // ---------------- // BSV additional libs @@ -32,8 +33,9 @@ import GetPut_Aux :: *; // Project imports // Main fabric -import AXI4_Types :: *; -import AXI4_Fabric :: *; +import AXI4_Types :: *; +import AXI4_Fabric :: *; +import AXI4_Deburster :: *; import Fabric_Defs :: *; import SoC_Map :: *; @@ -54,7 +56,8 @@ import Camera_Model :: *; `endif `ifdef INCLUDE_ACCEL0 -import Accel_AES :: *; +import AXI4_Accel_IFC :: *; +import AXI4_Accel :: *; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -62,16 +65,9 @@ import TV_Info :: *; `endif `ifdef INCLUDE_GDB_CONTROL -import External_Control :: *; // Control requests/responses from HSFE import Debug_Module :: *; `endif -// ================================================================ -// Local types and constants - -typedef enum {SOC_START, SOC_RESETTING, SOC_IDLE} SoC_State -deriving (Bits, Eq, FShow); - // ================================================================ // The outermost interface of the SoC @@ -80,8 +76,11 @@ interface SoC_Top_IFC; method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); `ifdef INCLUDE_GDB_CONTROL - // To external controller (E.g., GDB) - interface Server #(Control_Req, Control_Rsp) server_external_control; + // DMI (Debug Module Interface) facing remote debugger + interface DMI dmi; + + // Non-Debug-Module Reset (reset all except DM) + interface Client #(Bool, Bool) ndm_reset_client; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -96,15 +95,29 @@ interface SoC_Top_IFC; interface Get #(Bit #(8)) get_to_console; interface Put #(Bit #(8)) put_from_console; + // Catch-all status; return-value can identify the origin (0 = none) + (* always_ready *) + method Bit #(8) status; + + // Start CPU execution // For ISA tests: watch memory writes to addr - method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr); + method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr); endinterface +// ================================================================ +// Local types and constants + +typedef enum {SOC_START, + SOC_RESETTING, + SOC_IDLE} SoC_State +deriving (Bits, Eq, FShow); + // ================================================================ // The module (* synthesize *) -module mkSoC_Top (SoC_Top_IFC); +module mkSoC_Top #(Reset dm_power_on_reset) + (SoC_Top_IFC); Integer verbosity = 0; // Normally 0; non-zero for debugging Reg #(SoC_State) rg_state <- mkReg (SOC_START); @@ -113,23 +126,35 @@ module mkSoC_Top (SoC_Top_IFC); SoC_Map_IFC soc_map <- mkSoC_Map; // Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) - CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW; + // The Debug Module has its own RST_N reset signal (which comes + // from outside this module as a paramter) + CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW (dm_power_on_reset); // SoC Fabric Fabric_AXI4_IFC fabric <- mkFabric_AXI4; // SoC Boot ROM Boot_ROM_IFC boot_rom <- mkBoot_ROM; + // AXI4 Deburster in front of Boot_ROM + AXI4_Deburster_IFC #(Wd_Id, + Wd_Addr, + Wd_Data, + Wd_User) boot_rom_axi4_deburster <- mkAXI4_Deburster_A; // SoC Memory Mem_Controller_IFC mem0_controller <- mkMem_Controller; + // AXI4 Deburster in front of SoC Memory + AXI4_Deburster_IFC #(Wd_Id, + Wd_Addr, + Wd_Data, + Wd_User) mem0_controller_axi4_deburster <- mkAXI4_Deburster_A; // SoC IPs UART_IFC uart0 <- mkUART; `ifdef INCLUDE_ACCEL0 // Accel0 master to fabric - Accel_AES_IFC accel_aes0 <- mkAccel_AES; + AXI4_Accel_IFC accel0 <- mkAXI4_Accel; `endif // ---------------- @@ -143,26 +168,28 @@ module mkSoC_Top (SoC_Top_IFC); mkConnection (corew.cpu_dmem_master, fabric.v_from_masters [dmem_master_num]); `ifdef INCLUDE_ACCEL0 - // accel_aes0 to fabric - mkConnection (accel_aes0.master, fabric.v_from_masters [accel0_master_num]); + // accel to fabric + mkConnection (accel0.master, fabric.v_from_masters [accel0_master_num]); `endif // ---------------- // SoC fabric slave connections // Note: see 'SoC_Map' for 'slave_num' definitions - // Fabric to Boot ROM - mkConnection (fabric.v_to_slaves [boot_rom_slave_num], boot_rom.slave); + // Fabric to Deburster to Boot ROM + mkConnection (fabric.v_to_slaves [boot_rom_slave_num], boot_rom_axi4_deburster.from_master); + mkConnection (boot_rom_axi4_deburster.to_slave, boot_rom.slave); - // Fabric to Mem Controller - mkConnection (fabric.v_to_slaves [mem0_controller_slave_num], mem0_controller.slave); + // Fabric to Deburster to Mem Controller + mkConnection (fabric.v_to_slaves [mem0_controller_slave_num], mem0_controller_axi4_deburster.from_master); + mkConnection (mem0_controller_axi4_deburster.to_slave, mem0_controller.slave); // Fabric to UART0 - mkConnection (fabric.v_to_slaves [uart0_slave_num], uart0.slave); + mkConnection (fabric.v_to_slaves [uart0_slave_num], uart0.slave); `ifdef INCLUDE_ACCEL0 - // Fabric to accel_aes0 - mkConnection (fabric.v_to_slaves [accel0_slave_num], accel_aes0.slave); + // Fabric to accel0 + mkConnection (fabric.v_to_slaves [accel0_slave_num], accel0.slave); `endif `ifdef HTIF_MEMORY @@ -180,144 +207,99 @@ module mkSoC_Top (SoC_Top_IFC); // UART corew.core_external_interrupt_sources [irq_num_uart0].m_interrupt_req (intr); + Integer last_irq_num = irq_num_uart0; + +`ifdef INCLUDE_ACCEL0 + Bool intr_accel0 = accel0.interrupt_req; + core.core_external_interrupt_sources [irq_num_accel0].m_interrupt_req (intr_accel0); + last_irq_num = irq_num_accel0; +`endif // Tie off remaining interrupt request lines (1..N) - for (Integer j = 1; j < valueOf (N_External_Interrupt_Sources); j = j + 1) + for (Integer j = last_irq_num + 1; j < valueOf (N_External_Interrupt_Sources); j = j + 1) corew.core_external_interrupt_sources [j].m_interrupt_req (False); + + // Non-maskable interrupt request. [Tie-off; TODO: connect to genuine sources] + corew.nmi_req (False); endrule // ================================================================ - // RESET BEHAVIOR WITHOUT DEBUG MODULE + // MODULE INITIALIZATIONS - rule rl_reset_start_2 (rg_state == SOC_START); - corew.cpu_reset_server.request.put (?); - mem0_controller.server_reset.request.put (?); - uart0.server_reset.request.put (?); + function Action fa_reset_start_actions; + action + mem0_controller.server_reset.request.put (?); + uart0.server_reset.request.put (?); + fabric.reset; + endaction + endfunction - fabric.reset; + function Action fa_reset_complete_actions; + action + let mem0_controller_rsp <- mem0_controller.server_reset.response.get; + let uart0_rsp <- uart0.server_reset.response.get; - rg_state <= SOC_RESETTING; + // Initialize address maps of slave IPs + boot_rom.set_addr_map (soc_map.m_boot_rom_addr_base, + soc_map.m_boot_rom_addr_lim); - $display ("%0d: SoC_Top. Reset start ...", cur_cycle); - endrule + mem0_controller.set_addr_map (soc_map.m_mem0_controller_addr_base, + soc_map.m_mem0_controller_addr_lim); - // ================================================================ - // BEHAVIOR WITH DEBUG MODULE + uart0.set_addr_map (soc_map.m_uart0_addr_base, soc_map.m_uart0_addr_lim); -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // External debug requests and responses - - FIFOF #(Control_Req) f_external_control_reqs <- mkFIFOF; - FIFOF #(Control_Rsp) f_external_control_rsps <- mkFIFOF; - - Control_Req req = f_external_control_reqs.first; - - rule rl_handle_external_req_read_request (req.op == external_control_req_op_read_control_fabric); - f_external_control_reqs.deq; - corew.dm_dmi.read_addr (truncate (req.arg1)); - if (verbosity != 0) begin - $display ("%0d: SoC_Top.rl_handle_external_req_read_request", cur_cycle); - $display (" ", fshow (req)); - end - endrule - - rule rl_handle_external_req_read_response; - let x <- corew.dm_dmi.read_data; - let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x)}; - f_external_control_rsps.enq (rsp); - if (verbosity != 0) begin - $display ("%0d: SoC_Top.rl_handle_external_req_read_response", cur_cycle); - $display (" ", fshow (rsp)); - end - endrule - - rule rl_handle_external_req_write (req.op == external_control_req_op_write_control_fabric); - f_external_control_reqs.deq; - corew.dm_dmi.write (truncate (req.arg1), truncate (req.arg2)); - // let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: 0}; - // f_external_control_rsps.enq (rsp); - if (verbosity != 0) begin - $display ("%0d: SoC_Top.rl_handle_external_req_write", cur_cycle); - $display (" ", fshow (req)); - end - endrule - - rule rl_handle_external_req_err ( (req.op != external_control_req_op_read_control_fabric) - && (req.op != external_control_req_op_write_control_fabric)); - f_external_control_reqs.deq; - let rsp = Control_Rsp {status: external_control_rsp_status_err, result: 0}; - f_external_control_rsps.enq (rsp); - - $display ("%0d: SoC_Top.rl_handle_external_req_err: unknown req.op", cur_cycle); - $display (" ", fshow (req)); - endrule - - // ---------------------------------------------------------------- - // NDM reset (all except Debug Module) request from debug module - - rule rl_reset_start (rg_state != SOC_RESETTING); - let req <- corew.dm_ndm_reset_req_get.get; - - corew.cpu_reset_server.request.put (?); - mem0_controller.server_reset.request.put (?); - uart0.server_reset.request.put (?); - - fabric.reset; - - rg_state <= SOC_RESETTING; - - $display ("%0d: SoC_Top.rl_reset_start (Debug Module NDM reset, all except debug module) ...", - cur_cycle); - endrule +`ifdef INCLUDE_ACCEL0 + accel0.init (fabric_default_id, + soc_map.m_accel0_addr_base, + soc_map.m_accel0_addr_lim); `endif - rule rl_reset_complete (rg_state == SOC_RESETTING); - let cpu_rsp <- corew.cpu_reset_server.response.get; - let mem0_controller_rsp <- mem0_controller.server_reset.response.get; - let uart0_rsp <- uart0.server_reset.response.get; + if (verbosity != 0) begin + $display (" SoC address map:"); + $display (" Boot ROM: 0x%0h .. 0x%0h", + soc_map.m_boot_rom_addr_base, + soc_map.m_boot_rom_addr_lim); + $display (" Mem0 Controller: 0x%0h .. 0x%0h", + soc_map.m_mem0_controller_addr_base, + soc_map.m_mem0_controller_addr_lim); + $display (" UART0: 0x%0h .. 0x%0h", + soc_map.m_uart0_addr_base, + soc_map.m_uart0_addr_lim); + end + endaction + endfunction - // Initialize address maps of slave IPs - boot_rom.set_addr_map (soc_map.m_boot_rom_addr_base, - soc_map.m_boot_rom_addr_lim); + // ---------------- + // Initial reset - mem0_controller.set_addr_map (soc_map.m_mem0_controller_addr_base, - soc_map.m_mem0_controller_addr_lim); + rule rl_reset_start_initial (rg_state == SOC_START); + fa_reset_start_actions; + rg_state <= SOC_RESETTING; - uart0.set_addr_map (soc_map.m_uart0_addr_base, soc_map.m_uart0_addr_lim); + $display ("%0d: %m.rl_reset_start_initial ...", cur_cycle); + endrule + rule rl_reset_complete_initial (rg_state == SOC_RESETTING); + fa_reset_complete_actions; rg_state <= SOC_IDLE; -`ifdef INCLUDE_GDB_CONTROL - $display ("%0d: SoC_Top: NDM reset complete (all except debug module)", cur_cycle); -`else - $display ("%0d: SoC_Top. Reset complete ...", cur_cycle); -`endif - - if (verbosity != 0) begin - $display (" SoC address map:"); - $display (" Boot ROM: 0x%0h .. 0x%0h", - soc_map.m_boot_rom_addr_base, - soc_map.m_boot_rom_addr_lim); - $display (" Mem0 Controller: 0x%0h .. 0x%0h", - soc_map.m_mem0_controller_addr_base, - soc_map.m_mem0_controller_addr_lim); - $display (" UART0: 0x%0h .. 0x%0h", - soc_map.m_uart0_addr_base, - soc_map.m_uart0_addr_lim); - end + $display ("%0d: %m.rl_reset_complete_initial", cur_cycle); endrule // ================================================================ // INTERFACE - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - corew.set_verbosity (verbosity, logdelay); + method Action set_verbosity (Bit #(4) verbosity1, Bit #(64) logdelay); + corew.set_verbosity (verbosity1, logdelay); endmethod // To external controller (E.g., GDB) `ifdef INCLUDE_GDB_CONTROL - interface server_external_control = toGPServer (f_external_control_reqs, f_external_control_rsps); + // DMI (Debug Module Interface) facing remote debugger + interface DMI dmi = corew.dmi; + + // Non-Debug-Module Reset (reset all except DM) + interface Client ndm_reset_client = corew.ndm_reset_client; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -332,16 +314,34 @@ module mkSoC_Top (SoC_Top_IFC); interface get_to_console = uart0.get_to_console; interface put_from_console = uart0.put_from_console; + // Catch-all status; return-value can identify the origin (0 = none) + method Bit #(8) status; + return mem0_controller.status; + endmethod + + // Start CPU execution // For ISA tests: watch memory writes to addr - method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr); + method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr); + Bool watch_tohost = (tohost_addr != 0); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); - if (watch_tohost) begin - let fromhost_addr = 'h_8000_1040; - corew.set_htif_addrs (tohost_addr, fromhost_addr); - end + corew.start (tohost_addr, fromhost_addr); + $display ("%0d: %m.method start (tohost %0h, fromhost %0h)", + cur_cycle, tohost_addr, fromhost_addr); endmethod endmodule: mkSoC_Top +// ================================================================ +// Specialization of parameterized AXI4 Deburster for this SoC. + +(* synthesize *) +module mkAXI4_Deburster_A (AXI4_Deburster_IFC #(Wd_Id, + Wd_Addr, + Wd_Data, + Wd_User)); + let m <- mkAXI4_Deburster; + return m; +endmodule + // ================================================================ endpackage diff --git a/src_Testbench/Top/Top_HW_Side.bsv b/src_Testbench/Top/Top_HW_Side.bsv index 63fad9a..63fa752 100644 --- a/src_Testbench/Top/Top_HW_Side.bsv +++ b/src_Testbench/Top/Top_HW_Side.bsv @@ -1,4 +1,4 @@ -// Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved. +// Copyright (c) 2013-2020 Bluespec, Inc. All Rights Reserved. package Top_HW_Side; @@ -20,9 +20,11 @@ package Top_HW_Side; // ================================================================ // BSV lib imports +import FIFOF :: *; import GetPut :: *; import ClientServer :: *; import Connectable :: *; +import Clocks :: *; // ---------------- // BSV additional libs @@ -48,6 +50,7 @@ import C_Imports :: *; `ifdef INCLUDE_GDB_CONTROL import External_Control :: *; +import Debug_Module :: *; `endif // ================================================================ @@ -58,11 +61,111 @@ import External_Control :: *; (* synthesize *) module mkTop_HW_Side (Empty) ; - SoC_Top_IFC soc_top <- mkSoC_Top; - Mem_Model_IFC mem_model <- mkMem_Model; + // ================================================================ + // The RISC-V Debug Module is at the following point in the module hierarchy: + // soc_top.corew.debug_module + // (instances of mkSoC_Top, mkCoreW, mkDebug_Module) + + // The Debug Module is reset only once, on power-up, hence we pass + // its reset down from here. + + // (power-on reset) and the Debug Module's 'hart_reset' control. + + let power_on_reset <- exposeCurrentReset; + let dm_power_on_reset = power_on_reset; + + // The rest of the system (soc_top and mem_model) are reset: + // - on power-on, and + // - when the Debug Module requests an NDM reset (for non-DebugModule). + +`ifdef INCLUDE_GDB_CONTROL + let clk <- exposeCurrentClock; + Bool initial_reset_val = False; + Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM + let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); + + let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); +`else + let ndm_reset = power_on_reset; +`endif + + // ================================================================ + // STATE + + SoC_Top_IFC soc_top <- mkSoC_Top (dm_power_on_reset, reset_by ndm_reset); + Mem_Model_IFC mem_model <- mkMem_Model (reset_by ndm_reset); // Connect SoC to raw memory - let memCnx <- mkConnection (soc_top.to_raw_mem, mem_model.mem_server); + let memCnx <- mkConnection (soc_top.to_raw_mem, mem_model.mem_server, reset_by ndm_reset); + + // ================================================================ + // Actions on reset + + function Action fa_reset_actions; + action + $display ("================================================================"); + $display ("Bluespec RISC-V standalone system simulation v1.2"); + $display ("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); + $display ("================================================================"); + + // Set CPU verbosity and logdelay (simulation only) + Bool v1 <- $test$plusargs ("v1"); + Bool v2 <- $test$plusargs ("v2"); + Bit #(4) verbosity = ((v2 ? 2 : (v1 ? 1 : 0))); + Bit #(64) logdelay = 0; // # of instructions after which to set verbosity + soc_top.set_verbosity (verbosity, logdelay); + + // ---------------- + // Load optional tohost and fromhost addrs from symbol-table file + Fabric_Addr tohost_addr = 0; + Fabric_Addr fromhost_addr = 0; + + Bool watch_tohost <- $test$plusargs ("tohost"); +`ifndef IVERILOG + // Note: see 'CAVEAT FOR IVERILOG USERS' above + if (watch_tohost) begin + let tha <- c_get_symbol_val ("tohost"); + tohost_addr = truncate (tha); + + let fha <- c_get_symbol_val ("fromhost"); + fromhost_addr = truncate (fha); + end +`endif + $display ("INFO: watch_tohost %d, tohost_addr = 0x%0h, fromhost_addr = 0x%0h", + watch_tohost, tohost_addr, fromhost_addr); + soc_top.start (tohost_addr, fromhost_addr); + endaction + endfunction + + // ================================================================ + +`ifdef INCLUDE_GDB_CONTROL + // ================================================================ + // NDM reset from DM + + Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); + + rule rl_ndm_reset (rg_ndm_reset_delay == 0); + let x <- soc_top.ndm_reset_client.request.get; + ndm_reset_controller.assertReset; + rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 200); // NOTE: heuristic + + $display ("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + cur_cycle, ndm_reset_duration); + endrule + + rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); + if (rg_ndm_reset_delay == 1) begin + fa_reset_actions; + Bool is_running = True; + soc_top.ndm_reset_client.response.put (is_running); + $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + cur_cycle); + end + rg_ndm_reset_delay <= rg_ndm_reset_delay - 1; + endrule + // ================================================================ +`endif // ================================================================ // BEHAVIOR @@ -71,31 +174,9 @@ module mkTop_HW_Side (Empty) ; // Display a banner rule rl_step0 (! rg_banner_printed); - $display ("================================================================"); - $display ("Bluespec RISC-V standalone system simulation v1.2"); - $display ("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - $display ("================================================================"); - rg_banner_printed <= True; - // Set CPU verbosity and logdelay (simulation only) - Bool v1 <- $test$plusargs ("v1"); - Bool v2 <- $test$plusargs ("v2"); - Bit #(4) verbosity = ((v2 ? 2 : (v1 ? 1 : 0))); - Bit #(64) logdelay = 0; // # of instructions after which to set verbosity - soc_top.set_verbosity (verbosity, logdelay); - - // ---------------- - // Load tohost addr from symbol-table file -`ifndef IVERILOG - // Note: see 'CAVEAT FOR IVERILOG USERS' above - Bool watch_tohost <- $test$plusargs ("tohost"); - let tha <- c_get_symbol_val ("tohost"); - Fabric_Addr tohost_addr = truncate (tha); - $display ("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - pack (watch_tohost), tohost_addr); - soc_top.set_watch_tohost (watch_tohost, tohost_addr); -`endif + fa_reset_actions; // ---------------- // Open file for Tandem Verification trace output @@ -206,6 +287,10 @@ module mkTop_HW_Side (Empty) ; // Interaction with remote debug client `ifdef INCLUDE_GDB_CONTROL + + FIFOF #(Control_Req) f_external_control_reqs <- mkFIFOF; + FIFOF #(Control_Rsp) f_external_control_rsps <- mkFIFOF; + rule rl_debug_client_request_recv; Bit #(64) req <- c_debug_client_request_recv ('hAA); Bit #(8) status = req [63:56]; @@ -224,14 +309,14 @@ module mkTop_HW_Side (Empty) ; let control_req = Control_Req {op: external_control_req_op_read_control_fabric, arg1: zeroExtend (addr), arg2: 0}; - soc_top.server_external_control.request.put (control_req); + f_external_control_reqs.enq (control_req); end else if (op == dmi_op_write) begin // $display (" WRITE 0x%0h 0x%0h", addr, data); let control_req = Control_Req {op: external_control_req_op_write_control_fabric, arg1: zeroExtend (addr), arg2: zeroExtend (data)}; - soc_top.server_external_control.request.put (control_req); + f_external_control_reqs.enq (control_req); end else if (op == dmi_op_shutdown) begin $display ("Top_HW_Side.rl_debug_client_request_recv: SHUTDOWN"); @@ -246,7 +331,7 @@ module mkTop_HW_Side (Empty) ; endrule rule rl_debug_client_response_send; - let control_rsp <- soc_top.server_external_control.response.get; + let control_rsp <- pop (f_external_control_rsps); // $display ("Top_HW_Side.rl_debug_client_response_send: 0x%0h", control_rsp.result); let status <- c_debug_client_response_send (truncate (control_rsp.result)); if (status == dmi_status_err) begin @@ -255,6 +340,59 @@ module mkTop_HW_Side (Empty) ; $finish (1); end endrule + + // ---------------------------------------------------------------- + // External debug requests and responses + + Control_Req req = f_external_control_reqs.first; + Integer dmi_verbosity = 0; // For debugging + + rule rl_handle_external_req_read_request (req.op == external_control_req_op_read_control_fabric); + f_external_control_reqs.deq; + soc_top.dmi.read_addr (truncate (req.arg1)); + if (dmi_verbosity != 0) begin + $display ("%0d: %m.rl_handle_external_req_read_request", cur_cycle); + $display (" ", fshow (req)); + end + endrule + + rule rl_handle_external_req_read_response; + let x <- soc_top.dmi.read_data; + let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x)}; + f_external_control_rsps.enq (rsp); + if (dmi_verbosity != 0) begin + $display ("%0d: %m.rl_handle_external_req_read_response", cur_cycle); + $display (" ", fshow (rsp)); + end + endrule + + rule rl_handle_external_req_write (req.op == external_control_req_op_write_control_fabric); + f_external_control_reqs.deq; + soc_top.dmi.write (truncate (req.arg1), truncate (req.arg2)); + // let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: 0}; + // f_external_control_rsps.enq (rsp); + if (dmi_verbosity != 0) begin + $display ("%0d: %m.rl_handle_external_req_write", cur_cycle); + $display (" ", fshow (req)); + end + endrule + + rule rl_handle_external_req_err ( (req.op != external_control_req_op_read_control_fabric) + && (req.op != external_control_req_op_write_control_fabric)); + f_external_control_reqs.deq; + let rsp = Control_Rsp {status: external_control_rsp_status_err, result: 0}; + f_external_control_rsps.enq (rsp); + + $display ("%0d: %m.rl_handle_external_req_err: unknown req.op", cur_cycle); + $display (" ", fshow (req)); + endrule + + (* descending_urgency = "rl_handle_external_req_read_request, rl_handle_external_req_read_response" *) + (* descending_urgency = "rl_handle_external_req_read_response, rl_handle_external_req_write" *) + (* descending_urgency = "rl_handle_external_req_read_response, rl_handle_external_req_err" *) + (* descending_urgency = "rl_handle_external_req_write, rl_handle_external_req_err" *) + rule rl_handle_external_dummy_for_urgency_attribs_only; + endrule `endif // ================================================================