From 85b4a738a92631a0bf9573f5a6748886e0b4cb2e Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 8 Apr 2020 04:21:13 +0100 Subject: [PATCH] FetchStage.bsv: Fix a mkRegU that should be a mkReg We should not use a mkRegU for rg_pending_n_items, as otherwise there is a chance the epochs for rg_pending_f32d happen to match depending on the uninitialised values. Instead ensure we always reset with no pending items. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index f848372..bd8a66b 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -390,7 +390,7 @@ module mkFetchStage(FetchStage); Ehr #(2, Maybe #(Tuple3 #(Addr, Bit #(16), Bool))) ehr_pending_straddle <- mkEhr(tagged Invalid); // Reg to hold extra instructions from Fetch3 to send to decode the next cycle Reg #(Vector #(SupSizeX2S1, Inst_Item)) rg_pending_decode <- mkReg(replicate(defaultValue)); - Reg #(SupCntX2S1) rg_pending_n_items <- mkRegU; + Reg #(SupCntX2S1) rg_pending_n_items <- mkReg(0); Reg #(Fetch3ToDecode) rg_pending_f32d <- mkRegU; // Pipeline Stage FIFOs