From 8617d38e806a282a0cc1c8dde02de37dd4207884 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Tue, 14 Mar 2023 13:52:17 +0000 Subject: [PATCH] Config for L1D Stride-2 prefetcher --- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 6c599f5..8d2f243 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -1186,7 +1186,7 @@ endmodule module mkBRAMStridePCPrefetcher(PCPrefetcher) provisos( NumAlias#(strideTableSize, 64), - NumAlias#(cLinesAheadToPrefetch, 4), // TODO fetch more if have repeatedly hit an entry, and if stride big + NumAlias#(cLinesAheadToPrefetch, 2), // TODO fetch more if have repeatedly hit an entry, and if stride big Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize))) ); //Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0)));